1 //===-- SystemZISelLowering.cpp - SystemZ DAG Lowering Implementation -----==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SystemZTargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "systemz-lower"
16 #include "SystemZISelLowering.h"
18 #include "SystemZTargetMachine.h"
19 #include "SystemZSubtarget.h"
20 #include "llvm/DerivedTypes.h"
21 #include "llvm/Function.h"
22 #include "llvm/Intrinsics.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/GlobalVariable.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/CodeGen/CallingConvLower.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/PseudoSourceValue.h"
32 #include "llvm/CodeGen/SelectionDAGISel.h"
33 #include "llvm/CodeGen/ValueTypes.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Target/TargetOptions.h"
36 #include "llvm/ADT/VectorExtras.h"
39 SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm) :
40 TargetLowering(tm), Subtarget(*tm.getSubtargetImpl()), TM(tm) {
42 RegInfo = TM.getRegisterInfo();
44 // Set up the register classes.
45 addRegisterClass(MVT::i32, SystemZ::GR32RegisterClass);
46 addRegisterClass(MVT::i64, SystemZ::GR64RegisterClass);
47 addRegisterClass(MVT::v2i32,SystemZ::GR64PRegisterClass);
48 addRegisterClass(MVT::v2i64,SystemZ::GR128RegisterClass);
51 addRegisterClass(MVT::f32, SystemZ::FP32RegisterClass);
52 addRegisterClass(MVT::f64, SystemZ::FP64RegisterClass);
54 addLegalFPImmediate(APFloat(+0.0)); // lzer
55 addLegalFPImmediate(APFloat(+0.0f)); // lzdr
56 addLegalFPImmediate(APFloat(-0.0)); // lzer + lner
57 addLegalFPImmediate(APFloat(-0.0f)); // lzdr + lndr
60 // Compute derived properties from the register classes
61 computeRegisterProperties();
63 // Set shifts properties
64 setShiftAmountType(MVT::i64);
66 // Provide all sorts of operation actions
67 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
68 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
69 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
71 setLoadExtAction(ISD::SEXTLOAD, MVT::f32, Expand);
72 setLoadExtAction(ISD::ZEXTLOAD, MVT::f32, Expand);
73 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
75 setLoadExtAction(ISD::SEXTLOAD, MVT::f64, Expand);
76 setLoadExtAction(ISD::ZEXTLOAD, MVT::f64, Expand);
77 setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand);
79 setStackPointerRegisterToSaveRestore(SystemZ::R15D);
80 setSchedulingPreference(SchedulingForLatency);
81 setBooleanContents(ZeroOrOneBooleanContent);
83 setOperationAction(ISD::RET, MVT::Other, Custom);
85 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
86 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
87 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
88 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
89 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
90 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
91 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
92 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
93 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
94 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
95 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
97 setOperationAction(ISD::SDIV, MVT::i32, Expand);
98 setOperationAction(ISD::UDIV, MVT::i32, Expand);
99 setOperationAction(ISD::SDIV, MVT::i64, Expand);
100 setOperationAction(ISD::UDIV, MVT::i64, Expand);
101 setOperationAction(ISD::SREM, MVT::i32, Expand);
102 setOperationAction(ISD::UREM, MVT::i32, Expand);
103 setOperationAction(ISD::SREM, MVT::i64, Expand);
104 setOperationAction(ISD::UREM, MVT::i64, Expand);
106 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
108 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
109 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
110 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
111 setOperationAction(ISD::CTTZ, MVT::i64, Expand);
112 setOperationAction(ISD::CTLZ, MVT::i32, Promote);
113 setOperationAction(ISD::CTLZ, MVT::i64, Legal);
115 // FIXME: Can we lower these 2 efficiently?
116 setOperationAction(ISD::SETCC, MVT::i32, Expand);
117 setOperationAction(ISD::SETCC, MVT::i64, Expand);
118 setOperationAction(ISD::SETCC, MVT::f32, Expand);
119 setOperationAction(ISD::SETCC, MVT::f64, Expand);
120 setOperationAction(ISD::SELECT, MVT::i32, Expand);
121 setOperationAction(ISD::SELECT, MVT::i64, Expand);
122 setOperationAction(ISD::SELECT, MVT::f32, Expand);
123 setOperationAction(ISD::SELECT, MVT::f64, Expand);
124 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
125 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
126 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
127 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
129 // Funny enough: we don't have 64-bit signed versions of these stuff, but have
131 setOperationAction(ISD::MULHS, MVT::i64, Expand);
132 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
134 // Lower some FP stuff
135 setOperationAction(ISD::FSIN, MVT::f32, Expand);
136 setOperationAction(ISD::FSIN, MVT::f64, Expand);
137 setOperationAction(ISD::FCOS, MVT::f32, Expand);
138 setOperationAction(ISD::FCOS, MVT::f64, Expand);
139 setOperationAction(ISD::FREM, MVT::f32, Expand);
140 setOperationAction(ISD::FREM, MVT::f64, Expand);
142 // We have only 64-bit bitconverts
143 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
144 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
146 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
147 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
148 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
149 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
151 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
154 SDValue SystemZTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
155 switch (Op.getOpcode()) {
156 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
157 case ISD::RET: return LowerRET(Op, DAG);
158 case ISD::CALL: return LowerCALL(Op, DAG);
159 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
160 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
161 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
162 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
163 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
165 llvm_unreachable("Should not custom lower this!");
170 //===----------------------------------------------------------------------===//
171 // Calling Convention Implementation
172 //===----------------------------------------------------------------------===//
174 #include "SystemZGenCallingConv.inc"
176 SDValue SystemZTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op,
178 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
181 llvm_unreachable("Unsupported calling convention");
183 case CallingConv::Fast:
184 return LowerCCCArguments(Op, DAG);
188 SDValue SystemZTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
189 CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
190 unsigned CallingConv = TheCall->getCallingConv();
191 switch (CallingConv) {
193 llvm_unreachable("Unsupported calling convention");
194 case CallingConv::Fast:
196 return LowerCCCCallTo(Op, DAG, CallingConv);
200 /// LowerCCCArguments - transform physical registers into virtual registers and
201 /// generate load operations for arguments places on the stack.
202 // FIXME: struct return stuff
204 SDValue SystemZTargetLowering::LowerCCCArguments(SDValue Op,
206 MachineFunction &MF = DAG.getMachineFunction();
207 MachineFrameInfo *MFI = MF.getFrameInfo();
208 MachineRegisterInfo &RegInfo = MF.getRegInfo();
209 SDValue Root = Op.getOperand(0);
210 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
211 unsigned CC = MF.getFunction()->getCallingConv();
212 DebugLoc dl = Op.getDebugLoc();
214 // Assign locations to all of the incoming arguments.
215 SmallVector<CCValAssign, 16> ArgLocs;
216 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs, DAG.getContext());
217 CCInfo.AnalyzeFormalArguments(Op.getNode(), CC_SystemZ);
220 llvm_report_error("Varargs not supported yet");
222 SmallVector<SDValue, 16> ArgValues;
223 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
225 CCValAssign &VA = ArgLocs[i];
226 MVT LocVT = VA.getLocVT();
228 // Arguments passed in registers
229 TargetRegisterClass *RC;
230 switch (LocVT.getSimpleVT()) {
233 cerr << "LowerFORMAL_ARGUMENTS Unhandled argument type: "
234 << LocVT.getSimpleVT()
239 RC = SystemZ::GR64RegisterClass;
242 RC = SystemZ::FP32RegisterClass;
245 RC = SystemZ::FP64RegisterClass;
249 unsigned VReg = RegInfo.createVirtualRegister(RC);
250 RegInfo.addLiveIn(VA.getLocReg(), VReg);
251 ArgValue = DAG.getCopyFromReg(Root, dl, VReg, LocVT);
254 assert(VA.isMemLoc());
256 // Create the nodes corresponding to a load from this parameter slot.
257 // Create the frame index object for this incoming parameter...
258 int FI = MFI->CreateFixedObject(LocVT.getSizeInBits()/8,
259 VA.getLocMemOffset());
261 // Create the SelectionDAG nodes corresponding to a load
262 // from this parameter
263 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
264 ArgValue = DAG.getLoad(LocVT, dl, Root, FIN,
265 PseudoSourceValue::getFixedStack(FI), 0);
268 // If this is an 8/16/32-bit value, it is really passed promoted to 64
269 // bits. Insert an assert[sz]ext to capture this, then truncate to the
271 if (VA.getLocInfo() == CCValAssign::SExt)
272 ArgValue = DAG.getNode(ISD::AssertSext, dl, LocVT, ArgValue,
273 DAG.getValueType(VA.getValVT()));
274 else if (VA.getLocInfo() == CCValAssign::ZExt)
275 ArgValue = DAG.getNode(ISD::AssertZext, dl, LocVT, ArgValue,
276 DAG.getValueType(VA.getValVT()));
278 if (VA.getLocInfo() != CCValAssign::Full)
279 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
281 ArgValues.push_back(ArgValue);
284 ArgValues.push_back(Root);
286 // Return the new list of results.
287 return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
288 &ArgValues[0], ArgValues.size()).getValue(Op.getResNo());
291 /// LowerCCCCallTo - functions arguments are copied from virtual regs to
292 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
294 SDValue SystemZTargetLowering::LowerCCCCallTo(SDValue Op, SelectionDAG &DAG,
296 CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
297 SDValue Chain = TheCall->getChain();
298 SDValue Callee = TheCall->getCallee();
299 bool isVarArg = TheCall->isVarArg();
300 DebugLoc dl = Op.getDebugLoc();
301 MachineFunction &MF = DAG.getMachineFunction();
303 // Offset to first argument stack slot.
304 const unsigned FirstArgOffset = 160;
306 // Analyze operands of the call, assigning locations to each operand.
307 SmallVector<CCValAssign, 16> ArgLocs;
308 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs, DAG.getContext());
310 CCInfo.AnalyzeCallOperands(TheCall, CC_SystemZ);
312 // Get a count of how many bytes are to be pushed on the stack.
313 unsigned NumBytes = CCInfo.getNextStackOffset();
315 Chain = DAG.getCALLSEQ_START(Chain ,DAG.getConstant(NumBytes,
316 getPointerTy(), true));
318 SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
319 SmallVector<SDValue, 12> MemOpChains;
322 // Walk the register/memloc assignments, inserting copies/loads.
323 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
324 CCValAssign &VA = ArgLocs[i];
326 // Arguments start after the 5 first operands of ISD::CALL
327 SDValue Arg = TheCall->getArg(i);
329 // Promote the value if needed.
330 switch (VA.getLocInfo()) {
331 default: assert(0 && "Unknown loc info!");
332 case CCValAssign::Full: break;
333 case CCValAssign::SExt:
334 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
336 case CCValAssign::ZExt:
337 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
339 case CCValAssign::AExt:
340 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
344 // Arguments that can be passed on register must be kept at RegsToPass
347 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
349 assert(VA.isMemLoc());
351 if (StackPtr.getNode() == 0)
353 DAG.getCopyFromReg(Chain, dl,
354 (RegInfo->hasFP(MF) ?
355 SystemZ::R11D : SystemZ::R15D),
358 unsigned Offset = FirstArgOffset + VA.getLocMemOffset();
359 SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(),
361 DAG.getIntPtrConstant(Offset));
363 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
364 PseudoSourceValue::getStack(), Offset));
368 // Transform all store nodes into one single node because all store nodes are
369 // independent of each other.
370 if (!MemOpChains.empty())
371 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
372 &MemOpChains[0], MemOpChains.size());
374 // Build a sequence of copy-to-reg nodes chained together with token chain and
375 // flag operands which copy the outgoing args into registers. The InFlag in
376 // necessary since all emited instructions must be stuck together.
378 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
379 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
380 RegsToPass[i].second, InFlag);
381 InFlag = Chain.getValue(1);
384 // If the callee is a GlobalAddress node (quite common, every direct call is)
385 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
386 // Likewise ExternalSymbol -> TargetExternalSymbol.
387 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
388 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
389 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
390 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), getPointerTy());
392 // Returns a chain & a flag for retval copy to use.
393 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
394 SmallVector<SDValue, 8> Ops;
395 Ops.push_back(Chain);
396 Ops.push_back(Callee);
398 // Add argument registers to the end of the list so that they are
399 // known live into the call.
400 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
401 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
402 RegsToPass[i].second.getValueType()));
404 if (InFlag.getNode())
405 Ops.push_back(InFlag);
407 Chain = DAG.getNode(SystemZISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
408 InFlag = Chain.getValue(1);
410 // Create the CALLSEQ_END node.
411 Chain = DAG.getCALLSEQ_END(Chain,
412 DAG.getConstant(NumBytes, getPointerTy(), true),
413 DAG.getConstant(0, getPointerTy(), true),
415 InFlag = Chain.getValue(1);
417 // Handle result values, copying them out of physregs into vregs that we
419 return SDValue(LowerCallResult(Chain, InFlag, TheCall, CC, DAG),
423 /// LowerCallResult - Lower the result values of an ISD::CALL into the
424 /// appropriate copies out of appropriate physical registers. This assumes that
425 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
426 /// being lowered. Returns a SDNode with the same number of values as the
429 SystemZTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
431 unsigned CallingConv,
433 bool isVarArg = TheCall->isVarArg();
434 DebugLoc dl = TheCall->getDebugLoc();
436 // Assign locations to each value returned by this call.
437 SmallVector<CCValAssign, 16> RVLocs;
438 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs,
441 CCInfo.AnalyzeCallResult(TheCall, RetCC_SystemZ);
442 SmallVector<SDValue, 8> ResultVals;
444 // Copy all of the result registers out of their specified physreg.
445 for (unsigned i = 0; i != RVLocs.size(); ++i) {
446 CCValAssign &VA = RVLocs[i];
448 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
449 VA.getLocVT(), InFlag).getValue(1);
450 SDValue RetValue = Chain.getValue(0);
451 InFlag = Chain.getValue(2);
453 // If this is an 8/16/32-bit value, it is really passed promoted to 64
454 // bits. Insert an assert[sz]ext to capture this, then truncate to the
456 if (VA.getLocInfo() == CCValAssign::SExt)
457 RetValue = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), RetValue,
458 DAG.getValueType(VA.getValVT()));
459 else if (VA.getLocInfo() == CCValAssign::ZExt)
460 RetValue = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), RetValue,
461 DAG.getValueType(VA.getValVT()));
463 if (VA.getLocInfo() != CCValAssign::Full)
464 RetValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), RetValue);
466 ResultVals.push_back(RetValue);
469 ResultVals.push_back(Chain);
471 // Merge everything together with a MERGE_VALUES node.
472 return DAG.getNode(ISD::MERGE_VALUES, dl, TheCall->getVTList(),
473 &ResultVals[0], ResultVals.size()).getNode();
477 SDValue SystemZTargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) {
478 // CCValAssign - represent the assignment of the return value to a location
479 SmallVector<CCValAssign, 16> RVLocs;
480 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
481 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
482 DebugLoc dl = Op.getDebugLoc();
484 // CCState - Info about the registers and stack slot.
485 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs, DAG.getContext());
487 // Analize return values of ISD::RET
488 CCInfo.AnalyzeReturn(Op.getNode(), RetCC_SystemZ);
490 // If this is the first return lowered for this function, add the regs to the
491 // liveout set for the function.
492 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
493 for (unsigned i = 0; i != RVLocs.size(); ++i)
494 if (RVLocs[i].isRegLoc())
495 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
498 // The chain is always operand #0
499 SDValue Chain = Op.getOperand(0);
502 // Copy the result values into the output registers.
503 for (unsigned i = 0; i != RVLocs.size(); ++i) {
504 CCValAssign &VA = RVLocs[i];
505 SDValue ResValue = Op.getOperand(i*2+1);
506 assert(VA.isRegLoc() && "Can only return in registers!");
508 // If this is an 8/16/32-bit value, it is really should be passed promoted
510 if (VA.getLocInfo() == CCValAssign::SExt)
511 ResValue = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ResValue);
512 else if (VA.getLocInfo() == CCValAssign::ZExt)
513 ResValue = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ResValue);
514 else if (VA.getLocInfo() == CCValAssign::AExt)
515 ResValue = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ResValue);
517 // ISD::RET => ret chain, (regnum1,val1), ...
518 // So i*2+1 index only the regnums
519 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ResValue, Flag);
521 // Guarantee that all emitted copies are stuck together,
522 // avoiding something bad.
523 Flag = Chain.getValue(1);
527 return DAG.getNode(SystemZISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
530 return DAG.getNode(SystemZISD::RET_FLAG, dl, MVT::Other, Chain);
533 SDValue SystemZTargetLowering::EmitCmp(SDValue LHS, SDValue RHS,
534 ISD::CondCode CC, SDValue &SystemZCC,
536 // FIXME: Emit a test if RHS is zero
538 bool isUnsigned = false;
539 SystemZCC::CondCodes TCC;
542 llvm_unreachable("Invalid integer condition!");
548 TCC = SystemZCC::NLH;
564 if (LHS.getValueType().isFloatingPoint()) {
568 isUnsigned = true; // FALLTHROUGH
574 if (LHS.getValueType().isFloatingPoint()) {
578 isUnsigned = true; // FALLTHROUGH
584 if (LHS.getValueType().isFloatingPoint()) {
585 TCC = SystemZCC::NLE;
588 isUnsigned = true; // FALLTHROUGH
594 if (LHS.getValueType().isFloatingPoint()) {
595 TCC = SystemZCC::NHE;
598 isUnsigned = true; // FALLTHROUGH
605 SystemZCC = DAG.getConstant(TCC, MVT::i32);
607 DebugLoc dl = LHS.getDebugLoc();
608 return DAG.getNode((isUnsigned ? SystemZISD::UCMP : SystemZISD::CMP),
609 dl, MVT::Flag, LHS, RHS);
613 SDValue SystemZTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) {
614 SDValue Chain = Op.getOperand(0);
615 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
616 SDValue LHS = Op.getOperand(2);
617 SDValue RHS = Op.getOperand(3);
618 SDValue Dest = Op.getOperand(4);
619 DebugLoc dl = Op.getDebugLoc();
622 SDValue Flag = EmitCmp(LHS, RHS, CC, SystemZCC, DAG);
623 return DAG.getNode(SystemZISD::BRCOND, dl, Op.getValueType(),
624 Chain, Dest, SystemZCC, Flag);
627 SDValue SystemZTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
628 SDValue LHS = Op.getOperand(0);
629 SDValue RHS = Op.getOperand(1);
630 SDValue TrueV = Op.getOperand(2);
631 SDValue FalseV = Op.getOperand(3);
632 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
633 DebugLoc dl = Op.getDebugLoc();
636 SDValue Flag = EmitCmp(LHS, RHS, CC, SystemZCC, DAG);
638 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
639 SmallVector<SDValue, 4> Ops;
640 Ops.push_back(TrueV);
641 Ops.push_back(FalseV);
642 Ops.push_back(SystemZCC);
645 return DAG.getNode(SystemZISD::SELECT, dl, VTs, &Ops[0], Ops.size());
648 SDValue SystemZTargetLowering::LowerGlobalAddress(SDValue Op,
650 DebugLoc dl = Op.getDebugLoc();
651 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
652 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
654 bool IsPic = getTargetMachine().getRelocationModel() == Reloc::PIC_;
655 bool ExtraLoadRequired =
656 Subtarget.GVRequiresExtraLoad(GV, getTargetMachine(), false);
659 if (!IsPic && !ExtraLoadRequired) {
660 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
663 unsigned char OpFlags = 0;
664 if (ExtraLoadRequired)
665 OpFlags = SystemZII::MO_GOTENT;
667 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), 0, OpFlags);
670 Result = DAG.getNode(SystemZISD::PCRelativeWrapper, dl,
671 getPointerTy(), Result);
673 if (ExtraLoadRequired)
674 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
675 PseudoSourceValue::getGOT(), 0);
677 // If there was a non-zero offset that we didn't fold, create an explicit
680 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
681 DAG.getConstant(Offset, getPointerTy()));
687 SDValue SystemZTargetLowering::LowerJumpTable(SDValue Op,
689 DebugLoc dl = Op.getDebugLoc();
690 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
691 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy());
693 return DAG.getNode(SystemZISD::PCRelativeWrapper, dl, getPointerTy(), Result);
698 // FIXME: This is just dirty hack. We need to lower cpool properly
699 SDValue SystemZTargetLowering::LowerConstantPool(SDValue Op,
701 DebugLoc dl = Op.getDebugLoc();
702 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
704 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
708 return DAG.getNode(SystemZISD::PCRelativeWrapper, dl, getPointerTy(), Result);
711 const char *SystemZTargetLowering::getTargetNodeName(unsigned Opcode) const {
713 case SystemZISD::RET_FLAG: return "SystemZISD::RET_FLAG";
714 case SystemZISD::CALL: return "SystemZISD::CALL";
715 case SystemZISD::BRCOND: return "SystemZISD::BRCOND";
716 case SystemZISD::CMP: return "SystemZISD::CMP";
717 case SystemZISD::UCMP: return "SystemZISD::UCMP";
718 case SystemZISD::SELECT: return "SystemZISD::SELECT";
719 case SystemZISD::PCRelativeWrapper: return "SystemZISD::PCRelativeWrapper";
720 default: return NULL;
724 //===----------------------------------------------------------------------===//
725 // Other Lowering Code
726 //===----------------------------------------------------------------------===//
729 SystemZTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
730 MachineBasicBlock *BB) const {
731 const SystemZInstrInfo &TII = *TM.getInstrInfo();
732 DebugLoc dl = MI->getDebugLoc();
733 assert((MI->getOpcode() == SystemZ::Select32 ||
734 MI->getOpcode() == SystemZ::SelectF32 ||
735 MI->getOpcode() == SystemZ::Select64 ||
736 MI->getOpcode() == SystemZ::SelectF64) &&
737 "Unexpected instr type to insert");
739 // To "insert" a SELECT instruction, we actually have to insert the diamond
740 // control-flow pattern. The incoming instruction knows the destination vreg
741 // to set, the condition code register to branch on, the true/false values to
742 // select between, and a branch opcode to use.
743 const BasicBlock *LLVM_BB = BB->getBasicBlock();
744 MachineFunction::iterator I = BB;
752 // fallthrough --> copy0MBB
753 MachineBasicBlock *thisMBB = BB;
754 MachineFunction *F = BB->getParent();
755 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
756 MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
757 SystemZCC::CondCodes CC = (SystemZCC::CondCodes)MI->getOperand(3).getImm();
758 BuildMI(BB, dl, TII.getBrCond(CC)).addMBB(copy1MBB);
759 F->insert(I, copy0MBB);
760 F->insert(I, copy1MBB);
761 // Update machine-CFG edges by transferring all successors of the current
762 // block to the new block which will contain the Phi node for the select.
763 copy1MBB->transferSuccessors(BB);
764 // Next, add the true and fallthrough blocks as its successors.
765 BB->addSuccessor(copy0MBB);
766 BB->addSuccessor(copy1MBB);
770 // # fallthrough to copy1MBB
773 // Update machine-CFG edges
774 BB->addSuccessor(copy1MBB);
777 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
780 BuildMI(BB, dl, TII.get(SystemZ::PHI),
781 MI->getOperand(0).getReg())
782 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
783 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
785 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.