1 //===-- SystemZISelLowering.cpp - SystemZ DAG lowering implementation -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SystemZTargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "SystemZISelLowering.h"
15 #include "SystemZCallingConv.h"
16 #include "SystemZConstantPoolValue.h"
17 #include "SystemZMachineFunctionInfo.h"
18 #include "SystemZTargetMachine.h"
19 #include "llvm/CodeGen/CallingConvLower.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
23 #include "llvm/IR/Intrinsics.h"
28 #define DEBUG_TYPE "systemz-lower"
31 // Represents a sequence for extracting a 0/1 value from an IPM result:
32 // (((X ^ XORValue) + AddValue) >> Bit)
33 struct IPMConversion {
34 IPMConversion(unsigned xorValue, int64_t addValue, unsigned bit)
35 : XORValue(xorValue), AddValue(addValue), Bit(bit) {}
42 // Represents information about a comparison.
44 Comparison(SDValue Op0In, SDValue Op1In)
45 : Op0(Op0In), Op1(Op1In), Opcode(0), ICmpType(0), CCValid(0), CCMask(0) {}
47 // The operands to the comparison.
50 // The opcode that should be used to compare Op0 and Op1.
53 // A SystemZICMP value. Only used for integer comparisons.
56 // The mask of CC values that Opcode can produce.
59 // The mask of CC values for which the original condition is true.
62 } // end anonymous namespace
64 // Classify VT as either 32 or 64 bit.
65 static bool is32Bit(EVT VT) {
66 switch (VT.getSimpleVT().SimpleTy) {
72 llvm_unreachable("Unsupported type");
76 // Return a version of MachineOperand that can be safely used before the
78 static MachineOperand earlyUseOperand(MachineOperand Op) {
84 SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &tm,
85 const SystemZSubtarget &STI)
86 : TargetLowering(tm), Subtarget(STI) {
87 MVT PtrVT = getPointerTy();
89 // Set up the register classes.
90 if (Subtarget.hasHighWord())
91 addRegisterClass(MVT::i32, &SystemZ::GRX32BitRegClass);
93 addRegisterClass(MVT::i32, &SystemZ::GR32BitRegClass);
94 addRegisterClass(MVT::i64, &SystemZ::GR64BitRegClass);
95 if (Subtarget.hasVector()) {
96 addRegisterClass(MVT::f32, &SystemZ::VR32BitRegClass);
97 addRegisterClass(MVT::f64, &SystemZ::VR64BitRegClass);
99 addRegisterClass(MVT::f32, &SystemZ::FP32BitRegClass);
100 addRegisterClass(MVT::f64, &SystemZ::FP64BitRegClass);
102 addRegisterClass(MVT::f128, &SystemZ::FP128BitRegClass);
104 if (Subtarget.hasVector()) {
105 addRegisterClass(MVT::v16i8, &SystemZ::VR128BitRegClass);
106 addRegisterClass(MVT::v8i16, &SystemZ::VR128BitRegClass);
107 addRegisterClass(MVT::v4i32, &SystemZ::VR128BitRegClass);
108 addRegisterClass(MVT::v2i64, &SystemZ::VR128BitRegClass);
109 addRegisterClass(MVT::v4f32, &SystemZ::VR128BitRegClass);
110 addRegisterClass(MVT::v2f64, &SystemZ::VR128BitRegClass);
113 // Compute derived properties from the register classes
114 computeRegisterProperties(Subtarget.getRegisterInfo());
116 // Set up special registers.
117 setExceptionPointerRegister(SystemZ::R6D);
118 setExceptionSelectorRegister(SystemZ::R7D);
119 setStackPointerRegisterToSaveRestore(SystemZ::R15D);
121 // TODO: It may be better to default to latency-oriented scheduling, however
122 // LLVM's current latency-oriented scheduler can't handle physreg definitions
123 // such as SystemZ has with CC, so set this to the register-pressure
124 // scheduler, because it can.
125 setSchedulingPreference(Sched::RegPressure);
127 setBooleanContents(ZeroOrOneBooleanContent);
128 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
130 // Instructions are strings of 2-byte aligned 2-byte values.
131 setMinFunctionAlignment(2);
133 // Handle operations that are handled in a similar way for all types.
134 for (unsigned I = MVT::FIRST_INTEGER_VALUETYPE;
135 I <= MVT::LAST_FP_VALUETYPE;
137 MVT VT = MVT::SimpleValueType(I);
138 if (isTypeLegal(VT)) {
139 // Lower SET_CC into an IPM-based sequence.
140 setOperationAction(ISD::SETCC, VT, Custom);
142 // Expand SELECT(C, A, B) into SELECT_CC(X, 0, A, B, NE).
143 setOperationAction(ISD::SELECT, VT, Expand);
145 // Lower SELECT_CC and BR_CC into separate comparisons and branches.
146 setOperationAction(ISD::SELECT_CC, VT, Custom);
147 setOperationAction(ISD::BR_CC, VT, Custom);
151 // Expand jump table branches as address arithmetic followed by an
153 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
155 // Expand BRCOND into a BR_CC (see above).
156 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
158 // Handle integer types.
159 for (unsigned I = MVT::FIRST_INTEGER_VALUETYPE;
160 I <= MVT::LAST_INTEGER_VALUETYPE;
162 MVT VT = MVT::SimpleValueType(I);
163 if (isTypeLegal(VT)) {
164 // Expand individual DIV and REMs into DIVREMs.
165 setOperationAction(ISD::SDIV, VT, Expand);
166 setOperationAction(ISD::UDIV, VT, Expand);
167 setOperationAction(ISD::SREM, VT, Expand);
168 setOperationAction(ISD::UREM, VT, Expand);
169 setOperationAction(ISD::SDIVREM, VT, Custom);
170 setOperationAction(ISD::UDIVREM, VT, Custom);
172 // Lower ATOMIC_LOAD and ATOMIC_STORE into normal volatile loads and
173 // stores, putting a serialization instruction after the stores.
174 setOperationAction(ISD::ATOMIC_LOAD, VT, Custom);
175 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
177 // Lower ATOMIC_LOAD_SUB into ATOMIC_LOAD_ADD if LAA and LAAG are
178 // available, or if the operand is constant.
179 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
181 // Use POPCNT on z196 and above.
182 if (Subtarget.hasPopulationCount())
183 setOperationAction(ISD::CTPOP, VT, Custom);
185 setOperationAction(ISD::CTPOP, VT, Expand);
187 // No special instructions for these.
188 setOperationAction(ISD::CTTZ, VT, Expand);
189 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
190 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
191 setOperationAction(ISD::ROTR, VT, Expand);
193 // Use *MUL_LOHI where possible instead of MULH*.
194 setOperationAction(ISD::MULHS, VT, Expand);
195 setOperationAction(ISD::MULHU, VT, Expand);
196 setOperationAction(ISD::SMUL_LOHI, VT, Custom);
197 setOperationAction(ISD::UMUL_LOHI, VT, Custom);
199 // Only z196 and above have native support for conversions to unsigned.
200 if (!Subtarget.hasFPExtension())
201 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
205 // Type legalization will convert 8- and 16-bit atomic operations into
206 // forms that operate on i32s (but still keeping the original memory VT).
207 // Lower them into full i32 operations.
208 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Custom);
209 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Custom);
210 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom);
211 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Custom);
212 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Custom);
213 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Custom);
214 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Custom);
215 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Custom);
216 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Custom);
217 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Custom);
218 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Custom);
219 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
221 // z10 has instructions for signed but not unsigned FP conversion.
222 // Handle unsigned 32-bit types as signed 64-bit types.
223 if (!Subtarget.hasFPExtension()) {
224 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Promote);
225 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
228 // We have native support for a 64-bit CTLZ, via FLOGR.
229 setOperationAction(ISD::CTLZ, MVT::i32, Promote);
230 setOperationAction(ISD::CTLZ, MVT::i64, Legal);
232 // Give LowerOperation the chance to replace 64-bit ORs with subregs.
233 setOperationAction(ISD::OR, MVT::i64, Custom);
235 // FIXME: Can we support these natively?
236 setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand);
237 setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
238 setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand);
240 // We have native instructions for i8, i16 and i32 extensions, but not i1.
241 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
242 for (MVT VT : MVT::integer_valuetypes()) {
243 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
244 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
245 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
248 // Handle the various types of symbolic address.
249 setOperationAction(ISD::ConstantPool, PtrVT, Custom);
250 setOperationAction(ISD::GlobalAddress, PtrVT, Custom);
251 setOperationAction(ISD::GlobalTLSAddress, PtrVT, Custom);
252 setOperationAction(ISD::BlockAddress, PtrVT, Custom);
253 setOperationAction(ISD::JumpTable, PtrVT, Custom);
255 // We need to handle dynamic allocations specially because of the
256 // 160-byte area at the bottom of the stack.
257 setOperationAction(ISD::DYNAMIC_STACKALLOC, PtrVT, Custom);
259 // Use custom expanders so that we can force the function to use
261 setOperationAction(ISD::STACKSAVE, MVT::Other, Custom);
262 setOperationAction(ISD::STACKRESTORE, MVT::Other, Custom);
264 // Handle prefetches with PFD or PFDRL.
265 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
267 for (MVT VT : MVT::vector_valuetypes()) {
268 // Assume by default that all vector operations need to be expanded.
269 for (unsigned Opcode = 0; Opcode < ISD::BUILTIN_OP_END; ++Opcode)
270 if (getOperationAction(Opcode, VT) == Legal)
271 setOperationAction(Opcode, VT, Expand);
273 // Likewise all truncating stores and extending loads.
274 for (MVT InnerVT : MVT::vector_valuetypes()) {
275 setTruncStoreAction(VT, InnerVT, Expand);
276 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
277 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
278 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
281 if (isTypeLegal(VT)) {
282 // These operations are legal for anything that can be stored in a
283 // vector register, even if there is no native support for the format
284 // as such. In particular, we can do these for v4f32 even though there
285 // are no specific instructions for that format.
286 setOperationAction(ISD::LOAD, VT, Legal);
287 setOperationAction(ISD::STORE, VT, Legal);
288 setOperationAction(ISD::VSELECT, VT, Legal);
289 setOperationAction(ISD::BITCAST, VT, Legal);
290 setOperationAction(ISD::UNDEF, VT, Legal);
292 // Likewise, except that we need to replace the nodes with something
294 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
295 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
299 // Handle integer vector types.
300 for (MVT VT : MVT::integer_vector_valuetypes()) {
301 if (isTypeLegal(VT)) {
302 // These operations have direct equivalents.
303 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Legal);
304 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Legal);
305 setOperationAction(ISD::ADD, VT, Legal);
306 setOperationAction(ISD::SUB, VT, Legal);
307 if (VT != MVT::v2i64)
308 setOperationAction(ISD::MUL, VT, Legal);
309 setOperationAction(ISD::AND, VT, Legal);
310 setOperationAction(ISD::OR, VT, Legal);
311 setOperationAction(ISD::XOR, VT, Legal);
312 setOperationAction(ISD::CTPOP, VT, Custom);
313 setOperationAction(ISD::CTTZ, VT, Legal);
314 setOperationAction(ISD::CTLZ, VT, Legal);
315 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Custom);
316 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Custom);
318 // Convert a GPR scalar to a vector by inserting it into element 0.
319 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
321 // Use a series of unpacks for extensions.
322 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Custom);
323 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Custom);
325 // Detect shifts by a scalar amount and convert them into
327 setOperationAction(ISD::SHL, VT, Custom);
328 setOperationAction(ISD::SRA, VT, Custom);
329 setOperationAction(ISD::SRL, VT, Custom);
331 // At present ROTL isn't matched by DAGCombiner. ROTR should be
332 // converted into ROTL.
333 setOperationAction(ISD::ROTL, VT, Expand);
334 setOperationAction(ISD::ROTR, VT, Expand);
336 // Map SETCCs onto one of VCE, VCH or VCHL, swapping the operands
337 // and inverting the result as necessary.
338 setOperationAction(ISD::SETCC, VT, Custom);
342 if (Subtarget.hasVector()) {
343 // There should be no need to check for float types other than v2f64
344 // since <2 x f32> isn't a legal type.
345 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
346 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
347 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
348 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
351 // Handle floating-point types.
352 for (unsigned I = MVT::FIRST_FP_VALUETYPE;
353 I <= MVT::LAST_FP_VALUETYPE;
355 MVT VT = MVT::SimpleValueType(I);
356 if (isTypeLegal(VT)) {
357 // We can use FI for FRINT.
358 setOperationAction(ISD::FRINT, VT, Legal);
360 // We can use the extended form of FI for other rounding operations.
361 if (Subtarget.hasFPExtension()) {
362 setOperationAction(ISD::FNEARBYINT, VT, Legal);
363 setOperationAction(ISD::FFLOOR, VT, Legal);
364 setOperationAction(ISD::FCEIL, VT, Legal);
365 setOperationAction(ISD::FTRUNC, VT, Legal);
366 setOperationAction(ISD::FROUND, VT, Legal);
369 // No special instructions for these.
370 setOperationAction(ISD::FSIN, VT, Expand);
371 setOperationAction(ISD::FCOS, VT, Expand);
372 setOperationAction(ISD::FREM, VT, Expand);
376 // Handle floating-point vector types.
377 if (Subtarget.hasVector()) {
378 // Scalar-to-vector conversion is just a subreg.
379 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal);
380 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
382 // Some insertions and extractions can be done directly but others
383 // need to go via integers.
384 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
385 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
386 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
387 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
389 // These operations have direct equivalents.
390 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
391 setOperationAction(ISD::FNEG, MVT::v2f64, Legal);
392 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
393 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
394 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
395 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
396 setOperationAction(ISD::FABS, MVT::v2f64, Legal);
397 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
398 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
399 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
400 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
401 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
402 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
403 setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
406 // We have fused multiply-addition for f32 and f64 but not f128.
407 setOperationAction(ISD::FMA, MVT::f32, Legal);
408 setOperationAction(ISD::FMA, MVT::f64, Legal);
409 setOperationAction(ISD::FMA, MVT::f128, Expand);
411 // Needed so that we don't try to implement f128 constant loads using
412 // a load-and-extend of a f80 constant (in cases where the constant
413 // would fit in an f80).
414 for (MVT VT : MVT::fp_valuetypes())
415 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f80, Expand);
417 // Floating-point truncation and stores need to be done separately.
418 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
419 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
420 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
422 // We have 64-bit FPR<->GPR moves, but need special handling for
424 if (!Subtarget.hasVector()) {
425 setOperationAction(ISD::BITCAST, MVT::i32, Custom);
426 setOperationAction(ISD::BITCAST, MVT::f32, Custom);
429 // VASTART and VACOPY need to deal with the SystemZ-specific varargs
430 // structure, but VAEND is a no-op.
431 setOperationAction(ISD::VASTART, MVT::Other, Custom);
432 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
433 setOperationAction(ISD::VAEND, MVT::Other, Expand);
435 // Codes for which we want to perform some z-specific combinations.
436 setTargetDAGCombine(ISD::SIGN_EXTEND);
437 setTargetDAGCombine(ISD::STORE);
438 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
439 setTargetDAGCombine(ISD::FP_ROUND);
441 // Handle intrinsics.
442 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
443 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
445 // We want to use MVC in preference to even a single load/store pair.
446 MaxStoresPerMemcpy = 0;
447 MaxStoresPerMemcpyOptSize = 0;
449 // The main memset sequence is a byte store followed by an MVC.
450 // Two STC or MV..I stores win over that, but the kind of fused stores
451 // generated by target-independent code don't when the byte value is
452 // variable. E.g. "STC <reg>;MHI <reg>,257;STH <reg>" is not better
453 // than "STC;MVC". Handle the choice in target-specific code instead.
454 MaxStoresPerMemset = 0;
455 MaxStoresPerMemsetOptSize = 0;
458 EVT SystemZTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
461 return VT.changeVectorElementTypeToInteger();
464 bool SystemZTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
465 VT = VT.getScalarType();
470 switch (VT.getSimpleVT().SimpleTy) {
483 bool SystemZTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
484 // We can load zero using LZ?R and negative zero using LZ?R;LC?BR.
485 return Imm.isZero() || Imm.isNegZero();
488 bool SystemZTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
489 // We can use CGFI or CLGFI.
490 return isInt<32>(Imm) || isUInt<32>(Imm);
493 bool SystemZTargetLowering::isLegalAddImmediate(int64_t Imm) const {
494 // We can use ALGFI or SLGFI.
495 return isUInt<32>(Imm) || isUInt<32>(-Imm);
498 bool SystemZTargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
502 // Unaligned accesses should never be slower than the expanded version.
503 // We check specifically for aligned accesses in the few cases where
504 // they are required.
510 bool SystemZTargetLowering::isLegalAddressingMode(const AddrMode &AM,
513 // Punt on globals for now, although they can be used in limited
514 // RELATIVE LONG cases.
518 // Require a 20-bit signed offset.
519 if (!isInt<20>(AM.BaseOffs))
522 // Indexing is OK but no scale factor can be applied.
523 return AM.Scale == 0 || AM.Scale == 1;
526 bool SystemZTargetLowering::isTruncateFree(Type *FromType, Type *ToType) const {
527 if (!FromType->isIntegerTy() || !ToType->isIntegerTy())
529 unsigned FromBits = FromType->getPrimitiveSizeInBits();
530 unsigned ToBits = ToType->getPrimitiveSizeInBits();
531 return FromBits > ToBits;
534 bool SystemZTargetLowering::isTruncateFree(EVT FromVT, EVT ToVT) const {
535 if (!FromVT.isInteger() || !ToVT.isInteger())
537 unsigned FromBits = FromVT.getSizeInBits();
538 unsigned ToBits = ToVT.getSizeInBits();
539 return FromBits > ToBits;
542 //===----------------------------------------------------------------------===//
543 // Inline asm support
544 //===----------------------------------------------------------------------===//
546 TargetLowering::ConstraintType
547 SystemZTargetLowering::getConstraintType(const std::string &Constraint) const {
548 if (Constraint.size() == 1) {
549 switch (Constraint[0]) {
550 case 'a': // Address register
551 case 'd': // Data register (equivalent to 'r')
552 case 'f': // Floating-point register
553 case 'h': // High-part register
554 case 'r': // General-purpose register
555 return C_RegisterClass;
557 case 'Q': // Memory with base and unsigned 12-bit displacement
558 case 'R': // Likewise, plus an index
559 case 'S': // Memory with base and signed 20-bit displacement
560 case 'T': // Likewise, plus an index
561 case 'm': // Equivalent to 'T'.
564 case 'I': // Unsigned 8-bit constant
565 case 'J': // Unsigned 12-bit constant
566 case 'K': // Signed 16-bit constant
567 case 'L': // Signed 20-bit displacement (on all targets we support)
568 case 'M': // 0x7fffffff
575 return TargetLowering::getConstraintType(Constraint);
578 TargetLowering::ConstraintWeight SystemZTargetLowering::
579 getSingleConstraintMatchWeight(AsmOperandInfo &info,
580 const char *constraint) const {
581 ConstraintWeight weight = CW_Invalid;
582 Value *CallOperandVal = info.CallOperandVal;
583 // If we don't have a value, we can't do a match,
584 // but allow it at the lowest weight.
587 Type *type = CallOperandVal->getType();
588 // Look at the constraint type.
589 switch (*constraint) {
591 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
594 case 'a': // Address register
595 case 'd': // Data register (equivalent to 'r')
596 case 'h': // High-part register
597 case 'r': // General-purpose register
598 if (CallOperandVal->getType()->isIntegerTy())
599 weight = CW_Register;
602 case 'f': // Floating-point register
603 if (type->isFloatingPointTy())
604 weight = CW_Register;
607 case 'I': // Unsigned 8-bit constant
608 if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
609 if (isUInt<8>(C->getZExtValue()))
610 weight = CW_Constant;
613 case 'J': // Unsigned 12-bit constant
614 if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
615 if (isUInt<12>(C->getZExtValue()))
616 weight = CW_Constant;
619 case 'K': // Signed 16-bit constant
620 if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
621 if (isInt<16>(C->getSExtValue()))
622 weight = CW_Constant;
625 case 'L': // Signed 20-bit displacement (on all targets we support)
626 if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
627 if (isInt<20>(C->getSExtValue()))
628 weight = CW_Constant;
631 case 'M': // 0x7fffffff
632 if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
633 if (C->getZExtValue() == 0x7fffffff)
634 weight = CW_Constant;
640 // Parse a "{tNNN}" register constraint for which the register type "t"
641 // has already been verified. MC is the class associated with "t" and
642 // Map maps 0-based register numbers to LLVM register numbers.
643 static std::pair<unsigned, const TargetRegisterClass *>
644 parseRegisterNumber(const std::string &Constraint,
645 const TargetRegisterClass *RC, const unsigned *Map) {
646 assert(*(Constraint.end()-1) == '}' && "Missing '}'");
647 if (isdigit(Constraint[2])) {
648 std::string Suffix(Constraint.data() + 2, Constraint.size() - 2);
649 unsigned Index = atoi(Suffix.c_str());
650 if (Index < 16 && Map[Index])
651 return std::make_pair(Map[Index], RC);
653 return std::make_pair(0U, nullptr);
656 std::pair<unsigned, const TargetRegisterClass *>
657 SystemZTargetLowering::getRegForInlineAsmConstraint(
658 const TargetRegisterInfo *TRI, const std::string &Constraint,
660 if (Constraint.size() == 1) {
661 // GCC Constraint Letters
662 switch (Constraint[0]) {
664 case 'd': // Data register (equivalent to 'r')
665 case 'r': // General-purpose register
667 return std::make_pair(0U, &SystemZ::GR64BitRegClass);
668 else if (VT == MVT::i128)
669 return std::make_pair(0U, &SystemZ::GR128BitRegClass);
670 return std::make_pair(0U, &SystemZ::GR32BitRegClass);
672 case 'a': // Address register
674 return std::make_pair(0U, &SystemZ::ADDR64BitRegClass);
675 else if (VT == MVT::i128)
676 return std::make_pair(0U, &SystemZ::ADDR128BitRegClass);
677 return std::make_pair(0U, &SystemZ::ADDR32BitRegClass);
679 case 'h': // High-part register (an LLVM extension)
680 return std::make_pair(0U, &SystemZ::GRH32BitRegClass);
682 case 'f': // Floating-point register
684 return std::make_pair(0U, &SystemZ::FP64BitRegClass);
685 else if (VT == MVT::f128)
686 return std::make_pair(0U, &SystemZ::FP128BitRegClass);
687 return std::make_pair(0U, &SystemZ::FP32BitRegClass);
690 if (Constraint[0] == '{') {
691 // We need to override the default register parsing for GPRs and FPRs
692 // because the interpretation depends on VT. The internal names of
693 // the registers are also different from the external names
694 // (F0D and F0S instead of F0, etc.).
695 if (Constraint[1] == 'r') {
697 return parseRegisterNumber(Constraint, &SystemZ::GR32BitRegClass,
698 SystemZMC::GR32Regs);
700 return parseRegisterNumber(Constraint, &SystemZ::GR128BitRegClass,
701 SystemZMC::GR128Regs);
702 return parseRegisterNumber(Constraint, &SystemZ::GR64BitRegClass,
703 SystemZMC::GR64Regs);
705 if (Constraint[1] == 'f') {
707 return parseRegisterNumber(Constraint, &SystemZ::FP32BitRegClass,
708 SystemZMC::FP32Regs);
710 return parseRegisterNumber(Constraint, &SystemZ::FP128BitRegClass,
711 SystemZMC::FP128Regs);
712 return parseRegisterNumber(Constraint, &SystemZ::FP64BitRegClass,
713 SystemZMC::FP64Regs);
716 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
719 void SystemZTargetLowering::
720 LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
721 std::vector<SDValue> &Ops,
722 SelectionDAG &DAG) const {
723 // Only support length 1 constraints for now.
724 if (Constraint.length() == 1) {
725 switch (Constraint[0]) {
726 case 'I': // Unsigned 8-bit constant
727 if (auto *C = dyn_cast<ConstantSDNode>(Op))
728 if (isUInt<8>(C->getZExtValue()))
729 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
733 case 'J': // Unsigned 12-bit constant
734 if (auto *C = dyn_cast<ConstantSDNode>(Op))
735 if (isUInt<12>(C->getZExtValue()))
736 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
740 case 'K': // Signed 16-bit constant
741 if (auto *C = dyn_cast<ConstantSDNode>(Op))
742 if (isInt<16>(C->getSExtValue()))
743 Ops.push_back(DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
747 case 'L': // Signed 20-bit displacement (on all targets we support)
748 if (auto *C = dyn_cast<ConstantSDNode>(Op))
749 if (isInt<20>(C->getSExtValue()))
750 Ops.push_back(DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
754 case 'M': // 0x7fffffff
755 if (auto *C = dyn_cast<ConstantSDNode>(Op))
756 if (C->getZExtValue() == 0x7fffffff)
757 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
762 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
765 //===----------------------------------------------------------------------===//
766 // Calling conventions
767 //===----------------------------------------------------------------------===//
769 #include "SystemZGenCallingConv.inc"
771 bool SystemZTargetLowering::allowTruncateForTailCall(Type *FromType,
772 Type *ToType) const {
773 return isTruncateFree(FromType, ToType);
776 bool SystemZTargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
777 if (!CI->isTailCall())
782 // We do not yet support 128-bit single-element vector types. If the user
783 // attempts to use such types as function argument or return type, prefer
784 // to error out instead of emitting code violating the ABI.
785 static void VerifyVectorType(MVT VT, EVT ArgVT) {
786 if (ArgVT.isVector() && !VT.isVector())
787 report_fatal_error("Unsupported vector argument or return type");
790 static void VerifyVectorTypes(const SmallVectorImpl<ISD::InputArg> &Ins) {
791 for (unsigned i = 0; i < Ins.size(); ++i)
792 VerifyVectorType(Ins[i].VT, Ins[i].ArgVT);
795 static void VerifyVectorTypes(const SmallVectorImpl<ISD::OutputArg> &Outs) {
796 for (unsigned i = 0; i < Outs.size(); ++i)
797 VerifyVectorType(Outs[i].VT, Outs[i].ArgVT);
800 // Value is a value that has been passed to us in the location described by VA
801 // (and so has type VA.getLocVT()). Convert Value to VA.getValVT(), chaining
802 // any loads onto Chain.
803 static SDValue convertLocVTToValVT(SelectionDAG &DAG, SDLoc DL,
804 CCValAssign &VA, SDValue Chain,
806 // If the argument has been promoted from a smaller type, insert an
807 // assertion to capture this.
808 if (VA.getLocInfo() == CCValAssign::SExt)
809 Value = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Value,
810 DAG.getValueType(VA.getValVT()));
811 else if (VA.getLocInfo() == CCValAssign::ZExt)
812 Value = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Value,
813 DAG.getValueType(VA.getValVT()));
816 Value = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Value);
817 else if (VA.getLocInfo() == CCValAssign::Indirect)
818 Value = DAG.getLoad(VA.getValVT(), DL, Chain, Value,
819 MachinePointerInfo(), false, false, false, 0);
820 else if (VA.getLocInfo() == CCValAssign::BCvt) {
821 // If this is a short vector argument loaded from the stack,
822 // extend from i64 to full vector size and then bitcast.
823 assert(VA.getLocVT() == MVT::i64);
824 assert(VA.getValVT().isVector());
825 Value = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v2i64,
826 Value, DAG.getUNDEF(MVT::i64));
827 Value = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Value);
829 assert(VA.getLocInfo() == CCValAssign::Full && "Unsupported getLocInfo");
833 // Value is a value of type VA.getValVT() that we need to copy into
834 // the location described by VA. Return a copy of Value converted to
835 // VA.getValVT(). The caller is responsible for handling indirect values.
836 static SDValue convertValVTToLocVT(SelectionDAG &DAG, SDLoc DL,
837 CCValAssign &VA, SDValue Value) {
838 switch (VA.getLocInfo()) {
839 case CCValAssign::SExt:
840 return DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Value);
841 case CCValAssign::ZExt:
842 return DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Value);
843 case CCValAssign::AExt:
844 return DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Value);
845 case CCValAssign::BCvt:
846 // If this is a short vector argument to be stored to the stack,
847 // bitcast to v2i64 and then extract first element.
848 assert(VA.getLocVT() == MVT::i64);
849 assert(VA.getValVT().isVector());
850 Value = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Value);
851 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VA.getLocVT(), Value,
852 DAG.getConstant(0, DL, MVT::i32));
853 case CCValAssign::Full:
856 llvm_unreachable("Unhandled getLocInfo()");
860 SDValue SystemZTargetLowering::
861 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
862 const SmallVectorImpl<ISD::InputArg> &Ins,
863 SDLoc DL, SelectionDAG &DAG,
864 SmallVectorImpl<SDValue> &InVals) const {
865 MachineFunction &MF = DAG.getMachineFunction();
866 MachineFrameInfo *MFI = MF.getFrameInfo();
867 MachineRegisterInfo &MRI = MF.getRegInfo();
868 SystemZMachineFunctionInfo *FuncInfo =
869 MF.getInfo<SystemZMachineFunctionInfo>();
871 static_cast<const SystemZFrameLowering *>(Subtarget.getFrameLowering());
873 // Detect unsupported vector argument types.
874 if (Subtarget.hasVector())
875 VerifyVectorTypes(Ins);
877 // Assign locations to all of the incoming arguments.
878 SmallVector<CCValAssign, 16> ArgLocs;
879 SystemZCCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
880 CCInfo.AnalyzeFormalArguments(Ins, CC_SystemZ);
882 unsigned NumFixedGPRs = 0;
883 unsigned NumFixedFPRs = 0;
884 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
886 CCValAssign &VA = ArgLocs[I];
887 EVT LocVT = VA.getLocVT();
889 // Arguments passed in registers
890 const TargetRegisterClass *RC;
891 switch (LocVT.getSimpleVT().SimpleTy) {
893 // Integers smaller than i64 should be promoted to i64.
894 llvm_unreachable("Unexpected argument type");
897 RC = &SystemZ::GR32BitRegClass;
901 RC = &SystemZ::GR64BitRegClass;
905 RC = &SystemZ::FP32BitRegClass;
909 RC = &SystemZ::FP64BitRegClass;
917 RC = &SystemZ::VR128BitRegClass;
921 unsigned VReg = MRI.createVirtualRegister(RC);
922 MRI.addLiveIn(VA.getLocReg(), VReg);
923 ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, LocVT);
925 assert(VA.isMemLoc() && "Argument not register or memory");
927 // Create the frame index object for this incoming parameter.
928 int FI = MFI->CreateFixedObject(LocVT.getSizeInBits() / 8,
929 VA.getLocMemOffset(), true);
931 // Create the SelectionDAG nodes corresponding to a load
932 // from this parameter. Unpromoted ints and floats are
933 // passed as right-justified 8-byte values.
934 EVT PtrVT = getPointerTy();
935 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
936 if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32)
937 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN,
938 DAG.getIntPtrConstant(4, DL));
939 ArgValue = DAG.getLoad(LocVT, DL, Chain, FIN,
940 MachinePointerInfo::getFixedStack(FI),
941 false, false, false, 0);
944 // Convert the value of the argument register into the value that's
946 InVals.push_back(convertLocVTToValVT(DAG, DL, VA, Chain, ArgValue));
950 // Save the number of non-varargs registers for later use by va_start, etc.
951 FuncInfo->setVarArgsFirstGPR(NumFixedGPRs);
952 FuncInfo->setVarArgsFirstFPR(NumFixedFPRs);
954 // Likewise the address (in the form of a frame index) of where the
955 // first stack vararg would be. The 1-byte size here is arbitrary.
956 int64_t StackSize = CCInfo.getNextStackOffset();
957 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize, true));
959 // ...and a similar frame index for the caller-allocated save area
960 // that will be used to store the incoming registers.
961 int64_t RegSaveOffset = TFL->getOffsetOfLocalArea();
962 unsigned RegSaveIndex = MFI->CreateFixedObject(1, RegSaveOffset, true);
963 FuncInfo->setRegSaveFrameIndex(RegSaveIndex);
965 // Store the FPR varargs in the reserved frame slots. (We store the
966 // GPRs as part of the prologue.)
967 if (NumFixedFPRs < SystemZ::NumArgFPRs) {
968 SDValue MemOps[SystemZ::NumArgFPRs];
969 for (unsigned I = NumFixedFPRs; I < SystemZ::NumArgFPRs; ++I) {
970 unsigned Offset = TFL->getRegSpillOffset(SystemZ::ArgFPRs[I]);
971 int FI = MFI->CreateFixedObject(8, RegSaveOffset + Offset, true);
972 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
973 unsigned VReg = MF.addLiveIn(SystemZ::ArgFPRs[I],
974 &SystemZ::FP64BitRegClass);
975 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f64);
976 MemOps[I] = DAG.getStore(ArgValue.getValue(1), DL, ArgValue, FIN,
977 MachinePointerInfo::getFixedStack(FI),
981 // Join the stores, which are independent of one another.
982 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
983 makeArrayRef(&MemOps[NumFixedFPRs],
984 SystemZ::NumArgFPRs-NumFixedFPRs));
991 static bool canUseSiblingCall(const CCState &ArgCCInfo,
992 SmallVectorImpl<CCValAssign> &ArgLocs) {
993 // Punt if there are any indirect or stack arguments, or if the call
994 // needs the call-saved argument register R6.
995 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
996 CCValAssign &VA = ArgLocs[I];
997 if (VA.getLocInfo() == CCValAssign::Indirect)
1001 unsigned Reg = VA.getLocReg();
1002 if (Reg == SystemZ::R6H || Reg == SystemZ::R6L || Reg == SystemZ::R6D)
1009 SystemZTargetLowering::LowerCall(CallLoweringInfo &CLI,
1010 SmallVectorImpl<SDValue> &InVals) const {
1011 SelectionDAG &DAG = CLI.DAG;
1013 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
1014 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1015 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
1016 SDValue Chain = CLI.Chain;
1017 SDValue Callee = CLI.Callee;
1018 bool &IsTailCall = CLI.IsTailCall;
1019 CallingConv::ID CallConv = CLI.CallConv;
1020 bool IsVarArg = CLI.IsVarArg;
1021 MachineFunction &MF = DAG.getMachineFunction();
1022 EVT PtrVT = getPointerTy();
1024 // Detect unsupported vector argument and return types.
1025 if (Subtarget.hasVector()) {
1026 VerifyVectorTypes(Outs);
1027 VerifyVectorTypes(Ins);
1030 // Analyze the operands of the call, assigning locations to each operand.
1031 SmallVector<CCValAssign, 16> ArgLocs;
1032 SystemZCCState ArgCCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
1033 ArgCCInfo.AnalyzeCallOperands(Outs, CC_SystemZ);
1035 // We don't support GuaranteedTailCallOpt, only automatically-detected
1037 if (IsTailCall && !canUseSiblingCall(ArgCCInfo, ArgLocs))
1040 // Get a count of how many bytes are to be pushed on the stack.
1041 unsigned NumBytes = ArgCCInfo.getNextStackOffset();
1043 // Mark the start of the call.
1045 Chain = DAG.getCALLSEQ_START(Chain,
1046 DAG.getConstant(NumBytes, DL, PtrVT, true),
1049 // Copy argument values to their designated locations.
1050 SmallVector<std::pair<unsigned, SDValue>, 9> RegsToPass;
1051 SmallVector<SDValue, 8> MemOpChains;
1053 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
1054 CCValAssign &VA = ArgLocs[I];
1055 SDValue ArgValue = OutVals[I];
1057 if (VA.getLocInfo() == CCValAssign::Indirect) {
1058 // Store the argument in a stack slot and pass its address.
1059 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
1060 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
1061 MemOpChains.push_back(DAG.getStore(Chain, DL, ArgValue, SpillSlot,
1062 MachinePointerInfo::getFixedStack(FI),
1064 ArgValue = SpillSlot;
1066 ArgValue = convertValVTToLocVT(DAG, DL, VA, ArgValue);
1069 // Queue up the argument copies and emit them at the end.
1070 RegsToPass.push_back(std::make_pair(VA.getLocReg(), ArgValue));
1072 assert(VA.isMemLoc() && "Argument not register or memory");
1074 // Work out the address of the stack slot. Unpromoted ints and
1075 // floats are passed as right-justified 8-byte values.
1076 if (!StackPtr.getNode())
1077 StackPtr = DAG.getCopyFromReg(Chain, DL, SystemZ::R15D, PtrVT);
1078 unsigned Offset = SystemZMC::CallFrameSize + VA.getLocMemOffset();
1079 if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32)
1081 SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr,
1082 DAG.getIntPtrConstant(Offset, DL));
1085 MemOpChains.push_back(DAG.getStore(Chain, DL, ArgValue, Address,
1086 MachinePointerInfo(),
1091 // Join the stores, which are independent of one another.
1092 if (!MemOpChains.empty())
1093 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
1095 // Accept direct calls by converting symbolic call addresses to the
1096 // associated Target* opcodes. Force %r1 to be used for indirect
1099 if (auto *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1100 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, PtrVT);
1101 Callee = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Callee);
1102 } else if (auto *E = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1103 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), PtrVT);
1104 Callee = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Callee);
1105 } else if (IsTailCall) {
1106 Chain = DAG.getCopyToReg(Chain, DL, SystemZ::R1D, Callee, Glue);
1107 Glue = Chain.getValue(1);
1108 Callee = DAG.getRegister(SystemZ::R1D, Callee.getValueType());
1111 // Build a sequence of copy-to-reg nodes, chained and glued together.
1112 for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I) {
1113 Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[I].first,
1114 RegsToPass[I].second, Glue);
1115 Glue = Chain.getValue(1);
1118 // The first call operand is the chain and the second is the target address.
1119 SmallVector<SDValue, 8> Ops;
1120 Ops.push_back(Chain);
1121 Ops.push_back(Callee);
1123 // Add argument registers to the end of the list so that they are
1124 // known live into the call.
1125 for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I)
1126 Ops.push_back(DAG.getRegister(RegsToPass[I].first,
1127 RegsToPass[I].second.getValueType()));
1129 // Add a register mask operand representing the call-preserved registers.
1130 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
1131 const uint32_t *Mask = TRI->getCallPreservedMask(MF, CallConv);
1132 assert(Mask && "Missing call preserved mask for calling convention");
1133 Ops.push_back(DAG.getRegisterMask(Mask));
1135 // Glue the call to the argument copies, if any.
1137 Ops.push_back(Glue);
1140 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1142 return DAG.getNode(SystemZISD::SIBCALL, DL, NodeTys, Ops);
1143 Chain = DAG.getNode(SystemZISD::CALL, DL, NodeTys, Ops);
1144 Glue = Chain.getValue(1);
1146 // Mark the end of the call, which is glued to the call itself.
1147 Chain = DAG.getCALLSEQ_END(Chain,
1148 DAG.getConstant(NumBytes, DL, PtrVT, true),
1149 DAG.getConstant(0, DL, PtrVT, true),
1151 Glue = Chain.getValue(1);
1153 // Assign locations to each value returned by this call.
1154 SmallVector<CCValAssign, 16> RetLocs;
1155 CCState RetCCInfo(CallConv, IsVarArg, MF, RetLocs, *DAG.getContext());
1156 RetCCInfo.AnalyzeCallResult(Ins, RetCC_SystemZ);
1158 // Copy all of the result registers out of their specified physreg.
1159 for (unsigned I = 0, E = RetLocs.size(); I != E; ++I) {
1160 CCValAssign &VA = RetLocs[I];
1162 // Copy the value out, gluing the copy to the end of the call sequence.
1163 SDValue RetValue = DAG.getCopyFromReg(Chain, DL, VA.getLocReg(),
1164 VA.getLocVT(), Glue);
1165 Chain = RetValue.getValue(1);
1166 Glue = RetValue.getValue(2);
1168 // Convert the value of the return register into the value that's
1170 InVals.push_back(convertLocVTToValVT(DAG, DL, VA, Chain, RetValue));
1177 SystemZTargetLowering::LowerReturn(SDValue Chain,
1178 CallingConv::ID CallConv, bool IsVarArg,
1179 const SmallVectorImpl<ISD::OutputArg> &Outs,
1180 const SmallVectorImpl<SDValue> &OutVals,
1181 SDLoc DL, SelectionDAG &DAG) const {
1182 MachineFunction &MF = DAG.getMachineFunction();
1184 // Detect unsupported vector return types.
1185 if (Subtarget.hasVector())
1186 VerifyVectorTypes(Outs);
1188 // Assign locations to each returned value.
1189 SmallVector<CCValAssign, 16> RetLocs;
1190 CCState RetCCInfo(CallConv, IsVarArg, MF, RetLocs, *DAG.getContext());
1191 RetCCInfo.AnalyzeReturn(Outs, RetCC_SystemZ);
1193 // Quick exit for void returns
1194 if (RetLocs.empty())
1195 return DAG.getNode(SystemZISD::RET_FLAG, DL, MVT::Other, Chain);
1197 // Copy the result values into the output registers.
1199 SmallVector<SDValue, 4> RetOps;
1200 RetOps.push_back(Chain);
1201 for (unsigned I = 0, E = RetLocs.size(); I != E; ++I) {
1202 CCValAssign &VA = RetLocs[I];
1203 SDValue RetValue = OutVals[I];
1205 // Make the return register live on exit.
1206 assert(VA.isRegLoc() && "Can only return in registers!");
1208 // Promote the value as required.
1209 RetValue = convertValVTToLocVT(DAG, DL, VA, RetValue);
1211 // Chain and glue the copies together.
1212 unsigned Reg = VA.getLocReg();
1213 Chain = DAG.getCopyToReg(Chain, DL, Reg, RetValue, Glue);
1214 Glue = Chain.getValue(1);
1215 RetOps.push_back(DAG.getRegister(Reg, VA.getLocVT()));
1218 // Update chain and glue.
1221 RetOps.push_back(Glue);
1223 return DAG.getNode(SystemZISD::RET_FLAG, DL, MVT::Other, RetOps);
1226 SDValue SystemZTargetLowering::
1227 prepareVolatileOrAtomicLoad(SDValue Chain, SDLoc DL, SelectionDAG &DAG) const {
1228 return DAG.getNode(SystemZISD::SERIALIZE, DL, MVT::Other, Chain);
1231 // Return true if Op is an intrinsic node with chain that returns the CC value
1232 // as its only (other) argument. Provide the associated SystemZISD opcode and
1233 // the mask of valid CC values if so.
1234 static bool isIntrinsicWithCCAndChain(SDValue Op, unsigned &Opcode,
1235 unsigned &CCValid) {
1236 unsigned Id = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
1238 case Intrinsic::s390_tbegin:
1239 Opcode = SystemZISD::TBEGIN;
1240 CCValid = SystemZ::CCMASK_TBEGIN;
1243 case Intrinsic::s390_tbegin_nofloat:
1244 Opcode = SystemZISD::TBEGIN_NOFLOAT;
1245 CCValid = SystemZ::CCMASK_TBEGIN;
1248 case Intrinsic::s390_tend:
1249 Opcode = SystemZISD::TEND;
1250 CCValid = SystemZ::CCMASK_TEND;
1258 // Return true if Op is an intrinsic node without chain that returns the
1259 // CC value as its final argument. Provide the associated SystemZISD
1260 // opcode and the mask of valid CC values if so.
1261 static bool isIntrinsicWithCC(SDValue Op, unsigned &Opcode, unsigned &CCValid) {
1262 unsigned Id = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1264 case Intrinsic::s390_vpkshs:
1265 case Intrinsic::s390_vpksfs:
1266 case Intrinsic::s390_vpksgs:
1267 Opcode = SystemZISD::PACKS_CC;
1268 CCValid = SystemZ::CCMASK_VCMP;
1271 case Intrinsic::s390_vpklshs:
1272 case Intrinsic::s390_vpklsfs:
1273 case Intrinsic::s390_vpklsgs:
1274 Opcode = SystemZISD::PACKLS_CC;
1275 CCValid = SystemZ::CCMASK_VCMP;
1278 case Intrinsic::s390_vceqbs:
1279 case Intrinsic::s390_vceqhs:
1280 case Intrinsic::s390_vceqfs:
1281 case Intrinsic::s390_vceqgs:
1282 Opcode = SystemZISD::VICMPES;
1283 CCValid = SystemZ::CCMASK_VCMP;
1286 case Intrinsic::s390_vchbs:
1287 case Intrinsic::s390_vchhs:
1288 case Intrinsic::s390_vchfs:
1289 case Intrinsic::s390_vchgs:
1290 Opcode = SystemZISD::VICMPHS;
1291 CCValid = SystemZ::CCMASK_VCMP;
1294 case Intrinsic::s390_vchlbs:
1295 case Intrinsic::s390_vchlhs:
1296 case Intrinsic::s390_vchlfs:
1297 case Intrinsic::s390_vchlgs:
1298 Opcode = SystemZISD::VICMPHLS;
1299 CCValid = SystemZ::CCMASK_VCMP;
1302 case Intrinsic::s390_vtm:
1303 Opcode = SystemZISD::VTM;
1304 CCValid = SystemZ::CCMASK_VCMP;
1307 case Intrinsic::s390_vfaebs:
1308 case Intrinsic::s390_vfaehs:
1309 case Intrinsic::s390_vfaefs:
1310 Opcode = SystemZISD::VFAE_CC;
1311 CCValid = SystemZ::CCMASK_ANY;
1314 case Intrinsic::s390_vfaezbs:
1315 case Intrinsic::s390_vfaezhs:
1316 case Intrinsic::s390_vfaezfs:
1317 Opcode = SystemZISD::VFAEZ_CC;
1318 CCValid = SystemZ::CCMASK_ANY;
1321 case Intrinsic::s390_vfeebs:
1322 case Intrinsic::s390_vfeehs:
1323 case Intrinsic::s390_vfeefs:
1324 Opcode = SystemZISD::VFEE_CC;
1325 CCValid = SystemZ::CCMASK_ANY;
1328 case Intrinsic::s390_vfeezbs:
1329 case Intrinsic::s390_vfeezhs:
1330 case Intrinsic::s390_vfeezfs:
1331 Opcode = SystemZISD::VFEEZ_CC;
1332 CCValid = SystemZ::CCMASK_ANY;
1335 case Intrinsic::s390_vfenebs:
1336 case Intrinsic::s390_vfenehs:
1337 case Intrinsic::s390_vfenefs:
1338 Opcode = SystemZISD::VFENE_CC;
1339 CCValid = SystemZ::CCMASK_ANY;
1342 case Intrinsic::s390_vfenezbs:
1343 case Intrinsic::s390_vfenezhs:
1344 case Intrinsic::s390_vfenezfs:
1345 Opcode = SystemZISD::VFENEZ_CC;
1346 CCValid = SystemZ::CCMASK_ANY;
1349 case Intrinsic::s390_vistrbs:
1350 case Intrinsic::s390_vistrhs:
1351 case Intrinsic::s390_vistrfs:
1352 Opcode = SystemZISD::VISTR_CC;
1353 CCValid = SystemZ::CCMASK_0 | SystemZ::CCMASK_3;
1356 case Intrinsic::s390_vstrcbs:
1357 case Intrinsic::s390_vstrchs:
1358 case Intrinsic::s390_vstrcfs:
1359 Opcode = SystemZISD::VSTRC_CC;
1360 CCValid = SystemZ::CCMASK_ANY;
1363 case Intrinsic::s390_vstrczbs:
1364 case Intrinsic::s390_vstrczhs:
1365 case Intrinsic::s390_vstrczfs:
1366 Opcode = SystemZISD::VSTRCZ_CC;
1367 CCValid = SystemZ::CCMASK_ANY;
1370 case Intrinsic::s390_vfcedbs:
1371 Opcode = SystemZISD::VFCMPES;
1372 CCValid = SystemZ::CCMASK_VCMP;
1375 case Intrinsic::s390_vfchdbs:
1376 Opcode = SystemZISD::VFCMPHS;
1377 CCValid = SystemZ::CCMASK_VCMP;
1380 case Intrinsic::s390_vfchedbs:
1381 Opcode = SystemZISD::VFCMPHES;
1382 CCValid = SystemZ::CCMASK_VCMP;
1385 case Intrinsic::s390_vftcidb:
1386 Opcode = SystemZISD::VFTCI;
1387 CCValid = SystemZ::CCMASK_VCMP;
1395 // Emit an intrinsic with chain with a glued value instead of its CC result.
1396 static SDValue emitIntrinsicWithChainAndGlue(SelectionDAG &DAG, SDValue Op,
1398 // Copy all operands except the intrinsic ID.
1399 unsigned NumOps = Op.getNumOperands();
1400 SmallVector<SDValue, 6> Ops;
1401 Ops.reserve(NumOps - 1);
1402 Ops.push_back(Op.getOperand(0));
1403 for (unsigned I = 2; I < NumOps; ++I)
1404 Ops.push_back(Op.getOperand(I));
1406 assert(Op->getNumValues() == 2 && "Expected only CC result and chain");
1407 SDVTList RawVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1408 SDValue Intr = DAG.getNode(Opcode, SDLoc(Op), RawVTs, Ops);
1409 SDValue OldChain = SDValue(Op.getNode(), 1);
1410 SDValue NewChain = SDValue(Intr.getNode(), 0);
1411 DAG.ReplaceAllUsesOfValueWith(OldChain, NewChain);
1415 // Emit an intrinsic with a glued value instead of its CC result.
1416 static SDValue emitIntrinsicWithGlue(SelectionDAG &DAG, SDValue Op,
1418 // Copy all operands except the intrinsic ID.
1419 unsigned NumOps = Op.getNumOperands();
1420 SmallVector<SDValue, 6> Ops;
1421 Ops.reserve(NumOps - 1);
1422 for (unsigned I = 1; I < NumOps; ++I)
1423 Ops.push_back(Op.getOperand(I));
1425 if (Op->getNumValues() == 1)
1426 return DAG.getNode(Opcode, SDLoc(Op), MVT::Glue, Ops);
1427 assert(Op->getNumValues() == 2 && "Expected exactly one non-CC result");
1428 SDVTList RawVTs = DAG.getVTList(Op->getValueType(0), MVT::Glue);
1429 return DAG.getNode(Opcode, SDLoc(Op), RawVTs, Ops);
1432 // CC is a comparison that will be implemented using an integer or
1433 // floating-point comparison. Return the condition code mask for
1434 // a branch on true. In the integer case, CCMASK_CMP_UO is set for
1435 // unsigned comparisons and clear for signed ones. In the floating-point
1436 // case, CCMASK_CMP_UO has its normal mask meaning (unordered).
1437 static unsigned CCMaskForCondCode(ISD::CondCode CC) {
1439 case ISD::SET##X: return SystemZ::CCMASK_CMP_##X; \
1440 case ISD::SETO##X: return SystemZ::CCMASK_CMP_##X; \
1441 case ISD::SETU##X: return SystemZ::CCMASK_CMP_UO | SystemZ::CCMASK_CMP_##X
1445 llvm_unreachable("Invalid integer condition!");
1454 case ISD::SETO: return SystemZ::CCMASK_CMP_O;
1455 case ISD::SETUO: return SystemZ::CCMASK_CMP_UO;
1460 // Return a sequence for getting a 1 from an IPM result when CC has a
1461 // value in CCMask and a 0 when CC has a value in CCValid & ~CCMask.
1462 // The handling of CC values outside CCValid doesn't matter.
1463 static IPMConversion getIPMConversion(unsigned CCValid, unsigned CCMask) {
1464 // Deal with cases where the result can be taken directly from a bit
1465 // of the IPM result.
1466 if (CCMask == (CCValid & (SystemZ::CCMASK_1 | SystemZ::CCMASK_3)))
1467 return IPMConversion(0, 0, SystemZ::IPM_CC);
1468 if (CCMask == (CCValid & (SystemZ::CCMASK_2 | SystemZ::CCMASK_3)))
1469 return IPMConversion(0, 0, SystemZ::IPM_CC + 1);
1471 // Deal with cases where we can add a value to force the sign bit
1472 // to contain the right value. Putting the bit in 31 means we can
1473 // use SRL rather than RISBG(L), and also makes it easier to get a
1474 // 0/-1 value, so it has priority over the other tests below.
1476 // These sequences rely on the fact that the upper two bits of the
1477 // IPM result are zero.
1478 uint64_t TopBit = uint64_t(1) << 31;
1479 if (CCMask == (CCValid & SystemZ::CCMASK_0))
1480 return IPMConversion(0, -(1 << SystemZ::IPM_CC), 31);
1481 if (CCMask == (CCValid & (SystemZ::CCMASK_0 | SystemZ::CCMASK_1)))
1482 return IPMConversion(0, -(2 << SystemZ::IPM_CC), 31);
1483 if (CCMask == (CCValid & (SystemZ::CCMASK_0
1485 | SystemZ::CCMASK_2)))
1486 return IPMConversion(0, -(3 << SystemZ::IPM_CC), 31);
1487 if (CCMask == (CCValid & SystemZ::CCMASK_3))
1488 return IPMConversion(0, TopBit - (3 << SystemZ::IPM_CC), 31);
1489 if (CCMask == (CCValid & (SystemZ::CCMASK_1
1491 | SystemZ::CCMASK_3)))
1492 return IPMConversion(0, TopBit - (1 << SystemZ::IPM_CC), 31);
1494 // Next try inverting the value and testing a bit. 0/1 could be
1495 // handled this way too, but we dealt with that case above.
1496 if (CCMask == (CCValid & (SystemZ::CCMASK_0 | SystemZ::CCMASK_2)))
1497 return IPMConversion(-1, 0, SystemZ::IPM_CC);
1499 // Handle cases where adding a value forces a non-sign bit to contain
1501 if (CCMask == (CCValid & (SystemZ::CCMASK_1 | SystemZ::CCMASK_2)))
1502 return IPMConversion(0, 1 << SystemZ::IPM_CC, SystemZ::IPM_CC + 1);
1503 if (CCMask == (CCValid & (SystemZ::CCMASK_0 | SystemZ::CCMASK_3)))
1504 return IPMConversion(0, -(1 << SystemZ::IPM_CC), SystemZ::IPM_CC + 1);
1506 // The remaining cases are 1, 2, 0/1/3 and 0/2/3. All these are
1507 // can be done by inverting the low CC bit and applying one of the
1508 // sign-based extractions above.
1509 if (CCMask == (CCValid & SystemZ::CCMASK_1))
1510 return IPMConversion(1 << SystemZ::IPM_CC, -(1 << SystemZ::IPM_CC), 31);
1511 if (CCMask == (CCValid & SystemZ::CCMASK_2))
1512 return IPMConversion(1 << SystemZ::IPM_CC,
1513 TopBit - (3 << SystemZ::IPM_CC), 31);
1514 if (CCMask == (CCValid & (SystemZ::CCMASK_0
1516 | SystemZ::CCMASK_3)))
1517 return IPMConversion(1 << SystemZ::IPM_CC, -(3 << SystemZ::IPM_CC), 31);
1518 if (CCMask == (CCValid & (SystemZ::CCMASK_0
1520 | SystemZ::CCMASK_3)))
1521 return IPMConversion(1 << SystemZ::IPM_CC,
1522 TopBit - (1 << SystemZ::IPM_CC), 31);
1524 llvm_unreachable("Unexpected CC combination");
1527 // If C can be converted to a comparison against zero, adjust the operands
1529 static void adjustZeroCmp(SelectionDAG &DAG, SDLoc DL, Comparison &C) {
1530 if (C.ICmpType == SystemZICMP::UnsignedOnly)
1533 auto *ConstOp1 = dyn_cast<ConstantSDNode>(C.Op1.getNode());
1537 int64_t Value = ConstOp1->getSExtValue();
1538 if ((Value == -1 && C.CCMask == SystemZ::CCMASK_CMP_GT) ||
1539 (Value == -1 && C.CCMask == SystemZ::CCMASK_CMP_LE) ||
1540 (Value == 1 && C.CCMask == SystemZ::CCMASK_CMP_LT) ||
1541 (Value == 1 && C.CCMask == SystemZ::CCMASK_CMP_GE)) {
1542 C.CCMask ^= SystemZ::CCMASK_CMP_EQ;
1543 C.Op1 = DAG.getConstant(0, DL, C.Op1.getValueType());
1547 // If a comparison described by C is suitable for CLI(Y), CHHSI or CLHHSI,
1548 // adjust the operands as necessary.
1549 static void adjustSubwordCmp(SelectionDAG &DAG, SDLoc DL, Comparison &C) {
1550 // For us to make any changes, it must a comparison between a single-use
1551 // load and a constant.
1552 if (!C.Op0.hasOneUse() ||
1553 C.Op0.getOpcode() != ISD::LOAD ||
1554 C.Op1.getOpcode() != ISD::Constant)
1557 // We must have an 8- or 16-bit load.
1558 auto *Load = cast<LoadSDNode>(C.Op0);
1559 unsigned NumBits = Load->getMemoryVT().getStoreSizeInBits();
1560 if (NumBits != 8 && NumBits != 16)
1563 // The load must be an extending one and the constant must be within the
1564 // range of the unextended value.
1565 auto *ConstOp1 = cast<ConstantSDNode>(C.Op1);
1566 uint64_t Value = ConstOp1->getZExtValue();
1567 uint64_t Mask = (1 << NumBits) - 1;
1568 if (Load->getExtensionType() == ISD::SEXTLOAD) {
1569 // Make sure that ConstOp1 is in range of C.Op0.
1570 int64_t SignedValue = ConstOp1->getSExtValue();
1571 if (uint64_t(SignedValue) + (uint64_t(1) << (NumBits - 1)) > Mask)
1573 if (C.ICmpType != SystemZICMP::SignedOnly) {
1574 // Unsigned comparison between two sign-extended values is equivalent
1575 // to unsigned comparison between two zero-extended values.
1577 } else if (NumBits == 8) {
1578 // Try to treat the comparison as unsigned, so that we can use CLI.
1579 // Adjust CCMask and Value as necessary.
1580 if (Value == 0 && C.CCMask == SystemZ::CCMASK_CMP_LT)
1581 // Test whether the high bit of the byte is set.
1582 Value = 127, C.CCMask = SystemZ::CCMASK_CMP_GT;
1583 else if (Value == 0 && C.CCMask == SystemZ::CCMASK_CMP_GE)
1584 // Test whether the high bit of the byte is clear.
1585 Value = 128, C.CCMask = SystemZ::CCMASK_CMP_LT;
1587 // No instruction exists for this combination.
1589 C.ICmpType = SystemZICMP::UnsignedOnly;
1591 } else if (Load->getExtensionType() == ISD::ZEXTLOAD) {
1594 assert(C.ICmpType == SystemZICMP::Any &&
1595 "Signedness shouldn't matter here.");
1599 // Make sure that the first operand is an i32 of the right extension type.
1600 ISD::LoadExtType ExtType = (C.ICmpType == SystemZICMP::SignedOnly ?
1603 if (C.Op0.getValueType() != MVT::i32 ||
1604 Load->getExtensionType() != ExtType)
1605 C.Op0 = DAG.getExtLoad(ExtType, SDLoc(Load), MVT::i32,
1606 Load->getChain(), Load->getBasePtr(),
1607 Load->getPointerInfo(), Load->getMemoryVT(),
1608 Load->isVolatile(), Load->isNonTemporal(),
1609 Load->isInvariant(), Load->getAlignment());
1611 // Make sure that the second operand is an i32 with the right value.
1612 if (C.Op1.getValueType() != MVT::i32 ||
1613 Value != ConstOp1->getZExtValue())
1614 C.Op1 = DAG.getConstant(Value, DL, MVT::i32);
1617 // Return true if Op is either an unextended load, or a load suitable
1618 // for integer register-memory comparisons of type ICmpType.
1619 static bool isNaturalMemoryOperand(SDValue Op, unsigned ICmpType) {
1620 auto *Load = dyn_cast<LoadSDNode>(Op.getNode());
1622 // There are no instructions to compare a register with a memory byte.
1623 if (Load->getMemoryVT() == MVT::i8)
1625 // Otherwise decide on extension type.
1626 switch (Load->getExtensionType()) {
1627 case ISD::NON_EXTLOAD:
1630 return ICmpType != SystemZICMP::UnsignedOnly;
1632 return ICmpType != SystemZICMP::SignedOnly;
1640 // Return true if it is better to swap the operands of C.
1641 static bool shouldSwapCmpOperands(const Comparison &C) {
1642 // Leave f128 comparisons alone, since they have no memory forms.
1643 if (C.Op0.getValueType() == MVT::f128)
1646 // Always keep a floating-point constant second, since comparisons with
1647 // zero can use LOAD TEST and comparisons with other constants make a
1648 // natural memory operand.
1649 if (isa<ConstantFPSDNode>(C.Op1))
1652 // Never swap comparisons with zero since there are many ways to optimize
1654 auto *ConstOp1 = dyn_cast<ConstantSDNode>(C.Op1);
1655 if (ConstOp1 && ConstOp1->getZExtValue() == 0)
1658 // Also keep natural memory operands second if the loaded value is
1659 // only used here. Several comparisons have memory forms.
1660 if (isNaturalMemoryOperand(C.Op1, C.ICmpType) && C.Op1.hasOneUse())
1663 // Look for cases where Cmp0 is a single-use load and Cmp1 isn't.
1664 // In that case we generally prefer the memory to be second.
1665 if (isNaturalMemoryOperand(C.Op0, C.ICmpType) && C.Op0.hasOneUse()) {
1666 // The only exceptions are when the second operand is a constant and
1667 // we can use things like CHHSI.
1670 // The unsigned memory-immediate instructions can handle 16-bit
1671 // unsigned integers.
1672 if (C.ICmpType != SystemZICMP::SignedOnly &&
1673 isUInt<16>(ConstOp1->getZExtValue()))
1675 // The signed memory-immediate instructions can handle 16-bit
1677 if (C.ICmpType != SystemZICMP::UnsignedOnly &&
1678 isInt<16>(ConstOp1->getSExtValue()))
1683 // Try to promote the use of CGFR and CLGFR.
1684 unsigned Opcode0 = C.Op0.getOpcode();
1685 if (C.ICmpType != SystemZICMP::UnsignedOnly && Opcode0 == ISD::SIGN_EXTEND)
1687 if (C.ICmpType != SystemZICMP::SignedOnly && Opcode0 == ISD::ZERO_EXTEND)
1689 if (C.ICmpType != SystemZICMP::SignedOnly &&
1690 Opcode0 == ISD::AND &&
1691 C.Op0.getOperand(1).getOpcode() == ISD::Constant &&
1692 cast<ConstantSDNode>(C.Op0.getOperand(1))->getZExtValue() == 0xffffffff)
1698 // Return a version of comparison CC mask CCMask in which the LT and GT
1699 // actions are swapped.
1700 static unsigned reverseCCMask(unsigned CCMask) {
1701 return ((CCMask & SystemZ::CCMASK_CMP_EQ) |
1702 (CCMask & SystemZ::CCMASK_CMP_GT ? SystemZ::CCMASK_CMP_LT : 0) |
1703 (CCMask & SystemZ::CCMASK_CMP_LT ? SystemZ::CCMASK_CMP_GT : 0) |
1704 (CCMask & SystemZ::CCMASK_CMP_UO));
1707 // Check whether C tests for equality between X and Y and whether X - Y
1708 // or Y - X is also computed. In that case it's better to compare the
1709 // result of the subtraction against zero.
1710 static void adjustForSubtraction(SelectionDAG &DAG, SDLoc DL, Comparison &C) {
1711 if (C.CCMask == SystemZ::CCMASK_CMP_EQ ||
1712 C.CCMask == SystemZ::CCMASK_CMP_NE) {
1713 for (auto I = C.Op0->use_begin(), E = C.Op0->use_end(); I != E; ++I) {
1715 if (N->getOpcode() == ISD::SUB &&
1716 ((N->getOperand(0) == C.Op0 && N->getOperand(1) == C.Op1) ||
1717 (N->getOperand(0) == C.Op1 && N->getOperand(1) == C.Op0))) {
1718 C.Op0 = SDValue(N, 0);
1719 C.Op1 = DAG.getConstant(0, DL, N->getValueType(0));
1726 // Check whether C compares a floating-point value with zero and if that
1727 // floating-point value is also negated. In this case we can use the
1728 // negation to set CC, so avoiding separate LOAD AND TEST and
1729 // LOAD (NEGATIVE/COMPLEMENT) instructions.
1730 static void adjustForFNeg(Comparison &C) {
1731 auto *C1 = dyn_cast<ConstantFPSDNode>(C.Op1);
1732 if (C1 && C1->isZero()) {
1733 for (auto I = C.Op0->use_begin(), E = C.Op0->use_end(); I != E; ++I) {
1735 if (N->getOpcode() == ISD::FNEG) {
1736 C.Op0 = SDValue(N, 0);
1737 C.CCMask = reverseCCMask(C.CCMask);
1744 // Check whether C compares (shl X, 32) with 0 and whether X is
1745 // also sign-extended. In that case it is better to test the result
1746 // of the sign extension using LTGFR.
1748 // This case is important because InstCombine transforms a comparison
1749 // with (sext (trunc X)) into a comparison with (shl X, 32).
1750 static void adjustForLTGFR(Comparison &C) {
1751 // Check for a comparison between (shl X, 32) and 0.
1752 if (C.Op0.getOpcode() == ISD::SHL &&
1753 C.Op0.getValueType() == MVT::i64 &&
1754 C.Op1.getOpcode() == ISD::Constant &&
1755 cast<ConstantSDNode>(C.Op1)->getZExtValue() == 0) {
1756 auto *C1 = dyn_cast<ConstantSDNode>(C.Op0.getOperand(1));
1757 if (C1 && C1->getZExtValue() == 32) {
1758 SDValue ShlOp0 = C.Op0.getOperand(0);
1759 // See whether X has any SIGN_EXTEND_INREG uses.
1760 for (auto I = ShlOp0->use_begin(), E = ShlOp0->use_end(); I != E; ++I) {
1762 if (N->getOpcode() == ISD::SIGN_EXTEND_INREG &&
1763 cast<VTSDNode>(N->getOperand(1))->getVT() == MVT::i32) {
1764 C.Op0 = SDValue(N, 0);
1772 // If C compares the truncation of an extending load, try to compare
1773 // the untruncated value instead. This exposes more opportunities to
1775 static void adjustICmpTruncate(SelectionDAG &DAG, SDLoc DL, Comparison &C) {
1776 if (C.Op0.getOpcode() == ISD::TRUNCATE &&
1777 C.Op0.getOperand(0).getOpcode() == ISD::LOAD &&
1778 C.Op1.getOpcode() == ISD::Constant &&
1779 cast<ConstantSDNode>(C.Op1)->getZExtValue() == 0) {
1780 auto *L = cast<LoadSDNode>(C.Op0.getOperand(0));
1781 if (L->getMemoryVT().getStoreSizeInBits()
1782 <= C.Op0.getValueType().getSizeInBits()) {
1783 unsigned Type = L->getExtensionType();
1784 if ((Type == ISD::ZEXTLOAD && C.ICmpType != SystemZICMP::SignedOnly) ||
1785 (Type == ISD::SEXTLOAD && C.ICmpType != SystemZICMP::UnsignedOnly)) {
1786 C.Op0 = C.Op0.getOperand(0);
1787 C.Op1 = DAG.getConstant(0, DL, C.Op0.getValueType());
1793 // Return true if shift operation N has an in-range constant shift value.
1794 // Store it in ShiftVal if so.
1795 static bool isSimpleShift(SDValue N, unsigned &ShiftVal) {
1796 auto *Shift = dyn_cast<ConstantSDNode>(N.getOperand(1));
1800 uint64_t Amount = Shift->getZExtValue();
1801 if (Amount >= N.getValueType().getSizeInBits())
1808 // Check whether an AND with Mask is suitable for a TEST UNDER MASK
1809 // instruction and whether the CC value is descriptive enough to handle
1810 // a comparison of type Opcode between the AND result and CmpVal.
1811 // CCMask says which comparison result is being tested and BitSize is
1812 // the number of bits in the operands. If TEST UNDER MASK can be used,
1813 // return the corresponding CC mask, otherwise return 0.
1814 static unsigned getTestUnderMaskCond(unsigned BitSize, unsigned CCMask,
1815 uint64_t Mask, uint64_t CmpVal,
1816 unsigned ICmpType) {
1817 assert(Mask != 0 && "ANDs with zero should have been removed by now");
1819 // Check whether the mask is suitable for TMHH, TMHL, TMLH or TMLL.
1820 if (!SystemZ::isImmLL(Mask) && !SystemZ::isImmLH(Mask) &&
1821 !SystemZ::isImmHL(Mask) && !SystemZ::isImmHH(Mask))
1824 // Work out the masks for the lowest and highest bits.
1825 unsigned HighShift = 63 - countLeadingZeros(Mask);
1826 uint64_t High = uint64_t(1) << HighShift;
1827 uint64_t Low = uint64_t(1) << countTrailingZeros(Mask);
1829 // Signed ordered comparisons are effectively unsigned if the sign
1831 bool EffectivelyUnsigned = (ICmpType != SystemZICMP::SignedOnly);
1833 // Check for equality comparisons with 0, or the equivalent.
1835 if (CCMask == SystemZ::CCMASK_CMP_EQ)
1836 return SystemZ::CCMASK_TM_ALL_0;
1837 if (CCMask == SystemZ::CCMASK_CMP_NE)
1838 return SystemZ::CCMASK_TM_SOME_1;
1840 if (EffectivelyUnsigned && CmpVal <= Low) {
1841 if (CCMask == SystemZ::CCMASK_CMP_LT)
1842 return SystemZ::CCMASK_TM_ALL_0;
1843 if (CCMask == SystemZ::CCMASK_CMP_GE)
1844 return SystemZ::CCMASK_TM_SOME_1;
1846 if (EffectivelyUnsigned && CmpVal < Low) {
1847 if (CCMask == SystemZ::CCMASK_CMP_LE)
1848 return SystemZ::CCMASK_TM_ALL_0;
1849 if (CCMask == SystemZ::CCMASK_CMP_GT)
1850 return SystemZ::CCMASK_TM_SOME_1;
1853 // Check for equality comparisons with the mask, or the equivalent.
1854 if (CmpVal == Mask) {
1855 if (CCMask == SystemZ::CCMASK_CMP_EQ)
1856 return SystemZ::CCMASK_TM_ALL_1;
1857 if (CCMask == SystemZ::CCMASK_CMP_NE)
1858 return SystemZ::CCMASK_TM_SOME_0;
1860 if (EffectivelyUnsigned && CmpVal >= Mask - Low && CmpVal < Mask) {
1861 if (CCMask == SystemZ::CCMASK_CMP_GT)
1862 return SystemZ::CCMASK_TM_ALL_1;
1863 if (CCMask == SystemZ::CCMASK_CMP_LE)
1864 return SystemZ::CCMASK_TM_SOME_0;
1866 if (EffectivelyUnsigned && CmpVal > Mask - Low && CmpVal <= Mask) {
1867 if (CCMask == SystemZ::CCMASK_CMP_GE)
1868 return SystemZ::CCMASK_TM_ALL_1;
1869 if (CCMask == SystemZ::CCMASK_CMP_LT)
1870 return SystemZ::CCMASK_TM_SOME_0;
1873 // Check for ordered comparisons with the top bit.
1874 if (EffectivelyUnsigned && CmpVal >= Mask - High && CmpVal < High) {
1875 if (CCMask == SystemZ::CCMASK_CMP_LE)
1876 return SystemZ::CCMASK_TM_MSB_0;
1877 if (CCMask == SystemZ::CCMASK_CMP_GT)
1878 return SystemZ::CCMASK_TM_MSB_1;
1880 if (EffectivelyUnsigned && CmpVal > Mask - High && CmpVal <= High) {
1881 if (CCMask == SystemZ::CCMASK_CMP_LT)
1882 return SystemZ::CCMASK_TM_MSB_0;
1883 if (CCMask == SystemZ::CCMASK_CMP_GE)
1884 return SystemZ::CCMASK_TM_MSB_1;
1887 // If there are just two bits, we can do equality checks for Low and High
1889 if (Mask == Low + High) {
1890 if (CCMask == SystemZ::CCMASK_CMP_EQ && CmpVal == Low)
1891 return SystemZ::CCMASK_TM_MIXED_MSB_0;
1892 if (CCMask == SystemZ::CCMASK_CMP_NE && CmpVal == Low)
1893 return SystemZ::CCMASK_TM_MIXED_MSB_0 ^ SystemZ::CCMASK_ANY;
1894 if (CCMask == SystemZ::CCMASK_CMP_EQ && CmpVal == High)
1895 return SystemZ::CCMASK_TM_MIXED_MSB_1;
1896 if (CCMask == SystemZ::CCMASK_CMP_NE && CmpVal == High)
1897 return SystemZ::CCMASK_TM_MIXED_MSB_1 ^ SystemZ::CCMASK_ANY;
1900 // Looks like we've exhausted our options.
1904 // See whether C can be implemented as a TEST UNDER MASK instruction.
1905 // Update the arguments with the TM version if so.
1906 static void adjustForTestUnderMask(SelectionDAG &DAG, SDLoc DL, Comparison &C) {
1907 // Check that we have a comparison with a constant.
1908 auto *ConstOp1 = dyn_cast<ConstantSDNode>(C.Op1);
1911 uint64_t CmpVal = ConstOp1->getZExtValue();
1913 // Check whether the nonconstant input is an AND with a constant mask.
1916 ConstantSDNode *Mask = nullptr;
1917 if (C.Op0.getOpcode() == ISD::AND) {
1918 NewC.Op0 = C.Op0.getOperand(0);
1919 NewC.Op1 = C.Op0.getOperand(1);
1920 Mask = dyn_cast<ConstantSDNode>(NewC.Op1);
1923 MaskVal = Mask->getZExtValue();
1925 // There is no instruction to compare with a 64-bit immediate
1926 // so use TMHH instead if possible. We need an unsigned ordered
1927 // comparison with an i64 immediate.
1928 if (NewC.Op0.getValueType() != MVT::i64 ||
1929 NewC.CCMask == SystemZ::CCMASK_CMP_EQ ||
1930 NewC.CCMask == SystemZ::CCMASK_CMP_NE ||
1931 NewC.ICmpType == SystemZICMP::SignedOnly)
1933 // Convert LE and GT comparisons into LT and GE.
1934 if (NewC.CCMask == SystemZ::CCMASK_CMP_LE ||
1935 NewC.CCMask == SystemZ::CCMASK_CMP_GT) {
1936 if (CmpVal == uint64_t(-1))
1939 NewC.CCMask ^= SystemZ::CCMASK_CMP_EQ;
1941 // If the low N bits of Op1 are zero than the low N bits of Op0 can
1942 // be masked off without changing the result.
1943 MaskVal = -(CmpVal & -CmpVal);
1944 NewC.ICmpType = SystemZICMP::UnsignedOnly;
1949 // Check whether the combination of mask, comparison value and comparison
1950 // type are suitable.
1951 unsigned BitSize = NewC.Op0.getValueType().getSizeInBits();
1952 unsigned NewCCMask, ShiftVal;
1953 if (NewC.ICmpType != SystemZICMP::SignedOnly &&
1954 NewC.Op0.getOpcode() == ISD::SHL &&
1955 isSimpleShift(NewC.Op0, ShiftVal) &&
1956 (NewCCMask = getTestUnderMaskCond(BitSize, NewC.CCMask,
1957 MaskVal >> ShiftVal,
1959 SystemZICMP::Any))) {
1960 NewC.Op0 = NewC.Op0.getOperand(0);
1961 MaskVal >>= ShiftVal;
1962 } else if (NewC.ICmpType != SystemZICMP::SignedOnly &&
1963 NewC.Op0.getOpcode() == ISD::SRL &&
1964 isSimpleShift(NewC.Op0, ShiftVal) &&
1965 (NewCCMask = getTestUnderMaskCond(BitSize, NewC.CCMask,
1966 MaskVal << ShiftVal,
1968 SystemZICMP::UnsignedOnly))) {
1969 NewC.Op0 = NewC.Op0.getOperand(0);
1970 MaskVal <<= ShiftVal;
1972 NewCCMask = getTestUnderMaskCond(BitSize, NewC.CCMask, MaskVal, CmpVal,
1978 // Go ahead and make the change.
1979 C.Opcode = SystemZISD::TM;
1981 if (Mask && Mask->getZExtValue() == MaskVal)
1982 C.Op1 = SDValue(Mask, 0);
1984 C.Op1 = DAG.getConstant(MaskVal, DL, C.Op0.getValueType());
1985 C.CCValid = SystemZ::CCMASK_TM;
1986 C.CCMask = NewCCMask;
1989 // Return a Comparison that tests the condition-code result of intrinsic
1990 // node Call against constant integer CC using comparison code Cond.
1991 // Opcode is the opcode of the SystemZISD operation for the intrinsic
1992 // and CCValid is the set of possible condition-code results.
1993 static Comparison getIntrinsicCmp(SelectionDAG &DAG, unsigned Opcode,
1994 SDValue Call, unsigned CCValid, uint64_t CC,
1995 ISD::CondCode Cond) {
1996 Comparison C(Call, SDValue());
1998 C.CCValid = CCValid;
1999 if (Cond == ISD::SETEQ)
2000 // bit 3 for CC==0, bit 0 for CC==3, always false for CC>3.
2001 C.CCMask = CC < 4 ? 1 << (3 - CC) : 0;
2002 else if (Cond == ISD::SETNE)
2003 // ...and the inverse of that.
2004 C.CCMask = CC < 4 ? ~(1 << (3 - CC)) : -1;
2005 else if (Cond == ISD::SETLT || Cond == ISD::SETULT)
2006 // bits above bit 3 for CC==0 (always false), bits above bit 0 for CC==3,
2007 // always true for CC>3.
2008 C.CCMask = CC < 4 ? -1 << (4 - CC) : -1;
2009 else if (Cond == ISD::SETGE || Cond == ISD::SETUGE)
2010 // ...and the inverse of that.
2011 C.CCMask = CC < 4 ? ~(-1 << (4 - CC)) : 0;
2012 else if (Cond == ISD::SETLE || Cond == ISD::SETULE)
2013 // bit 3 and above for CC==0, bit 0 and above for CC==3 (always true),
2014 // always true for CC>3.
2015 C.CCMask = CC < 4 ? -1 << (3 - CC) : -1;
2016 else if (Cond == ISD::SETGT || Cond == ISD::SETUGT)
2017 // ...and the inverse of that.
2018 C.CCMask = CC < 4 ? ~(-1 << (3 - CC)) : 0;
2020 llvm_unreachable("Unexpected integer comparison type");
2021 C.CCMask &= CCValid;
2025 // Decide how to implement a comparison of type Cond between CmpOp0 with CmpOp1.
2026 static Comparison getCmp(SelectionDAG &DAG, SDValue CmpOp0, SDValue CmpOp1,
2027 ISD::CondCode Cond, SDLoc DL) {
2028 if (CmpOp1.getOpcode() == ISD::Constant) {
2029 uint64_t Constant = cast<ConstantSDNode>(CmpOp1)->getZExtValue();
2030 unsigned Opcode, CCValid;
2031 if (CmpOp0.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
2032 CmpOp0.getResNo() == 0 && CmpOp0->hasNUsesOfValue(1, 0) &&
2033 isIntrinsicWithCCAndChain(CmpOp0, Opcode, CCValid))
2034 return getIntrinsicCmp(DAG, Opcode, CmpOp0, CCValid, Constant, Cond);
2035 if (CmpOp0.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
2036 CmpOp0.getResNo() == CmpOp0->getNumValues() - 1 &&
2037 isIntrinsicWithCC(CmpOp0, Opcode, CCValid))
2038 return getIntrinsicCmp(DAG, Opcode, CmpOp0, CCValid, Constant, Cond);
2040 Comparison C(CmpOp0, CmpOp1);
2041 C.CCMask = CCMaskForCondCode(Cond);
2042 if (C.Op0.getValueType().isFloatingPoint()) {
2043 C.CCValid = SystemZ::CCMASK_FCMP;
2044 C.Opcode = SystemZISD::FCMP;
2047 C.CCValid = SystemZ::CCMASK_ICMP;
2048 C.Opcode = SystemZISD::ICMP;
2049 // Choose the type of comparison. Equality and inequality tests can
2050 // use either signed or unsigned comparisons. The choice also doesn't
2051 // matter if both sign bits are known to be clear. In those cases we
2052 // want to give the main isel code the freedom to choose whichever
2054 if (C.CCMask == SystemZ::CCMASK_CMP_EQ ||
2055 C.CCMask == SystemZ::CCMASK_CMP_NE ||
2056 (DAG.SignBitIsZero(C.Op0) && DAG.SignBitIsZero(C.Op1)))
2057 C.ICmpType = SystemZICMP::Any;
2058 else if (C.CCMask & SystemZ::CCMASK_CMP_UO)
2059 C.ICmpType = SystemZICMP::UnsignedOnly;
2061 C.ICmpType = SystemZICMP::SignedOnly;
2062 C.CCMask &= ~SystemZ::CCMASK_CMP_UO;
2063 adjustZeroCmp(DAG, DL, C);
2064 adjustSubwordCmp(DAG, DL, C);
2065 adjustForSubtraction(DAG, DL, C);
2067 adjustICmpTruncate(DAG, DL, C);
2070 if (shouldSwapCmpOperands(C)) {
2071 std::swap(C.Op0, C.Op1);
2072 C.CCMask = reverseCCMask(C.CCMask);
2075 adjustForTestUnderMask(DAG, DL, C);
2079 // Emit the comparison instruction described by C.
2080 static SDValue emitCmp(SelectionDAG &DAG, SDLoc DL, Comparison &C) {
2081 if (!C.Op1.getNode()) {
2083 switch (C.Op0.getOpcode()) {
2084 case ISD::INTRINSIC_W_CHAIN:
2085 Op = emitIntrinsicWithChainAndGlue(DAG, C.Op0, C.Opcode);
2087 case ISD::INTRINSIC_WO_CHAIN:
2088 Op = emitIntrinsicWithGlue(DAG, C.Op0, C.Opcode);
2091 llvm_unreachable("Invalid comparison operands");
2093 return SDValue(Op.getNode(), Op->getNumValues() - 1);
2095 if (C.Opcode == SystemZISD::ICMP)
2096 return DAG.getNode(SystemZISD::ICMP, DL, MVT::Glue, C.Op0, C.Op1,
2097 DAG.getConstant(C.ICmpType, DL, MVT::i32));
2098 if (C.Opcode == SystemZISD::TM) {
2099 bool RegisterOnly = (bool(C.CCMask & SystemZ::CCMASK_TM_MIXED_MSB_0) !=
2100 bool(C.CCMask & SystemZ::CCMASK_TM_MIXED_MSB_1));
2101 return DAG.getNode(SystemZISD::TM, DL, MVT::Glue, C.Op0, C.Op1,
2102 DAG.getConstant(RegisterOnly, DL, MVT::i32));
2104 return DAG.getNode(C.Opcode, DL, MVT::Glue, C.Op0, C.Op1);
2107 // Implement a 32-bit *MUL_LOHI operation by extending both operands to
2108 // 64 bits. Extend is the extension type to use. Store the high part
2109 // in Hi and the low part in Lo.
2110 static void lowerMUL_LOHI32(SelectionDAG &DAG, SDLoc DL,
2111 unsigned Extend, SDValue Op0, SDValue Op1,
2112 SDValue &Hi, SDValue &Lo) {
2113 Op0 = DAG.getNode(Extend, DL, MVT::i64, Op0);
2114 Op1 = DAG.getNode(Extend, DL, MVT::i64, Op1);
2115 SDValue Mul = DAG.getNode(ISD::MUL, DL, MVT::i64, Op0, Op1);
2116 Hi = DAG.getNode(ISD::SRL, DL, MVT::i64, Mul,
2117 DAG.getConstant(32, DL, MVT::i64));
2118 Hi = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Hi);
2119 Lo = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mul);
2122 // Lower a binary operation that produces two VT results, one in each
2123 // half of a GR128 pair. Op0 and Op1 are the VT operands to the operation,
2124 // Extend extends Op0 to a GR128, and Opcode performs the GR128 operation
2125 // on the extended Op0 and (unextended) Op1. Store the even register result
2126 // in Even and the odd register result in Odd.
2127 static void lowerGR128Binary(SelectionDAG &DAG, SDLoc DL, EVT VT,
2128 unsigned Extend, unsigned Opcode,
2129 SDValue Op0, SDValue Op1,
2130 SDValue &Even, SDValue &Odd) {
2131 SDNode *In128 = DAG.getMachineNode(Extend, DL, MVT::Untyped, Op0);
2132 SDValue Result = DAG.getNode(Opcode, DL, MVT::Untyped,
2133 SDValue(In128, 0), Op1);
2134 bool Is32Bit = is32Bit(VT);
2135 Even = DAG.getTargetExtractSubreg(SystemZ::even128(Is32Bit), DL, VT, Result);
2136 Odd = DAG.getTargetExtractSubreg(SystemZ::odd128(Is32Bit), DL, VT, Result);
2139 // Return an i32 value that is 1 if the CC value produced by Glue is
2140 // in the mask CCMask and 0 otherwise. CC is known to have a value
2141 // in CCValid, so other values can be ignored.
2142 static SDValue emitSETCC(SelectionDAG &DAG, SDLoc DL, SDValue Glue,
2143 unsigned CCValid, unsigned CCMask) {
2144 IPMConversion Conversion = getIPMConversion(CCValid, CCMask);
2145 SDValue Result = DAG.getNode(SystemZISD::IPM, DL, MVT::i32, Glue);
2147 if (Conversion.XORValue)
2148 Result = DAG.getNode(ISD::XOR, DL, MVT::i32, Result,
2149 DAG.getConstant(Conversion.XORValue, DL, MVT::i32));
2151 if (Conversion.AddValue)
2152 Result = DAG.getNode(ISD::ADD, DL, MVT::i32, Result,
2153 DAG.getConstant(Conversion.AddValue, DL, MVT::i32));
2155 // The SHR/AND sequence should get optimized to an RISBG.
2156 Result = DAG.getNode(ISD::SRL, DL, MVT::i32, Result,
2157 DAG.getConstant(Conversion.Bit, DL, MVT::i32));
2158 if (Conversion.Bit != 31)
2159 Result = DAG.getNode(ISD::AND, DL, MVT::i32, Result,
2160 DAG.getConstant(1, DL, MVT::i32));
2164 // Return the SystemISD vector comparison operation for CC, or 0 if it cannot
2165 // be done directly. IsFP is true if CC is for a floating-point rather than
2166 // integer comparison.
2167 static unsigned getVectorComparison(ISD::CondCode CC, bool IsFP) {
2171 return IsFP ? SystemZISD::VFCMPE : SystemZISD::VICMPE;
2175 return IsFP ? SystemZISD::VFCMPHE : static_cast<SystemZISD::NodeType>(0);
2179 return IsFP ? SystemZISD::VFCMPH : SystemZISD::VICMPH;
2182 return IsFP ? static_cast<SystemZISD::NodeType>(0) : SystemZISD::VICMPHL;
2189 // Return the SystemZISD vector comparison operation for CC or its inverse,
2190 // or 0 if neither can be done directly. Indicate in Invert whether the
2191 // result is for the inverse of CC. IsFP is true if CC is for a
2192 // floating-point rather than integer comparison.
2193 static unsigned getVectorComparisonOrInvert(ISD::CondCode CC, bool IsFP,
2195 if (unsigned Opcode = getVectorComparison(CC, IsFP)) {
2200 CC = ISD::getSetCCInverse(CC, !IsFP);
2201 if (unsigned Opcode = getVectorComparison(CC, IsFP)) {
2209 // Return a v2f64 that contains the extended form of elements Start and Start+1
2210 // of v4f32 value Op.
2211 static SDValue expandV4F32ToV2F64(SelectionDAG &DAG, int Start, SDLoc DL,
2213 int Mask[] = { Start, -1, Start + 1, -1 };
2214 Op = DAG.getVectorShuffle(MVT::v4f32, DL, Op, DAG.getUNDEF(MVT::v4f32), Mask);
2215 return DAG.getNode(SystemZISD::VEXTEND, DL, MVT::v2f64, Op);
2218 // Build a comparison of vectors CmpOp0 and CmpOp1 using opcode Opcode,
2219 // producing a result of type VT.
2220 static SDValue getVectorCmp(SelectionDAG &DAG, unsigned Opcode, SDLoc DL,
2221 EVT VT, SDValue CmpOp0, SDValue CmpOp1) {
2222 // There is no hardware support for v4f32, so extend the vector into
2223 // two v2f64s and compare those.
2224 if (CmpOp0.getValueType() == MVT::v4f32) {
2225 SDValue H0 = expandV4F32ToV2F64(DAG, 0, DL, CmpOp0);
2226 SDValue L0 = expandV4F32ToV2F64(DAG, 2, DL, CmpOp0);
2227 SDValue H1 = expandV4F32ToV2F64(DAG, 0, DL, CmpOp1);
2228 SDValue L1 = expandV4F32ToV2F64(DAG, 2, DL, CmpOp1);
2229 SDValue HRes = DAG.getNode(Opcode, DL, MVT::v2i64, H0, H1);
2230 SDValue LRes = DAG.getNode(Opcode, DL, MVT::v2i64, L0, L1);
2231 return DAG.getNode(SystemZISD::PACK, DL, VT, HRes, LRes);
2233 return DAG.getNode(Opcode, DL, VT, CmpOp0, CmpOp1);
2236 // Lower a vector comparison of type CC between CmpOp0 and CmpOp1, producing
2237 // an integer mask of type VT.
2238 static SDValue lowerVectorSETCC(SelectionDAG &DAG, SDLoc DL, EVT VT,
2239 ISD::CondCode CC, SDValue CmpOp0,
2241 bool IsFP = CmpOp0.getValueType().isFloatingPoint();
2242 bool Invert = false;
2245 // Handle tests for order using (or (ogt y x) (oge x y)).
2249 assert(IsFP && "Unexpected integer comparison");
2250 SDValue LT = getVectorCmp(DAG, SystemZISD::VFCMPH, DL, VT, CmpOp1, CmpOp0);
2251 SDValue GE = getVectorCmp(DAG, SystemZISD::VFCMPHE, DL, VT, CmpOp0, CmpOp1);
2252 Cmp = DAG.getNode(ISD::OR, DL, VT, LT, GE);
2256 // Handle <> tests using (or (ogt y x) (ogt x y)).
2260 assert(IsFP && "Unexpected integer comparison");
2261 SDValue LT = getVectorCmp(DAG, SystemZISD::VFCMPH, DL, VT, CmpOp1, CmpOp0);
2262 SDValue GT = getVectorCmp(DAG, SystemZISD::VFCMPH, DL, VT, CmpOp0, CmpOp1);
2263 Cmp = DAG.getNode(ISD::OR, DL, VT, LT, GT);
2267 // Otherwise a single comparison is enough. It doesn't really
2268 // matter whether we try the inversion or the swap first, since
2269 // there are no cases where both work.
2271 if (unsigned Opcode = getVectorComparisonOrInvert(CC, IsFP, Invert))
2272 Cmp = getVectorCmp(DAG, Opcode, DL, VT, CmpOp0, CmpOp1);
2274 CC = ISD::getSetCCSwappedOperands(CC);
2275 if (unsigned Opcode = getVectorComparisonOrInvert(CC, IsFP, Invert))
2276 Cmp = getVectorCmp(DAG, Opcode, DL, VT, CmpOp1, CmpOp0);
2278 llvm_unreachable("Unhandled comparison");
2283 SDValue Mask = DAG.getNode(SystemZISD::BYTE_MASK, DL, MVT::v16i8,
2284 DAG.getConstant(65535, DL, MVT::i32));
2285 Mask = DAG.getNode(ISD::BITCAST, DL, VT, Mask);
2286 Cmp = DAG.getNode(ISD::XOR, DL, VT, Cmp, Mask);
2291 SDValue SystemZTargetLowering::lowerSETCC(SDValue Op,
2292 SelectionDAG &DAG) const {
2293 SDValue CmpOp0 = Op.getOperand(0);
2294 SDValue CmpOp1 = Op.getOperand(1);
2295 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
2297 EVT VT = Op.getValueType();
2299 return lowerVectorSETCC(DAG, DL, VT, CC, CmpOp0, CmpOp1);
2301 Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC, DL));
2302 SDValue Glue = emitCmp(DAG, DL, C);
2303 return emitSETCC(DAG, DL, Glue, C.CCValid, C.CCMask);
2306 SDValue SystemZTargetLowering::lowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
2307 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2308 SDValue CmpOp0 = Op.getOperand(2);
2309 SDValue CmpOp1 = Op.getOperand(3);
2310 SDValue Dest = Op.getOperand(4);
2313 Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC, DL));
2314 SDValue Glue = emitCmp(DAG, DL, C);
2315 return DAG.getNode(SystemZISD::BR_CCMASK, DL, Op.getValueType(),
2316 Op.getOperand(0), DAG.getConstant(C.CCValid, DL, MVT::i32),
2317 DAG.getConstant(C.CCMask, DL, MVT::i32), Dest, Glue);
2320 // Return true if Pos is CmpOp and Neg is the negative of CmpOp,
2321 // allowing Pos and Neg to be wider than CmpOp.
2322 static bool isAbsolute(SDValue CmpOp, SDValue Pos, SDValue Neg) {
2323 return (Neg.getOpcode() == ISD::SUB &&
2324 Neg.getOperand(0).getOpcode() == ISD::Constant &&
2325 cast<ConstantSDNode>(Neg.getOperand(0))->getZExtValue() == 0 &&
2326 Neg.getOperand(1) == Pos &&
2328 (Pos.getOpcode() == ISD::SIGN_EXTEND &&
2329 Pos.getOperand(0) == CmpOp)));
2332 // Return the absolute or negative absolute of Op; IsNegative decides which.
2333 static SDValue getAbsolute(SelectionDAG &DAG, SDLoc DL, SDValue Op,
2335 Op = DAG.getNode(SystemZISD::IABS, DL, Op.getValueType(), Op);
2337 Op = DAG.getNode(ISD::SUB, DL, Op.getValueType(),
2338 DAG.getConstant(0, DL, Op.getValueType()), Op);
2342 SDValue SystemZTargetLowering::lowerSELECT_CC(SDValue Op,
2343 SelectionDAG &DAG) const {
2344 SDValue CmpOp0 = Op.getOperand(0);
2345 SDValue CmpOp1 = Op.getOperand(1);
2346 SDValue TrueOp = Op.getOperand(2);
2347 SDValue FalseOp = Op.getOperand(3);
2348 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2351 Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC, DL));
2353 // Check for absolute and negative-absolute selections, including those
2354 // where the comparison value is sign-extended (for LPGFR and LNGFR).
2355 // This check supplements the one in DAGCombiner.
2356 if (C.Opcode == SystemZISD::ICMP &&
2357 C.CCMask != SystemZ::CCMASK_CMP_EQ &&
2358 C.CCMask != SystemZ::CCMASK_CMP_NE &&
2359 C.Op1.getOpcode() == ISD::Constant &&
2360 cast<ConstantSDNode>(C.Op1)->getZExtValue() == 0) {
2361 if (isAbsolute(C.Op0, TrueOp, FalseOp))
2362 return getAbsolute(DAG, DL, TrueOp, C.CCMask & SystemZ::CCMASK_CMP_LT);
2363 if (isAbsolute(C.Op0, FalseOp, TrueOp))
2364 return getAbsolute(DAG, DL, FalseOp, C.CCMask & SystemZ::CCMASK_CMP_GT);
2367 SDValue Glue = emitCmp(DAG, DL, C);
2369 // Special case for handling -1/0 results. The shifts we use here
2370 // should get optimized with the IPM conversion sequence.
2371 auto *TrueC = dyn_cast<ConstantSDNode>(TrueOp);
2372 auto *FalseC = dyn_cast<ConstantSDNode>(FalseOp);
2373 if (TrueC && FalseC) {
2374 int64_t TrueVal = TrueC->getSExtValue();
2375 int64_t FalseVal = FalseC->getSExtValue();
2376 if ((TrueVal == -1 && FalseVal == 0) || (TrueVal == 0 && FalseVal == -1)) {
2377 // Invert the condition if we want -1 on false.
2379 C.CCMask ^= C.CCValid;
2380 SDValue Result = emitSETCC(DAG, DL, Glue, C.CCValid, C.CCMask);
2381 EVT VT = Op.getValueType();
2382 // Extend the result to VT. Upper bits are ignored.
2384 Result = DAG.getNode(ISD::ANY_EXTEND, DL, VT, Result);
2385 // Sign-extend from the low bit.
2386 SDValue ShAmt = DAG.getConstant(VT.getSizeInBits() - 1, DL, MVT::i32);
2387 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, Result, ShAmt);
2388 return DAG.getNode(ISD::SRA, DL, VT, Shl, ShAmt);
2392 SDValue Ops[] = {TrueOp, FalseOp, DAG.getConstant(C.CCValid, DL, MVT::i32),
2393 DAG.getConstant(C.CCMask, DL, MVT::i32), Glue};
2395 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
2396 return DAG.getNode(SystemZISD::SELECT_CCMASK, DL, VTs, Ops);
2399 SDValue SystemZTargetLowering::lowerGlobalAddress(GlobalAddressSDNode *Node,
2400 SelectionDAG &DAG) const {
2402 const GlobalValue *GV = Node->getGlobal();
2403 int64_t Offset = Node->getOffset();
2404 EVT PtrVT = getPointerTy();
2405 Reloc::Model RM = DAG.getTarget().getRelocationModel();
2406 CodeModel::Model CM = DAG.getTarget().getCodeModel();
2409 if (Subtarget.isPC32DBLSymbol(GV, RM, CM)) {
2410 // Assign anchors at 1<<12 byte boundaries.
2411 uint64_t Anchor = Offset & ~uint64_t(0xfff);
2412 Result = DAG.getTargetGlobalAddress(GV, DL, PtrVT, Anchor);
2413 Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
2415 // The offset can be folded into the address if it is aligned to a halfword.
2417 if (Offset != 0 && (Offset & 1) == 0) {
2418 SDValue Full = DAG.getTargetGlobalAddress(GV, DL, PtrVT, Anchor + Offset);
2419 Result = DAG.getNode(SystemZISD::PCREL_OFFSET, DL, PtrVT, Full, Result);
2423 Result = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, SystemZII::MO_GOT);
2424 Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
2425 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
2426 MachinePointerInfo::getGOT(), false, false, false, 0);
2429 // If there was a non-zero offset that we didn't fold, create an explicit
2432 Result = DAG.getNode(ISD::ADD, DL, PtrVT, Result,
2433 DAG.getConstant(Offset, DL, PtrVT));
2438 SDValue SystemZTargetLowering::lowerTLSGetOffset(GlobalAddressSDNode *Node,
2441 SDValue GOTOffset) const {
2443 EVT PtrVT = getPointerTy();
2444 SDValue Chain = DAG.getEntryNode();
2447 // __tls_get_offset takes the GOT offset in %r2 and the GOT in %r12.
2448 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
2449 Chain = DAG.getCopyToReg(Chain, DL, SystemZ::R12D, GOT, Glue);
2450 Glue = Chain.getValue(1);
2451 Chain = DAG.getCopyToReg(Chain, DL, SystemZ::R2D, GOTOffset, Glue);
2452 Glue = Chain.getValue(1);
2454 // The first call operand is the chain and the second is the TLS symbol.
2455 SmallVector<SDValue, 8> Ops;
2456 Ops.push_back(Chain);
2457 Ops.push_back(DAG.getTargetGlobalAddress(Node->getGlobal(), DL,
2458 Node->getValueType(0),
2461 // Add argument registers to the end of the list so that they are
2462 // known live into the call.
2463 Ops.push_back(DAG.getRegister(SystemZ::R2D, PtrVT));
2464 Ops.push_back(DAG.getRegister(SystemZ::R12D, PtrVT));
2466 // Add a register mask operand representing the call-preserved registers.
2467 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
2468 const uint32_t *Mask =
2469 TRI->getCallPreservedMask(DAG.getMachineFunction(), CallingConv::C);
2470 assert(Mask && "Missing call preserved mask for calling convention");
2471 Ops.push_back(DAG.getRegisterMask(Mask));
2473 // Glue the call to the argument copies.
2474 Ops.push_back(Glue);
2477 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2478 Chain = DAG.getNode(Opcode, DL, NodeTys, Ops);
2479 Glue = Chain.getValue(1);
2481 // Copy the return value from %r2.
2482 return DAG.getCopyFromReg(Chain, DL, SystemZ::R2D, PtrVT, Glue);
2485 SDValue SystemZTargetLowering::lowerGlobalTLSAddress(GlobalAddressSDNode *Node,
2486 SelectionDAG &DAG) const {
2488 const GlobalValue *GV = Node->getGlobal();
2489 EVT PtrVT = getPointerTy();
2490 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
2492 // The high part of the thread pointer is in access register 0.
2493 SDValue TPHi = DAG.getNode(SystemZISD::EXTRACT_ACCESS, DL, MVT::i32,
2494 DAG.getConstant(0, DL, MVT::i32));
2495 TPHi = DAG.getNode(ISD::ANY_EXTEND, DL, PtrVT, TPHi);
2497 // The low part of the thread pointer is in access register 1.
2498 SDValue TPLo = DAG.getNode(SystemZISD::EXTRACT_ACCESS, DL, MVT::i32,
2499 DAG.getConstant(1, DL, MVT::i32));
2500 TPLo = DAG.getNode(ISD::ZERO_EXTEND, DL, PtrVT, TPLo);
2502 // Merge them into a single 64-bit address.
2503 SDValue TPHiShifted = DAG.getNode(ISD::SHL, DL, PtrVT, TPHi,
2504 DAG.getConstant(32, DL, PtrVT));
2505 SDValue TP = DAG.getNode(ISD::OR, DL, PtrVT, TPHiShifted, TPLo);
2507 // Get the offset of GA from the thread pointer, based on the TLS model.
2510 case TLSModel::GeneralDynamic: {
2511 // Load the GOT offset of the tls_index (module ID / per-symbol offset).
2512 SystemZConstantPoolValue *CPV =
2513 SystemZConstantPoolValue::Create(GV, SystemZCP::TLSGD);
2515 Offset = DAG.getConstantPool(CPV, PtrVT, 8);
2516 Offset = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(),
2517 Offset, MachinePointerInfo::getConstantPool(),
2518 false, false, false, 0);
2520 // Call __tls_get_offset to retrieve the offset.
2521 Offset = lowerTLSGetOffset(Node, DAG, SystemZISD::TLS_GDCALL, Offset);
2525 case TLSModel::LocalDynamic: {
2526 // Load the GOT offset of the module ID.
2527 SystemZConstantPoolValue *CPV =
2528 SystemZConstantPoolValue::Create(GV, SystemZCP::TLSLDM);
2530 Offset = DAG.getConstantPool(CPV, PtrVT, 8);
2531 Offset = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(),
2532 Offset, MachinePointerInfo::getConstantPool(),
2533 false, false, false, 0);
2535 // Call __tls_get_offset to retrieve the module base offset.
2536 Offset = lowerTLSGetOffset(Node, DAG, SystemZISD::TLS_LDCALL, Offset);
2538 // Note: The SystemZLDCleanupPass will remove redundant computations
2539 // of the module base offset. Count total number of local-dynamic
2540 // accesses to trigger execution of that pass.
2541 SystemZMachineFunctionInfo* MFI =
2542 DAG.getMachineFunction().getInfo<SystemZMachineFunctionInfo>();
2543 MFI->incNumLocalDynamicTLSAccesses();
2545 // Add the per-symbol offset.
2546 CPV = SystemZConstantPoolValue::Create(GV, SystemZCP::DTPOFF);
2548 SDValue DTPOffset = DAG.getConstantPool(CPV, PtrVT, 8);
2549 DTPOffset = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(),
2550 DTPOffset, MachinePointerInfo::getConstantPool(),
2551 false, false, false, 0);
2553 Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Offset, DTPOffset);
2557 case TLSModel::InitialExec: {
2558 // Load the offset from the GOT.
2559 Offset = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2560 SystemZII::MO_INDNTPOFF);
2561 Offset = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Offset);
2562 Offset = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(),
2563 Offset, MachinePointerInfo::getGOT(),
2564 false, false, false, 0);
2568 case TLSModel::LocalExec: {
2569 // Force the offset into the constant pool and load it from there.
2570 SystemZConstantPoolValue *CPV =
2571 SystemZConstantPoolValue::Create(GV, SystemZCP::NTPOFF);
2573 Offset = DAG.getConstantPool(CPV, PtrVT, 8);
2574 Offset = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(),
2575 Offset, MachinePointerInfo::getConstantPool(),
2576 false, false, false, 0);
2581 // Add the base and offset together.
2582 return DAG.getNode(ISD::ADD, DL, PtrVT, TP, Offset);
2585 SDValue SystemZTargetLowering::lowerBlockAddress(BlockAddressSDNode *Node,
2586 SelectionDAG &DAG) const {
2588 const BlockAddress *BA = Node->getBlockAddress();
2589 int64_t Offset = Node->getOffset();
2590 EVT PtrVT = getPointerTy();
2592 SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT, Offset);
2593 Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
2597 SDValue SystemZTargetLowering::lowerJumpTable(JumpTableSDNode *JT,
2598 SelectionDAG &DAG) const {
2600 EVT PtrVT = getPointerTy();
2601 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
2603 // Use LARL to load the address of the table.
2604 return DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
2607 SDValue SystemZTargetLowering::lowerConstantPool(ConstantPoolSDNode *CP,
2608 SelectionDAG &DAG) const {
2610 EVT PtrVT = getPointerTy();
2613 if (CP->isMachineConstantPoolEntry())
2614 Result = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
2615 CP->getAlignment());
2617 Result = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
2618 CP->getAlignment(), CP->getOffset());
2620 // Use LARL to load the address of the constant pool entry.
2621 return DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
2624 SDValue SystemZTargetLowering::lowerBITCAST(SDValue Op,
2625 SelectionDAG &DAG) const {
2627 SDValue In = Op.getOperand(0);
2628 EVT InVT = In.getValueType();
2629 EVT ResVT = Op.getValueType();
2631 // Convert loads directly. This is normally done by DAGCombiner,
2632 // but we need this case for bitcasts that are created during lowering
2633 // and which are then lowered themselves.
2634 if (auto *LoadN = dyn_cast<LoadSDNode>(In))
2635 return DAG.getLoad(ResVT, DL, LoadN->getChain(), LoadN->getBasePtr(),
2636 LoadN->getMemOperand());
2638 if (InVT == MVT::i32 && ResVT == MVT::f32) {
2640 if (Subtarget.hasHighWord()) {
2641 SDNode *U64 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL,
2643 In64 = DAG.getTargetInsertSubreg(SystemZ::subreg_h32, DL,
2644 MVT::i64, SDValue(U64, 0), In);
2646 In64 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, In);
2647 In64 = DAG.getNode(ISD::SHL, DL, MVT::i64, In64,
2648 DAG.getConstant(32, DL, MVT::i64));
2650 SDValue Out64 = DAG.getNode(ISD::BITCAST, DL, MVT::f64, In64);
2651 return DAG.getTargetExtractSubreg(SystemZ::subreg_r32,
2652 DL, MVT::f32, Out64);
2654 if (InVT == MVT::f32 && ResVT == MVT::i32) {
2655 SDNode *U64 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, MVT::f64);
2656 SDValue In64 = DAG.getTargetInsertSubreg(SystemZ::subreg_r32, DL,
2657 MVT::f64, SDValue(U64, 0), In);
2658 SDValue Out64 = DAG.getNode(ISD::BITCAST, DL, MVT::i64, In64);
2659 if (Subtarget.hasHighWord())
2660 return DAG.getTargetExtractSubreg(SystemZ::subreg_h32, DL,
2662 SDValue Shift = DAG.getNode(ISD::SRL, DL, MVT::i64, Out64,
2663 DAG.getConstant(32, DL, MVT::i64));
2664 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Shift);
2666 llvm_unreachable("Unexpected bitcast combination");
2669 SDValue SystemZTargetLowering::lowerVASTART(SDValue Op,
2670 SelectionDAG &DAG) const {
2671 MachineFunction &MF = DAG.getMachineFunction();
2672 SystemZMachineFunctionInfo *FuncInfo =
2673 MF.getInfo<SystemZMachineFunctionInfo>();
2674 EVT PtrVT = getPointerTy();
2676 SDValue Chain = Op.getOperand(0);
2677 SDValue Addr = Op.getOperand(1);
2678 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2681 // The initial values of each field.
2682 const unsigned NumFields = 4;
2683 SDValue Fields[NumFields] = {
2684 DAG.getConstant(FuncInfo->getVarArgsFirstGPR(), DL, PtrVT),
2685 DAG.getConstant(FuncInfo->getVarArgsFirstFPR(), DL, PtrVT),
2686 DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT),
2687 DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), PtrVT)
2690 // Store each field into its respective slot.
2691 SDValue MemOps[NumFields];
2692 unsigned Offset = 0;
2693 for (unsigned I = 0; I < NumFields; ++I) {
2694 SDValue FieldAddr = Addr;
2696 FieldAddr = DAG.getNode(ISD::ADD, DL, PtrVT, FieldAddr,
2697 DAG.getIntPtrConstant(Offset, DL));
2698 MemOps[I] = DAG.getStore(Chain, DL, Fields[I], FieldAddr,
2699 MachinePointerInfo(SV, Offset),
2703 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
2706 SDValue SystemZTargetLowering::lowerVACOPY(SDValue Op,
2707 SelectionDAG &DAG) const {
2708 SDValue Chain = Op.getOperand(0);
2709 SDValue DstPtr = Op.getOperand(1);
2710 SDValue SrcPtr = Op.getOperand(2);
2711 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
2712 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
2715 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr, DAG.getIntPtrConstant(32, DL),
2716 /*Align*/8, /*isVolatile*/false, /*AlwaysInline*/false,
2717 /*isTailCall*/false,
2718 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
2721 SDValue SystemZTargetLowering::
2722 lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const {
2723 SDValue Chain = Op.getOperand(0);
2724 SDValue Size = Op.getOperand(1);
2727 unsigned SPReg = getStackPointerRegisterToSaveRestore();
2729 // Get a reference to the stack pointer.
2730 SDValue OldSP = DAG.getCopyFromReg(Chain, DL, SPReg, MVT::i64);
2732 // Get the new stack pointer value.
2733 SDValue NewSP = DAG.getNode(ISD::SUB, DL, MVT::i64, OldSP, Size);
2735 // Copy the new stack pointer back.
2736 Chain = DAG.getCopyToReg(Chain, DL, SPReg, NewSP);
2738 // The allocated data lives above the 160 bytes allocated for the standard
2739 // frame, plus any outgoing stack arguments. We don't know how much that
2740 // amounts to yet, so emit a special ADJDYNALLOC placeholder.
2741 SDValue ArgAdjust = DAG.getNode(SystemZISD::ADJDYNALLOC, DL, MVT::i64);
2742 SDValue Result = DAG.getNode(ISD::ADD, DL, MVT::i64, NewSP, ArgAdjust);
2744 SDValue Ops[2] = { Result, Chain };
2745 return DAG.getMergeValues(Ops, DL);
2748 SDValue SystemZTargetLowering::lowerSMUL_LOHI(SDValue Op,
2749 SelectionDAG &DAG) const {
2750 EVT VT = Op.getValueType();
2754 // Just do a normal 64-bit multiplication and extract the results.
2755 // We define this so that it can be used for constant division.
2756 lowerMUL_LOHI32(DAG, DL, ISD::SIGN_EXTEND, Op.getOperand(0),
2757 Op.getOperand(1), Ops[1], Ops[0]);
2759 // Do a full 128-bit multiplication based on UMUL_LOHI64:
2761 // (ll * rl) + ((lh * rl) << 64) + ((ll * rh) << 64)
2763 // but using the fact that the upper halves are either all zeros
2766 // (ll * rl) - ((lh & rl) << 64) - ((ll & rh) << 64)
2768 // and grouping the right terms together since they are quicker than the
2771 // (ll * rl) - (((lh & rl) + (ll & rh)) << 64)
2772 SDValue C63 = DAG.getConstant(63, DL, MVT::i64);
2773 SDValue LL = Op.getOperand(0);
2774 SDValue RL = Op.getOperand(1);
2775 SDValue LH = DAG.getNode(ISD::SRA, DL, VT, LL, C63);
2776 SDValue RH = DAG.getNode(ISD::SRA, DL, VT, RL, C63);
2777 // UMUL_LOHI64 returns the low result in the odd register and the high
2778 // result in the even register. SMUL_LOHI is defined to return the
2779 // low half first, so the results are in reverse order.
2780 lowerGR128Binary(DAG, DL, VT, SystemZ::AEXT128_64, SystemZISD::UMUL_LOHI64,
2781 LL, RL, Ops[1], Ops[0]);
2782 SDValue NegLLTimesRH = DAG.getNode(ISD::AND, DL, VT, LL, RH);
2783 SDValue NegLHTimesRL = DAG.getNode(ISD::AND, DL, VT, LH, RL);
2784 SDValue NegSum = DAG.getNode(ISD::ADD, DL, VT, NegLLTimesRH, NegLHTimesRL);
2785 Ops[1] = DAG.getNode(ISD::SUB, DL, VT, Ops[1], NegSum);
2787 return DAG.getMergeValues(Ops, DL);
2790 SDValue SystemZTargetLowering::lowerUMUL_LOHI(SDValue Op,
2791 SelectionDAG &DAG) const {
2792 EVT VT = Op.getValueType();
2796 // Just do a normal 64-bit multiplication and extract the results.
2797 // We define this so that it can be used for constant division.
2798 lowerMUL_LOHI32(DAG, DL, ISD::ZERO_EXTEND, Op.getOperand(0),
2799 Op.getOperand(1), Ops[1], Ops[0]);
2801 // UMUL_LOHI64 returns the low result in the odd register and the high
2802 // result in the even register. UMUL_LOHI is defined to return the
2803 // low half first, so the results are in reverse order.
2804 lowerGR128Binary(DAG, DL, VT, SystemZ::AEXT128_64, SystemZISD::UMUL_LOHI64,
2805 Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
2806 return DAG.getMergeValues(Ops, DL);
2809 SDValue SystemZTargetLowering::lowerSDIVREM(SDValue Op,
2810 SelectionDAG &DAG) const {
2811 SDValue Op0 = Op.getOperand(0);
2812 SDValue Op1 = Op.getOperand(1);
2813 EVT VT = Op.getValueType();
2817 // We use DSGF for 32-bit division.
2819 Op0 = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i64, Op0);
2820 Opcode = SystemZISD::SDIVREM32;
2821 } else if (DAG.ComputeNumSignBits(Op1) > 32) {
2822 Op1 = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Op1);
2823 Opcode = SystemZISD::SDIVREM32;
2825 Opcode = SystemZISD::SDIVREM64;
2827 // DSG(F) takes a 64-bit dividend, so the even register in the GR128
2828 // input is "don't care". The instruction returns the remainder in
2829 // the even register and the quotient in the odd register.
2831 lowerGR128Binary(DAG, DL, VT, SystemZ::AEXT128_64, Opcode,
2832 Op0, Op1, Ops[1], Ops[0]);
2833 return DAG.getMergeValues(Ops, DL);
2836 SDValue SystemZTargetLowering::lowerUDIVREM(SDValue Op,
2837 SelectionDAG &DAG) const {
2838 EVT VT = Op.getValueType();
2841 // DL(G) uses a double-width dividend, so we need to clear the even
2842 // register in the GR128 input. The instruction returns the remainder
2843 // in the even register and the quotient in the odd register.
2846 lowerGR128Binary(DAG, DL, VT, SystemZ::ZEXT128_32, SystemZISD::UDIVREM32,
2847 Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
2849 lowerGR128Binary(DAG, DL, VT, SystemZ::ZEXT128_64, SystemZISD::UDIVREM64,
2850 Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
2851 return DAG.getMergeValues(Ops, DL);
2854 SDValue SystemZTargetLowering::lowerOR(SDValue Op, SelectionDAG &DAG) const {
2855 assert(Op.getValueType() == MVT::i64 && "Should be 64-bit operation");
2857 // Get the known-zero masks for each operand.
2858 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1) };
2859 APInt KnownZero[2], KnownOne[2];
2860 DAG.computeKnownBits(Ops[0], KnownZero[0], KnownOne[0]);
2861 DAG.computeKnownBits(Ops[1], KnownZero[1], KnownOne[1]);
2863 // See if the upper 32 bits of one operand and the lower 32 bits of the
2864 // other are known zero. They are the low and high operands respectively.
2865 uint64_t Masks[] = { KnownZero[0].getZExtValue(),
2866 KnownZero[1].getZExtValue() };
2868 if ((Masks[0] >> 32) == 0xffffffff && uint32_t(Masks[1]) == 0xffffffff)
2870 else if ((Masks[1] >> 32) == 0xffffffff && uint32_t(Masks[0]) == 0xffffffff)
2875 SDValue LowOp = Ops[Low];
2876 SDValue HighOp = Ops[High];
2878 // If the high part is a constant, we're better off using IILH.
2879 if (HighOp.getOpcode() == ISD::Constant)
2882 // If the low part is a constant that is outside the range of LHI,
2883 // then we're better off using IILF.
2884 if (LowOp.getOpcode() == ISD::Constant) {
2885 int64_t Value = int32_t(cast<ConstantSDNode>(LowOp)->getZExtValue());
2886 if (!isInt<16>(Value))
2890 // Check whether the high part is an AND that doesn't change the
2891 // high 32 bits and just masks out low bits. We can skip it if so.
2892 if (HighOp.getOpcode() == ISD::AND &&
2893 HighOp.getOperand(1).getOpcode() == ISD::Constant) {
2894 SDValue HighOp0 = HighOp.getOperand(0);
2895 uint64_t Mask = cast<ConstantSDNode>(HighOp.getOperand(1))->getZExtValue();
2896 if (DAG.MaskedValueIsZero(HighOp0, APInt(64, ~(Mask | 0xffffffff))))
2900 // Take advantage of the fact that all GR32 operations only change the
2901 // low 32 bits by truncating Low to an i32 and inserting it directly
2902 // using a subreg. The interesting cases are those where the truncation
2905 SDValue Low32 = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, LowOp);
2906 return DAG.getTargetInsertSubreg(SystemZ::subreg_l32, DL,
2907 MVT::i64, HighOp, Low32);
2910 SDValue SystemZTargetLowering::lowerCTPOP(SDValue Op,
2911 SelectionDAG &DAG) const {
2912 EVT VT = Op.getValueType();
2914 Op = Op.getOperand(0);
2916 // Handle vector types via VPOPCT.
2917 if (VT.isVector()) {
2918 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Op);
2919 Op = DAG.getNode(SystemZISD::POPCNT, DL, MVT::v16i8, Op);
2920 switch (VT.getVectorElementType().getSizeInBits()) {
2924 Op = DAG.getNode(ISD::BITCAST, DL, VT, Op);
2925 SDValue Shift = DAG.getConstant(8, DL, MVT::i32);
2926 SDValue Tmp = DAG.getNode(SystemZISD::VSHL_BY_SCALAR, DL, VT, Op, Shift);
2927 Op = DAG.getNode(ISD::ADD, DL, VT, Op, Tmp);
2928 Op = DAG.getNode(SystemZISD::VSRL_BY_SCALAR, DL, VT, Op, Shift);
2932 SDValue Tmp = DAG.getNode(SystemZISD::BYTE_MASK, DL, MVT::v16i8,
2933 DAG.getConstant(0, DL, MVT::i32));
2934 Op = DAG.getNode(SystemZISD::VSUM, DL, VT, Op, Tmp);
2938 SDValue Tmp = DAG.getNode(SystemZISD::BYTE_MASK, DL, MVT::v16i8,
2939 DAG.getConstant(0, DL, MVT::i32));
2940 Op = DAG.getNode(SystemZISD::VSUM, DL, MVT::v4i32, Op, Tmp);
2941 Op = DAG.getNode(SystemZISD::VSUM, DL, VT, Op, Tmp);
2945 llvm_unreachable("Unexpected type");
2950 // Get the known-zero mask for the operand.
2951 APInt KnownZero, KnownOne;
2952 DAG.computeKnownBits(Op, KnownZero, KnownOne);
2953 unsigned NumSignificantBits = (~KnownZero).getActiveBits();
2954 if (NumSignificantBits == 0)
2955 return DAG.getConstant(0, DL, VT);
2957 // Skip known-zero high parts of the operand.
2958 int64_t OrigBitSize = VT.getSizeInBits();
2959 int64_t BitSize = (int64_t)1 << Log2_32_Ceil(NumSignificantBits);
2960 BitSize = std::min(BitSize, OrigBitSize);
2962 // The POPCNT instruction counts the number of bits in each byte.
2963 Op = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op);
2964 Op = DAG.getNode(SystemZISD::POPCNT, DL, MVT::i64, Op);
2965 Op = DAG.getNode(ISD::TRUNCATE, DL, VT, Op);
2967 // Add up per-byte counts in a binary tree. All bits of Op at
2968 // position larger than BitSize remain zero throughout.
2969 for (int64_t I = BitSize / 2; I >= 8; I = I / 2) {
2970 SDValue Tmp = DAG.getNode(ISD::SHL, DL, VT, Op, DAG.getConstant(I, DL, VT));
2971 if (BitSize != OrigBitSize)
2972 Tmp = DAG.getNode(ISD::AND, DL, VT, Tmp,
2973 DAG.getConstant(((uint64_t)1 << BitSize) - 1, DL, VT));
2974 Op = DAG.getNode(ISD::ADD, DL, VT, Op, Tmp);
2977 // Extract overall result from high byte.
2979 Op = DAG.getNode(ISD::SRL, DL, VT, Op,
2980 DAG.getConstant(BitSize - 8, DL, VT));
2985 // Op is an atomic load. Lower it into a normal volatile load.
2986 SDValue SystemZTargetLowering::lowerATOMIC_LOAD(SDValue Op,
2987 SelectionDAG &DAG) const {
2988 auto *Node = cast<AtomicSDNode>(Op.getNode());
2989 return DAG.getExtLoad(ISD::EXTLOAD, SDLoc(Op), Op.getValueType(),
2990 Node->getChain(), Node->getBasePtr(),
2991 Node->getMemoryVT(), Node->getMemOperand());
2994 // Op is an atomic store. Lower it into a normal volatile store followed
2995 // by a serialization.
2996 SDValue SystemZTargetLowering::lowerATOMIC_STORE(SDValue Op,
2997 SelectionDAG &DAG) const {
2998 auto *Node = cast<AtomicSDNode>(Op.getNode());
2999 SDValue Chain = DAG.getTruncStore(Node->getChain(), SDLoc(Op), Node->getVal(),
3000 Node->getBasePtr(), Node->getMemoryVT(),
3001 Node->getMemOperand());
3002 return SDValue(DAG.getMachineNode(SystemZ::Serialize, SDLoc(Op), MVT::Other,
3006 // Op is an 8-, 16-bit or 32-bit ATOMIC_LOAD_* operation. Lower the first
3007 // two into the fullword ATOMIC_LOADW_* operation given by Opcode.
3008 SDValue SystemZTargetLowering::lowerATOMIC_LOAD_OP(SDValue Op,
3010 unsigned Opcode) const {
3011 auto *Node = cast<AtomicSDNode>(Op.getNode());
3013 // 32-bit operations need no code outside the main loop.
3014 EVT NarrowVT = Node->getMemoryVT();
3015 EVT WideVT = MVT::i32;
3016 if (NarrowVT == WideVT)
3019 int64_t BitSize = NarrowVT.getSizeInBits();
3020 SDValue ChainIn = Node->getChain();
3021 SDValue Addr = Node->getBasePtr();
3022 SDValue Src2 = Node->getVal();
3023 MachineMemOperand *MMO = Node->getMemOperand();
3025 EVT PtrVT = Addr.getValueType();
3027 // Convert atomic subtracts of constants into additions.
3028 if (Opcode == SystemZISD::ATOMIC_LOADW_SUB)
3029 if (auto *Const = dyn_cast<ConstantSDNode>(Src2)) {
3030 Opcode = SystemZISD::ATOMIC_LOADW_ADD;
3031 Src2 = DAG.getConstant(-Const->getSExtValue(), DL, Src2.getValueType());
3034 // Get the address of the containing word.
3035 SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr,
3036 DAG.getConstant(-4, DL, PtrVT));
3038 // Get the number of bits that the word must be rotated left in order
3039 // to bring the field to the top bits of a GR32.
3040 SDValue BitShift = DAG.getNode(ISD::SHL, DL, PtrVT, Addr,
3041 DAG.getConstant(3, DL, PtrVT));
3042 BitShift = DAG.getNode(ISD::TRUNCATE, DL, WideVT, BitShift);
3044 // Get the complementing shift amount, for rotating a field in the top
3045 // bits back to its proper position.
3046 SDValue NegBitShift = DAG.getNode(ISD::SUB, DL, WideVT,
3047 DAG.getConstant(0, DL, WideVT), BitShift);
3049 // Extend the source operand to 32 bits and prepare it for the inner loop.
3050 // ATOMIC_SWAPW uses RISBG to rotate the field left, but all other
3051 // operations require the source to be shifted in advance. (This shift
3052 // can be folded if the source is constant.) For AND and NAND, the lower
3053 // bits must be set, while for other opcodes they should be left clear.
3054 if (Opcode != SystemZISD::ATOMIC_SWAPW)
3055 Src2 = DAG.getNode(ISD::SHL, DL, WideVT, Src2,
3056 DAG.getConstant(32 - BitSize, DL, WideVT));
3057 if (Opcode == SystemZISD::ATOMIC_LOADW_AND ||
3058 Opcode == SystemZISD::ATOMIC_LOADW_NAND)
3059 Src2 = DAG.getNode(ISD::OR, DL, WideVT, Src2,
3060 DAG.getConstant(uint32_t(-1) >> BitSize, DL, WideVT));
3062 // Construct the ATOMIC_LOADW_* node.
3063 SDVTList VTList = DAG.getVTList(WideVT, MVT::Other);
3064 SDValue Ops[] = { ChainIn, AlignedAddr, Src2, BitShift, NegBitShift,
3065 DAG.getConstant(BitSize, DL, WideVT) };
3066 SDValue AtomicOp = DAG.getMemIntrinsicNode(Opcode, DL, VTList, Ops,
3069 // Rotate the result of the final CS so that the field is in the lower
3070 // bits of a GR32, then truncate it.
3071 SDValue ResultShift = DAG.getNode(ISD::ADD, DL, WideVT, BitShift,
3072 DAG.getConstant(BitSize, DL, WideVT));
3073 SDValue Result = DAG.getNode(ISD::ROTL, DL, WideVT, AtomicOp, ResultShift);
3075 SDValue RetOps[2] = { Result, AtomicOp.getValue(1) };
3076 return DAG.getMergeValues(RetOps, DL);
3079 // Op is an ATOMIC_LOAD_SUB operation. Lower 8- and 16-bit operations
3080 // into ATOMIC_LOADW_SUBs and decide whether to convert 32- and 64-bit
3081 // operations into additions.
3082 SDValue SystemZTargetLowering::lowerATOMIC_LOAD_SUB(SDValue Op,
3083 SelectionDAG &DAG) const {
3084 auto *Node = cast<AtomicSDNode>(Op.getNode());
3085 EVT MemVT = Node->getMemoryVT();
3086 if (MemVT == MVT::i32 || MemVT == MVT::i64) {
3087 // A full-width operation.
3088 assert(Op.getValueType() == MemVT && "Mismatched VTs");
3089 SDValue Src2 = Node->getVal();
3093 if (auto *Op2 = dyn_cast<ConstantSDNode>(Src2)) {
3094 // Use an addition if the operand is constant and either LAA(G) is
3095 // available or the negative value is in the range of A(G)FHI.
3096 int64_t Value = (-Op2->getAPIntValue()).getSExtValue();
3097 if (isInt<32>(Value) || Subtarget.hasInterlockedAccess1())
3098 NegSrc2 = DAG.getConstant(Value, DL, MemVT);
3099 } else if (Subtarget.hasInterlockedAccess1())
3100 // Use LAA(G) if available.
3101 NegSrc2 = DAG.getNode(ISD::SUB, DL, MemVT, DAG.getConstant(0, DL, MemVT),
3104 if (NegSrc2.getNode())
3105 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, DL, MemVT,
3106 Node->getChain(), Node->getBasePtr(), NegSrc2,
3107 Node->getMemOperand(), Node->getOrdering(),
3108 Node->getSynchScope());
3110 // Use the node as-is.
3114 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_SUB);
3117 // Node is an 8- or 16-bit ATOMIC_CMP_SWAP operation. Lower the first two
3118 // into a fullword ATOMIC_CMP_SWAPW operation.
3119 SDValue SystemZTargetLowering::lowerATOMIC_CMP_SWAP(SDValue Op,
3120 SelectionDAG &DAG) const {
3121 auto *Node = cast<AtomicSDNode>(Op.getNode());
3123 // We have native support for 32-bit compare and swap.
3124 EVT NarrowVT = Node->getMemoryVT();
3125 EVT WideVT = MVT::i32;
3126 if (NarrowVT == WideVT)
3129 int64_t BitSize = NarrowVT.getSizeInBits();
3130 SDValue ChainIn = Node->getOperand(0);
3131 SDValue Addr = Node->getOperand(1);
3132 SDValue CmpVal = Node->getOperand(2);
3133 SDValue SwapVal = Node->getOperand(3);
3134 MachineMemOperand *MMO = Node->getMemOperand();
3136 EVT PtrVT = Addr.getValueType();
3138 // Get the address of the containing word.
3139 SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr,
3140 DAG.getConstant(-4, DL, PtrVT));
3142 // Get the number of bits that the word must be rotated left in order
3143 // to bring the field to the top bits of a GR32.
3144 SDValue BitShift = DAG.getNode(ISD::SHL, DL, PtrVT, Addr,
3145 DAG.getConstant(3, DL, PtrVT));
3146 BitShift = DAG.getNode(ISD::TRUNCATE, DL, WideVT, BitShift);
3148 // Get the complementing shift amount, for rotating a field in the top
3149 // bits back to its proper position.
3150 SDValue NegBitShift = DAG.getNode(ISD::SUB, DL, WideVT,
3151 DAG.getConstant(0, DL, WideVT), BitShift);
3153 // Construct the ATOMIC_CMP_SWAPW node.
3154 SDVTList VTList = DAG.getVTList(WideVT, MVT::Other);
3155 SDValue Ops[] = { ChainIn, AlignedAddr, CmpVal, SwapVal, BitShift,
3156 NegBitShift, DAG.getConstant(BitSize, DL, WideVT) };
3157 SDValue AtomicOp = DAG.getMemIntrinsicNode(SystemZISD::ATOMIC_CMP_SWAPW, DL,
3158 VTList, Ops, NarrowVT, MMO);
3162 SDValue SystemZTargetLowering::lowerSTACKSAVE(SDValue Op,
3163 SelectionDAG &DAG) const {
3164 MachineFunction &MF = DAG.getMachineFunction();
3165 MF.getInfo<SystemZMachineFunctionInfo>()->setManipulatesSP(true);
3166 return DAG.getCopyFromReg(Op.getOperand(0), SDLoc(Op),
3167 SystemZ::R15D, Op.getValueType());
3170 SDValue SystemZTargetLowering::lowerSTACKRESTORE(SDValue Op,
3171 SelectionDAG &DAG) const {
3172 MachineFunction &MF = DAG.getMachineFunction();
3173 MF.getInfo<SystemZMachineFunctionInfo>()->setManipulatesSP(true);
3174 return DAG.getCopyToReg(Op.getOperand(0), SDLoc(Op),
3175 SystemZ::R15D, Op.getOperand(1));
3178 SDValue SystemZTargetLowering::lowerPREFETCH(SDValue Op,
3179 SelectionDAG &DAG) const {
3180 bool IsData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
3182 // Just preserve the chain.
3183 return Op.getOperand(0);
3186 bool IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
3187 unsigned Code = IsWrite ? SystemZ::PFD_WRITE : SystemZ::PFD_READ;
3188 auto *Node = cast<MemIntrinsicSDNode>(Op.getNode());
3191 DAG.getConstant(Code, DL, MVT::i32),
3194 return DAG.getMemIntrinsicNode(SystemZISD::PREFETCH, DL,
3195 Node->getVTList(), Ops,
3196 Node->getMemoryVT(), Node->getMemOperand());
3199 // Return an i32 that contains the value of CC immediately after After,
3200 // whose final operand must be MVT::Glue.
3201 static SDValue getCCResult(SelectionDAG &DAG, SDNode *After) {
3203 SDValue Glue = SDValue(After, After->getNumValues() - 1);
3204 SDValue IPM = DAG.getNode(SystemZISD::IPM, DL, MVT::i32, Glue);
3205 return DAG.getNode(ISD::SRL, DL, MVT::i32, IPM,
3206 DAG.getConstant(SystemZ::IPM_CC, DL, MVT::i32));
3210 SystemZTargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op,
3211 SelectionDAG &DAG) const {
3212 unsigned Opcode, CCValid;
3213 if (isIntrinsicWithCCAndChain(Op, Opcode, CCValid)) {
3214 assert(Op->getNumValues() == 2 && "Expected only CC result and chain");
3215 SDValue Glued = emitIntrinsicWithChainAndGlue(DAG, Op, Opcode);
3216 SDValue CC = getCCResult(DAG, Glued.getNode());
3217 DAG.ReplaceAllUsesOfValueWith(SDValue(Op.getNode(), 0), CC);
3225 SystemZTargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
3226 SelectionDAG &DAG) const {
3227 unsigned Opcode, CCValid;
3228 if (isIntrinsicWithCC(Op, Opcode, CCValid)) {
3229 SDValue Glued = emitIntrinsicWithGlue(DAG, Op, Opcode);
3230 SDValue CC = getCCResult(DAG, Glued.getNode());
3231 if (Op->getNumValues() == 1)
3233 assert(Op->getNumValues() == 2 && "Expected a CC and non-CC result");
3234 return DAG.getNode(ISD::MERGE_VALUES, SDLoc(Op), Op->getVTList(),
3238 unsigned Id = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3240 case Intrinsic::s390_vpdi:
3241 return DAG.getNode(SystemZISD::PERMUTE_DWORDS, SDLoc(Op), Op.getValueType(),
3242 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
3244 case Intrinsic::s390_vperm:
3245 return DAG.getNode(SystemZISD::PERMUTE, SDLoc(Op), Op.getValueType(),
3246 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
3248 case Intrinsic::s390_vuphb:
3249 case Intrinsic::s390_vuphh:
3250 case Intrinsic::s390_vuphf:
3251 return DAG.getNode(SystemZISD::UNPACK_HIGH, SDLoc(Op), Op.getValueType(),
3254 case Intrinsic::s390_vuplhb:
3255 case Intrinsic::s390_vuplhh:
3256 case Intrinsic::s390_vuplhf:
3257 return DAG.getNode(SystemZISD::UNPACKL_HIGH, SDLoc(Op), Op.getValueType(),
3260 case Intrinsic::s390_vuplb:
3261 case Intrinsic::s390_vuplhw:
3262 case Intrinsic::s390_vuplf:
3263 return DAG.getNode(SystemZISD::UNPACK_LOW, SDLoc(Op), Op.getValueType(),
3266 case Intrinsic::s390_vupllb:
3267 case Intrinsic::s390_vupllh:
3268 case Intrinsic::s390_vupllf:
3269 return DAG.getNode(SystemZISD::UNPACKL_LOW, SDLoc(Op), Op.getValueType(),
3272 case Intrinsic::s390_vsumb:
3273 case Intrinsic::s390_vsumh:
3274 case Intrinsic::s390_vsumgh:
3275 case Intrinsic::s390_vsumgf:
3276 case Intrinsic::s390_vsumqf:
3277 case Intrinsic::s390_vsumqg:
3278 return DAG.getNode(SystemZISD::VSUM, SDLoc(Op), Op.getValueType(),
3279 Op.getOperand(1), Op.getOperand(2));
3286 // Says that SystemZISD operation Opcode can be used to perform the equivalent
3287 // of a VPERM with permute vector Bytes. If Opcode takes three operands,
3288 // Operand is the constant third operand, otherwise it is the number of
3289 // bytes in each element of the result.
3293 unsigned char Bytes[SystemZ::VectorBytes];
3297 static const Permute PermuteForms[] = {
3299 { SystemZISD::MERGE_HIGH, 8,
3300 { 0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 23 } },
3302 { SystemZISD::MERGE_HIGH, 4,
3303 { 0, 1, 2, 3, 16, 17, 18, 19, 4, 5, 6, 7, 20, 21, 22, 23 } },
3305 { SystemZISD::MERGE_HIGH, 2,
3306 { 0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23 } },
3308 { SystemZISD::MERGE_HIGH, 1,
3309 { 0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23 } },
3311 { SystemZISD::MERGE_LOW, 8,
3312 { 8, 9, 10, 11, 12, 13, 14, 15, 24, 25, 26, 27, 28, 29, 30, 31 } },
3314 { SystemZISD::MERGE_LOW, 4,
3315 { 8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31 } },
3317 { SystemZISD::MERGE_LOW, 2,
3318 { 8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, 30, 31 } },
3320 { SystemZISD::MERGE_LOW, 1,
3321 { 8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31 } },
3323 { SystemZISD::PACK, 4,
3324 { 4, 5, 6, 7, 12, 13, 14, 15, 20, 21, 22, 23, 28, 29, 30, 31 } },
3326 { SystemZISD::PACK, 2,
3327 { 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31 } },
3329 { SystemZISD::PACK, 1,
3330 { 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 } },
3331 // VPDI V1, V2, 4 (low half of V1, high half of V2)
3332 { SystemZISD::PERMUTE_DWORDS, 4,
3333 { 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 } },
3334 // VPDI V1, V2, 1 (high half of V1, low half of V2)
3335 { SystemZISD::PERMUTE_DWORDS, 1,
3336 { 0, 1, 2, 3, 4, 5, 6, 7, 24, 25, 26, 27, 28, 29, 30, 31 } }
3339 // Called after matching a vector shuffle against a particular pattern.
3340 // Both the original shuffle and the pattern have two vector operands.
3341 // OpNos[0] is the operand of the original shuffle that should be used for
3342 // operand 0 of the pattern, or -1 if operand 0 of the pattern can be anything.
3343 // OpNos[1] is the same for operand 1 of the pattern. Resolve these -1s and
3344 // set OpNo0 and OpNo1 to the shuffle operands that should actually be used
3345 // for operands 0 and 1 of the pattern.
3346 static bool chooseShuffleOpNos(int *OpNos, unsigned &OpNo0, unsigned &OpNo1) {
3350 OpNo0 = OpNo1 = OpNos[1];
3351 } else if (OpNos[1] < 0) {
3352 OpNo0 = OpNo1 = OpNos[0];
3360 // Bytes is a VPERM-like permute vector, except that -1 is used for
3361 // undefined bytes. Return true if the VPERM can be implemented using P.
3362 // When returning true set OpNo0 to the VPERM operand that should be
3363 // used for operand 0 of P and likewise OpNo1 for operand 1 of P.
3365 // For example, if swapping the VPERM operands allows P to match, OpNo0
3366 // will be 1 and OpNo1 will be 0. If instead Bytes only refers to one
3367 // operand, but rewriting it to use two duplicated operands allows it to
3368 // match P, then OpNo0 and OpNo1 will be the same.
3369 static bool matchPermute(const SmallVectorImpl<int> &Bytes, const Permute &P,
3370 unsigned &OpNo0, unsigned &OpNo1) {
3371 int OpNos[] = { -1, -1 };
3372 for (unsigned I = 0; I < SystemZ::VectorBytes; ++I) {
3375 // Make sure that the two permute vectors use the same suboperand
3376 // byte number. Only the operand numbers (the high bits) are
3377 // allowed to differ.
3378 if ((Elt ^ P.Bytes[I]) & (SystemZ::VectorBytes - 1))
3380 int ModelOpNo = P.Bytes[I] / SystemZ::VectorBytes;
3381 int RealOpNo = unsigned(Elt) / SystemZ::VectorBytes;
3382 // Make sure that the operand mappings are consistent with previous
3384 if (OpNos[ModelOpNo] == 1 - RealOpNo)
3386 OpNos[ModelOpNo] = RealOpNo;
3389 return chooseShuffleOpNos(OpNos, OpNo0, OpNo1);
3392 // As above, but search for a matching permute.
3393 static const Permute *matchPermute(const SmallVectorImpl<int> &Bytes,
3394 unsigned &OpNo0, unsigned &OpNo1) {
3395 for (auto &P : PermuteForms)
3396 if (matchPermute(Bytes, P, OpNo0, OpNo1))
3401 // Bytes is a VPERM-like permute vector, except that -1 is used for
3402 // undefined bytes. This permute is an operand of an outer permute.
3403 // See whether redistributing the -1 bytes gives a shuffle that can be
3404 // implemented using P. If so, set Transform to a VPERM-like permute vector
3405 // that, when applied to the result of P, gives the original permute in Bytes.
3406 static bool matchDoublePermute(const SmallVectorImpl<int> &Bytes,
3408 SmallVectorImpl<int> &Transform) {
3410 for (unsigned From = 0; From < SystemZ::VectorBytes; ++From) {
3411 int Elt = Bytes[From];
3413 // Byte number From of the result is undefined.
3414 Transform[From] = -1;
3416 while (P.Bytes[To] != Elt) {
3418 if (To == SystemZ::VectorBytes)
3421 Transform[From] = To;
3427 // As above, but search for a matching permute.
3428 static const Permute *matchDoublePermute(const SmallVectorImpl<int> &Bytes,
3429 SmallVectorImpl<int> &Transform) {
3430 for (auto &P : PermuteForms)
3431 if (matchDoublePermute(Bytes, P, Transform))
3436 // Convert the mask of the given VECTOR_SHUFFLE into a byte-level mask,
3437 // as if it had type vNi8.
3438 static void getVPermMask(ShuffleVectorSDNode *VSN,
3439 SmallVectorImpl<int> &Bytes) {
3440 EVT VT = VSN->getValueType(0);
3441 unsigned NumElements = VT.getVectorNumElements();
3442 unsigned BytesPerElement = VT.getVectorElementType().getStoreSize();
3443 Bytes.resize(NumElements * BytesPerElement, -1);
3444 for (unsigned I = 0; I < NumElements; ++I) {
3445 int Index = VSN->getMaskElt(I);
3447 for (unsigned J = 0; J < BytesPerElement; ++J)
3448 Bytes[I * BytesPerElement + J] = Index * BytesPerElement + J;
3452 // Bytes is a VPERM-like permute vector, except that -1 is used for
3453 // undefined bytes. See whether bytes [Start, Start + BytesPerElement) of
3454 // the result come from a contiguous sequence of bytes from one input.
3455 // Set Base to the selector for the first byte if so.
3456 static bool getShuffleInput(const SmallVectorImpl<int> &Bytes, unsigned Start,
3457 unsigned BytesPerElement, int &Base) {
3459 for (unsigned I = 0; I < BytesPerElement; ++I) {
3460 if (Bytes[Start + I] >= 0) {
3461 unsigned Elem = Bytes[Start + I];
3464 // Make sure the bytes would come from one input operand.
3465 if (unsigned(Base) % Bytes.size() + BytesPerElement > Bytes.size())
3467 } else if (unsigned(Base) != Elem - I)
3474 // Bytes is a VPERM-like permute vector, except that -1 is used for
3475 // undefined bytes. Return true if it can be performed using VSLDI.
3476 // When returning true, set StartIndex to the shift amount and OpNo0
3477 // and OpNo1 to the VPERM operands that should be used as the first
3478 // and second shift operand respectively.
3479 static bool isShlDoublePermute(const SmallVectorImpl<int> &Bytes,
3480 unsigned &StartIndex, unsigned &OpNo0,
3482 int OpNos[] = { -1, -1 };
3484 for (unsigned I = 0; I < 16; ++I) {
3485 int Index = Bytes[I];
3487 int ExpectedShift = (Index - I) % SystemZ::VectorBytes;
3488 int ModelOpNo = unsigned(ExpectedShift + I) / SystemZ::VectorBytes;
3489 int RealOpNo = unsigned(Index) / SystemZ::VectorBytes;
3491 Shift = ExpectedShift;
3492 else if (Shift != ExpectedShift)
3494 // Make sure that the operand mappings are consistent with previous
3496 if (OpNos[ModelOpNo] == 1 - RealOpNo)
3498 OpNos[ModelOpNo] = RealOpNo;
3502 return chooseShuffleOpNos(OpNos, OpNo0, OpNo1);
3505 // Create a node that performs P on operands Op0 and Op1, casting the
3506 // operands to the appropriate type. The type of the result is determined by P.
3507 static SDValue getPermuteNode(SelectionDAG &DAG, SDLoc DL,
3508 const Permute &P, SDValue Op0, SDValue Op1) {
3509 // VPDI (PERMUTE_DWORDS) always operates on v2i64s. The input
3510 // elements of a PACK are twice as wide as the outputs.
3511 unsigned InBytes = (P.Opcode == SystemZISD::PERMUTE_DWORDS ? 8 :
3512 P.Opcode == SystemZISD::PACK ? P.Operand * 2 :
3514 // Cast both operands to the appropriate type.
3515 MVT InVT = MVT::getVectorVT(MVT::getIntegerVT(InBytes * 8),
3516 SystemZ::VectorBytes / InBytes);
3517 Op0 = DAG.getNode(ISD::BITCAST, DL, InVT, Op0);
3518 Op1 = DAG.getNode(ISD::BITCAST, DL, InVT, Op1);
3520 if (P.Opcode == SystemZISD::PERMUTE_DWORDS) {
3521 SDValue Op2 = DAG.getConstant(P.Operand, DL, MVT::i32);
3522 Op = DAG.getNode(SystemZISD::PERMUTE_DWORDS, DL, InVT, Op0, Op1, Op2);
3523 } else if (P.Opcode == SystemZISD::PACK) {
3524 MVT OutVT = MVT::getVectorVT(MVT::getIntegerVT(P.Operand * 8),
3525 SystemZ::VectorBytes / P.Operand);
3526 Op = DAG.getNode(SystemZISD::PACK, DL, OutVT, Op0, Op1);
3528 Op = DAG.getNode(P.Opcode, DL, InVT, Op0, Op1);
3533 // Bytes is a VPERM-like permute vector, except that -1 is used for
3534 // undefined bytes. Implement it on operands Ops[0] and Ops[1] using
3536 static SDValue getGeneralPermuteNode(SelectionDAG &DAG, SDLoc DL, SDValue *Ops,
3537 const SmallVectorImpl<int> &Bytes) {
3538 for (unsigned I = 0; I < 2; ++I)
3539 Ops[I] = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Ops[I]);
3541 // First see whether VSLDI can be used.
3542 unsigned StartIndex, OpNo0, OpNo1;
3543 if (isShlDoublePermute(Bytes, StartIndex, OpNo0, OpNo1))
3544 return DAG.getNode(SystemZISD::SHL_DOUBLE, DL, MVT::v16i8, Ops[OpNo0],
3545 Ops[OpNo1], DAG.getConstant(StartIndex, DL, MVT::i32));
3547 // Fall back on VPERM. Construct an SDNode for the permute vector.
3548 SDValue IndexNodes[SystemZ::VectorBytes];
3549 for (unsigned I = 0; I < SystemZ::VectorBytes; ++I)
3551 IndexNodes[I] = DAG.getConstant(Bytes[I], DL, MVT::i32);
3553 IndexNodes[I] = DAG.getUNDEF(MVT::i32);
3554 SDValue Op2 = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, IndexNodes);
3555 return DAG.getNode(SystemZISD::PERMUTE, DL, MVT::v16i8, Ops[0], Ops[1], Op2);
3559 // Describes a general N-operand vector shuffle.
3560 struct GeneralShuffle {
3561 GeneralShuffle(EVT vt) : VT(vt) {}
3563 void add(SDValue, unsigned);
3564 SDValue getNode(SelectionDAG &, SDLoc);
3566 // The operands of the shuffle.
3567 SmallVector<SDValue, SystemZ::VectorBytes> Ops;
3569 // Index I is -1 if byte I of the result is undefined. Otherwise the
3570 // result comes from byte Bytes[I] % SystemZ::VectorBytes of operand
3571 // Bytes[I] / SystemZ::VectorBytes.
3572 SmallVector<int, SystemZ::VectorBytes> Bytes;
3574 // The type of the shuffle result.
3579 // Add an extra undefined element to the shuffle.
3580 void GeneralShuffle::addUndef() {
3581 unsigned BytesPerElement = VT.getVectorElementType().getStoreSize();
3582 for (unsigned I = 0; I < BytesPerElement; ++I)
3583 Bytes.push_back(-1);
3586 // Add an extra element to the shuffle, taking it from element Elem of Op.
3587 // A null Op indicates a vector input whose value will be calculated later;
3588 // there is at most one such input per shuffle and it always has the same
3589 // type as the result.
3590 void GeneralShuffle::add(SDValue Op, unsigned Elem) {
3591 unsigned BytesPerElement = VT.getVectorElementType().getStoreSize();
3593 // The source vector can have wider elements than the result,
3594 // either through an explicit TRUNCATE or because of type legalization.
3595 // We want the least significant part.
3596 EVT FromVT = Op.getNode() ? Op.getValueType() : VT;
3597 unsigned FromBytesPerElement = FromVT.getVectorElementType().getStoreSize();
3598 assert(FromBytesPerElement >= BytesPerElement &&
3599 "Invalid EXTRACT_VECTOR_ELT");
3600 unsigned Byte = ((Elem * FromBytesPerElement) % SystemZ::VectorBytes +
3601 (FromBytesPerElement - BytesPerElement));
3603 // Look through things like shuffles and bitcasts.
3604 while (Op.getNode()) {
3605 if (Op.getOpcode() == ISD::BITCAST)
3606 Op = Op.getOperand(0);
3607 else if (Op.getOpcode() == ISD::VECTOR_SHUFFLE && Op.hasOneUse()) {
3608 // See whether the bytes we need come from a contiguous part of one
3610 SmallVector<int, SystemZ::VectorBytes> OpBytes;
3611 getVPermMask(cast<ShuffleVectorSDNode>(Op), OpBytes);
3613 if (!getShuffleInput(OpBytes, Byte, BytesPerElement, NewByte))
3619 Op = Op.getOperand(unsigned(NewByte) / SystemZ::VectorBytes);
3620 Byte = unsigned(NewByte) % SystemZ::VectorBytes;
3621 } else if (Op.getOpcode() == ISD::UNDEF) {
3628 // Make sure that the source of the extraction is in Ops.
3630 for (; OpNo < Ops.size(); ++OpNo)
3631 if (Ops[OpNo] == Op)
3633 if (OpNo == Ops.size())
3636 // Add the element to Bytes.
3637 unsigned Base = OpNo * SystemZ::VectorBytes + Byte;
3638 for (unsigned I = 0; I < BytesPerElement; ++I)
3639 Bytes.push_back(Base + I);
3642 // Return SDNodes for the completed shuffle.
3643 SDValue GeneralShuffle::getNode(SelectionDAG &DAG, SDLoc DL) {
3644 assert(Bytes.size() == SystemZ::VectorBytes && "Incomplete vector");
3646 if (Ops.size() == 0)
3647 return DAG.getUNDEF(VT);
3649 // Make sure that there are at least two shuffle operands.
3650 if (Ops.size() == 1)
3651 Ops.push_back(DAG.getUNDEF(MVT::v16i8));
3653 // Create a tree of shuffles, deferring root node until after the loop.
3654 // Try to redistribute the undefined elements of non-root nodes so that
3655 // the non-root shuffles match something like a pack or merge, then adjust
3656 // the parent node's permute vector to compensate for the new order.
3657 // Among other things, this copes with vectors like <2 x i16> that were
3658 // padded with undefined elements during type legalization.
3660 // In the best case this redistribution will lead to the whole tree
3661 // using packs and merges. It should rarely be a loss in other cases.
3662 unsigned Stride = 1;
3663 for (; Stride * 2 < Ops.size(); Stride *= 2) {
3664 for (unsigned I = 0; I < Ops.size() - Stride; I += Stride * 2) {
3665 SDValue SubOps[] = { Ops[I], Ops[I + Stride] };
3667 // Create a mask for just these two operands.
3668 SmallVector<int, SystemZ::VectorBytes> NewBytes(SystemZ::VectorBytes);
3669 for (unsigned J = 0; J < SystemZ::VectorBytes; ++J) {
3670 unsigned OpNo = unsigned(Bytes[J]) / SystemZ::VectorBytes;
3671 unsigned Byte = unsigned(Bytes[J]) % SystemZ::VectorBytes;
3674 else if (OpNo == I + Stride)
3675 NewBytes[J] = SystemZ::VectorBytes + Byte;
3679 // See if it would be better to reorganize NewMask to avoid using VPERM.
3680 SmallVector<int, SystemZ::VectorBytes> NewBytesMap(SystemZ::VectorBytes);
3681 if (const Permute *P = matchDoublePermute(NewBytes, NewBytesMap)) {
3682 Ops[I] = getPermuteNode(DAG, DL, *P, SubOps[0], SubOps[1]);
3683 // Applying NewBytesMap to Ops[I] gets back to NewBytes.
3684 for (unsigned J = 0; J < SystemZ::VectorBytes; ++J) {
3685 if (NewBytes[J] >= 0) {
3686 assert(unsigned(NewBytesMap[J]) < SystemZ::VectorBytes &&
3687 "Invalid double permute");
3688 Bytes[J] = I * SystemZ::VectorBytes + NewBytesMap[J];
3690 assert(NewBytesMap[J] < 0 && "Invalid double permute");
3693 // Just use NewBytes on the operands.
3694 Ops[I] = getGeneralPermuteNode(DAG, DL, SubOps, NewBytes);
3695 for (unsigned J = 0; J < SystemZ::VectorBytes; ++J)
3696 if (NewBytes[J] >= 0)
3697 Bytes[J] = I * SystemZ::VectorBytes + J;
3702 // Now we just have 2 inputs. Put the second operand in Ops[1].
3704 Ops[1] = Ops[Stride];
3705 for (unsigned I = 0; I < SystemZ::VectorBytes; ++I)
3706 if (Bytes[I] >= int(SystemZ::VectorBytes))
3707 Bytes[I] -= (Stride - 1) * SystemZ::VectorBytes;
3710 // Look for an instruction that can do the permute without resorting
3712 unsigned OpNo0, OpNo1;
3714 if (const Permute *P = matchPermute(Bytes, OpNo0, OpNo1))
3715 Op = getPermuteNode(DAG, DL, *P, Ops[OpNo0], Ops[OpNo1]);
3717 Op = getGeneralPermuteNode(DAG, DL, &Ops[0], Bytes);
3718 return DAG.getNode(ISD::BITCAST, DL, VT, Op);
3721 // Return true if the given BUILD_VECTOR is a scalar-to-vector conversion.
3722 static bool isScalarToVector(SDValue Op) {
3723 for (unsigned I = 1, E = Op.getNumOperands(); I != E; ++I)
3724 if (Op.getOperand(I).getOpcode() != ISD::UNDEF)
3729 // Return a vector of type VT that contains Value in the first element.
3730 // The other elements don't matter.
3731 static SDValue buildScalarToVector(SelectionDAG &DAG, SDLoc DL, EVT VT,
3733 // If we have a constant, replicate it to all elements and let the
3734 // BUILD_VECTOR lowering take care of it.
3735 if (Value.getOpcode() == ISD::Constant ||
3736 Value.getOpcode() == ISD::ConstantFP) {
3737 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Value);
3738 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Ops);
3740 if (Value.getOpcode() == ISD::UNDEF)
3741 return DAG.getUNDEF(VT);
3742 return DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VT, Value);
3745 // Return a vector of type VT in which Op0 is in element 0 and Op1 is in
3746 // element 1. Used for cases in which replication is cheap.
3747 static SDValue buildMergeScalars(SelectionDAG &DAG, SDLoc DL, EVT VT,
3748 SDValue Op0, SDValue Op1) {
3749 if (Op0.getOpcode() == ISD::UNDEF) {
3750 if (Op1.getOpcode() == ISD::UNDEF)
3751 return DAG.getUNDEF(VT);
3752 return DAG.getNode(SystemZISD::REPLICATE, DL, VT, Op1);
3754 if (Op1.getOpcode() == ISD::UNDEF)
3755 return DAG.getNode(SystemZISD::REPLICATE, DL, VT, Op0);
3756 return DAG.getNode(SystemZISD::MERGE_HIGH, DL, VT,
3757 buildScalarToVector(DAG, DL, VT, Op0),
3758 buildScalarToVector(DAG, DL, VT, Op1));
3761 // Extend GPR scalars Op0 and Op1 to doublewords and return a v2i64
3763 static SDValue joinDwords(SelectionDAG &DAG, SDLoc DL, SDValue Op0,
3765 if (Op0.getOpcode() == ISD::UNDEF && Op1.getOpcode() == ISD::UNDEF)
3766 return DAG.getUNDEF(MVT::v2i64);
3767 // If one of the two inputs is undefined then replicate the other one,
3768 // in order to avoid using another register unnecessarily.
3769 if (Op0.getOpcode() == ISD::UNDEF)
3770 Op0 = Op1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op1);
3771 else if (Op1.getOpcode() == ISD::UNDEF)
3772 Op0 = Op1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op0);
3774 Op0 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op0);
3775 Op1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op1);
3777 return DAG.getNode(SystemZISD::JOIN_DWORDS, DL, MVT::v2i64, Op0, Op1);
3780 // Try to represent constant BUILD_VECTOR node BVN using a
3781 // SystemZISD::BYTE_MASK-style mask. Store the mask value in Mask
3783 static bool tryBuildVectorByteMask(BuildVectorSDNode *BVN, uint64_t &Mask) {
3784 EVT ElemVT = BVN->getValueType(0).getVectorElementType();
3785 unsigned BytesPerElement = ElemVT.getStoreSize();
3786 for (unsigned I = 0, E = BVN->getNumOperands(); I != E; ++I) {
3787 SDValue Op = BVN->getOperand(I);
3788 if (Op.getOpcode() != ISD::UNDEF) {
3790 if (Op.getOpcode() == ISD::Constant)
3791 Value = dyn_cast<ConstantSDNode>(Op)->getZExtValue();
3792 else if (Op.getOpcode() == ISD::ConstantFP)
3793 Value = (dyn_cast<ConstantFPSDNode>(Op)->getValueAPF().bitcastToAPInt()
3797 for (unsigned J = 0; J < BytesPerElement; ++J) {
3798 uint64_t Byte = (Value >> (J * 8)) & 0xff;
3800 Mask |= 1ULL << ((E - I - 1) * BytesPerElement + J);
3809 // Try to load a vector constant in which BitsPerElement-bit value Value
3810 // is replicated to fill the vector. VT is the type of the resulting
3811 // constant, which may have elements of a different size from BitsPerElement.
3812 // Return the SDValue of the constant on success, otherwise return
3814 static SDValue tryBuildVectorReplicate(SelectionDAG &DAG,
3815 const SystemZInstrInfo *TII,
3816 SDLoc DL, EVT VT, uint64_t Value,
3817 unsigned BitsPerElement) {
3818 // Signed 16-bit values can be replicated using VREPI.
3819 int64_t SignedValue = SignExtend64(Value, BitsPerElement);
3820 if (isInt<16>(SignedValue)) {
3821 MVT VecVT = MVT::getVectorVT(MVT::getIntegerVT(BitsPerElement),
3822 SystemZ::VectorBits / BitsPerElement);
3823 SDValue Op = DAG.getNode(SystemZISD::REPLICATE, DL, VecVT,
3824 DAG.getConstant(SignedValue, DL, MVT::i32));
3825 return DAG.getNode(ISD::BITCAST, DL, VT, Op);
3827 // See whether rotating the constant left some N places gives a value that
3828 // is one less than a power of 2 (i.e. all zeros followed by all ones).
3829 // If so we can use VGM.
3830 unsigned Start, End;
3831 if (TII->isRxSBGMask(Value, BitsPerElement, Start, End)) {
3832 // isRxSBGMask returns the bit numbers for a full 64-bit value,
3833 // with 0 denoting 1 << 63 and 63 denoting 1. Convert them to
3834 // bit numbers for an BitsPerElement value, so that 0 denotes
3835 // 1 << (BitsPerElement-1).
3836 Start -= 64 - BitsPerElement;
3837 End -= 64 - BitsPerElement;
3838 MVT VecVT = MVT::getVectorVT(MVT::getIntegerVT(BitsPerElement),
3839 SystemZ::VectorBits / BitsPerElement);
3840 SDValue Op = DAG.getNode(SystemZISD::ROTATE_MASK, DL, VecVT,
3841 DAG.getConstant(Start, DL, MVT::i32),
3842 DAG.getConstant(End, DL, MVT::i32));
3843 return DAG.getNode(ISD::BITCAST, DL, VT, Op);
3848 // If a BUILD_VECTOR contains some EXTRACT_VECTOR_ELTs, it's usually
3849 // better to use VECTOR_SHUFFLEs on them, only using BUILD_VECTOR for
3850 // the non-EXTRACT_VECTOR_ELT elements. See if the given BUILD_VECTOR
3851 // would benefit from this representation and return it if so.
3852 static SDValue tryBuildVectorShuffle(SelectionDAG &DAG,
3853 BuildVectorSDNode *BVN) {
3854 EVT VT = BVN->getValueType(0);
3855 unsigned NumElements = VT.getVectorNumElements();
3857 // Represent the BUILD_VECTOR as an N-operand VECTOR_SHUFFLE-like operation
3858 // on byte vectors. If there are non-EXTRACT_VECTOR_ELT elements that still
3859 // need a BUILD_VECTOR, add an additional placeholder operand for that
3860 // BUILD_VECTOR and store its operands in ResidueOps.
3861 GeneralShuffle GS(VT);
3862 SmallVector<SDValue, SystemZ::VectorBytes> ResidueOps;
3863 bool FoundOne = false;
3864 for (unsigned I = 0; I < NumElements; ++I) {
3865 SDValue Op = BVN->getOperand(I);
3866 if (Op.getOpcode() == ISD::TRUNCATE)
3867 Op = Op.getOperand(0);
3868 if (Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
3869 Op.getOperand(1).getOpcode() == ISD::Constant) {
3870 unsigned Elem = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
3871 GS.add(Op.getOperand(0), Elem);
3873 } else if (Op.getOpcode() == ISD::UNDEF) {
3876 GS.add(SDValue(), ResidueOps.size());
3877 ResidueOps.push_back(Op);
3881 // Nothing to do if there are no EXTRACT_VECTOR_ELTs.
3885 // Create the BUILD_VECTOR for the remaining elements, if any.
3886 if (!ResidueOps.empty()) {
3887 while (ResidueOps.size() < NumElements)
3888 ResidueOps.push_back(DAG.getUNDEF(VT.getVectorElementType()));
3889 for (auto &Op : GS.Ops) {
3890 if (!Op.getNode()) {
3891 Op = DAG.getNode(ISD::BUILD_VECTOR, SDLoc(BVN), VT, ResidueOps);
3896 return GS.getNode(DAG, SDLoc(BVN));
3899 // Combine GPR scalar values Elems into a vector of type VT.
3900 static SDValue buildVector(SelectionDAG &DAG, SDLoc DL, EVT VT,
3901 SmallVectorImpl<SDValue> &Elems) {
3902 // See whether there is a single replicated value.
3904 unsigned int NumElements = Elems.size();
3905 unsigned int Count = 0;
3906 for (auto Elem : Elems) {
3907 if (Elem.getOpcode() != ISD::UNDEF) {
3908 if (!Single.getNode())
3910 else if (Elem != Single) {
3917 // There are three cases here:
3919 // - if the only defined element is a loaded one, the best sequence
3920 // is a replicating load.
3922 // - otherwise, if the only defined element is an i64 value, we will
3923 // end up with the same VLVGP sequence regardless of whether we short-cut
3924 // for replication or fall through to the later code.
3926 // - otherwise, if the only defined element is an i32 or smaller value,
3927 // we would need 2 instructions to replicate it: VLVGP followed by VREPx.
3928 // This is only a win if the single defined element is used more than once.
3929 // In other cases we're better off using a single VLVGx.
3930 if (Single.getNode() && (Count > 1 || Single.getOpcode() == ISD::LOAD))
3931 return DAG.getNode(SystemZISD::REPLICATE, DL, VT, Single);
3933 // The best way of building a v2i64 from two i64s is to use VLVGP.
3934 if (VT == MVT::v2i64)
3935 return joinDwords(DAG, DL, Elems[0], Elems[1]);
3937 // Use a 64-bit merge high to combine two doubles.
3938 if (VT == MVT::v2f64)
3939 return buildMergeScalars(DAG, DL, VT, Elems[0], Elems[1]);
3941 // Build v4f32 values directly from the FPRs:
3943 // <Axxx> <Bxxx> <Cxxxx> <Dxxx>
3948 if (VT == MVT::v4f32) {
3949 SDValue Op01 = buildMergeScalars(DAG, DL, VT, Elems[0], Elems[1]);
3950 SDValue Op23 = buildMergeScalars(DAG, DL, VT, Elems[2], Elems[3]);
3951 // Avoid unnecessary undefs by reusing the other operand.
3952 if (Op01.getOpcode() == ISD::UNDEF)
3954 else if (Op23.getOpcode() == ISD::UNDEF)
3956 // Merging identical replications is a no-op.
3957 if (Op01.getOpcode() == SystemZISD::REPLICATE && Op01 == Op23)
3959 Op01 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Op01);
3960 Op23 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Op23);
3961 SDValue Op = DAG.getNode(SystemZISD::MERGE_HIGH,
3962 DL, MVT::v2i64, Op01, Op23);
3963 return DAG.getNode(ISD::BITCAST, DL, VT, Op);
3966 // Collect the constant terms.
3967 SmallVector<SDValue, SystemZ::VectorBytes> Constants(NumElements, SDValue());
3968 SmallVector<bool, SystemZ::VectorBytes> Done(NumElements, false);
3970 unsigned NumConstants = 0;
3971 for (unsigned I = 0; I < NumElements; ++I) {
3972 SDValue Elem = Elems[I];
3973 if (Elem.getOpcode() == ISD::Constant ||
3974 Elem.getOpcode() == ISD::ConstantFP) {
3976 Constants[I] = Elem;
3980 // If there was at least one constant, fill in the other elements of
3981 // Constants with undefs to get a full vector constant and use that
3982 // as the starting point.
3984 if (NumConstants > 0) {
3985 for (unsigned I = 0; I < NumElements; ++I)
3986 if (!Constants[I].getNode())
3987 Constants[I] = DAG.getUNDEF(Elems[I].getValueType());
3988 Result = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Constants);
3990 // Otherwise try to use VLVGP to start the sequence in order to
3991 // avoid a false dependency on any previous contents of the vector
3992 // register. This only makes sense if one of the associated elements
3994 unsigned I1 = NumElements / 2 - 1;
3995 unsigned I2 = NumElements - 1;
3996 bool Def1 = (Elems[I1].getOpcode() != ISD::UNDEF);
3997 bool Def2 = (Elems[I2].getOpcode() != ISD::UNDEF);
3999 SDValue Elem1 = Elems[Def1 ? I1 : I2];
4000 SDValue Elem2 = Elems[Def2 ? I2 : I1];
4001 Result = DAG.getNode(ISD::BITCAST, DL, VT,
4002 joinDwords(DAG, DL, Elem1, Elem2));
4006 Result = DAG.getUNDEF(VT);
4009 // Use VLVGx to insert the other elements.
4010 for (unsigned I = 0; I < NumElements; ++I)
4011 if (!Done[I] && Elems[I].getOpcode() != ISD::UNDEF)
4012 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, Result, Elems[I],
4013 DAG.getConstant(I, DL, MVT::i32));
4017 SDValue SystemZTargetLowering::lowerBUILD_VECTOR(SDValue Op,
4018 SelectionDAG &DAG) const {
4019 const SystemZInstrInfo *TII =
4020 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
4021 auto *BVN = cast<BuildVectorSDNode>(Op.getNode());
4023 EVT VT = Op.getValueType();
4025 if (BVN->isConstant()) {
4026 // Try using VECTOR GENERATE BYTE MASK. This is the architecturally-
4027 // preferred way of creating all-zero and all-one vectors so give it
4028 // priority over other methods below.
4030 if (tryBuildVectorByteMask(BVN, Mask)) {
4031 SDValue Op = DAG.getNode(SystemZISD::BYTE_MASK, DL, MVT::v16i8,
4032 DAG.getConstant(Mask, DL, MVT::i32));
4033 return DAG.getNode(ISD::BITCAST, DL, VT, Op);
4036 // Try using some form of replication.
4037 APInt SplatBits, SplatUndef;
4038 unsigned SplatBitSize;
4040 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs,
4042 SplatBitSize <= 64) {
4043 // First try assuming that any undefined bits above the highest set bit
4044 // and below the lowest set bit are 1s. This increases the likelihood of
4045 // being able to use a sign-extended element value in VECTOR REPLICATE
4046 // IMMEDIATE or a wraparound mask in VECTOR GENERATE MASK.
4047 uint64_t SplatBitsZ = SplatBits.getZExtValue();
4048 uint64_t SplatUndefZ = SplatUndef.getZExtValue();
4049 uint64_t Lower = (SplatUndefZ
4050 & ((uint64_t(1) << findFirstSet(SplatBitsZ)) - 1));
4051 uint64_t Upper = (SplatUndefZ
4052 & ~((uint64_t(1) << findLastSet(SplatBitsZ)) - 1));
4053 uint64_t Value = SplatBitsZ | Upper | Lower;
4054 SDValue Op = tryBuildVectorReplicate(DAG, TII, DL, VT, Value,
4059 // Now try assuming that any undefined bits between the first and
4060 // last defined set bits are set. This increases the chances of
4061 // using a non-wraparound mask.
4062 uint64_t Middle = SplatUndefZ & ~Upper & ~Lower;
4063 Value = SplatBitsZ | Middle;
4064 Op = tryBuildVectorReplicate(DAG, TII, DL, VT, Value, SplatBitSize);
4069 // Fall back to loading it from memory.
4073 // See if we should use shuffles to construct the vector from other vectors.
4074 SDValue Res = tryBuildVectorShuffle(DAG, BVN);
4078 // Detect SCALAR_TO_VECTOR conversions.
4079 if (isOperationLegal(ISD::SCALAR_TO_VECTOR, VT) && isScalarToVector(Op))
4080 return buildScalarToVector(DAG, DL, VT, Op.getOperand(0));
4082 // Otherwise use buildVector to build the vector up from GPRs.
4083 unsigned NumElements = Op.getNumOperands();
4084 SmallVector<SDValue, SystemZ::VectorBytes> Ops(NumElements);
4085 for (unsigned I = 0; I < NumElements; ++I)
4086 Ops[I] = Op.getOperand(I);
4087 return buildVector(DAG, DL, VT, Ops);
4090 SDValue SystemZTargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
4091 SelectionDAG &DAG) const {
4092 auto *VSN = cast<ShuffleVectorSDNode>(Op.getNode());
4094 EVT VT = Op.getValueType();
4095 unsigned NumElements = VT.getVectorNumElements();
4097 if (VSN->isSplat()) {
4098 SDValue Op0 = Op.getOperand(0);
4099 unsigned Index = VSN->getSplatIndex();
4100 assert(Index < VT.getVectorNumElements() &&
4101 "Splat index should be defined and in first operand");
4102 // See whether the value we're splatting is directly available as a scalar.
4103 if ((Index == 0 && Op0.getOpcode() == ISD::SCALAR_TO_VECTOR) ||
4104 Op0.getOpcode() == ISD::BUILD_VECTOR)
4105 return DAG.getNode(SystemZISD::REPLICATE, DL, VT, Op0.getOperand(Index));
4106 // Otherwise keep it as a vector-to-vector operation.
4107 return DAG.getNode(SystemZISD::SPLAT, DL, VT, Op.getOperand(0),
4108 DAG.getConstant(Index, DL, MVT::i32));
4111 GeneralShuffle GS(VT);
4112 for (unsigned I = 0; I < NumElements; ++I) {
4113 int Elt = VSN->getMaskElt(I);
4117 GS.add(Op.getOperand(unsigned(Elt) / NumElements),
4118 unsigned(Elt) % NumElements);
4120 return GS.getNode(DAG, SDLoc(VSN));
4123 SDValue SystemZTargetLowering::lowerSCALAR_TO_VECTOR(SDValue Op,
4124 SelectionDAG &DAG) const {
4126 // Just insert the scalar into element 0 of an undefined vector.
4127 return DAG.getNode(ISD::INSERT_VECTOR_ELT, DL,
4128 Op.getValueType(), DAG.getUNDEF(Op.getValueType()),
4129 Op.getOperand(0), DAG.getConstant(0, DL, MVT::i32));
4132 SDValue SystemZTargetLowering::lowerINSERT_VECTOR_ELT(SDValue Op,
4133 SelectionDAG &DAG) const {
4134 // Handle insertions of floating-point values.
4136 SDValue Op0 = Op.getOperand(0);
4137 SDValue Op1 = Op.getOperand(1);
4138 SDValue Op2 = Op.getOperand(2);
4139 EVT VT = Op.getValueType();
4141 // Insertions into constant indices of a v2f64 can be done using VPDI.
4142 // However, if the inserted value is a bitcast or a constant then it's
4143 // better to use GPRs, as below.
4144 if (VT == MVT::v2f64 &&
4145 Op1.getOpcode() != ISD::BITCAST &&
4146 Op1.getOpcode() != ISD::ConstantFP &&
4147 Op2.getOpcode() == ISD::Constant) {
4148 uint64_t Index = dyn_cast<ConstantSDNode>(Op2)->getZExtValue();
4149 unsigned Mask = VT.getVectorNumElements() - 1;
4154 // Otherwise bitcast to the equivalent integer form and insert via a GPR.
4155 MVT IntVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
4156 MVT IntVecVT = MVT::getVectorVT(IntVT, VT.getVectorNumElements());
4157 SDValue Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, IntVecVT,
4158 DAG.getNode(ISD::BITCAST, DL, IntVecVT, Op0),
4159 DAG.getNode(ISD::BITCAST, DL, IntVT, Op1), Op2);
4160 return DAG.getNode(ISD::BITCAST, DL, VT, Res);
4164 SystemZTargetLowering::lowerEXTRACT_VECTOR_ELT(SDValue Op,
4165 SelectionDAG &DAG) const {
4166 // Handle extractions of floating-point values.
4168 SDValue Op0 = Op.getOperand(0);
4169 SDValue Op1 = Op.getOperand(1);
4170 EVT VT = Op.getValueType();
4171 EVT VecVT = Op0.getValueType();
4173 // Extractions of constant indices can be done directly.
4174 if (auto *CIndexN = dyn_cast<ConstantSDNode>(Op1)) {
4175 uint64_t Index = CIndexN->getZExtValue();
4176 unsigned Mask = VecVT.getVectorNumElements() - 1;
4181 // Otherwise bitcast to the equivalent integer form and extract via a GPR.
4182 MVT IntVT = MVT::getIntegerVT(VT.getSizeInBits());
4183 MVT IntVecVT = MVT::getVectorVT(IntVT, VecVT.getVectorNumElements());
4184 SDValue Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, IntVT,
4185 DAG.getNode(ISD::BITCAST, DL, IntVecVT, Op0), Op1);
4186 return DAG.getNode(ISD::BITCAST, DL, VT, Res);
4190 SystemZTargetLowering::lowerExtendVectorInreg(SDValue Op, SelectionDAG &DAG,
4191 unsigned UnpackHigh) const {
4192 SDValue PackedOp = Op.getOperand(0);
4193 EVT OutVT = Op.getValueType();
4194 EVT InVT = PackedOp.getValueType();
4195 unsigned ToBits = OutVT.getVectorElementType().getSizeInBits();
4196 unsigned FromBits = InVT.getVectorElementType().getSizeInBits();
4199 EVT OutVT = MVT::getVectorVT(MVT::getIntegerVT(FromBits),
4200 SystemZ::VectorBits / FromBits);
4201 PackedOp = DAG.getNode(UnpackHigh, SDLoc(PackedOp), OutVT, PackedOp);
4202 } while (FromBits != ToBits);
4206 SDValue SystemZTargetLowering::lowerShift(SDValue Op, SelectionDAG &DAG,
4207 unsigned ByScalar) const {
4208 // Look for cases where a vector shift can use the *_BY_SCALAR form.
4209 SDValue Op0 = Op.getOperand(0);
4210 SDValue Op1 = Op.getOperand(1);
4212 EVT VT = Op.getValueType();
4213 unsigned ElemBitSize = VT.getVectorElementType().getSizeInBits();
4215 // See whether the shift vector is a splat represented as BUILD_VECTOR.
4216 if (auto *BVN = dyn_cast<BuildVectorSDNode>(Op1)) {
4217 APInt SplatBits, SplatUndef;
4218 unsigned SplatBitSize;
4220 // Check for constant splats. Use ElemBitSize as the minimum element
4221 // width and reject splats that need wider elements.
4222 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs,
4223 ElemBitSize, true) &&
4224 SplatBitSize == ElemBitSize) {
4225 SDValue Shift = DAG.getConstant(SplatBits.getZExtValue() & 0xfff,
4227 return DAG.getNode(ByScalar, DL, VT, Op0, Shift);
4229 // Check for variable splats.
4230 BitVector UndefElements;
4231 SDValue Splat = BVN->getSplatValue(&UndefElements);
4233 // Since i32 is the smallest legal type, we either need a no-op
4235 SDValue Shift = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Splat);
4236 return DAG.getNode(ByScalar, DL, VT, Op0, Shift);
4240 // See whether the shift vector is a splat represented as SHUFFLE_VECTOR,
4241 // and the shift amount is directly available in a GPR.
4242 if (auto *VSN = dyn_cast<ShuffleVectorSDNode>(Op1)) {
4243 if (VSN->isSplat()) {
4244 SDValue VSNOp0 = VSN->getOperand(0);
4245 unsigned Index = VSN->getSplatIndex();
4246 assert(Index < VT.getVectorNumElements() &&
4247 "Splat index should be defined and in first operand");
4248 if ((Index == 0 && VSNOp0.getOpcode() == ISD::SCALAR_TO_VECTOR) ||
4249 VSNOp0.getOpcode() == ISD::BUILD_VECTOR) {
4250 // Since i32 is the smallest legal type, we either need a no-op
4252 SDValue Shift = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32,
4253 VSNOp0.getOperand(Index));
4254 return DAG.getNode(ByScalar, DL, VT, Op0, Shift);
4259 // Otherwise just treat the current form as legal.
4263 SDValue SystemZTargetLowering::LowerOperation(SDValue Op,
4264 SelectionDAG &DAG) const {
4265 switch (Op.getOpcode()) {
4267 return lowerBR_CC(Op, DAG);
4268 case ISD::SELECT_CC:
4269 return lowerSELECT_CC(Op, DAG);
4271 return lowerSETCC(Op, DAG);
4272 case ISD::GlobalAddress:
4273 return lowerGlobalAddress(cast<GlobalAddressSDNode>(Op), DAG);
4274 case ISD::GlobalTLSAddress:
4275 return lowerGlobalTLSAddress(cast<GlobalAddressSDNode>(Op), DAG);
4276 case ISD::BlockAddress:
4277 return lowerBlockAddress(cast<BlockAddressSDNode>(Op), DAG);
4278 case ISD::JumpTable:
4279 return lowerJumpTable(cast<JumpTableSDNode>(Op), DAG);
4280 case ISD::ConstantPool:
4281 return lowerConstantPool(cast<ConstantPoolSDNode>(Op), DAG);
4283 return lowerBITCAST(Op, DAG);
4285 return lowerVASTART(Op, DAG);
4287 return lowerVACOPY(Op, DAG);
4288 case ISD::DYNAMIC_STACKALLOC:
4289 return lowerDYNAMIC_STACKALLOC(Op, DAG);
4290 case ISD::SMUL_LOHI:
4291 return lowerSMUL_LOHI(Op, DAG);
4292 case ISD::UMUL_LOHI:
4293 return lowerUMUL_LOHI(Op, DAG);
4295 return lowerSDIVREM(Op, DAG);
4297 return lowerUDIVREM(Op, DAG);
4299 return lowerOR(Op, DAG);
4301 return lowerCTPOP(Op, DAG);
4302 case ISD::CTLZ_ZERO_UNDEF:
4303 return DAG.getNode(ISD::CTLZ, SDLoc(Op),
4304 Op.getValueType(), Op.getOperand(0));
4305 case ISD::CTTZ_ZERO_UNDEF:
4306 return DAG.getNode(ISD::CTTZ, SDLoc(Op),
4307 Op.getValueType(), Op.getOperand(0));
4308 case ISD::ATOMIC_SWAP:
4309 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_SWAPW);
4310 case ISD::ATOMIC_STORE:
4311 return lowerATOMIC_STORE(Op, DAG);
4312 case ISD::ATOMIC_LOAD:
4313 return lowerATOMIC_LOAD(Op, DAG);
4314 case ISD::ATOMIC_LOAD_ADD:
4315 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_ADD);
4316 case ISD::ATOMIC_LOAD_SUB:
4317 return lowerATOMIC_LOAD_SUB(Op, DAG);
4318 case ISD::ATOMIC_LOAD_AND:
4319 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_AND);
4320 case ISD::ATOMIC_LOAD_OR:
4321 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_OR);
4322 case ISD::ATOMIC_LOAD_XOR:
4323 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_XOR);
4324 case ISD::ATOMIC_LOAD_NAND:
4325 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_NAND);
4326 case ISD::ATOMIC_LOAD_MIN:
4327 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_MIN);
4328 case ISD::ATOMIC_LOAD_MAX:
4329 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_MAX);
4330 case ISD::ATOMIC_LOAD_UMIN:
4331 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_UMIN);
4332 case ISD::ATOMIC_LOAD_UMAX:
4333 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_UMAX);
4334 case ISD::ATOMIC_CMP_SWAP:
4335 return lowerATOMIC_CMP_SWAP(Op, DAG);
4336 case ISD::STACKSAVE:
4337 return lowerSTACKSAVE(Op, DAG);
4338 case ISD::STACKRESTORE:
4339 return lowerSTACKRESTORE(Op, DAG);
4341 return lowerPREFETCH(Op, DAG);
4342 case ISD::INTRINSIC_W_CHAIN:
4343 return lowerINTRINSIC_W_CHAIN(Op, DAG);
4344 case ISD::INTRINSIC_WO_CHAIN:
4345 return lowerINTRINSIC_WO_CHAIN(Op, DAG);
4346 case ISD::BUILD_VECTOR:
4347 return lowerBUILD_VECTOR(Op, DAG);
4348 case ISD::VECTOR_SHUFFLE:
4349 return lowerVECTOR_SHUFFLE(Op, DAG);
4350 case ISD::SCALAR_TO_VECTOR:
4351 return lowerSCALAR_TO_VECTOR(Op, DAG);
4352 case ISD::INSERT_VECTOR_ELT:
4353 return lowerINSERT_VECTOR_ELT(Op, DAG);
4354 case ISD::EXTRACT_VECTOR_ELT:
4355 return lowerEXTRACT_VECTOR_ELT(Op, DAG);
4356 case ISD::SIGN_EXTEND_VECTOR_INREG:
4357 return lowerExtendVectorInreg(Op, DAG, SystemZISD::UNPACK_HIGH);
4358 case ISD::ZERO_EXTEND_VECTOR_INREG:
4359 return lowerExtendVectorInreg(Op, DAG, SystemZISD::UNPACKL_HIGH);
4361 return lowerShift(Op, DAG, SystemZISD::VSHL_BY_SCALAR);
4363 return lowerShift(Op, DAG, SystemZISD::VSRL_BY_SCALAR);
4365 return lowerShift(Op, DAG, SystemZISD::VSRA_BY_SCALAR);
4367 llvm_unreachable("Unexpected node to lower");
4371 const char *SystemZTargetLowering::getTargetNodeName(unsigned Opcode) const {
4372 #define OPCODE(NAME) case SystemZISD::NAME: return "SystemZISD::" #NAME
4373 switch ((SystemZISD::NodeType)Opcode) {
4374 case SystemZISD::FIRST_NUMBER: break;
4380 OPCODE(PCREL_WRAPPER);
4381 OPCODE(PCREL_OFFSET);
4387 OPCODE(SELECT_CCMASK);
4388 OPCODE(ADJDYNALLOC);
4389 OPCODE(EXTRACT_ACCESS);
4391 OPCODE(UMUL_LOHI64);
4408 OPCODE(SEARCH_STRING);
4412 OPCODE(TBEGIN_NOFLOAT);
4415 OPCODE(ROTATE_MASK);
4417 OPCODE(JOIN_DWORDS);
4422 OPCODE(PERMUTE_DWORDS);
4427 OPCODE(UNPACK_HIGH);
4428 OPCODE(UNPACKL_HIGH);
4430 OPCODE(UNPACKL_LOW);
4431 OPCODE(VSHL_BY_SCALAR);
4432 OPCODE(VSRL_BY_SCALAR);
4433 OPCODE(VSRA_BY_SCALAR);
4460 OPCODE(ATOMIC_SWAPW);
4461 OPCODE(ATOMIC_LOADW_ADD);
4462 OPCODE(ATOMIC_LOADW_SUB);
4463 OPCODE(ATOMIC_LOADW_AND);
4464 OPCODE(ATOMIC_LOADW_OR);
4465 OPCODE(ATOMIC_LOADW_XOR);
4466 OPCODE(ATOMIC_LOADW_NAND);
4467 OPCODE(ATOMIC_LOADW_MIN);
4468 OPCODE(ATOMIC_LOADW_MAX);
4469 OPCODE(ATOMIC_LOADW_UMIN);
4470 OPCODE(ATOMIC_LOADW_UMAX);
4471 OPCODE(ATOMIC_CMP_SWAPW);
4478 // Return true if VT is a vector whose elements are a whole number of bytes
4480 static bool canTreatAsByteVector(EVT VT) {
4481 return VT.isVector() && VT.getVectorElementType().getSizeInBits() % 8 == 0;
4484 // Try to simplify an EXTRACT_VECTOR_ELT from a vector of type VecVT
4485 // producing a result of type ResVT. Op is a possibly bitcast version
4486 // of the input vector and Index is the index (based on type VecVT) that
4487 // should be extracted. Return the new extraction if a simplification
4488 // was possible or if Force is true.
4489 SDValue SystemZTargetLowering::combineExtract(SDLoc DL, EVT ResVT, EVT VecVT,
4490 SDValue Op, unsigned Index,
4491 DAGCombinerInfo &DCI,
4493 SelectionDAG &DAG = DCI.DAG;
4495 // The number of bytes being extracted.
4496 unsigned BytesPerElement = VecVT.getVectorElementType().getStoreSize();
4499 unsigned Opcode = Op.getOpcode();
4500 if (Opcode == ISD::BITCAST)
4501 // Look through bitcasts.
4502 Op = Op.getOperand(0);
4503 else if (Opcode == ISD::VECTOR_SHUFFLE &&
4504 canTreatAsByteVector(Op.getValueType())) {
4505 // Get a VPERM-like permute mask and see whether the bytes covered
4506 // by the extracted element are a contiguous sequence from one
4508 SmallVector<int, SystemZ::VectorBytes> Bytes;
4509 getVPermMask(cast<ShuffleVectorSDNode>(Op), Bytes);
4511 if (!getShuffleInput(Bytes, Index * BytesPerElement,
4512 BytesPerElement, First))
4515 return DAG.getUNDEF(ResVT);
4516 // Make sure the contiguous sequence starts at a multiple of the
4517 // original element size.
4518 unsigned Byte = unsigned(First) % Bytes.size();
4519 if (Byte % BytesPerElement != 0)
4521 // We can get the extracted value directly from an input.
4522 Index = Byte / BytesPerElement;
4523 Op = Op.getOperand(unsigned(First) / Bytes.size());
4525 } else if (Opcode == ISD::BUILD_VECTOR &&
4526 canTreatAsByteVector(Op.getValueType())) {
4527 // We can only optimize this case if the BUILD_VECTOR elements are
4528 // at least as wide as the extracted value.
4529 EVT OpVT = Op.getValueType();
4530 unsigned OpBytesPerElement = OpVT.getVectorElementType().getStoreSize();
4531 if (OpBytesPerElement < BytesPerElement)
4533 // Make sure that the least-significant bit of the extracted value
4534 // is the least significant bit of an input.
4535 unsigned End = (Index + 1) * BytesPerElement;
4536 if (End % OpBytesPerElement != 0)
4538 // We're extracting the low part of one operand of the BUILD_VECTOR.
4539 Op = Op.getOperand(End / OpBytesPerElement - 1);
4540 if (!Op.getValueType().isInteger()) {
4541 EVT VT = MVT::getIntegerVT(Op.getValueType().getSizeInBits());
4542 Op = DAG.getNode(ISD::BITCAST, DL, VT, Op);
4543 DCI.AddToWorklist(Op.getNode());
4545 EVT VT = MVT::getIntegerVT(ResVT.getSizeInBits());
4546 Op = DAG.getNode(ISD::TRUNCATE, DL, VT, Op);
4548 DCI.AddToWorklist(Op.getNode());
4549 Op = DAG.getNode(ISD::BITCAST, DL, ResVT, Op);
4552 } else if ((Opcode == ISD::SIGN_EXTEND_VECTOR_INREG ||
4553 Opcode == ISD::ZERO_EXTEND_VECTOR_INREG ||
4554 Opcode == ISD::ANY_EXTEND_VECTOR_INREG) &&
4555 canTreatAsByteVector(Op.getValueType()) &&
4556 canTreatAsByteVector(Op.getOperand(0).getValueType())) {
4557 // Make sure that only the unextended bits are significant.
4558 EVT ExtVT = Op.getValueType();
4559 EVT OpVT = Op.getOperand(0).getValueType();
4560 unsigned ExtBytesPerElement = ExtVT.getVectorElementType().getStoreSize();
4561 unsigned OpBytesPerElement = OpVT.getVectorElementType().getStoreSize();
4562 unsigned Byte = Index * BytesPerElement;
4563 unsigned SubByte = Byte % ExtBytesPerElement;
4564 unsigned MinSubByte = ExtBytesPerElement - OpBytesPerElement;
4565 if (SubByte < MinSubByte ||
4566 SubByte + BytesPerElement > ExtBytesPerElement)
4568 // Get the byte offset of the unextended element
4569 Byte = Byte / ExtBytesPerElement * OpBytesPerElement;
4570 // ...then add the byte offset relative to that element.
4571 Byte += SubByte - MinSubByte;
4572 if (Byte % BytesPerElement != 0)
4574 Op = Op.getOperand(0);
4575 Index = Byte / BytesPerElement;
4581 if (Op.getValueType() != VecVT) {
4582 Op = DAG.getNode(ISD::BITCAST, DL, VecVT, Op);
4583 DCI.AddToWorklist(Op.getNode());
4585 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ResVT, Op,
4586 DAG.getConstant(Index, DL, MVT::i32));
4591 // Optimize vector operations in scalar value Op on the basis that Op
4592 // is truncated to TruncVT.
4594 SystemZTargetLowering::combineTruncateExtract(SDLoc DL, EVT TruncVT, SDValue Op,
4595 DAGCombinerInfo &DCI) const {
4596 // If we have (trunc (extract_vector_elt X, Y)), try to turn it into
4597 // (extract_vector_elt (bitcast X), Y'), where (bitcast X) has elements
4599 if (Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
4600 TruncVT.getSizeInBits() % 8 == 0) {
4601 SDValue Vec = Op.getOperand(0);
4602 EVT VecVT = Vec.getValueType();
4603 if (canTreatAsByteVector(VecVT)) {
4604 if (auto *IndexN = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
4605 unsigned BytesPerElement = VecVT.getVectorElementType().getStoreSize();
4606 unsigned TruncBytes = TruncVT.getStoreSize();
4607 if (BytesPerElement % TruncBytes == 0) {
4608 // Calculate the value of Y' in the above description. We are
4609 // splitting the original elements into Scale equal-sized pieces
4610 // and for truncation purposes want the last (least-significant)
4611 // of these pieces for IndexN. This is easiest to do by calculating
4612 // the start index of the following element and then subtracting 1.
4613 unsigned Scale = BytesPerElement / TruncBytes;
4614 unsigned NewIndex = (IndexN->getZExtValue() + 1) * Scale - 1;
4616 // Defer the creation of the bitcast from X to combineExtract,
4617 // which might be able to optimize the extraction.
4618 VecVT = MVT::getVectorVT(MVT::getIntegerVT(TruncBytes * 8),
4619 VecVT.getStoreSize() / TruncBytes);
4620 EVT ResVT = (TruncBytes < 4 ? MVT::i32 : TruncVT);
4621 return combineExtract(DL, ResVT, VecVT, Vec, NewIndex, DCI, true);
4629 SDValue SystemZTargetLowering::PerformDAGCombine(SDNode *N,
4630 DAGCombinerInfo &DCI) const {
4631 SelectionDAG &DAG = DCI.DAG;
4632 unsigned Opcode = N->getOpcode();
4633 if (Opcode == ISD::SIGN_EXTEND) {
4634 // Convert (sext (ashr (shl X, C1), C2)) to
4635 // (ashr (shl (anyext X), C1'), C2')), since wider shifts are as
4636 // cheap as narrower ones.
4637 SDValue N0 = N->getOperand(0);
4638 EVT VT = N->getValueType(0);
4639 if (N0.hasOneUse() && N0.getOpcode() == ISD::SRA) {
4640 auto *SraAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1));
4641 SDValue Inner = N0.getOperand(0);
4642 if (SraAmt && Inner.hasOneUse() && Inner.getOpcode() == ISD::SHL) {
4643 if (auto *ShlAmt = dyn_cast<ConstantSDNode>(Inner.getOperand(1))) {
4644 unsigned Extra = (VT.getSizeInBits() -
4645 N0.getValueType().getSizeInBits());
4646 unsigned NewShlAmt = ShlAmt->getZExtValue() + Extra;
4647 unsigned NewSraAmt = SraAmt->getZExtValue() + Extra;
4648 EVT ShiftVT = N0.getOperand(1).getValueType();
4649 SDValue Ext = DAG.getNode(ISD::ANY_EXTEND, SDLoc(Inner), VT,
4650 Inner.getOperand(0));
4651 SDValue Shl = DAG.getNode(ISD::SHL, SDLoc(Inner), VT, Ext,
4652 DAG.getConstant(NewShlAmt, SDLoc(Inner),
4654 return DAG.getNode(ISD::SRA, SDLoc(N0), VT, Shl,
4655 DAG.getConstant(NewSraAmt, SDLoc(N0), ShiftVT));
4660 if (Opcode == SystemZISD::MERGE_HIGH ||
4661 Opcode == SystemZISD::MERGE_LOW) {
4662 SDValue Op0 = N->getOperand(0);
4663 SDValue Op1 = N->getOperand(1);
4664 if (Op0.getOpcode() == ISD::BITCAST)
4665 Op0 = Op0.getOperand(0);
4666 if (Op0.getOpcode() == SystemZISD::BYTE_MASK &&
4667 cast<ConstantSDNode>(Op0.getOperand(0))->getZExtValue() == 0) {
4668 // (z_merge_* 0, 0) -> 0. This is mostly useful for using VLLEZF
4670 if (Op1 == N->getOperand(0))
4672 // (z_merge_? 0, X) -> (z_unpackl_? 0, X).
4673 EVT VT = Op1.getValueType();
4674 unsigned ElemBytes = VT.getVectorElementType().getStoreSize();
4675 if (ElemBytes <= 4) {
4676 Opcode = (Opcode == SystemZISD::MERGE_HIGH ?
4677 SystemZISD::UNPACKL_HIGH : SystemZISD::UNPACKL_LOW);
4678 EVT InVT = VT.changeVectorElementTypeToInteger();
4679 EVT OutVT = MVT::getVectorVT(MVT::getIntegerVT(ElemBytes * 16),
4680 SystemZ::VectorBytes / ElemBytes / 2);
4682 Op1 = DAG.getNode(ISD::BITCAST, SDLoc(N), InVT, Op1);
4683 DCI.AddToWorklist(Op1.getNode());
4685 SDValue Op = DAG.getNode(Opcode, SDLoc(N), OutVT, Op1);
4686 DCI.AddToWorklist(Op.getNode());
4687 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
4691 // If we have (truncstoreiN (extract_vector_elt X, Y), Z) then it is better
4692 // for the extraction to be done on a vMiN value, so that we can use VSTE.
4693 // If X has wider elements then convert it to:
4694 // (truncstoreiN (extract_vector_elt (bitcast X), Y2), Z).
4695 if (Opcode == ISD::STORE) {
4696 auto *SN = cast<StoreSDNode>(N);
4697 EVT MemVT = SN->getMemoryVT();
4698 if (MemVT.isInteger()) {
4699 SDValue Value = combineTruncateExtract(SDLoc(N), MemVT,
4700 SN->getValue(), DCI);
4701 if (Value.getNode()) {
4702 DCI.AddToWorklist(Value.getNode());
4704 // Rewrite the store with the new form of stored value.
4705 return DAG.getTruncStore(SN->getChain(), SDLoc(SN), Value,
4706 SN->getBasePtr(), SN->getMemoryVT(),
4707 SN->getMemOperand());
4711 // Try to simplify a vector extraction.
4712 if (Opcode == ISD::EXTRACT_VECTOR_ELT) {
4713 if (auto *IndexN = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
4714 SDValue Op0 = N->getOperand(0);
4715 EVT VecVT = Op0.getValueType();
4716 return combineExtract(SDLoc(N), N->getValueType(0), VecVT, Op0,
4717 IndexN->getZExtValue(), DCI, false);
4720 // (join_dwords X, X) == (replicate X)
4721 if (Opcode == SystemZISD::JOIN_DWORDS &&
4722 N->getOperand(0) == N->getOperand(1))
4723 return DAG.getNode(SystemZISD::REPLICATE, SDLoc(N), N->getValueType(0),
4725 // (fround (extract_vector_elt X 0))
4726 // (fround (extract_vector_elt X 1)) ->
4727 // (extract_vector_elt (VROUND X) 0)
4728 // (extract_vector_elt (VROUND X) 1)
4730 // This is a special case since the target doesn't really support v2f32s.
4731 if (Opcode == ISD::FP_ROUND) {
4732 SDValue Op0 = N->getOperand(0);
4733 if (N->getValueType(0) == MVT::f32 &&
4735 Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
4736 Op0.getOperand(0).getValueType() == MVT::v2f64 &&
4737 Op0.getOperand(1).getOpcode() == ISD::Constant &&
4738 cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue() == 0) {
4739 SDValue Vec = Op0.getOperand(0);
4740 for (auto *U : Vec->uses()) {
4741 if (U != Op0.getNode() &&
4743 U->getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
4744 U->getOperand(0) == Vec &&
4745 U->getOperand(1).getOpcode() == ISD::Constant &&
4746 cast<ConstantSDNode>(U->getOperand(1))->getZExtValue() == 1) {
4747 SDValue OtherRound = SDValue(*U->use_begin(), 0);
4748 if (OtherRound.getOpcode() == ISD::FP_ROUND &&
4749 OtherRound.getOperand(0) == SDValue(U, 0) &&
4750 OtherRound.getValueType() == MVT::f32) {
4751 SDValue VRound = DAG.getNode(SystemZISD::VROUND, SDLoc(N),
4753 DCI.AddToWorklist(VRound.getNode());
4755 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(U), MVT::f32,
4756 VRound, DAG.getConstant(2, SDLoc(U), MVT::i32));
4757 DCI.AddToWorklist(Extract1.getNode());
4758 DAG.ReplaceAllUsesOfValueWith(OtherRound, Extract1);
4760 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op0), MVT::f32,
4761 VRound, DAG.getConstant(0, SDLoc(Op0), MVT::i32));
4771 //===----------------------------------------------------------------------===//
4773 //===----------------------------------------------------------------------===//
4775 // Create a new basic block after MBB.
4776 static MachineBasicBlock *emitBlockAfter(MachineBasicBlock *MBB) {
4777 MachineFunction &MF = *MBB->getParent();
4778 MachineBasicBlock *NewMBB = MF.CreateMachineBasicBlock(MBB->getBasicBlock());
4779 MF.insert(std::next(MachineFunction::iterator(MBB)), NewMBB);
4783 // Split MBB after MI and return the new block (the one that contains
4784 // instructions after MI).
4785 static MachineBasicBlock *splitBlockAfter(MachineInstr *MI,
4786 MachineBasicBlock *MBB) {
4787 MachineBasicBlock *NewMBB = emitBlockAfter(MBB);
4788 NewMBB->splice(NewMBB->begin(), MBB,
4789 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
4790 NewMBB->transferSuccessorsAndUpdatePHIs(MBB);
4794 // Split MBB before MI and return the new block (the one that contains MI).
4795 static MachineBasicBlock *splitBlockBefore(MachineInstr *MI,
4796 MachineBasicBlock *MBB) {
4797 MachineBasicBlock *NewMBB = emitBlockAfter(MBB);
4798 NewMBB->splice(NewMBB->begin(), MBB, MI, MBB->end());
4799 NewMBB->transferSuccessorsAndUpdatePHIs(MBB);
4803 // Force base value Base into a register before MI. Return the register.
4804 static unsigned forceReg(MachineInstr *MI, MachineOperand &Base,
4805 const SystemZInstrInfo *TII) {
4807 return Base.getReg();
4809 MachineBasicBlock *MBB = MI->getParent();
4810 MachineFunction &MF = *MBB->getParent();
4811 MachineRegisterInfo &MRI = MF.getRegInfo();
4813 unsigned Reg = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
4814 BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(SystemZ::LA), Reg)
4815 .addOperand(Base).addImm(0).addReg(0);
4819 // Implement EmitInstrWithCustomInserter for pseudo Select* instruction MI.
4821 SystemZTargetLowering::emitSelect(MachineInstr *MI,
4822 MachineBasicBlock *MBB) const {
4823 const SystemZInstrInfo *TII =
4824 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
4826 unsigned DestReg = MI->getOperand(0).getReg();
4827 unsigned TrueReg = MI->getOperand(1).getReg();
4828 unsigned FalseReg = MI->getOperand(2).getReg();
4829 unsigned CCValid = MI->getOperand(3).getImm();
4830 unsigned CCMask = MI->getOperand(4).getImm();
4831 DebugLoc DL = MI->getDebugLoc();
4833 MachineBasicBlock *StartMBB = MBB;
4834 MachineBasicBlock *JoinMBB = splitBlockBefore(MI, MBB);
4835 MachineBasicBlock *FalseMBB = emitBlockAfter(StartMBB);
4838 // BRC CCMask, JoinMBB
4839 // # fallthrough to FalseMBB
4841 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
4842 .addImm(CCValid).addImm(CCMask).addMBB(JoinMBB);
4843 MBB->addSuccessor(JoinMBB);
4844 MBB->addSuccessor(FalseMBB);
4847 // # fallthrough to JoinMBB
4849 MBB->addSuccessor(JoinMBB);
4852 // %Result = phi [ %FalseReg, FalseMBB ], [ %TrueReg, StartMBB ]
4855 BuildMI(*MBB, MI, DL, TII->get(SystemZ::PHI), DestReg)
4856 .addReg(TrueReg).addMBB(StartMBB)
4857 .addReg(FalseReg).addMBB(FalseMBB);
4859 MI->eraseFromParent();
4863 // Implement EmitInstrWithCustomInserter for pseudo CondStore* instruction MI.
4864 // StoreOpcode is the store to use and Invert says whether the store should
4865 // happen when the condition is false rather than true. If a STORE ON
4866 // CONDITION is available, STOCOpcode is its opcode, otherwise it is 0.
4868 SystemZTargetLowering::emitCondStore(MachineInstr *MI,
4869 MachineBasicBlock *MBB,
4870 unsigned StoreOpcode, unsigned STOCOpcode,
4871 bool Invert) const {
4872 const SystemZInstrInfo *TII =
4873 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
4875 unsigned SrcReg = MI->getOperand(0).getReg();
4876 MachineOperand Base = MI->getOperand(1);
4877 int64_t Disp = MI->getOperand(2).getImm();
4878 unsigned IndexReg = MI->getOperand(3).getReg();
4879 unsigned CCValid = MI->getOperand(4).getImm();
4880 unsigned CCMask = MI->getOperand(5).getImm();
4881 DebugLoc DL = MI->getDebugLoc();
4883 StoreOpcode = TII->getOpcodeForOffset(StoreOpcode, Disp);
4885 // Use STOCOpcode if possible. We could use different store patterns in
4886 // order to avoid matching the index register, but the performance trade-offs
4887 // might be more complicated in that case.
4888 if (STOCOpcode && !IndexReg && Subtarget.hasLoadStoreOnCond()) {
4891 BuildMI(*MBB, MI, DL, TII->get(STOCOpcode))
4892 .addReg(SrcReg).addOperand(Base).addImm(Disp)
4893 .addImm(CCValid).addImm(CCMask);
4894 MI->eraseFromParent();
4898 // Get the condition needed to branch around the store.
4902 MachineBasicBlock *StartMBB = MBB;
4903 MachineBasicBlock *JoinMBB = splitBlockBefore(MI, MBB);
4904 MachineBasicBlock *FalseMBB = emitBlockAfter(StartMBB);
4907 // BRC CCMask, JoinMBB
4908 // # fallthrough to FalseMBB
4910 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
4911 .addImm(CCValid).addImm(CCMask).addMBB(JoinMBB);
4912 MBB->addSuccessor(JoinMBB);
4913 MBB->addSuccessor(FalseMBB);
4916 // store %SrcReg, %Disp(%Index,%Base)
4917 // # fallthrough to JoinMBB
4919 BuildMI(MBB, DL, TII->get(StoreOpcode))
4920 .addReg(SrcReg).addOperand(Base).addImm(Disp).addReg(IndexReg);
4921 MBB->addSuccessor(JoinMBB);
4923 MI->eraseFromParent();
4927 // Implement EmitInstrWithCustomInserter for pseudo ATOMIC_LOAD{,W}_*
4928 // or ATOMIC_SWAP{,W} instruction MI. BinOpcode is the instruction that
4929 // performs the binary operation elided by "*", or 0 for ATOMIC_SWAP{,W}.
4930 // BitSize is the width of the field in bits, or 0 if this is a partword
4931 // ATOMIC_LOADW_* or ATOMIC_SWAPW instruction, in which case the bitsize
4932 // is one of the operands. Invert says whether the field should be
4933 // inverted after performing BinOpcode (e.g. for NAND).
4935 SystemZTargetLowering::emitAtomicLoadBinary(MachineInstr *MI,
4936 MachineBasicBlock *MBB,
4939 bool Invert) const {
4940 MachineFunction &MF = *MBB->getParent();
4941 const SystemZInstrInfo *TII =
4942 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
4943 MachineRegisterInfo &MRI = MF.getRegInfo();
4944 bool IsSubWord = (BitSize < 32);
4946 // Extract the operands. Base can be a register or a frame index.
4947 // Src2 can be a register or immediate.
4948 unsigned Dest = MI->getOperand(0).getReg();
4949 MachineOperand Base = earlyUseOperand(MI->getOperand(1));
4950 int64_t Disp = MI->getOperand(2).getImm();
4951 MachineOperand Src2 = earlyUseOperand(MI->getOperand(3));
4952 unsigned BitShift = (IsSubWord ? MI->getOperand(4).getReg() : 0);
4953 unsigned NegBitShift = (IsSubWord ? MI->getOperand(5).getReg() : 0);
4954 DebugLoc DL = MI->getDebugLoc();
4956 BitSize = MI->getOperand(6).getImm();
4958 // Subword operations use 32-bit registers.
4959 const TargetRegisterClass *RC = (BitSize <= 32 ?
4960 &SystemZ::GR32BitRegClass :
4961 &SystemZ::GR64BitRegClass);
4962 unsigned LOpcode = BitSize <= 32 ? SystemZ::L : SystemZ::LG;
4963 unsigned CSOpcode = BitSize <= 32 ? SystemZ::CS : SystemZ::CSG;
4965 // Get the right opcodes for the displacement.
4966 LOpcode = TII->getOpcodeForOffset(LOpcode, Disp);
4967 CSOpcode = TII->getOpcodeForOffset(CSOpcode, Disp);
4968 assert(LOpcode && CSOpcode && "Displacement out of range");
4970 // Create virtual registers for temporary results.
4971 unsigned OrigVal = MRI.createVirtualRegister(RC);
4972 unsigned OldVal = MRI.createVirtualRegister(RC);
4973 unsigned NewVal = (BinOpcode || IsSubWord ?
4974 MRI.createVirtualRegister(RC) : Src2.getReg());
4975 unsigned RotatedOldVal = (IsSubWord ? MRI.createVirtualRegister(RC) : OldVal);
4976 unsigned RotatedNewVal = (IsSubWord ? MRI.createVirtualRegister(RC) : NewVal);
4978 // Insert a basic block for the main loop.
4979 MachineBasicBlock *StartMBB = MBB;
4980 MachineBasicBlock *DoneMBB = splitBlockBefore(MI, MBB);
4981 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
4985 // %OrigVal = L Disp(%Base)
4986 // # fall through to LoopMMB
4988 BuildMI(MBB, DL, TII->get(LOpcode), OrigVal)
4989 .addOperand(Base).addImm(Disp).addReg(0);
4990 MBB->addSuccessor(LoopMBB);
4993 // %OldVal = phi [ %OrigVal, StartMBB ], [ %Dest, LoopMBB ]
4994 // %RotatedOldVal = RLL %OldVal, 0(%BitShift)
4995 // %RotatedNewVal = OP %RotatedOldVal, %Src2
4996 // %NewVal = RLL %RotatedNewVal, 0(%NegBitShift)
4997 // %Dest = CS %OldVal, %NewVal, Disp(%Base)
4999 // # fall through to DoneMMB
5001 BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
5002 .addReg(OrigVal).addMBB(StartMBB)
5003 .addReg(Dest).addMBB(LoopMBB);
5005 BuildMI(MBB, DL, TII->get(SystemZ::RLL), RotatedOldVal)
5006 .addReg(OldVal).addReg(BitShift).addImm(0);
5008 // Perform the operation normally and then invert every bit of the field.
5009 unsigned Tmp = MRI.createVirtualRegister(RC);
5010 BuildMI(MBB, DL, TII->get(BinOpcode), Tmp)
5011 .addReg(RotatedOldVal).addOperand(Src2);
5013 // XILF with the upper BitSize bits set.
5014 BuildMI(MBB, DL, TII->get(SystemZ::XILF), RotatedNewVal)
5015 .addReg(Tmp).addImm(-1U << (32 - BitSize));
5017 // Use LCGR and add -1 to the result, which is more compact than
5018 // an XILF, XILH pair.
5019 unsigned Tmp2 = MRI.createVirtualRegister(RC);
5020 BuildMI(MBB, DL, TII->get(SystemZ::LCGR), Tmp2).addReg(Tmp);
5021 BuildMI(MBB, DL, TII->get(SystemZ::AGHI), RotatedNewVal)
5022 .addReg(Tmp2).addImm(-1);
5024 } else if (BinOpcode)
5025 // A simply binary operation.
5026 BuildMI(MBB, DL, TII->get(BinOpcode), RotatedNewVal)
5027 .addReg(RotatedOldVal).addOperand(Src2);
5029 // Use RISBG to rotate Src2 into position and use it to replace the
5030 // field in RotatedOldVal.
5031 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RotatedNewVal)
5032 .addReg(RotatedOldVal).addReg(Src2.getReg())
5033 .addImm(32).addImm(31 + BitSize).addImm(32 - BitSize);
5035 BuildMI(MBB, DL, TII->get(SystemZ::RLL), NewVal)
5036 .addReg(RotatedNewVal).addReg(NegBitShift).addImm(0);
5037 BuildMI(MBB, DL, TII->get(CSOpcode), Dest)
5038 .addReg(OldVal).addReg(NewVal).addOperand(Base).addImm(Disp);
5039 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
5040 .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
5041 MBB->addSuccessor(LoopMBB);
5042 MBB->addSuccessor(DoneMBB);
5044 MI->eraseFromParent();
5048 // Implement EmitInstrWithCustomInserter for pseudo
5049 // ATOMIC_LOAD{,W}_{,U}{MIN,MAX} instruction MI. CompareOpcode is the
5050 // instruction that should be used to compare the current field with the
5051 // minimum or maximum value. KeepOldMask is the BRC condition-code mask
5052 // for when the current field should be kept. BitSize is the width of
5053 // the field in bits, or 0 if this is a partword ATOMIC_LOADW_* instruction.
5055 SystemZTargetLowering::emitAtomicLoadMinMax(MachineInstr *MI,
5056 MachineBasicBlock *MBB,
5057 unsigned CompareOpcode,
5058 unsigned KeepOldMask,
5059 unsigned BitSize) const {
5060 MachineFunction &MF = *MBB->getParent();
5061 const SystemZInstrInfo *TII =
5062 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
5063 MachineRegisterInfo &MRI = MF.getRegInfo();
5064 bool IsSubWord = (BitSize < 32);
5066 // Extract the operands. Base can be a register or a frame index.
5067 unsigned Dest = MI->getOperand(0).getReg();
5068 MachineOperand Base = earlyUseOperand(MI->getOperand(1));
5069 int64_t Disp = MI->getOperand(2).getImm();
5070 unsigned Src2 = MI->getOperand(3).getReg();
5071 unsigned BitShift = (IsSubWord ? MI->getOperand(4).getReg() : 0);
5072 unsigned NegBitShift = (IsSubWord ? MI->getOperand(5).getReg() : 0);
5073 DebugLoc DL = MI->getDebugLoc();
5075 BitSize = MI->getOperand(6).getImm();
5077 // Subword operations use 32-bit registers.
5078 const TargetRegisterClass *RC = (BitSize <= 32 ?
5079 &SystemZ::GR32BitRegClass :
5080 &SystemZ::GR64BitRegClass);
5081 unsigned LOpcode = BitSize <= 32 ? SystemZ::L : SystemZ::LG;
5082 unsigned CSOpcode = BitSize <= 32 ? SystemZ::CS : SystemZ::CSG;
5084 // Get the right opcodes for the displacement.
5085 LOpcode = TII->getOpcodeForOffset(LOpcode, Disp);
5086 CSOpcode = TII->getOpcodeForOffset(CSOpcode, Disp);
5087 assert(LOpcode && CSOpcode && "Displacement out of range");
5089 // Create virtual registers for temporary results.
5090 unsigned OrigVal = MRI.createVirtualRegister(RC);
5091 unsigned OldVal = MRI.createVirtualRegister(RC);
5092 unsigned NewVal = MRI.createVirtualRegister(RC);
5093 unsigned RotatedOldVal = (IsSubWord ? MRI.createVirtualRegister(RC) : OldVal);
5094 unsigned RotatedAltVal = (IsSubWord ? MRI.createVirtualRegister(RC) : Src2);
5095 unsigned RotatedNewVal = (IsSubWord ? MRI.createVirtualRegister(RC) : NewVal);
5097 // Insert 3 basic blocks for the loop.
5098 MachineBasicBlock *StartMBB = MBB;
5099 MachineBasicBlock *DoneMBB = splitBlockBefore(MI, MBB);
5100 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
5101 MachineBasicBlock *UseAltMBB = emitBlockAfter(LoopMBB);
5102 MachineBasicBlock *UpdateMBB = emitBlockAfter(UseAltMBB);
5106 // %OrigVal = L Disp(%Base)
5107 // # fall through to LoopMMB
5109 BuildMI(MBB, DL, TII->get(LOpcode), OrigVal)
5110 .addOperand(Base).addImm(Disp).addReg(0);
5111 MBB->addSuccessor(LoopMBB);
5114 // %OldVal = phi [ %OrigVal, StartMBB ], [ %Dest, UpdateMBB ]
5115 // %RotatedOldVal = RLL %OldVal, 0(%BitShift)
5116 // CompareOpcode %RotatedOldVal, %Src2
5117 // BRC KeepOldMask, UpdateMBB
5119 BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
5120 .addReg(OrigVal).addMBB(StartMBB)
5121 .addReg(Dest).addMBB(UpdateMBB);
5123 BuildMI(MBB, DL, TII->get(SystemZ::RLL), RotatedOldVal)
5124 .addReg(OldVal).addReg(BitShift).addImm(0);
5125 BuildMI(MBB, DL, TII->get(CompareOpcode))
5126 .addReg(RotatedOldVal).addReg(Src2);
5127 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
5128 .addImm(SystemZ::CCMASK_ICMP).addImm(KeepOldMask).addMBB(UpdateMBB);
5129 MBB->addSuccessor(UpdateMBB);
5130 MBB->addSuccessor(UseAltMBB);
5133 // %RotatedAltVal = RISBG %RotatedOldVal, %Src2, 32, 31 + BitSize, 0
5134 // # fall through to UpdateMMB
5137 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RotatedAltVal)
5138 .addReg(RotatedOldVal).addReg(Src2)
5139 .addImm(32).addImm(31 + BitSize).addImm(0);
5140 MBB->addSuccessor(UpdateMBB);
5143 // %RotatedNewVal = PHI [ %RotatedOldVal, LoopMBB ],
5144 // [ %RotatedAltVal, UseAltMBB ]
5145 // %NewVal = RLL %RotatedNewVal, 0(%NegBitShift)
5146 // %Dest = CS %OldVal, %NewVal, Disp(%Base)
5148 // # fall through to DoneMMB
5150 BuildMI(MBB, DL, TII->get(SystemZ::PHI), RotatedNewVal)
5151 .addReg(RotatedOldVal).addMBB(LoopMBB)
5152 .addReg(RotatedAltVal).addMBB(UseAltMBB);
5154 BuildMI(MBB, DL, TII->get(SystemZ::RLL), NewVal)
5155 .addReg(RotatedNewVal).addReg(NegBitShift).addImm(0);
5156 BuildMI(MBB, DL, TII->get(CSOpcode), Dest)
5157 .addReg(OldVal).addReg(NewVal).addOperand(Base).addImm(Disp);
5158 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
5159 .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
5160 MBB->addSuccessor(LoopMBB);
5161 MBB->addSuccessor(DoneMBB);
5163 MI->eraseFromParent();
5167 // Implement EmitInstrWithCustomInserter for pseudo ATOMIC_CMP_SWAPW
5170 SystemZTargetLowering::emitAtomicCmpSwapW(MachineInstr *MI,
5171 MachineBasicBlock *MBB) const {
5172 MachineFunction &MF = *MBB->getParent();
5173 const SystemZInstrInfo *TII =
5174 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
5175 MachineRegisterInfo &MRI = MF.getRegInfo();
5177 // Extract the operands. Base can be a register or a frame index.
5178 unsigned Dest = MI->getOperand(0).getReg();
5179 MachineOperand Base = earlyUseOperand(MI->getOperand(1));
5180 int64_t Disp = MI->getOperand(2).getImm();
5181 unsigned OrigCmpVal = MI->getOperand(3).getReg();
5182 unsigned OrigSwapVal = MI->getOperand(4).getReg();
5183 unsigned BitShift = MI->getOperand(5).getReg();
5184 unsigned NegBitShift = MI->getOperand(6).getReg();
5185 int64_t BitSize = MI->getOperand(7).getImm();
5186 DebugLoc DL = MI->getDebugLoc();
5188 const TargetRegisterClass *RC = &SystemZ::GR32BitRegClass;
5190 // Get the right opcodes for the displacement.
5191 unsigned LOpcode = TII->getOpcodeForOffset(SystemZ::L, Disp);
5192 unsigned CSOpcode = TII->getOpcodeForOffset(SystemZ::CS, Disp);
5193 assert(LOpcode && CSOpcode && "Displacement out of range");
5195 // Create virtual registers for temporary results.
5196 unsigned OrigOldVal = MRI.createVirtualRegister(RC);
5197 unsigned OldVal = MRI.createVirtualRegister(RC);
5198 unsigned CmpVal = MRI.createVirtualRegister(RC);
5199 unsigned SwapVal = MRI.createVirtualRegister(RC);
5200 unsigned StoreVal = MRI.createVirtualRegister(RC);
5201 unsigned RetryOldVal = MRI.createVirtualRegister(RC);
5202 unsigned RetryCmpVal = MRI.createVirtualRegister(RC);
5203 unsigned RetrySwapVal = MRI.createVirtualRegister(RC);
5205 // Insert 2 basic blocks for the loop.
5206 MachineBasicBlock *StartMBB = MBB;
5207 MachineBasicBlock *DoneMBB = splitBlockBefore(MI, MBB);
5208 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
5209 MachineBasicBlock *SetMBB = emitBlockAfter(LoopMBB);
5213 // %OrigOldVal = L Disp(%Base)
5214 // # fall through to LoopMMB
5216 BuildMI(MBB, DL, TII->get(LOpcode), OrigOldVal)
5217 .addOperand(Base).addImm(Disp).addReg(0);
5218 MBB->addSuccessor(LoopMBB);
5221 // %OldVal = phi [ %OrigOldVal, EntryBB ], [ %RetryOldVal, SetMBB ]
5222 // %CmpVal = phi [ %OrigCmpVal, EntryBB ], [ %RetryCmpVal, SetMBB ]
5223 // %SwapVal = phi [ %OrigSwapVal, EntryBB ], [ %RetrySwapVal, SetMBB ]
5224 // %Dest = RLL %OldVal, BitSize(%BitShift)
5225 // ^^ The low BitSize bits contain the field
5227 // %RetryCmpVal = RISBG32 %CmpVal, %Dest, 32, 63-BitSize, 0
5228 // ^^ Replace the upper 32-BitSize bits of the
5229 // comparison value with those that we loaded,
5230 // so that we can use a full word comparison.
5231 // CR %Dest, %RetryCmpVal
5233 // # Fall through to SetMBB
5235 BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
5236 .addReg(OrigOldVal).addMBB(StartMBB)
5237 .addReg(RetryOldVal).addMBB(SetMBB);
5238 BuildMI(MBB, DL, TII->get(SystemZ::PHI), CmpVal)
5239 .addReg(OrigCmpVal).addMBB(StartMBB)
5240 .addReg(RetryCmpVal).addMBB(SetMBB);
5241 BuildMI(MBB, DL, TII->get(SystemZ::PHI), SwapVal)
5242 .addReg(OrigSwapVal).addMBB(StartMBB)
5243 .addReg(RetrySwapVal).addMBB(SetMBB);
5244 BuildMI(MBB, DL, TII->get(SystemZ::RLL), Dest)
5245 .addReg(OldVal).addReg(BitShift).addImm(BitSize);
5246 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RetryCmpVal)
5247 .addReg(CmpVal).addReg(Dest).addImm(32).addImm(63 - BitSize).addImm(0);
5248 BuildMI(MBB, DL, TII->get(SystemZ::CR))
5249 .addReg(Dest).addReg(RetryCmpVal);
5250 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
5251 .addImm(SystemZ::CCMASK_ICMP)
5252 .addImm(SystemZ::CCMASK_CMP_NE).addMBB(DoneMBB);
5253 MBB->addSuccessor(DoneMBB);
5254 MBB->addSuccessor(SetMBB);
5257 // %RetrySwapVal = RISBG32 %SwapVal, %Dest, 32, 63-BitSize, 0
5258 // ^^ Replace the upper 32-BitSize bits of the new
5259 // value with those that we loaded.
5260 // %StoreVal = RLL %RetrySwapVal, -BitSize(%NegBitShift)
5261 // ^^ Rotate the new field to its proper position.
5262 // %RetryOldVal = CS %Dest, %StoreVal, Disp(%Base)
5264 // # fall through to ExitMMB
5266 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RetrySwapVal)
5267 .addReg(SwapVal).addReg(Dest).addImm(32).addImm(63 - BitSize).addImm(0);
5268 BuildMI(MBB, DL, TII->get(SystemZ::RLL), StoreVal)
5269 .addReg(RetrySwapVal).addReg(NegBitShift).addImm(-BitSize);
5270 BuildMI(MBB, DL, TII->get(CSOpcode), RetryOldVal)
5271 .addReg(OldVal).addReg(StoreVal).addOperand(Base).addImm(Disp);
5272 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
5273 .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
5274 MBB->addSuccessor(LoopMBB);
5275 MBB->addSuccessor(DoneMBB);
5277 MI->eraseFromParent();
5281 // Emit an extension from a GR32 or GR64 to a GR128. ClearEven is true
5282 // if the high register of the GR128 value must be cleared or false if
5283 // it's "don't care". SubReg is subreg_l32 when extending a GR32
5284 // and subreg_l64 when extending a GR64.
5286 SystemZTargetLowering::emitExt128(MachineInstr *MI,
5287 MachineBasicBlock *MBB,
5288 bool ClearEven, unsigned SubReg) const {
5289 MachineFunction &MF = *MBB->getParent();
5290 const SystemZInstrInfo *TII =
5291 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
5292 MachineRegisterInfo &MRI = MF.getRegInfo();
5293 DebugLoc DL = MI->getDebugLoc();
5295 unsigned Dest = MI->getOperand(0).getReg();
5296 unsigned Src = MI->getOperand(1).getReg();
5297 unsigned In128 = MRI.createVirtualRegister(&SystemZ::GR128BitRegClass);
5299 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::IMPLICIT_DEF), In128);
5301 unsigned NewIn128 = MRI.createVirtualRegister(&SystemZ::GR128BitRegClass);
5302 unsigned Zero64 = MRI.createVirtualRegister(&SystemZ::GR64BitRegClass);
5304 BuildMI(*MBB, MI, DL, TII->get(SystemZ::LLILL), Zero64)
5306 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::INSERT_SUBREG), NewIn128)
5307 .addReg(In128).addReg(Zero64).addImm(SystemZ::subreg_h64);
5310 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::INSERT_SUBREG), Dest)
5311 .addReg(In128).addReg(Src).addImm(SubReg);
5313 MI->eraseFromParent();
5318 SystemZTargetLowering::emitMemMemWrapper(MachineInstr *MI,
5319 MachineBasicBlock *MBB,
5320 unsigned Opcode) const {
5321 MachineFunction &MF = *MBB->getParent();
5322 const SystemZInstrInfo *TII =
5323 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
5324 MachineRegisterInfo &MRI = MF.getRegInfo();
5325 DebugLoc DL = MI->getDebugLoc();
5327 MachineOperand DestBase = earlyUseOperand(MI->getOperand(0));
5328 uint64_t DestDisp = MI->getOperand(1).getImm();
5329 MachineOperand SrcBase = earlyUseOperand(MI->getOperand(2));
5330 uint64_t SrcDisp = MI->getOperand(3).getImm();
5331 uint64_t Length = MI->getOperand(4).getImm();
5333 // When generating more than one CLC, all but the last will need to
5334 // branch to the end when a difference is found.
5335 MachineBasicBlock *EndMBB = (Length > 256 && Opcode == SystemZ::CLC ?
5336 splitBlockAfter(MI, MBB) : nullptr);
5338 // Check for the loop form, in which operand 5 is the trip count.
5339 if (MI->getNumExplicitOperands() > 5) {
5340 bool HaveSingleBase = DestBase.isIdenticalTo(SrcBase);
5342 uint64_t StartCountReg = MI->getOperand(5).getReg();
5343 uint64_t StartSrcReg = forceReg(MI, SrcBase, TII);
5344 uint64_t StartDestReg = (HaveSingleBase ? StartSrcReg :
5345 forceReg(MI, DestBase, TII));
5347 const TargetRegisterClass *RC = &SystemZ::ADDR64BitRegClass;
5348 uint64_t ThisSrcReg = MRI.createVirtualRegister(RC);
5349 uint64_t ThisDestReg = (HaveSingleBase ? ThisSrcReg :
5350 MRI.createVirtualRegister(RC));
5351 uint64_t NextSrcReg = MRI.createVirtualRegister(RC);
5352 uint64_t NextDestReg = (HaveSingleBase ? NextSrcReg :
5353 MRI.createVirtualRegister(RC));
5355 RC = &SystemZ::GR64BitRegClass;
5356 uint64_t ThisCountReg = MRI.createVirtualRegister(RC);
5357 uint64_t NextCountReg = MRI.createVirtualRegister(RC);
5359 MachineBasicBlock *StartMBB = MBB;
5360 MachineBasicBlock *DoneMBB = splitBlockBefore(MI, MBB);
5361 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
5362 MachineBasicBlock *NextMBB = (EndMBB ? emitBlockAfter(LoopMBB) : LoopMBB);
5365 // # fall through to LoopMMB
5366 MBB->addSuccessor(LoopMBB);
5369 // %ThisDestReg = phi [ %StartDestReg, StartMBB ],
5370 // [ %NextDestReg, NextMBB ]
5371 // %ThisSrcReg = phi [ %StartSrcReg, StartMBB ],
5372 // [ %NextSrcReg, NextMBB ]
5373 // %ThisCountReg = phi [ %StartCountReg, StartMBB ],
5374 // [ %NextCountReg, NextMBB ]
5375 // ( PFD 2, 768+DestDisp(%ThisDestReg) )
5376 // Opcode DestDisp(256,%ThisDestReg), SrcDisp(%ThisSrcReg)
5379 // The prefetch is used only for MVC. The JLH is used only for CLC.
5382 BuildMI(MBB, DL, TII->get(SystemZ::PHI), ThisDestReg)
5383 .addReg(StartDestReg).addMBB(StartMBB)
5384 .addReg(NextDestReg).addMBB(NextMBB);
5385 if (!HaveSingleBase)
5386 BuildMI(MBB, DL, TII->get(SystemZ::PHI), ThisSrcReg)
5387 .addReg(StartSrcReg).addMBB(StartMBB)
5388 .addReg(NextSrcReg).addMBB(NextMBB);
5389 BuildMI(MBB, DL, TII->get(SystemZ::PHI), ThisCountReg)
5390 .addReg(StartCountReg).addMBB(StartMBB)
5391 .addReg(NextCountReg).addMBB(NextMBB);
5392 if (Opcode == SystemZ::MVC)
5393 BuildMI(MBB, DL, TII->get(SystemZ::PFD))
5394 .addImm(SystemZ::PFD_WRITE)
5395 .addReg(ThisDestReg).addImm(DestDisp + 768).addReg(0);
5396 BuildMI(MBB, DL, TII->get(Opcode))
5397 .addReg(ThisDestReg).addImm(DestDisp).addImm(256)
5398 .addReg(ThisSrcReg).addImm(SrcDisp);
5400 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
5401 .addImm(SystemZ::CCMASK_ICMP).addImm(SystemZ::CCMASK_CMP_NE)
5403 MBB->addSuccessor(EndMBB);
5404 MBB->addSuccessor(NextMBB);
5408 // %NextDestReg = LA 256(%ThisDestReg)
5409 // %NextSrcReg = LA 256(%ThisSrcReg)
5410 // %NextCountReg = AGHI %ThisCountReg, -1
5411 // CGHI %NextCountReg, 0
5413 // # fall through to DoneMMB
5415 // The AGHI, CGHI and JLH should be converted to BRCTG by later passes.
5418 BuildMI(MBB, DL, TII->get(SystemZ::LA), NextDestReg)
5419 .addReg(ThisDestReg).addImm(256).addReg(0);
5420 if (!HaveSingleBase)
5421 BuildMI(MBB, DL, TII->get(SystemZ::LA), NextSrcReg)
5422 .addReg(ThisSrcReg).addImm(256).addReg(0);
5423 BuildMI(MBB, DL, TII->get(SystemZ::AGHI), NextCountReg)
5424 .addReg(ThisCountReg).addImm(-1);
5425 BuildMI(MBB, DL, TII->get(SystemZ::CGHI))
5426 .addReg(NextCountReg).addImm(0);
5427 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
5428 .addImm(SystemZ::CCMASK_ICMP).addImm(SystemZ::CCMASK_CMP_NE)
5430 MBB->addSuccessor(LoopMBB);
5431 MBB->addSuccessor(DoneMBB);
5433 DestBase = MachineOperand::CreateReg(NextDestReg, false);
5434 SrcBase = MachineOperand::CreateReg(NextSrcReg, false);
5438 // Handle any remaining bytes with straight-line code.
5439 while (Length > 0) {
5440 uint64_t ThisLength = std::min(Length, uint64_t(256));
5441 // The previous iteration might have created out-of-range displacements.
5442 // Apply them using LAY if so.
5443 if (!isUInt<12>(DestDisp)) {
5444 unsigned Reg = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
5445 BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(SystemZ::LAY), Reg)
5446 .addOperand(DestBase).addImm(DestDisp).addReg(0);
5447 DestBase = MachineOperand::CreateReg(Reg, false);
5450 if (!isUInt<12>(SrcDisp)) {
5451 unsigned Reg = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
5452 BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(SystemZ::LAY), Reg)
5453 .addOperand(SrcBase).addImm(SrcDisp).addReg(0);
5454 SrcBase = MachineOperand::CreateReg(Reg, false);
5457 BuildMI(*MBB, MI, DL, TII->get(Opcode))
5458 .addOperand(DestBase).addImm(DestDisp).addImm(ThisLength)
5459 .addOperand(SrcBase).addImm(SrcDisp);
5460 DestDisp += ThisLength;
5461 SrcDisp += ThisLength;
5462 Length -= ThisLength;
5463 // If there's another CLC to go, branch to the end if a difference
5465 if (EndMBB && Length > 0) {
5466 MachineBasicBlock *NextMBB = splitBlockBefore(MI, MBB);
5467 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
5468 .addImm(SystemZ::CCMASK_ICMP).addImm(SystemZ::CCMASK_CMP_NE)
5470 MBB->addSuccessor(EndMBB);
5471 MBB->addSuccessor(NextMBB);
5476 MBB->addSuccessor(EndMBB);
5478 MBB->addLiveIn(SystemZ::CC);
5481 MI->eraseFromParent();
5485 // Decompose string pseudo-instruction MI into a loop that continually performs
5486 // Opcode until CC != 3.
5488 SystemZTargetLowering::emitStringWrapper(MachineInstr *MI,
5489 MachineBasicBlock *MBB,
5490 unsigned Opcode) const {
5491 MachineFunction &MF = *MBB->getParent();
5492 const SystemZInstrInfo *TII =
5493 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
5494 MachineRegisterInfo &MRI = MF.getRegInfo();
5495 DebugLoc DL = MI->getDebugLoc();
5497 uint64_t End1Reg = MI->getOperand(0).getReg();
5498 uint64_t Start1Reg = MI->getOperand(1).getReg();
5499 uint64_t Start2Reg = MI->getOperand(2).getReg();
5500 uint64_t CharReg = MI->getOperand(3).getReg();
5502 const TargetRegisterClass *RC = &SystemZ::GR64BitRegClass;
5503 uint64_t This1Reg = MRI.createVirtualRegister(RC);
5504 uint64_t This2Reg = MRI.createVirtualRegister(RC);
5505 uint64_t End2Reg = MRI.createVirtualRegister(RC);
5507 MachineBasicBlock *StartMBB = MBB;
5508 MachineBasicBlock *DoneMBB = splitBlockBefore(MI, MBB);
5509 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
5512 // # fall through to LoopMMB
5513 MBB->addSuccessor(LoopMBB);
5516 // %This1Reg = phi [ %Start1Reg, StartMBB ], [ %End1Reg, LoopMBB ]
5517 // %This2Reg = phi [ %Start2Reg, StartMBB ], [ %End2Reg, LoopMBB ]
5519 // %End1Reg, %End2Reg = CLST %This1Reg, %This2Reg -- uses R0L
5521 // # fall through to DoneMMB
5523 // The load of R0L can be hoisted by post-RA LICM.
5526 BuildMI(MBB, DL, TII->get(SystemZ::PHI), This1Reg)
5527 .addReg(Start1Reg).addMBB(StartMBB)
5528 .addReg(End1Reg).addMBB(LoopMBB);
5529 BuildMI(MBB, DL, TII->get(SystemZ::PHI), This2Reg)
5530 .addReg(Start2Reg).addMBB(StartMBB)
5531 .addReg(End2Reg).addMBB(LoopMBB);
5532 BuildMI(MBB, DL, TII->get(TargetOpcode::COPY), SystemZ::R0L).addReg(CharReg);
5533 BuildMI(MBB, DL, TII->get(Opcode))
5534 .addReg(End1Reg, RegState::Define).addReg(End2Reg, RegState::Define)
5535 .addReg(This1Reg).addReg(This2Reg);
5536 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
5537 .addImm(SystemZ::CCMASK_ANY).addImm(SystemZ::CCMASK_3).addMBB(LoopMBB);
5538 MBB->addSuccessor(LoopMBB);
5539 MBB->addSuccessor(DoneMBB);
5541 DoneMBB->addLiveIn(SystemZ::CC);
5543 MI->eraseFromParent();
5547 // Update TBEGIN instruction with final opcode and register clobbers.
5549 SystemZTargetLowering::emitTransactionBegin(MachineInstr *MI,
5550 MachineBasicBlock *MBB,
5552 bool NoFloat) const {
5553 MachineFunction &MF = *MBB->getParent();
5554 const TargetFrameLowering *TFI = Subtarget.getFrameLowering();
5555 const SystemZInstrInfo *TII = Subtarget.getInstrInfo();
5558 MI->setDesc(TII->get(Opcode));
5560 // We cannot handle a TBEGIN that clobbers the stack or frame pointer.
5561 // Make sure to add the corresponding GRSM bits if they are missing.
5562 uint64_t Control = MI->getOperand(2).getImm();
5563 static const unsigned GPRControlBit[16] = {
5564 0x8000, 0x8000, 0x4000, 0x4000, 0x2000, 0x2000, 0x1000, 0x1000,
5565 0x0800, 0x0800, 0x0400, 0x0400, 0x0200, 0x0200, 0x0100, 0x0100
5567 Control |= GPRControlBit[15];
5569 Control |= GPRControlBit[11];
5570 MI->getOperand(2).setImm(Control);
5572 // Add GPR clobbers.
5573 for (int I = 0; I < 16; I++) {
5574 if ((Control & GPRControlBit[I]) == 0) {
5575 unsigned Reg = SystemZMC::GR64Regs[I];
5576 MI->addOperand(MachineOperand::CreateReg(Reg, true, true));
5580 // Add FPR/VR clobbers.
5581 if (!NoFloat && (Control & 4) != 0) {
5582 if (Subtarget.hasVector()) {
5583 for (int I = 0; I < 32; I++) {
5584 unsigned Reg = SystemZMC::VR128Regs[I];
5585 MI->addOperand(MachineOperand::CreateReg(Reg, true, true));
5588 for (int I = 0; I < 16; I++) {
5589 unsigned Reg = SystemZMC::FP64Regs[I];
5590 MI->addOperand(MachineOperand::CreateReg(Reg, true, true));
5598 MachineBasicBlock *SystemZTargetLowering::
5599 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const {
5600 switch (MI->getOpcode()) {
5601 case SystemZ::Select32Mux:
5602 case SystemZ::Select32:
5603 case SystemZ::SelectF32:
5604 case SystemZ::Select64:
5605 case SystemZ::SelectF64:
5606 case SystemZ::SelectF128:
5607 return emitSelect(MI, MBB);
5609 case SystemZ::CondStore8Mux:
5610 return emitCondStore(MI, MBB, SystemZ::STCMux, 0, false);
5611 case SystemZ::CondStore8MuxInv:
5612 return emitCondStore(MI, MBB, SystemZ::STCMux, 0, true);
5613 case SystemZ::CondStore16Mux:
5614 return emitCondStore(MI, MBB, SystemZ::STHMux, 0, false);
5615 case SystemZ::CondStore16MuxInv:
5616 return emitCondStore(MI, MBB, SystemZ::STHMux, 0, true);
5617 case SystemZ::CondStore8:
5618 return emitCondStore(MI, MBB, SystemZ::STC, 0, false);
5619 case SystemZ::CondStore8Inv:
5620 return emitCondStore(MI, MBB, SystemZ::STC, 0, true);
5621 case SystemZ::CondStore16:
5622 return emitCondStore(MI, MBB, SystemZ::STH, 0, false);
5623 case SystemZ::CondStore16Inv:
5624 return emitCondStore(MI, MBB, SystemZ::STH, 0, true);
5625 case SystemZ::CondStore32:
5626 return emitCondStore(MI, MBB, SystemZ::ST, SystemZ::STOC, false);
5627 case SystemZ::CondStore32Inv:
5628 return emitCondStore(MI, MBB, SystemZ::ST, SystemZ::STOC, true);
5629 case SystemZ::CondStore64:
5630 return emitCondStore(MI, MBB, SystemZ::STG, SystemZ::STOCG, false);
5631 case SystemZ::CondStore64Inv:
5632 return emitCondStore(MI, MBB, SystemZ::STG, SystemZ::STOCG, true);
5633 case SystemZ::CondStoreF32:
5634 return emitCondStore(MI, MBB, SystemZ::STE, 0, false);
5635 case SystemZ::CondStoreF32Inv:
5636 return emitCondStore(MI, MBB, SystemZ::STE, 0, true);
5637 case SystemZ::CondStoreF64:
5638 return emitCondStore(MI, MBB, SystemZ::STD, 0, false);
5639 case SystemZ::CondStoreF64Inv:
5640 return emitCondStore(MI, MBB, SystemZ::STD, 0, true);
5642 case SystemZ::AEXT128_64:
5643 return emitExt128(MI, MBB, false, SystemZ::subreg_l64);
5644 case SystemZ::ZEXT128_32:
5645 return emitExt128(MI, MBB, true, SystemZ::subreg_l32);
5646 case SystemZ::ZEXT128_64:
5647 return emitExt128(MI, MBB, true, SystemZ::subreg_l64);
5649 case SystemZ::ATOMIC_SWAPW:
5650 return emitAtomicLoadBinary(MI, MBB, 0, 0);
5651 case SystemZ::ATOMIC_SWAP_32:
5652 return emitAtomicLoadBinary(MI, MBB, 0, 32);
5653 case SystemZ::ATOMIC_SWAP_64:
5654 return emitAtomicLoadBinary(MI, MBB, 0, 64);
5656 case SystemZ::ATOMIC_LOADW_AR:
5657 return emitAtomicLoadBinary(MI, MBB, SystemZ::AR, 0);
5658 case SystemZ::ATOMIC_LOADW_AFI:
5659 return emitAtomicLoadBinary(MI, MBB, SystemZ::AFI, 0);
5660 case SystemZ::ATOMIC_LOAD_AR:
5661 return emitAtomicLoadBinary(MI, MBB, SystemZ::AR, 32);
5662 case SystemZ::ATOMIC_LOAD_AHI:
5663 return emitAtomicLoadBinary(MI, MBB, SystemZ::AHI, 32);
5664 case SystemZ::ATOMIC_LOAD_AFI:
5665 return emitAtomicLoadBinary(MI, MBB, SystemZ::AFI, 32);
5666 case SystemZ::ATOMIC_LOAD_AGR:
5667 return emitAtomicLoadBinary(MI, MBB, SystemZ::AGR, 64);
5668 case SystemZ::ATOMIC_LOAD_AGHI:
5669 return emitAtomicLoadBinary(MI, MBB, SystemZ::AGHI, 64);
5670 case SystemZ::ATOMIC_LOAD_AGFI:
5671 return emitAtomicLoadBinary(MI, MBB, SystemZ::AGFI, 64);
5673 case SystemZ::ATOMIC_LOADW_SR:
5674 return emitAtomicLoadBinary(MI, MBB, SystemZ::SR, 0);
5675 case SystemZ::ATOMIC_LOAD_SR:
5676 return emitAtomicLoadBinary(MI, MBB, SystemZ::SR, 32);
5677 case SystemZ::ATOMIC_LOAD_SGR:
5678 return emitAtomicLoadBinary(MI, MBB, SystemZ::SGR, 64);
5680 case SystemZ::ATOMIC_LOADW_NR:
5681 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 0);
5682 case SystemZ::ATOMIC_LOADW_NILH:
5683 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 0);
5684 case SystemZ::ATOMIC_LOAD_NR:
5685 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 32);
5686 case SystemZ::ATOMIC_LOAD_NILL:
5687 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL, 32);
5688 case SystemZ::ATOMIC_LOAD_NILH:
5689 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 32);
5690 case SystemZ::ATOMIC_LOAD_NILF:
5691 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF, 32);
5692 case SystemZ::ATOMIC_LOAD_NGR:
5693 return emitAtomicLoadBinary(MI, MBB, SystemZ::NGR, 64);
5694 case SystemZ::ATOMIC_LOAD_NILL64:
5695 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL64, 64);
5696 case SystemZ::ATOMIC_LOAD_NILH64:
5697 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH64, 64);
5698 case SystemZ::ATOMIC_LOAD_NIHL64:
5699 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHL64, 64);
5700 case SystemZ::ATOMIC_LOAD_NIHH64:
5701 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHH64, 64);
5702 case SystemZ::ATOMIC_LOAD_NILF64:
5703 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF64, 64);
5704 case SystemZ::ATOMIC_LOAD_NIHF64:
5705 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHF64, 64);
5707 case SystemZ::ATOMIC_LOADW_OR:
5708 return emitAtomicLoadBinary(MI, MBB, SystemZ::OR, 0);
5709 case SystemZ::ATOMIC_LOADW_OILH:
5710 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILH, 0);
5711 case SystemZ::ATOMIC_LOAD_OR:
5712 return emitAtomicLoadBinary(MI, MBB, SystemZ::OR, 32);
5713 case SystemZ::ATOMIC_LOAD_OILL:
5714 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILL, 32);
5715 case SystemZ::ATOMIC_LOAD_OILH:
5716 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILH, 32);
5717 case SystemZ::ATOMIC_LOAD_OILF:
5718 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILF, 32);
5719 case SystemZ::ATOMIC_LOAD_OGR:
5720 return emitAtomicLoadBinary(MI, MBB, SystemZ::OGR, 64);
5721 case SystemZ::ATOMIC_LOAD_OILL64:
5722 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILL64, 64);
5723 case SystemZ::ATOMIC_LOAD_OILH64:
5724 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILH64, 64);
5725 case SystemZ::ATOMIC_LOAD_OIHL64:
5726 return emitAtomicLoadBinary(MI, MBB, SystemZ::OIHL64, 64);
5727 case SystemZ::ATOMIC_LOAD_OIHH64:
5728 return emitAtomicLoadBinary(MI, MBB, SystemZ::OIHH64, 64);
5729 case SystemZ::ATOMIC_LOAD_OILF64:
5730 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILF64, 64);
5731 case SystemZ::ATOMIC_LOAD_OIHF64:
5732 return emitAtomicLoadBinary(MI, MBB, SystemZ::OIHF64, 64);
5734 case SystemZ::ATOMIC_LOADW_XR:
5735 return emitAtomicLoadBinary(MI, MBB, SystemZ::XR, 0);
5736 case SystemZ::ATOMIC_LOADW_XILF:
5737 return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF, 0);
5738 case SystemZ::ATOMIC_LOAD_XR:
5739 return emitAtomicLoadBinary(MI, MBB, SystemZ::XR, 32);
5740 case SystemZ::ATOMIC_LOAD_XILF:
5741 return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF, 32);
5742 case SystemZ::ATOMIC_LOAD_XGR:
5743 return emitAtomicLoadBinary(MI, MBB, SystemZ::XGR, 64);
5744 case SystemZ::ATOMIC_LOAD_XILF64:
5745 return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF64, 64);
5746 case SystemZ::ATOMIC_LOAD_XIHF64:
5747 return emitAtomicLoadBinary(MI, MBB, SystemZ::XIHF64, 64);
5749 case SystemZ::ATOMIC_LOADW_NRi:
5750 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 0, true);
5751 case SystemZ::ATOMIC_LOADW_NILHi:
5752 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 0, true);
5753 case SystemZ::ATOMIC_LOAD_NRi:
5754 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 32, true);
5755 case SystemZ::ATOMIC_LOAD_NILLi:
5756 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL, 32, true);
5757 case SystemZ::ATOMIC_LOAD_NILHi:
5758 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 32, true);
5759 case SystemZ::ATOMIC_LOAD_NILFi:
5760 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF, 32, true);
5761 case SystemZ::ATOMIC_LOAD_NGRi:
5762 return emitAtomicLoadBinary(MI, MBB, SystemZ::NGR, 64, true);
5763 case SystemZ::ATOMIC_LOAD_NILL64i:
5764 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL64, 64, true);
5765 case SystemZ::ATOMIC_LOAD_NILH64i:
5766 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH64, 64, true);
5767 case SystemZ::ATOMIC_LOAD_NIHL64i:
5768 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHL64, 64, true);
5769 case SystemZ::ATOMIC_LOAD_NIHH64i:
5770 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHH64, 64, true);
5771 case SystemZ::ATOMIC_LOAD_NILF64i:
5772 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF64, 64, true);
5773 case SystemZ::ATOMIC_LOAD_NIHF64i:
5774 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHF64, 64, true);
5776 case SystemZ::ATOMIC_LOADW_MIN:
5777 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
5778 SystemZ::CCMASK_CMP_LE, 0);
5779 case SystemZ::ATOMIC_LOAD_MIN_32:
5780 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
5781 SystemZ::CCMASK_CMP_LE, 32);
5782 case SystemZ::ATOMIC_LOAD_MIN_64:
5783 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CGR,
5784 SystemZ::CCMASK_CMP_LE, 64);
5786 case SystemZ::ATOMIC_LOADW_MAX:
5787 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
5788 SystemZ::CCMASK_CMP_GE, 0);
5789 case SystemZ::ATOMIC_LOAD_MAX_32:
5790 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
5791 SystemZ::CCMASK_CMP_GE, 32);
5792 case SystemZ::ATOMIC_LOAD_MAX_64:
5793 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CGR,
5794 SystemZ::CCMASK_CMP_GE, 64);
5796 case SystemZ::ATOMIC_LOADW_UMIN:
5797 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
5798 SystemZ::CCMASK_CMP_LE, 0);
5799 case SystemZ::ATOMIC_LOAD_UMIN_32:
5800 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
5801 SystemZ::CCMASK_CMP_LE, 32);
5802 case SystemZ::ATOMIC_LOAD_UMIN_64:
5803 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLGR,
5804 SystemZ::CCMASK_CMP_LE, 64);
5806 case SystemZ::ATOMIC_LOADW_UMAX:
5807 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
5808 SystemZ::CCMASK_CMP_GE, 0);
5809 case SystemZ::ATOMIC_LOAD_UMAX_32:
5810 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
5811 SystemZ::CCMASK_CMP_GE, 32);
5812 case SystemZ::ATOMIC_LOAD_UMAX_64:
5813 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLGR,
5814 SystemZ::CCMASK_CMP_GE, 64);
5816 case SystemZ::ATOMIC_CMP_SWAPW:
5817 return emitAtomicCmpSwapW(MI, MBB);
5818 case SystemZ::MVCSequence:
5819 case SystemZ::MVCLoop:
5820 return emitMemMemWrapper(MI, MBB, SystemZ::MVC);
5821 case SystemZ::NCSequence:
5822 case SystemZ::NCLoop:
5823 return emitMemMemWrapper(MI, MBB, SystemZ::NC);
5824 case SystemZ::OCSequence:
5825 case SystemZ::OCLoop:
5826 return emitMemMemWrapper(MI, MBB, SystemZ::OC);
5827 case SystemZ::XCSequence:
5828 case SystemZ::XCLoop:
5829 return emitMemMemWrapper(MI, MBB, SystemZ::XC);
5830 case SystemZ::CLCSequence:
5831 case SystemZ::CLCLoop:
5832 return emitMemMemWrapper(MI, MBB, SystemZ::CLC);
5833 case SystemZ::CLSTLoop:
5834 return emitStringWrapper(MI, MBB, SystemZ::CLST);
5835 case SystemZ::MVSTLoop:
5836 return emitStringWrapper(MI, MBB, SystemZ::MVST);
5837 case SystemZ::SRSTLoop:
5838 return emitStringWrapper(MI, MBB, SystemZ::SRST);
5839 case SystemZ::TBEGIN:
5840 return emitTransactionBegin(MI, MBB, SystemZ::TBEGIN, false);
5841 case SystemZ::TBEGIN_nofloat:
5842 return emitTransactionBegin(MI, MBB, SystemZ::TBEGIN, true);
5843 case SystemZ::TBEGINC:
5844 return emitTransactionBegin(MI, MBB, SystemZ::TBEGINC, true);
5846 llvm_unreachable("Unexpected instr type to insert");