1 //===-- SystemZISelLowering.cpp - SystemZ DAG lowering implementation -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SystemZTargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "SystemZISelLowering.h"
15 #include "SystemZCallingConv.h"
16 #include "SystemZConstantPoolValue.h"
17 #include "SystemZMachineFunctionInfo.h"
18 #include "SystemZTargetMachine.h"
19 #include "llvm/CodeGen/CallingConvLower.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
27 #define DEBUG_TYPE "systemz-lower"
30 // Represents a sequence for extracting a 0/1 value from an IPM result:
31 // (((X ^ XORValue) + AddValue) >> Bit)
32 struct IPMConversion {
33 IPMConversion(unsigned xorValue, int64_t addValue, unsigned bit)
34 : XORValue(xorValue), AddValue(addValue), Bit(bit) {}
41 // Represents information about a comparison.
43 Comparison(SDValue Op0In, SDValue Op1In)
44 : Op0(Op0In), Op1(Op1In), Opcode(0), ICmpType(0), CCValid(0), CCMask(0) {}
46 // The operands to the comparison.
49 // The opcode that should be used to compare Op0 and Op1.
52 // A SystemZICMP value. Only used for integer comparisons.
55 // The mask of CC values that Opcode can produce.
58 // The mask of CC values for which the original condition is true.
61 } // end anonymous namespace
63 // Classify VT as either 32 or 64 bit.
64 static bool is32Bit(EVT VT) {
65 switch (VT.getSimpleVT().SimpleTy) {
71 llvm_unreachable("Unsupported type");
75 // Return a version of MachineOperand that can be safely used before the
77 static MachineOperand earlyUseOperand(MachineOperand Op) {
83 SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &tm,
84 const SystemZSubtarget &STI)
85 : TargetLowering(tm), Subtarget(STI) {
86 MVT PtrVT = getPointerTy();
88 // Set up the register classes.
89 if (Subtarget.hasHighWord())
90 addRegisterClass(MVT::i32, &SystemZ::GRX32BitRegClass);
92 addRegisterClass(MVT::i32, &SystemZ::GR32BitRegClass);
93 addRegisterClass(MVT::i64, &SystemZ::GR64BitRegClass);
94 addRegisterClass(MVT::f32, &SystemZ::FP32BitRegClass);
95 addRegisterClass(MVT::f64, &SystemZ::FP64BitRegClass);
96 addRegisterClass(MVT::f128, &SystemZ::FP128BitRegClass);
98 // Compute derived properties from the register classes
99 computeRegisterProperties();
101 // Set up special registers.
102 setExceptionPointerRegister(SystemZ::R6D);
103 setExceptionSelectorRegister(SystemZ::R7D);
104 setStackPointerRegisterToSaveRestore(SystemZ::R15D);
106 // TODO: It may be better to default to latency-oriented scheduling, however
107 // LLVM's current latency-oriented scheduler can't handle physreg definitions
108 // such as SystemZ has with CC, so set this to the register-pressure
109 // scheduler, because it can.
110 setSchedulingPreference(Sched::RegPressure);
112 setBooleanContents(ZeroOrOneBooleanContent);
113 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
115 // Instructions are strings of 2-byte aligned 2-byte values.
116 setMinFunctionAlignment(2);
118 // Handle operations that are handled in a similar way for all types.
119 for (unsigned I = MVT::FIRST_INTEGER_VALUETYPE;
120 I <= MVT::LAST_FP_VALUETYPE;
122 MVT VT = MVT::SimpleValueType(I);
123 if (isTypeLegal(VT)) {
124 // Lower SET_CC into an IPM-based sequence.
125 setOperationAction(ISD::SETCC, VT, Custom);
127 // Expand SELECT(C, A, B) into SELECT_CC(X, 0, A, B, NE).
128 setOperationAction(ISD::SELECT, VT, Expand);
130 // Lower SELECT_CC and BR_CC into separate comparisons and branches.
131 setOperationAction(ISD::SELECT_CC, VT, Custom);
132 setOperationAction(ISD::BR_CC, VT, Custom);
136 // Expand jump table branches as address arithmetic followed by an
138 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
140 // Expand BRCOND into a BR_CC (see above).
141 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
143 // Handle integer types.
144 for (unsigned I = MVT::FIRST_INTEGER_VALUETYPE;
145 I <= MVT::LAST_INTEGER_VALUETYPE;
147 MVT VT = MVT::SimpleValueType(I);
148 if (isTypeLegal(VT)) {
149 // Expand individual DIV and REMs into DIVREMs.
150 setOperationAction(ISD::SDIV, VT, Expand);
151 setOperationAction(ISD::UDIV, VT, Expand);
152 setOperationAction(ISD::SREM, VT, Expand);
153 setOperationAction(ISD::UREM, VT, Expand);
154 setOperationAction(ISD::SDIVREM, VT, Custom);
155 setOperationAction(ISD::UDIVREM, VT, Custom);
157 // Lower ATOMIC_LOAD and ATOMIC_STORE into normal volatile loads and
158 // stores, putting a serialization instruction after the stores.
159 setOperationAction(ISD::ATOMIC_LOAD, VT, Custom);
160 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
162 // Lower ATOMIC_LOAD_SUB into ATOMIC_LOAD_ADD if LAA and LAAG are
163 // available, or if the operand is constant.
164 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
166 // No special instructions for these.
167 setOperationAction(ISD::CTPOP, VT, Expand);
168 setOperationAction(ISD::CTTZ, VT, Expand);
169 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
170 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
171 setOperationAction(ISD::ROTR, VT, Expand);
173 // Use *MUL_LOHI where possible instead of MULH*.
174 setOperationAction(ISD::MULHS, VT, Expand);
175 setOperationAction(ISD::MULHU, VT, Expand);
176 setOperationAction(ISD::SMUL_LOHI, VT, Custom);
177 setOperationAction(ISD::UMUL_LOHI, VT, Custom);
179 // Only z196 and above have native support for conversions to unsigned.
180 if (!Subtarget.hasFPExtension())
181 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
185 // Type legalization will convert 8- and 16-bit atomic operations into
186 // forms that operate on i32s (but still keeping the original memory VT).
187 // Lower them into full i32 operations.
188 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Custom);
189 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Custom);
190 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom);
191 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Custom);
192 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Custom);
193 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Custom);
194 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Custom);
195 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Custom);
196 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Custom);
197 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Custom);
198 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Custom);
199 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
201 // z10 has instructions for signed but not unsigned FP conversion.
202 // Handle unsigned 32-bit types as signed 64-bit types.
203 if (!Subtarget.hasFPExtension()) {
204 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Promote);
205 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
208 // We have native support for a 64-bit CTLZ, via FLOGR.
209 setOperationAction(ISD::CTLZ, MVT::i32, Promote);
210 setOperationAction(ISD::CTLZ, MVT::i64, Legal);
212 // Give LowerOperation the chance to replace 64-bit ORs with subregs.
213 setOperationAction(ISD::OR, MVT::i64, Custom);
215 // FIXME: Can we support these natively?
216 setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand);
217 setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
218 setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand);
220 // We have native instructions for i8, i16 and i32 extensions, but not i1.
221 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
222 for (MVT VT : MVT::integer_valuetypes()) {
223 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
224 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
225 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
228 // Handle the various types of symbolic address.
229 setOperationAction(ISD::ConstantPool, PtrVT, Custom);
230 setOperationAction(ISD::GlobalAddress, PtrVT, Custom);
231 setOperationAction(ISD::GlobalTLSAddress, PtrVT, Custom);
232 setOperationAction(ISD::BlockAddress, PtrVT, Custom);
233 setOperationAction(ISD::JumpTable, PtrVT, Custom);
235 // We need to handle dynamic allocations specially because of the
236 // 160-byte area at the bottom of the stack.
237 setOperationAction(ISD::DYNAMIC_STACKALLOC, PtrVT, Custom);
239 // Use custom expanders so that we can force the function to use
241 setOperationAction(ISD::STACKSAVE, MVT::Other, Custom);
242 setOperationAction(ISD::STACKRESTORE, MVT::Other, Custom);
244 // Handle prefetches with PFD or PFDRL.
245 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
247 // Handle floating-point types.
248 for (unsigned I = MVT::FIRST_FP_VALUETYPE;
249 I <= MVT::LAST_FP_VALUETYPE;
251 MVT VT = MVT::SimpleValueType(I);
252 if (isTypeLegal(VT)) {
253 // We can use FI for FRINT.
254 setOperationAction(ISD::FRINT, VT, Legal);
256 // We can use the extended form of FI for other rounding operations.
257 if (Subtarget.hasFPExtension()) {
258 setOperationAction(ISD::FNEARBYINT, VT, Legal);
259 setOperationAction(ISD::FFLOOR, VT, Legal);
260 setOperationAction(ISD::FCEIL, VT, Legal);
261 setOperationAction(ISD::FTRUNC, VT, Legal);
262 setOperationAction(ISD::FROUND, VT, Legal);
265 // No special instructions for these.
266 setOperationAction(ISD::FSIN, VT, Expand);
267 setOperationAction(ISD::FCOS, VT, Expand);
268 setOperationAction(ISD::FREM, VT, Expand);
272 // We have fused multiply-addition for f32 and f64 but not f128.
273 setOperationAction(ISD::FMA, MVT::f32, Legal);
274 setOperationAction(ISD::FMA, MVT::f64, Legal);
275 setOperationAction(ISD::FMA, MVT::f128, Expand);
277 // Needed so that we don't try to implement f128 constant loads using
278 // a load-and-extend of a f80 constant (in cases where the constant
279 // would fit in an f80).
280 for (MVT VT : MVT::fp_valuetypes())
281 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f80, Expand);
283 // Floating-point truncation and stores need to be done separately.
284 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
285 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
286 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
288 // We have 64-bit FPR<->GPR moves, but need special handling for
290 setOperationAction(ISD::BITCAST, MVT::i32, Custom);
291 setOperationAction(ISD::BITCAST, MVT::f32, Custom);
293 // VASTART and VACOPY need to deal with the SystemZ-specific varargs
294 // structure, but VAEND is a no-op.
295 setOperationAction(ISD::VASTART, MVT::Other, Custom);
296 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
297 setOperationAction(ISD::VAEND, MVT::Other, Expand);
299 // Codes for which we want to perform some z-specific combinations.
300 setTargetDAGCombine(ISD::SIGN_EXTEND);
302 // We want to use MVC in preference to even a single load/store pair.
303 MaxStoresPerMemcpy = 0;
304 MaxStoresPerMemcpyOptSize = 0;
306 // The main memset sequence is a byte store followed by an MVC.
307 // Two STC or MV..I stores win over that, but the kind of fused stores
308 // generated by target-independent code don't when the byte value is
309 // variable. E.g. "STC <reg>;MHI <reg>,257;STH <reg>" is not better
310 // than "STC;MVC". Handle the choice in target-specific code instead.
311 MaxStoresPerMemset = 0;
312 MaxStoresPerMemsetOptSize = 0;
315 EVT SystemZTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
318 return VT.changeVectorElementTypeToInteger();
321 bool SystemZTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
322 VT = VT.getScalarType();
327 switch (VT.getSimpleVT().SimpleTy) {
340 bool SystemZTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
341 // We can load zero using LZ?R and negative zero using LZ?R;LC?BR.
342 return Imm.isZero() || Imm.isNegZero();
345 bool SystemZTargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
349 // Unaligned accesses should never be slower than the expanded version.
350 // We check specifically for aligned accesses in the few cases where
351 // they are required.
357 bool SystemZTargetLowering::isLegalAddressingMode(const AddrMode &AM,
359 // Punt on globals for now, although they can be used in limited
360 // RELATIVE LONG cases.
364 // Require a 20-bit signed offset.
365 if (!isInt<20>(AM.BaseOffs))
368 // Indexing is OK but no scale factor can be applied.
369 return AM.Scale == 0 || AM.Scale == 1;
372 bool SystemZTargetLowering::isTruncateFree(Type *FromType, Type *ToType) const {
373 if (!FromType->isIntegerTy() || !ToType->isIntegerTy())
375 unsigned FromBits = FromType->getPrimitiveSizeInBits();
376 unsigned ToBits = ToType->getPrimitiveSizeInBits();
377 return FromBits > ToBits;
380 bool SystemZTargetLowering::isTruncateFree(EVT FromVT, EVT ToVT) const {
381 if (!FromVT.isInteger() || !ToVT.isInteger())
383 unsigned FromBits = FromVT.getSizeInBits();
384 unsigned ToBits = ToVT.getSizeInBits();
385 return FromBits > ToBits;
388 //===----------------------------------------------------------------------===//
389 // Inline asm support
390 //===----------------------------------------------------------------------===//
392 TargetLowering::ConstraintType
393 SystemZTargetLowering::getConstraintType(const std::string &Constraint) const {
394 if (Constraint.size() == 1) {
395 switch (Constraint[0]) {
396 case 'a': // Address register
397 case 'd': // Data register (equivalent to 'r')
398 case 'f': // Floating-point register
399 case 'h': // High-part register
400 case 'r': // General-purpose register
401 return C_RegisterClass;
403 case 'Q': // Memory with base and unsigned 12-bit displacement
404 case 'R': // Likewise, plus an index
405 case 'S': // Memory with base and signed 20-bit displacement
406 case 'T': // Likewise, plus an index
407 case 'm': // Equivalent to 'T'.
410 case 'I': // Unsigned 8-bit constant
411 case 'J': // Unsigned 12-bit constant
412 case 'K': // Signed 16-bit constant
413 case 'L': // Signed 20-bit displacement (on all targets we support)
414 case 'M': // 0x7fffffff
421 return TargetLowering::getConstraintType(Constraint);
424 TargetLowering::ConstraintWeight SystemZTargetLowering::
425 getSingleConstraintMatchWeight(AsmOperandInfo &info,
426 const char *constraint) const {
427 ConstraintWeight weight = CW_Invalid;
428 Value *CallOperandVal = info.CallOperandVal;
429 // If we don't have a value, we can't do a match,
430 // but allow it at the lowest weight.
433 Type *type = CallOperandVal->getType();
434 // Look at the constraint type.
435 switch (*constraint) {
437 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
440 case 'a': // Address register
441 case 'd': // Data register (equivalent to 'r')
442 case 'h': // High-part register
443 case 'r': // General-purpose register
444 if (CallOperandVal->getType()->isIntegerTy())
445 weight = CW_Register;
448 case 'f': // Floating-point register
449 if (type->isFloatingPointTy())
450 weight = CW_Register;
453 case 'I': // Unsigned 8-bit constant
454 if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
455 if (isUInt<8>(C->getZExtValue()))
456 weight = CW_Constant;
459 case 'J': // Unsigned 12-bit constant
460 if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
461 if (isUInt<12>(C->getZExtValue()))
462 weight = CW_Constant;
465 case 'K': // Signed 16-bit constant
466 if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
467 if (isInt<16>(C->getSExtValue()))
468 weight = CW_Constant;
471 case 'L': // Signed 20-bit displacement (on all targets we support)
472 if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
473 if (isInt<20>(C->getSExtValue()))
474 weight = CW_Constant;
477 case 'M': // 0x7fffffff
478 if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
479 if (C->getZExtValue() == 0x7fffffff)
480 weight = CW_Constant;
486 // Parse a "{tNNN}" register constraint for which the register type "t"
487 // has already been verified. MC is the class associated with "t" and
488 // Map maps 0-based register numbers to LLVM register numbers.
489 static std::pair<unsigned, const TargetRegisterClass *>
490 parseRegisterNumber(const std::string &Constraint,
491 const TargetRegisterClass *RC, const unsigned *Map) {
492 assert(*(Constraint.end()-1) == '}' && "Missing '}'");
493 if (isdigit(Constraint[2])) {
494 std::string Suffix(Constraint.data() + 2, Constraint.size() - 2);
495 unsigned Index = atoi(Suffix.c_str());
496 if (Index < 16 && Map[Index])
497 return std::make_pair(Map[Index], RC);
499 return std::make_pair(0U, nullptr);
502 std::pair<unsigned, const TargetRegisterClass *> SystemZTargetLowering::
503 getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const {
504 if (Constraint.size() == 1) {
505 // GCC Constraint Letters
506 switch (Constraint[0]) {
508 case 'd': // Data register (equivalent to 'r')
509 case 'r': // General-purpose register
511 return std::make_pair(0U, &SystemZ::GR64BitRegClass);
512 else if (VT == MVT::i128)
513 return std::make_pair(0U, &SystemZ::GR128BitRegClass);
514 return std::make_pair(0U, &SystemZ::GR32BitRegClass);
516 case 'a': // Address register
518 return std::make_pair(0U, &SystemZ::ADDR64BitRegClass);
519 else if (VT == MVT::i128)
520 return std::make_pair(0U, &SystemZ::ADDR128BitRegClass);
521 return std::make_pair(0U, &SystemZ::ADDR32BitRegClass);
523 case 'h': // High-part register (an LLVM extension)
524 return std::make_pair(0U, &SystemZ::GRH32BitRegClass);
526 case 'f': // Floating-point register
528 return std::make_pair(0U, &SystemZ::FP64BitRegClass);
529 else if (VT == MVT::f128)
530 return std::make_pair(0U, &SystemZ::FP128BitRegClass);
531 return std::make_pair(0U, &SystemZ::FP32BitRegClass);
534 if (Constraint[0] == '{') {
535 // We need to override the default register parsing for GPRs and FPRs
536 // because the interpretation depends on VT. The internal names of
537 // the registers are also different from the external names
538 // (F0D and F0S instead of F0, etc.).
539 if (Constraint[1] == 'r') {
541 return parseRegisterNumber(Constraint, &SystemZ::GR32BitRegClass,
542 SystemZMC::GR32Regs);
544 return parseRegisterNumber(Constraint, &SystemZ::GR128BitRegClass,
545 SystemZMC::GR128Regs);
546 return parseRegisterNumber(Constraint, &SystemZ::GR64BitRegClass,
547 SystemZMC::GR64Regs);
549 if (Constraint[1] == 'f') {
551 return parseRegisterNumber(Constraint, &SystemZ::FP32BitRegClass,
552 SystemZMC::FP32Regs);
554 return parseRegisterNumber(Constraint, &SystemZ::FP128BitRegClass,
555 SystemZMC::FP128Regs);
556 return parseRegisterNumber(Constraint, &SystemZ::FP64BitRegClass,
557 SystemZMC::FP64Regs);
560 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
563 void SystemZTargetLowering::
564 LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
565 std::vector<SDValue> &Ops,
566 SelectionDAG &DAG) const {
567 // Only support length 1 constraints for now.
568 if (Constraint.length() == 1) {
569 switch (Constraint[0]) {
570 case 'I': // Unsigned 8-bit constant
571 if (auto *C = dyn_cast<ConstantSDNode>(Op))
572 if (isUInt<8>(C->getZExtValue()))
573 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(),
577 case 'J': // Unsigned 12-bit constant
578 if (auto *C = dyn_cast<ConstantSDNode>(Op))
579 if (isUInt<12>(C->getZExtValue()))
580 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(),
584 case 'K': // Signed 16-bit constant
585 if (auto *C = dyn_cast<ConstantSDNode>(Op))
586 if (isInt<16>(C->getSExtValue()))
587 Ops.push_back(DAG.getTargetConstant(C->getSExtValue(),
591 case 'L': // Signed 20-bit displacement (on all targets we support)
592 if (auto *C = dyn_cast<ConstantSDNode>(Op))
593 if (isInt<20>(C->getSExtValue()))
594 Ops.push_back(DAG.getTargetConstant(C->getSExtValue(),
598 case 'M': // 0x7fffffff
599 if (auto *C = dyn_cast<ConstantSDNode>(Op))
600 if (C->getZExtValue() == 0x7fffffff)
601 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(),
606 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
609 //===----------------------------------------------------------------------===//
610 // Calling conventions
611 //===----------------------------------------------------------------------===//
613 #include "SystemZGenCallingConv.inc"
615 bool SystemZTargetLowering::allowTruncateForTailCall(Type *FromType,
616 Type *ToType) const {
617 return isTruncateFree(FromType, ToType);
620 bool SystemZTargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
621 if (!CI->isTailCall())
626 // Value is a value that has been passed to us in the location described by VA
627 // (and so has type VA.getLocVT()). Convert Value to VA.getValVT(), chaining
628 // any loads onto Chain.
629 static SDValue convertLocVTToValVT(SelectionDAG &DAG, SDLoc DL,
630 CCValAssign &VA, SDValue Chain,
632 // If the argument has been promoted from a smaller type, insert an
633 // assertion to capture this.
634 if (VA.getLocInfo() == CCValAssign::SExt)
635 Value = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Value,
636 DAG.getValueType(VA.getValVT()));
637 else if (VA.getLocInfo() == CCValAssign::ZExt)
638 Value = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Value,
639 DAG.getValueType(VA.getValVT()));
642 Value = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Value);
643 else if (VA.getLocInfo() == CCValAssign::Indirect)
644 Value = DAG.getLoad(VA.getValVT(), DL, Chain, Value,
645 MachinePointerInfo(), false, false, false, 0);
647 assert(VA.getLocInfo() == CCValAssign::Full && "Unsupported getLocInfo");
651 // Value is a value of type VA.getValVT() that we need to copy into
652 // the location described by VA. Return a copy of Value converted to
653 // VA.getValVT(). The caller is responsible for handling indirect values.
654 static SDValue convertValVTToLocVT(SelectionDAG &DAG, SDLoc DL,
655 CCValAssign &VA, SDValue Value) {
656 switch (VA.getLocInfo()) {
657 case CCValAssign::SExt:
658 return DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Value);
659 case CCValAssign::ZExt:
660 return DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Value);
661 case CCValAssign::AExt:
662 return DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Value);
663 case CCValAssign::Full:
666 llvm_unreachable("Unhandled getLocInfo()");
670 SDValue SystemZTargetLowering::
671 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
672 const SmallVectorImpl<ISD::InputArg> &Ins,
673 SDLoc DL, SelectionDAG &DAG,
674 SmallVectorImpl<SDValue> &InVals) const {
675 MachineFunction &MF = DAG.getMachineFunction();
676 MachineFrameInfo *MFI = MF.getFrameInfo();
677 MachineRegisterInfo &MRI = MF.getRegInfo();
678 SystemZMachineFunctionInfo *FuncInfo =
679 MF.getInfo<SystemZMachineFunctionInfo>();
681 static_cast<const SystemZFrameLowering *>(Subtarget.getFrameLowering());
683 // Assign locations to all of the incoming arguments.
684 SmallVector<CCValAssign, 16> ArgLocs;
685 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
686 CCInfo.AnalyzeFormalArguments(Ins, CC_SystemZ);
688 unsigned NumFixedGPRs = 0;
689 unsigned NumFixedFPRs = 0;
690 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
692 CCValAssign &VA = ArgLocs[I];
693 EVT LocVT = VA.getLocVT();
695 // Arguments passed in registers
696 const TargetRegisterClass *RC;
697 switch (LocVT.getSimpleVT().SimpleTy) {
699 // Integers smaller than i64 should be promoted to i64.
700 llvm_unreachable("Unexpected argument type");
703 RC = &SystemZ::GR32BitRegClass;
707 RC = &SystemZ::GR64BitRegClass;
711 RC = &SystemZ::FP32BitRegClass;
715 RC = &SystemZ::FP64BitRegClass;
719 unsigned VReg = MRI.createVirtualRegister(RC);
720 MRI.addLiveIn(VA.getLocReg(), VReg);
721 ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, LocVT);
723 assert(VA.isMemLoc() && "Argument not register or memory");
725 // Create the frame index object for this incoming parameter.
726 int FI = MFI->CreateFixedObject(LocVT.getSizeInBits() / 8,
727 VA.getLocMemOffset(), true);
729 // Create the SelectionDAG nodes corresponding to a load
730 // from this parameter. Unpromoted ints and floats are
731 // passed as right-justified 8-byte values.
732 EVT PtrVT = getPointerTy();
733 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
734 if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32)
735 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4));
736 ArgValue = DAG.getLoad(LocVT, DL, Chain, FIN,
737 MachinePointerInfo::getFixedStack(FI),
738 false, false, false, 0);
741 // Convert the value of the argument register into the value that's
743 InVals.push_back(convertLocVTToValVT(DAG, DL, VA, Chain, ArgValue));
747 // Save the number of non-varargs registers for later use by va_start, etc.
748 FuncInfo->setVarArgsFirstGPR(NumFixedGPRs);
749 FuncInfo->setVarArgsFirstFPR(NumFixedFPRs);
751 // Likewise the address (in the form of a frame index) of where the
752 // first stack vararg would be. The 1-byte size here is arbitrary.
753 int64_t StackSize = CCInfo.getNextStackOffset();
754 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize, true));
756 // ...and a similar frame index for the caller-allocated save area
757 // that will be used to store the incoming registers.
758 int64_t RegSaveOffset = TFL->getOffsetOfLocalArea();
759 unsigned RegSaveIndex = MFI->CreateFixedObject(1, RegSaveOffset, true);
760 FuncInfo->setRegSaveFrameIndex(RegSaveIndex);
762 // Store the FPR varargs in the reserved frame slots. (We store the
763 // GPRs as part of the prologue.)
764 if (NumFixedFPRs < SystemZ::NumArgFPRs) {
765 SDValue MemOps[SystemZ::NumArgFPRs];
766 for (unsigned I = NumFixedFPRs; I < SystemZ::NumArgFPRs; ++I) {
767 unsigned Offset = TFL->getRegSpillOffset(SystemZ::ArgFPRs[I]);
768 int FI = MFI->CreateFixedObject(8, RegSaveOffset + Offset, true);
769 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
770 unsigned VReg = MF.addLiveIn(SystemZ::ArgFPRs[I],
771 &SystemZ::FP64BitRegClass);
772 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f64);
773 MemOps[I] = DAG.getStore(ArgValue.getValue(1), DL, ArgValue, FIN,
774 MachinePointerInfo::getFixedStack(FI),
778 // Join the stores, which are independent of one another.
779 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
780 makeArrayRef(&MemOps[NumFixedFPRs],
781 SystemZ::NumArgFPRs-NumFixedFPRs));
788 static bool canUseSiblingCall(const CCState &ArgCCInfo,
789 SmallVectorImpl<CCValAssign> &ArgLocs) {
790 // Punt if there are any indirect or stack arguments, or if the call
791 // needs the call-saved argument register R6.
792 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
793 CCValAssign &VA = ArgLocs[I];
794 if (VA.getLocInfo() == CCValAssign::Indirect)
798 unsigned Reg = VA.getLocReg();
799 if (Reg == SystemZ::R6H || Reg == SystemZ::R6L || Reg == SystemZ::R6D)
806 SystemZTargetLowering::LowerCall(CallLoweringInfo &CLI,
807 SmallVectorImpl<SDValue> &InVals) const {
808 SelectionDAG &DAG = CLI.DAG;
810 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
811 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
812 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
813 SDValue Chain = CLI.Chain;
814 SDValue Callee = CLI.Callee;
815 bool &IsTailCall = CLI.IsTailCall;
816 CallingConv::ID CallConv = CLI.CallConv;
817 bool IsVarArg = CLI.IsVarArg;
818 MachineFunction &MF = DAG.getMachineFunction();
819 EVT PtrVT = getPointerTy();
821 // Analyze the operands of the call, assigning locations to each operand.
822 SmallVector<CCValAssign, 16> ArgLocs;
823 CCState ArgCCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
824 ArgCCInfo.AnalyzeCallOperands(Outs, CC_SystemZ);
826 // We don't support GuaranteedTailCallOpt, only automatically-detected
828 if (IsTailCall && !canUseSiblingCall(ArgCCInfo, ArgLocs))
831 // Get a count of how many bytes are to be pushed on the stack.
832 unsigned NumBytes = ArgCCInfo.getNextStackOffset();
834 // Mark the start of the call.
836 Chain = DAG.getCALLSEQ_START(Chain, DAG.getConstant(NumBytes, PtrVT, true),
839 // Copy argument values to their designated locations.
840 SmallVector<std::pair<unsigned, SDValue>, 9> RegsToPass;
841 SmallVector<SDValue, 8> MemOpChains;
843 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
844 CCValAssign &VA = ArgLocs[I];
845 SDValue ArgValue = OutVals[I];
847 if (VA.getLocInfo() == CCValAssign::Indirect) {
848 // Store the argument in a stack slot and pass its address.
849 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
850 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
851 MemOpChains.push_back(DAG.getStore(Chain, DL, ArgValue, SpillSlot,
852 MachinePointerInfo::getFixedStack(FI),
854 ArgValue = SpillSlot;
856 ArgValue = convertValVTToLocVT(DAG, DL, VA, ArgValue);
859 // Queue up the argument copies and emit them at the end.
860 RegsToPass.push_back(std::make_pair(VA.getLocReg(), ArgValue));
862 assert(VA.isMemLoc() && "Argument not register or memory");
864 // Work out the address of the stack slot. Unpromoted ints and
865 // floats are passed as right-justified 8-byte values.
866 if (!StackPtr.getNode())
867 StackPtr = DAG.getCopyFromReg(Chain, DL, SystemZ::R15D, PtrVT);
868 unsigned Offset = SystemZMC::CallFrameSize + VA.getLocMemOffset();
869 if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32)
871 SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr,
872 DAG.getIntPtrConstant(Offset));
875 MemOpChains.push_back(DAG.getStore(Chain, DL, ArgValue, Address,
876 MachinePointerInfo(),
881 // Join the stores, which are independent of one another.
882 if (!MemOpChains.empty())
883 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
885 // Accept direct calls by converting symbolic call addresses to the
886 // associated Target* opcodes. Force %r1 to be used for indirect
889 if (auto *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
890 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, PtrVT);
891 Callee = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Callee);
892 } else if (auto *E = dyn_cast<ExternalSymbolSDNode>(Callee)) {
893 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), PtrVT);
894 Callee = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Callee);
895 } else if (IsTailCall) {
896 Chain = DAG.getCopyToReg(Chain, DL, SystemZ::R1D, Callee, Glue);
897 Glue = Chain.getValue(1);
898 Callee = DAG.getRegister(SystemZ::R1D, Callee.getValueType());
901 // Build a sequence of copy-to-reg nodes, chained and glued together.
902 for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I) {
903 Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[I].first,
904 RegsToPass[I].second, Glue);
905 Glue = Chain.getValue(1);
908 // The first call operand is the chain and the second is the target address.
909 SmallVector<SDValue, 8> Ops;
910 Ops.push_back(Chain);
911 Ops.push_back(Callee);
913 // Add argument registers to the end of the list so that they are
914 // known live into the call.
915 for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I)
916 Ops.push_back(DAG.getRegister(RegsToPass[I].first,
917 RegsToPass[I].second.getValueType()));
919 // Add a register mask operand representing the call-preserved registers.
920 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
921 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
922 assert(Mask && "Missing call preserved mask for calling convention");
923 Ops.push_back(DAG.getRegisterMask(Mask));
925 // Glue the call to the argument copies, if any.
930 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
932 return DAG.getNode(SystemZISD::SIBCALL, DL, NodeTys, Ops);
933 Chain = DAG.getNode(SystemZISD::CALL, DL, NodeTys, Ops);
934 Glue = Chain.getValue(1);
936 // Mark the end of the call, which is glued to the call itself.
937 Chain = DAG.getCALLSEQ_END(Chain,
938 DAG.getConstant(NumBytes, PtrVT, true),
939 DAG.getConstant(0, PtrVT, true),
941 Glue = Chain.getValue(1);
943 // Assign locations to each value returned by this call.
944 SmallVector<CCValAssign, 16> RetLocs;
945 CCState RetCCInfo(CallConv, IsVarArg, MF, RetLocs, *DAG.getContext());
946 RetCCInfo.AnalyzeCallResult(Ins, RetCC_SystemZ);
948 // Copy all of the result registers out of their specified physreg.
949 for (unsigned I = 0, E = RetLocs.size(); I != E; ++I) {
950 CCValAssign &VA = RetLocs[I];
952 // Copy the value out, gluing the copy to the end of the call sequence.
953 SDValue RetValue = DAG.getCopyFromReg(Chain, DL, VA.getLocReg(),
954 VA.getLocVT(), Glue);
955 Chain = RetValue.getValue(1);
956 Glue = RetValue.getValue(2);
958 // Convert the value of the return register into the value that's
960 InVals.push_back(convertLocVTToValVT(DAG, DL, VA, Chain, RetValue));
967 SystemZTargetLowering::LowerReturn(SDValue Chain,
968 CallingConv::ID CallConv, bool IsVarArg,
969 const SmallVectorImpl<ISD::OutputArg> &Outs,
970 const SmallVectorImpl<SDValue> &OutVals,
971 SDLoc DL, SelectionDAG &DAG) const {
972 MachineFunction &MF = DAG.getMachineFunction();
974 // Assign locations to each returned value.
975 SmallVector<CCValAssign, 16> RetLocs;
976 CCState RetCCInfo(CallConv, IsVarArg, MF, RetLocs, *DAG.getContext());
977 RetCCInfo.AnalyzeReturn(Outs, RetCC_SystemZ);
979 // Quick exit for void returns
981 return DAG.getNode(SystemZISD::RET_FLAG, DL, MVT::Other, Chain);
983 // Copy the result values into the output registers.
985 SmallVector<SDValue, 4> RetOps;
986 RetOps.push_back(Chain);
987 for (unsigned I = 0, E = RetLocs.size(); I != E; ++I) {
988 CCValAssign &VA = RetLocs[I];
989 SDValue RetValue = OutVals[I];
991 // Make the return register live on exit.
992 assert(VA.isRegLoc() && "Can only return in registers!");
994 // Promote the value as required.
995 RetValue = convertValVTToLocVT(DAG, DL, VA, RetValue);
997 // Chain and glue the copies together.
998 unsigned Reg = VA.getLocReg();
999 Chain = DAG.getCopyToReg(Chain, DL, Reg, RetValue, Glue);
1000 Glue = Chain.getValue(1);
1001 RetOps.push_back(DAG.getRegister(Reg, VA.getLocVT()));
1004 // Update chain and glue.
1007 RetOps.push_back(Glue);
1009 return DAG.getNode(SystemZISD::RET_FLAG, DL, MVT::Other, RetOps);
1012 SDValue SystemZTargetLowering::
1013 prepareVolatileOrAtomicLoad(SDValue Chain, SDLoc DL, SelectionDAG &DAG) const {
1014 return DAG.getNode(SystemZISD::SERIALIZE, DL, MVT::Other, Chain);
1017 // CC is a comparison that will be implemented using an integer or
1018 // floating-point comparison. Return the condition code mask for
1019 // a branch on true. In the integer case, CCMASK_CMP_UO is set for
1020 // unsigned comparisons and clear for signed ones. In the floating-point
1021 // case, CCMASK_CMP_UO has its normal mask meaning (unordered).
1022 static unsigned CCMaskForCondCode(ISD::CondCode CC) {
1024 case ISD::SET##X: return SystemZ::CCMASK_CMP_##X; \
1025 case ISD::SETO##X: return SystemZ::CCMASK_CMP_##X; \
1026 case ISD::SETU##X: return SystemZ::CCMASK_CMP_UO | SystemZ::CCMASK_CMP_##X
1030 llvm_unreachable("Invalid integer condition!");
1039 case ISD::SETO: return SystemZ::CCMASK_CMP_O;
1040 case ISD::SETUO: return SystemZ::CCMASK_CMP_UO;
1045 // Return a sequence for getting a 1 from an IPM result when CC has a
1046 // value in CCMask and a 0 when CC has a value in CCValid & ~CCMask.
1047 // The handling of CC values outside CCValid doesn't matter.
1048 static IPMConversion getIPMConversion(unsigned CCValid, unsigned CCMask) {
1049 // Deal with cases where the result can be taken directly from a bit
1050 // of the IPM result.
1051 if (CCMask == (CCValid & (SystemZ::CCMASK_1 | SystemZ::CCMASK_3)))
1052 return IPMConversion(0, 0, SystemZ::IPM_CC);
1053 if (CCMask == (CCValid & (SystemZ::CCMASK_2 | SystemZ::CCMASK_3)))
1054 return IPMConversion(0, 0, SystemZ::IPM_CC + 1);
1056 // Deal with cases where we can add a value to force the sign bit
1057 // to contain the right value. Putting the bit in 31 means we can
1058 // use SRL rather than RISBG(L), and also makes it easier to get a
1059 // 0/-1 value, so it has priority over the other tests below.
1061 // These sequences rely on the fact that the upper two bits of the
1062 // IPM result are zero.
1063 uint64_t TopBit = uint64_t(1) << 31;
1064 if (CCMask == (CCValid & SystemZ::CCMASK_0))
1065 return IPMConversion(0, -(1 << SystemZ::IPM_CC), 31);
1066 if (CCMask == (CCValid & (SystemZ::CCMASK_0 | SystemZ::CCMASK_1)))
1067 return IPMConversion(0, -(2 << SystemZ::IPM_CC), 31);
1068 if (CCMask == (CCValid & (SystemZ::CCMASK_0
1070 | SystemZ::CCMASK_2)))
1071 return IPMConversion(0, -(3 << SystemZ::IPM_CC), 31);
1072 if (CCMask == (CCValid & SystemZ::CCMASK_3))
1073 return IPMConversion(0, TopBit - (3 << SystemZ::IPM_CC), 31);
1074 if (CCMask == (CCValid & (SystemZ::CCMASK_1
1076 | SystemZ::CCMASK_3)))
1077 return IPMConversion(0, TopBit - (1 << SystemZ::IPM_CC), 31);
1079 // Next try inverting the value and testing a bit. 0/1 could be
1080 // handled this way too, but we dealt with that case above.
1081 if (CCMask == (CCValid & (SystemZ::CCMASK_0 | SystemZ::CCMASK_2)))
1082 return IPMConversion(-1, 0, SystemZ::IPM_CC);
1084 // Handle cases where adding a value forces a non-sign bit to contain
1086 if (CCMask == (CCValid & (SystemZ::CCMASK_1 | SystemZ::CCMASK_2)))
1087 return IPMConversion(0, 1 << SystemZ::IPM_CC, SystemZ::IPM_CC + 1);
1088 if (CCMask == (CCValid & (SystemZ::CCMASK_0 | SystemZ::CCMASK_3)))
1089 return IPMConversion(0, -(1 << SystemZ::IPM_CC), SystemZ::IPM_CC + 1);
1091 // The remaining cases are 1, 2, 0/1/3 and 0/2/3. All these are
1092 // can be done by inverting the low CC bit and applying one of the
1093 // sign-based extractions above.
1094 if (CCMask == (CCValid & SystemZ::CCMASK_1))
1095 return IPMConversion(1 << SystemZ::IPM_CC, -(1 << SystemZ::IPM_CC), 31);
1096 if (CCMask == (CCValid & SystemZ::CCMASK_2))
1097 return IPMConversion(1 << SystemZ::IPM_CC,
1098 TopBit - (3 << SystemZ::IPM_CC), 31);
1099 if (CCMask == (CCValid & (SystemZ::CCMASK_0
1101 | SystemZ::CCMASK_3)))
1102 return IPMConversion(1 << SystemZ::IPM_CC, -(3 << SystemZ::IPM_CC), 31);
1103 if (CCMask == (CCValid & (SystemZ::CCMASK_0
1105 | SystemZ::CCMASK_3)))
1106 return IPMConversion(1 << SystemZ::IPM_CC,
1107 TopBit - (1 << SystemZ::IPM_CC), 31);
1109 llvm_unreachable("Unexpected CC combination");
1112 // If C can be converted to a comparison against zero, adjust the operands
1114 static void adjustZeroCmp(SelectionDAG &DAG, Comparison &C) {
1115 if (C.ICmpType == SystemZICMP::UnsignedOnly)
1118 auto *ConstOp1 = dyn_cast<ConstantSDNode>(C.Op1.getNode());
1122 int64_t Value = ConstOp1->getSExtValue();
1123 if ((Value == -1 && C.CCMask == SystemZ::CCMASK_CMP_GT) ||
1124 (Value == -1 && C.CCMask == SystemZ::CCMASK_CMP_LE) ||
1125 (Value == 1 && C.CCMask == SystemZ::CCMASK_CMP_LT) ||
1126 (Value == 1 && C.CCMask == SystemZ::CCMASK_CMP_GE)) {
1127 C.CCMask ^= SystemZ::CCMASK_CMP_EQ;
1128 C.Op1 = DAG.getConstant(0, C.Op1.getValueType());
1132 // If a comparison described by C is suitable for CLI(Y), CHHSI or CLHHSI,
1133 // adjust the operands as necessary.
1134 static void adjustSubwordCmp(SelectionDAG &DAG, Comparison &C) {
1135 // For us to make any changes, it must a comparison between a single-use
1136 // load and a constant.
1137 if (!C.Op0.hasOneUse() ||
1138 C.Op0.getOpcode() != ISD::LOAD ||
1139 C.Op1.getOpcode() != ISD::Constant)
1142 // We must have an 8- or 16-bit load.
1143 auto *Load = cast<LoadSDNode>(C.Op0);
1144 unsigned NumBits = Load->getMemoryVT().getStoreSizeInBits();
1145 if (NumBits != 8 && NumBits != 16)
1148 // The load must be an extending one and the constant must be within the
1149 // range of the unextended value.
1150 auto *ConstOp1 = cast<ConstantSDNode>(C.Op1);
1151 uint64_t Value = ConstOp1->getZExtValue();
1152 uint64_t Mask = (1 << NumBits) - 1;
1153 if (Load->getExtensionType() == ISD::SEXTLOAD) {
1154 // Make sure that ConstOp1 is in range of C.Op0.
1155 int64_t SignedValue = ConstOp1->getSExtValue();
1156 if (uint64_t(SignedValue) + (uint64_t(1) << (NumBits - 1)) > Mask)
1158 if (C.ICmpType != SystemZICMP::SignedOnly) {
1159 // Unsigned comparison between two sign-extended values is equivalent
1160 // to unsigned comparison between two zero-extended values.
1162 } else if (NumBits == 8) {
1163 // Try to treat the comparison as unsigned, so that we can use CLI.
1164 // Adjust CCMask and Value as necessary.
1165 if (Value == 0 && C.CCMask == SystemZ::CCMASK_CMP_LT)
1166 // Test whether the high bit of the byte is set.
1167 Value = 127, C.CCMask = SystemZ::CCMASK_CMP_GT;
1168 else if (Value == 0 && C.CCMask == SystemZ::CCMASK_CMP_GE)
1169 // Test whether the high bit of the byte is clear.
1170 Value = 128, C.CCMask = SystemZ::CCMASK_CMP_LT;
1172 // No instruction exists for this combination.
1174 C.ICmpType = SystemZICMP::UnsignedOnly;
1176 } else if (Load->getExtensionType() == ISD::ZEXTLOAD) {
1179 assert(C.ICmpType == SystemZICMP::Any &&
1180 "Signedness shouldn't matter here.");
1184 // Make sure that the first operand is an i32 of the right extension type.
1185 ISD::LoadExtType ExtType = (C.ICmpType == SystemZICMP::SignedOnly ?
1188 if (C.Op0.getValueType() != MVT::i32 ||
1189 Load->getExtensionType() != ExtType)
1190 C.Op0 = DAG.getExtLoad(ExtType, SDLoc(Load), MVT::i32,
1191 Load->getChain(), Load->getBasePtr(),
1192 Load->getPointerInfo(), Load->getMemoryVT(),
1193 Load->isVolatile(), Load->isNonTemporal(),
1194 Load->isInvariant(), Load->getAlignment());
1196 // Make sure that the second operand is an i32 with the right value.
1197 if (C.Op1.getValueType() != MVT::i32 ||
1198 Value != ConstOp1->getZExtValue())
1199 C.Op1 = DAG.getConstant(Value, MVT::i32);
1202 // Return true if Op is either an unextended load, or a load suitable
1203 // for integer register-memory comparisons of type ICmpType.
1204 static bool isNaturalMemoryOperand(SDValue Op, unsigned ICmpType) {
1205 auto *Load = dyn_cast<LoadSDNode>(Op.getNode());
1207 // There are no instructions to compare a register with a memory byte.
1208 if (Load->getMemoryVT() == MVT::i8)
1210 // Otherwise decide on extension type.
1211 switch (Load->getExtensionType()) {
1212 case ISD::NON_EXTLOAD:
1215 return ICmpType != SystemZICMP::UnsignedOnly;
1217 return ICmpType != SystemZICMP::SignedOnly;
1225 // Return true if it is better to swap the operands of C.
1226 static bool shouldSwapCmpOperands(const Comparison &C) {
1227 // Leave f128 comparisons alone, since they have no memory forms.
1228 if (C.Op0.getValueType() == MVT::f128)
1231 // Always keep a floating-point constant second, since comparisons with
1232 // zero can use LOAD TEST and comparisons with other constants make a
1233 // natural memory operand.
1234 if (isa<ConstantFPSDNode>(C.Op1))
1237 // Never swap comparisons with zero since there are many ways to optimize
1239 auto *ConstOp1 = dyn_cast<ConstantSDNode>(C.Op1);
1240 if (ConstOp1 && ConstOp1->getZExtValue() == 0)
1243 // Also keep natural memory operands second if the loaded value is
1244 // only used here. Several comparisons have memory forms.
1245 if (isNaturalMemoryOperand(C.Op1, C.ICmpType) && C.Op1.hasOneUse())
1248 // Look for cases where Cmp0 is a single-use load and Cmp1 isn't.
1249 // In that case we generally prefer the memory to be second.
1250 if (isNaturalMemoryOperand(C.Op0, C.ICmpType) && C.Op0.hasOneUse()) {
1251 // The only exceptions are when the second operand is a constant and
1252 // we can use things like CHHSI.
1255 // The unsigned memory-immediate instructions can handle 16-bit
1256 // unsigned integers.
1257 if (C.ICmpType != SystemZICMP::SignedOnly &&
1258 isUInt<16>(ConstOp1->getZExtValue()))
1260 // The signed memory-immediate instructions can handle 16-bit
1262 if (C.ICmpType != SystemZICMP::UnsignedOnly &&
1263 isInt<16>(ConstOp1->getSExtValue()))
1268 // Try to promote the use of CGFR and CLGFR.
1269 unsigned Opcode0 = C.Op0.getOpcode();
1270 if (C.ICmpType != SystemZICMP::UnsignedOnly && Opcode0 == ISD::SIGN_EXTEND)
1272 if (C.ICmpType != SystemZICMP::SignedOnly && Opcode0 == ISD::ZERO_EXTEND)
1274 if (C.ICmpType != SystemZICMP::SignedOnly &&
1275 Opcode0 == ISD::AND &&
1276 C.Op0.getOperand(1).getOpcode() == ISD::Constant &&
1277 cast<ConstantSDNode>(C.Op0.getOperand(1))->getZExtValue() == 0xffffffff)
1283 // Return a version of comparison CC mask CCMask in which the LT and GT
1284 // actions are swapped.
1285 static unsigned reverseCCMask(unsigned CCMask) {
1286 return ((CCMask & SystemZ::CCMASK_CMP_EQ) |
1287 (CCMask & SystemZ::CCMASK_CMP_GT ? SystemZ::CCMASK_CMP_LT : 0) |
1288 (CCMask & SystemZ::CCMASK_CMP_LT ? SystemZ::CCMASK_CMP_GT : 0) |
1289 (CCMask & SystemZ::CCMASK_CMP_UO));
1292 // Check whether C tests for equality between X and Y and whether X - Y
1293 // or Y - X is also computed. In that case it's better to compare the
1294 // result of the subtraction against zero.
1295 static void adjustForSubtraction(SelectionDAG &DAG, Comparison &C) {
1296 if (C.CCMask == SystemZ::CCMASK_CMP_EQ ||
1297 C.CCMask == SystemZ::CCMASK_CMP_NE) {
1298 for (auto I = C.Op0->use_begin(), E = C.Op0->use_end(); I != E; ++I) {
1300 if (N->getOpcode() == ISD::SUB &&
1301 ((N->getOperand(0) == C.Op0 && N->getOperand(1) == C.Op1) ||
1302 (N->getOperand(0) == C.Op1 && N->getOperand(1) == C.Op0))) {
1303 C.Op0 = SDValue(N, 0);
1304 C.Op1 = DAG.getConstant(0, N->getValueType(0));
1311 // Check whether C compares a floating-point value with zero and if that
1312 // floating-point value is also negated. In this case we can use the
1313 // negation to set CC, so avoiding separate LOAD AND TEST and
1314 // LOAD (NEGATIVE/COMPLEMENT) instructions.
1315 static void adjustForFNeg(Comparison &C) {
1316 auto *C1 = dyn_cast<ConstantFPSDNode>(C.Op1);
1317 if (C1 && C1->isZero()) {
1318 for (auto I = C.Op0->use_begin(), E = C.Op0->use_end(); I != E; ++I) {
1320 if (N->getOpcode() == ISD::FNEG) {
1321 C.Op0 = SDValue(N, 0);
1322 C.CCMask = reverseCCMask(C.CCMask);
1329 // Check whether C compares (shl X, 32) with 0 and whether X is
1330 // also sign-extended. In that case it is better to test the result
1331 // of the sign extension using LTGFR.
1333 // This case is important because InstCombine transforms a comparison
1334 // with (sext (trunc X)) into a comparison with (shl X, 32).
1335 static void adjustForLTGFR(Comparison &C) {
1336 // Check for a comparison between (shl X, 32) and 0.
1337 if (C.Op0.getOpcode() == ISD::SHL &&
1338 C.Op0.getValueType() == MVT::i64 &&
1339 C.Op1.getOpcode() == ISD::Constant &&
1340 cast<ConstantSDNode>(C.Op1)->getZExtValue() == 0) {
1341 auto *C1 = dyn_cast<ConstantSDNode>(C.Op0.getOperand(1));
1342 if (C1 && C1->getZExtValue() == 32) {
1343 SDValue ShlOp0 = C.Op0.getOperand(0);
1344 // See whether X has any SIGN_EXTEND_INREG uses.
1345 for (auto I = ShlOp0->use_begin(), E = ShlOp0->use_end(); I != E; ++I) {
1347 if (N->getOpcode() == ISD::SIGN_EXTEND_INREG &&
1348 cast<VTSDNode>(N->getOperand(1))->getVT() == MVT::i32) {
1349 C.Op0 = SDValue(N, 0);
1357 // If C compares the truncation of an extending load, try to compare
1358 // the untruncated value instead. This exposes more opportunities to
1360 static void adjustICmpTruncate(SelectionDAG &DAG, Comparison &C) {
1361 if (C.Op0.getOpcode() == ISD::TRUNCATE &&
1362 C.Op0.getOperand(0).getOpcode() == ISD::LOAD &&
1363 C.Op1.getOpcode() == ISD::Constant &&
1364 cast<ConstantSDNode>(C.Op1)->getZExtValue() == 0) {
1365 auto *L = cast<LoadSDNode>(C.Op0.getOperand(0));
1366 if (L->getMemoryVT().getStoreSizeInBits()
1367 <= C.Op0.getValueType().getSizeInBits()) {
1368 unsigned Type = L->getExtensionType();
1369 if ((Type == ISD::ZEXTLOAD && C.ICmpType != SystemZICMP::SignedOnly) ||
1370 (Type == ISD::SEXTLOAD && C.ICmpType != SystemZICMP::UnsignedOnly)) {
1371 C.Op0 = C.Op0.getOperand(0);
1372 C.Op1 = DAG.getConstant(0, C.Op0.getValueType());
1378 // Return true if shift operation N has an in-range constant shift value.
1379 // Store it in ShiftVal if so.
1380 static bool isSimpleShift(SDValue N, unsigned &ShiftVal) {
1381 auto *Shift = dyn_cast<ConstantSDNode>(N.getOperand(1));
1385 uint64_t Amount = Shift->getZExtValue();
1386 if (Amount >= N.getValueType().getSizeInBits())
1393 // Check whether an AND with Mask is suitable for a TEST UNDER MASK
1394 // instruction and whether the CC value is descriptive enough to handle
1395 // a comparison of type Opcode between the AND result and CmpVal.
1396 // CCMask says which comparison result is being tested and BitSize is
1397 // the number of bits in the operands. If TEST UNDER MASK can be used,
1398 // return the corresponding CC mask, otherwise return 0.
1399 static unsigned getTestUnderMaskCond(unsigned BitSize, unsigned CCMask,
1400 uint64_t Mask, uint64_t CmpVal,
1401 unsigned ICmpType) {
1402 assert(Mask != 0 && "ANDs with zero should have been removed by now");
1404 // Check whether the mask is suitable for TMHH, TMHL, TMLH or TMLL.
1405 if (!SystemZ::isImmLL(Mask) && !SystemZ::isImmLH(Mask) &&
1406 !SystemZ::isImmHL(Mask) && !SystemZ::isImmHH(Mask))
1409 // Work out the masks for the lowest and highest bits.
1410 unsigned HighShift = 63 - countLeadingZeros(Mask);
1411 uint64_t High = uint64_t(1) << HighShift;
1412 uint64_t Low = uint64_t(1) << countTrailingZeros(Mask);
1414 // Signed ordered comparisons are effectively unsigned if the sign
1416 bool EffectivelyUnsigned = (ICmpType != SystemZICMP::SignedOnly);
1418 // Check for equality comparisons with 0, or the equivalent.
1420 if (CCMask == SystemZ::CCMASK_CMP_EQ)
1421 return SystemZ::CCMASK_TM_ALL_0;
1422 if (CCMask == SystemZ::CCMASK_CMP_NE)
1423 return SystemZ::CCMASK_TM_SOME_1;
1425 if (EffectivelyUnsigned && CmpVal <= Low) {
1426 if (CCMask == SystemZ::CCMASK_CMP_LT)
1427 return SystemZ::CCMASK_TM_ALL_0;
1428 if (CCMask == SystemZ::CCMASK_CMP_GE)
1429 return SystemZ::CCMASK_TM_SOME_1;
1431 if (EffectivelyUnsigned && CmpVal < Low) {
1432 if (CCMask == SystemZ::CCMASK_CMP_LE)
1433 return SystemZ::CCMASK_TM_ALL_0;
1434 if (CCMask == SystemZ::CCMASK_CMP_GT)
1435 return SystemZ::CCMASK_TM_SOME_1;
1438 // Check for equality comparisons with the mask, or the equivalent.
1439 if (CmpVal == Mask) {
1440 if (CCMask == SystemZ::CCMASK_CMP_EQ)
1441 return SystemZ::CCMASK_TM_ALL_1;
1442 if (CCMask == SystemZ::CCMASK_CMP_NE)
1443 return SystemZ::CCMASK_TM_SOME_0;
1445 if (EffectivelyUnsigned && CmpVal >= Mask - Low && CmpVal < Mask) {
1446 if (CCMask == SystemZ::CCMASK_CMP_GT)
1447 return SystemZ::CCMASK_TM_ALL_1;
1448 if (CCMask == SystemZ::CCMASK_CMP_LE)
1449 return SystemZ::CCMASK_TM_SOME_0;
1451 if (EffectivelyUnsigned && CmpVal > Mask - Low && CmpVal <= Mask) {
1452 if (CCMask == SystemZ::CCMASK_CMP_GE)
1453 return SystemZ::CCMASK_TM_ALL_1;
1454 if (CCMask == SystemZ::CCMASK_CMP_LT)
1455 return SystemZ::CCMASK_TM_SOME_0;
1458 // Check for ordered comparisons with the top bit.
1459 if (EffectivelyUnsigned && CmpVal >= Mask - High && CmpVal < High) {
1460 if (CCMask == SystemZ::CCMASK_CMP_LE)
1461 return SystemZ::CCMASK_TM_MSB_0;
1462 if (CCMask == SystemZ::CCMASK_CMP_GT)
1463 return SystemZ::CCMASK_TM_MSB_1;
1465 if (EffectivelyUnsigned && CmpVal > Mask - High && CmpVal <= High) {
1466 if (CCMask == SystemZ::CCMASK_CMP_LT)
1467 return SystemZ::CCMASK_TM_MSB_0;
1468 if (CCMask == SystemZ::CCMASK_CMP_GE)
1469 return SystemZ::CCMASK_TM_MSB_1;
1472 // If there are just two bits, we can do equality checks for Low and High
1474 if (Mask == Low + High) {
1475 if (CCMask == SystemZ::CCMASK_CMP_EQ && CmpVal == Low)
1476 return SystemZ::CCMASK_TM_MIXED_MSB_0;
1477 if (CCMask == SystemZ::CCMASK_CMP_NE && CmpVal == Low)
1478 return SystemZ::CCMASK_TM_MIXED_MSB_0 ^ SystemZ::CCMASK_ANY;
1479 if (CCMask == SystemZ::CCMASK_CMP_EQ && CmpVal == High)
1480 return SystemZ::CCMASK_TM_MIXED_MSB_1;
1481 if (CCMask == SystemZ::CCMASK_CMP_NE && CmpVal == High)
1482 return SystemZ::CCMASK_TM_MIXED_MSB_1 ^ SystemZ::CCMASK_ANY;
1485 // Looks like we've exhausted our options.
1489 // See whether C can be implemented as a TEST UNDER MASK instruction.
1490 // Update the arguments with the TM version if so.
1491 static void adjustForTestUnderMask(SelectionDAG &DAG, Comparison &C) {
1492 // Check that we have a comparison with a constant.
1493 auto *ConstOp1 = dyn_cast<ConstantSDNode>(C.Op1);
1496 uint64_t CmpVal = ConstOp1->getZExtValue();
1498 // Check whether the nonconstant input is an AND with a constant mask.
1501 ConstantSDNode *Mask = nullptr;
1502 if (C.Op0.getOpcode() == ISD::AND) {
1503 NewC.Op0 = C.Op0.getOperand(0);
1504 NewC.Op1 = C.Op0.getOperand(1);
1505 Mask = dyn_cast<ConstantSDNode>(NewC.Op1);
1508 MaskVal = Mask->getZExtValue();
1510 // There is no instruction to compare with a 64-bit immediate
1511 // so use TMHH instead if possible. We need an unsigned ordered
1512 // comparison with an i64 immediate.
1513 if (NewC.Op0.getValueType() != MVT::i64 ||
1514 NewC.CCMask == SystemZ::CCMASK_CMP_EQ ||
1515 NewC.CCMask == SystemZ::CCMASK_CMP_NE ||
1516 NewC.ICmpType == SystemZICMP::SignedOnly)
1518 // Convert LE and GT comparisons into LT and GE.
1519 if (NewC.CCMask == SystemZ::CCMASK_CMP_LE ||
1520 NewC.CCMask == SystemZ::CCMASK_CMP_GT) {
1521 if (CmpVal == uint64_t(-1))
1524 NewC.CCMask ^= SystemZ::CCMASK_CMP_EQ;
1526 // If the low N bits of Op1 are zero than the low N bits of Op0 can
1527 // be masked off without changing the result.
1528 MaskVal = -(CmpVal & -CmpVal);
1529 NewC.ICmpType = SystemZICMP::UnsignedOnly;
1532 // Check whether the combination of mask, comparison value and comparison
1533 // type are suitable.
1534 unsigned BitSize = NewC.Op0.getValueType().getSizeInBits();
1535 unsigned NewCCMask, ShiftVal;
1536 if (NewC.ICmpType != SystemZICMP::SignedOnly &&
1537 NewC.Op0.getOpcode() == ISD::SHL &&
1538 isSimpleShift(NewC.Op0, ShiftVal) &&
1539 (NewCCMask = getTestUnderMaskCond(BitSize, NewC.CCMask,
1540 MaskVal >> ShiftVal,
1542 SystemZICMP::Any))) {
1543 NewC.Op0 = NewC.Op0.getOperand(0);
1544 MaskVal >>= ShiftVal;
1545 } else if (NewC.ICmpType != SystemZICMP::SignedOnly &&
1546 NewC.Op0.getOpcode() == ISD::SRL &&
1547 isSimpleShift(NewC.Op0, ShiftVal) &&
1548 (NewCCMask = getTestUnderMaskCond(BitSize, NewC.CCMask,
1549 MaskVal << ShiftVal,
1551 SystemZICMP::UnsignedOnly))) {
1552 NewC.Op0 = NewC.Op0.getOperand(0);
1553 MaskVal <<= ShiftVal;
1555 NewCCMask = getTestUnderMaskCond(BitSize, NewC.CCMask, MaskVal, CmpVal,
1561 // Go ahead and make the change.
1562 C.Opcode = SystemZISD::TM;
1564 if (Mask && Mask->getZExtValue() == MaskVal)
1565 C.Op1 = SDValue(Mask, 0);
1567 C.Op1 = DAG.getConstant(MaskVal, C.Op0.getValueType());
1568 C.CCValid = SystemZ::CCMASK_TM;
1569 C.CCMask = NewCCMask;
1572 // Decide how to implement a comparison of type Cond between CmpOp0 with CmpOp1.
1573 static Comparison getCmp(SelectionDAG &DAG, SDValue CmpOp0, SDValue CmpOp1,
1574 ISD::CondCode Cond) {
1575 Comparison C(CmpOp0, CmpOp1);
1576 C.CCMask = CCMaskForCondCode(Cond);
1577 if (C.Op0.getValueType().isFloatingPoint()) {
1578 C.CCValid = SystemZ::CCMASK_FCMP;
1579 C.Opcode = SystemZISD::FCMP;
1582 C.CCValid = SystemZ::CCMASK_ICMP;
1583 C.Opcode = SystemZISD::ICMP;
1584 // Choose the type of comparison. Equality and inequality tests can
1585 // use either signed or unsigned comparisons. The choice also doesn't
1586 // matter if both sign bits are known to be clear. In those cases we
1587 // want to give the main isel code the freedom to choose whichever
1589 if (C.CCMask == SystemZ::CCMASK_CMP_EQ ||
1590 C.CCMask == SystemZ::CCMASK_CMP_NE ||
1591 (DAG.SignBitIsZero(C.Op0) && DAG.SignBitIsZero(C.Op1)))
1592 C.ICmpType = SystemZICMP::Any;
1593 else if (C.CCMask & SystemZ::CCMASK_CMP_UO)
1594 C.ICmpType = SystemZICMP::UnsignedOnly;
1596 C.ICmpType = SystemZICMP::SignedOnly;
1597 C.CCMask &= ~SystemZ::CCMASK_CMP_UO;
1598 adjustZeroCmp(DAG, C);
1599 adjustSubwordCmp(DAG, C);
1600 adjustForSubtraction(DAG, C);
1602 adjustICmpTruncate(DAG, C);
1605 if (shouldSwapCmpOperands(C)) {
1606 std::swap(C.Op0, C.Op1);
1607 C.CCMask = reverseCCMask(C.CCMask);
1610 adjustForTestUnderMask(DAG, C);
1614 // Emit the comparison instruction described by C.
1615 static SDValue emitCmp(SelectionDAG &DAG, SDLoc DL, Comparison &C) {
1616 if (C.Opcode == SystemZISD::ICMP)
1617 return DAG.getNode(SystemZISD::ICMP, DL, MVT::Glue, C.Op0, C.Op1,
1618 DAG.getConstant(C.ICmpType, MVT::i32));
1619 if (C.Opcode == SystemZISD::TM) {
1620 bool RegisterOnly = (bool(C.CCMask & SystemZ::CCMASK_TM_MIXED_MSB_0) !=
1621 bool(C.CCMask & SystemZ::CCMASK_TM_MIXED_MSB_1));
1622 return DAG.getNode(SystemZISD::TM, DL, MVT::Glue, C.Op0, C.Op1,
1623 DAG.getConstant(RegisterOnly, MVT::i32));
1625 return DAG.getNode(C.Opcode, DL, MVT::Glue, C.Op0, C.Op1);
1628 // Implement a 32-bit *MUL_LOHI operation by extending both operands to
1629 // 64 bits. Extend is the extension type to use. Store the high part
1630 // in Hi and the low part in Lo.
1631 static void lowerMUL_LOHI32(SelectionDAG &DAG, SDLoc DL,
1632 unsigned Extend, SDValue Op0, SDValue Op1,
1633 SDValue &Hi, SDValue &Lo) {
1634 Op0 = DAG.getNode(Extend, DL, MVT::i64, Op0);
1635 Op1 = DAG.getNode(Extend, DL, MVT::i64, Op1);
1636 SDValue Mul = DAG.getNode(ISD::MUL, DL, MVT::i64, Op0, Op1);
1637 Hi = DAG.getNode(ISD::SRL, DL, MVT::i64, Mul, DAG.getConstant(32, MVT::i64));
1638 Hi = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Hi);
1639 Lo = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mul);
1642 // Lower a binary operation that produces two VT results, one in each
1643 // half of a GR128 pair. Op0 and Op1 are the VT operands to the operation,
1644 // Extend extends Op0 to a GR128, and Opcode performs the GR128 operation
1645 // on the extended Op0 and (unextended) Op1. Store the even register result
1646 // in Even and the odd register result in Odd.
1647 static void lowerGR128Binary(SelectionDAG &DAG, SDLoc DL, EVT VT,
1648 unsigned Extend, unsigned Opcode,
1649 SDValue Op0, SDValue Op1,
1650 SDValue &Even, SDValue &Odd) {
1651 SDNode *In128 = DAG.getMachineNode(Extend, DL, MVT::Untyped, Op0);
1652 SDValue Result = DAG.getNode(Opcode, DL, MVT::Untyped,
1653 SDValue(In128, 0), Op1);
1654 bool Is32Bit = is32Bit(VT);
1655 Even = DAG.getTargetExtractSubreg(SystemZ::even128(Is32Bit), DL, VT, Result);
1656 Odd = DAG.getTargetExtractSubreg(SystemZ::odd128(Is32Bit), DL, VT, Result);
1659 // Return an i32 value that is 1 if the CC value produced by Glue is
1660 // in the mask CCMask and 0 otherwise. CC is known to have a value
1661 // in CCValid, so other values can be ignored.
1662 static SDValue emitSETCC(SelectionDAG &DAG, SDLoc DL, SDValue Glue,
1663 unsigned CCValid, unsigned CCMask) {
1664 IPMConversion Conversion = getIPMConversion(CCValid, CCMask);
1665 SDValue Result = DAG.getNode(SystemZISD::IPM, DL, MVT::i32, Glue);
1667 if (Conversion.XORValue)
1668 Result = DAG.getNode(ISD::XOR, DL, MVT::i32, Result,
1669 DAG.getConstant(Conversion.XORValue, MVT::i32));
1671 if (Conversion.AddValue)
1672 Result = DAG.getNode(ISD::ADD, DL, MVT::i32, Result,
1673 DAG.getConstant(Conversion.AddValue, MVT::i32));
1675 // The SHR/AND sequence should get optimized to an RISBG.
1676 Result = DAG.getNode(ISD::SRL, DL, MVT::i32, Result,
1677 DAG.getConstant(Conversion.Bit, MVT::i32));
1678 if (Conversion.Bit != 31)
1679 Result = DAG.getNode(ISD::AND, DL, MVT::i32, Result,
1680 DAG.getConstant(1, MVT::i32));
1684 SDValue SystemZTargetLowering::lowerSETCC(SDValue Op,
1685 SelectionDAG &DAG) const {
1686 SDValue CmpOp0 = Op.getOperand(0);
1687 SDValue CmpOp1 = Op.getOperand(1);
1688 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1691 Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC));
1692 SDValue Glue = emitCmp(DAG, DL, C);
1693 return emitSETCC(DAG, DL, Glue, C.CCValid, C.CCMask);
1696 SDValue SystemZTargetLowering::lowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
1697 SDValue Chain = Op.getOperand(0);
1698 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
1699 SDValue CmpOp0 = Op.getOperand(2);
1700 SDValue CmpOp1 = Op.getOperand(3);
1701 SDValue Dest = Op.getOperand(4);
1704 Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC));
1705 SDValue Glue = emitCmp(DAG, DL, C);
1706 return DAG.getNode(SystemZISD::BR_CCMASK, DL, Op.getValueType(),
1707 Chain, DAG.getConstant(C.CCValid, MVT::i32),
1708 DAG.getConstant(C.CCMask, MVT::i32), Dest, Glue);
1711 // Return true if Pos is CmpOp and Neg is the negative of CmpOp,
1712 // allowing Pos and Neg to be wider than CmpOp.
1713 static bool isAbsolute(SDValue CmpOp, SDValue Pos, SDValue Neg) {
1714 return (Neg.getOpcode() == ISD::SUB &&
1715 Neg.getOperand(0).getOpcode() == ISD::Constant &&
1716 cast<ConstantSDNode>(Neg.getOperand(0))->getZExtValue() == 0 &&
1717 Neg.getOperand(1) == Pos &&
1719 (Pos.getOpcode() == ISD::SIGN_EXTEND &&
1720 Pos.getOperand(0) == CmpOp)));
1723 // Return the absolute or negative absolute of Op; IsNegative decides which.
1724 static SDValue getAbsolute(SelectionDAG &DAG, SDLoc DL, SDValue Op,
1726 Op = DAG.getNode(SystemZISD::IABS, DL, Op.getValueType(), Op);
1728 Op = DAG.getNode(ISD::SUB, DL, Op.getValueType(),
1729 DAG.getConstant(0, Op.getValueType()), Op);
1733 SDValue SystemZTargetLowering::lowerSELECT_CC(SDValue Op,
1734 SelectionDAG &DAG) const {
1735 SDValue CmpOp0 = Op.getOperand(0);
1736 SDValue CmpOp1 = Op.getOperand(1);
1737 SDValue TrueOp = Op.getOperand(2);
1738 SDValue FalseOp = Op.getOperand(3);
1739 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1742 Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC));
1744 // Check for absolute and negative-absolute selections, including those
1745 // where the comparison value is sign-extended (for LPGFR and LNGFR).
1746 // This check supplements the one in DAGCombiner.
1747 if (C.Opcode == SystemZISD::ICMP &&
1748 C.CCMask != SystemZ::CCMASK_CMP_EQ &&
1749 C.CCMask != SystemZ::CCMASK_CMP_NE &&
1750 C.Op1.getOpcode() == ISD::Constant &&
1751 cast<ConstantSDNode>(C.Op1)->getZExtValue() == 0) {
1752 if (isAbsolute(C.Op0, TrueOp, FalseOp))
1753 return getAbsolute(DAG, DL, TrueOp, C.CCMask & SystemZ::CCMASK_CMP_LT);
1754 if (isAbsolute(C.Op0, FalseOp, TrueOp))
1755 return getAbsolute(DAG, DL, FalseOp, C.CCMask & SystemZ::CCMASK_CMP_GT);
1758 SDValue Glue = emitCmp(DAG, DL, C);
1760 // Special case for handling -1/0 results. The shifts we use here
1761 // should get optimized with the IPM conversion sequence.
1762 auto *TrueC = dyn_cast<ConstantSDNode>(TrueOp);
1763 auto *FalseC = dyn_cast<ConstantSDNode>(FalseOp);
1764 if (TrueC && FalseC) {
1765 int64_t TrueVal = TrueC->getSExtValue();
1766 int64_t FalseVal = FalseC->getSExtValue();
1767 if ((TrueVal == -1 && FalseVal == 0) || (TrueVal == 0 && FalseVal == -1)) {
1768 // Invert the condition if we want -1 on false.
1770 C.CCMask ^= C.CCValid;
1771 SDValue Result = emitSETCC(DAG, DL, Glue, C.CCValid, C.CCMask);
1772 EVT VT = Op.getValueType();
1773 // Extend the result to VT. Upper bits are ignored.
1775 Result = DAG.getNode(ISD::ANY_EXTEND, DL, VT, Result);
1776 // Sign-extend from the low bit.
1777 SDValue ShAmt = DAG.getConstant(VT.getSizeInBits() - 1, MVT::i32);
1778 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, Result, ShAmt);
1779 return DAG.getNode(ISD::SRA, DL, VT, Shl, ShAmt);
1783 SmallVector<SDValue, 5> Ops;
1784 Ops.push_back(TrueOp);
1785 Ops.push_back(FalseOp);
1786 Ops.push_back(DAG.getConstant(C.CCValid, MVT::i32));
1787 Ops.push_back(DAG.getConstant(C.CCMask, MVT::i32));
1788 Ops.push_back(Glue);
1790 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
1791 return DAG.getNode(SystemZISD::SELECT_CCMASK, DL, VTs, Ops);
1794 SDValue SystemZTargetLowering::lowerGlobalAddress(GlobalAddressSDNode *Node,
1795 SelectionDAG &DAG) const {
1797 const GlobalValue *GV = Node->getGlobal();
1798 int64_t Offset = Node->getOffset();
1799 EVT PtrVT = getPointerTy();
1800 Reloc::Model RM = DAG.getTarget().getRelocationModel();
1801 CodeModel::Model CM = DAG.getTarget().getCodeModel();
1804 if (Subtarget.isPC32DBLSymbol(GV, RM, CM)) {
1805 // Assign anchors at 1<<12 byte boundaries.
1806 uint64_t Anchor = Offset & ~uint64_t(0xfff);
1807 Result = DAG.getTargetGlobalAddress(GV, DL, PtrVT, Anchor);
1808 Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
1810 // The offset can be folded into the address if it is aligned to a halfword.
1812 if (Offset != 0 && (Offset & 1) == 0) {
1813 SDValue Full = DAG.getTargetGlobalAddress(GV, DL, PtrVT, Anchor + Offset);
1814 Result = DAG.getNode(SystemZISD::PCREL_OFFSET, DL, PtrVT, Full, Result);
1818 Result = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, SystemZII::MO_GOT);
1819 Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
1820 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
1821 MachinePointerInfo::getGOT(), false, false, false, 0);
1824 // If there was a non-zero offset that we didn't fold, create an explicit
1827 Result = DAG.getNode(ISD::ADD, DL, PtrVT, Result,
1828 DAG.getConstant(Offset, PtrVT));
1833 SDValue SystemZTargetLowering::lowerGlobalTLSAddress(GlobalAddressSDNode *Node,
1834 SelectionDAG &DAG) const {
1836 const GlobalValue *GV = Node->getGlobal();
1837 EVT PtrVT = getPointerTy();
1838 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
1840 if (model != TLSModel::LocalExec)
1841 llvm_unreachable("only local-exec TLS mode supported");
1843 // The high part of the thread pointer is in access register 0.
1844 SDValue TPHi = DAG.getNode(SystemZISD::EXTRACT_ACCESS, DL, MVT::i32,
1845 DAG.getConstant(0, MVT::i32));
1846 TPHi = DAG.getNode(ISD::ANY_EXTEND, DL, PtrVT, TPHi);
1848 // The low part of the thread pointer is in access register 1.
1849 SDValue TPLo = DAG.getNode(SystemZISD::EXTRACT_ACCESS, DL, MVT::i32,
1850 DAG.getConstant(1, MVT::i32));
1851 TPLo = DAG.getNode(ISD::ZERO_EXTEND, DL, PtrVT, TPLo);
1853 // Merge them into a single 64-bit address.
1854 SDValue TPHiShifted = DAG.getNode(ISD::SHL, DL, PtrVT, TPHi,
1855 DAG.getConstant(32, PtrVT));
1856 SDValue TP = DAG.getNode(ISD::OR, DL, PtrVT, TPHiShifted, TPLo);
1858 // Get the offset of GA from the thread pointer.
1859 SystemZConstantPoolValue *CPV =
1860 SystemZConstantPoolValue::Create(GV, SystemZCP::NTPOFF);
1862 // Force the offset into the constant pool and load it from there.
1863 SDValue CPAddr = DAG.getConstantPool(CPV, PtrVT, 8);
1864 SDValue Offset = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(),
1865 CPAddr, MachinePointerInfo::getConstantPool(),
1866 false, false, false, 0);
1868 // Add the base and offset together.
1869 return DAG.getNode(ISD::ADD, DL, PtrVT, TP, Offset);
1872 SDValue SystemZTargetLowering::lowerBlockAddress(BlockAddressSDNode *Node,
1873 SelectionDAG &DAG) const {
1875 const BlockAddress *BA = Node->getBlockAddress();
1876 int64_t Offset = Node->getOffset();
1877 EVT PtrVT = getPointerTy();
1879 SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT, Offset);
1880 Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
1884 SDValue SystemZTargetLowering::lowerJumpTable(JumpTableSDNode *JT,
1885 SelectionDAG &DAG) const {
1887 EVT PtrVT = getPointerTy();
1888 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1890 // Use LARL to load the address of the table.
1891 return DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
1894 SDValue SystemZTargetLowering::lowerConstantPool(ConstantPoolSDNode *CP,
1895 SelectionDAG &DAG) const {
1897 EVT PtrVT = getPointerTy();
1900 if (CP->isMachineConstantPoolEntry())
1901 Result = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
1902 CP->getAlignment());
1904 Result = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
1905 CP->getAlignment(), CP->getOffset());
1907 // Use LARL to load the address of the constant pool entry.
1908 return DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
1911 SDValue SystemZTargetLowering::lowerBITCAST(SDValue Op,
1912 SelectionDAG &DAG) const {
1914 SDValue In = Op.getOperand(0);
1915 EVT InVT = In.getValueType();
1916 EVT ResVT = Op.getValueType();
1918 if (InVT == MVT::i32 && ResVT == MVT::f32) {
1920 if (Subtarget.hasHighWord()) {
1921 SDNode *U64 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL,
1923 In64 = DAG.getTargetInsertSubreg(SystemZ::subreg_h32, DL,
1924 MVT::i64, SDValue(U64, 0), In);
1926 In64 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, In);
1927 In64 = DAG.getNode(ISD::SHL, DL, MVT::i64, In64,
1928 DAG.getConstant(32, MVT::i64));
1930 SDValue Out64 = DAG.getNode(ISD::BITCAST, DL, MVT::f64, In64);
1931 return DAG.getTargetExtractSubreg(SystemZ::subreg_h32,
1932 DL, MVT::f32, Out64);
1934 if (InVT == MVT::f32 && ResVT == MVT::i32) {
1935 SDNode *U64 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, MVT::f64);
1936 SDValue In64 = DAG.getTargetInsertSubreg(SystemZ::subreg_h32, DL,
1937 MVT::f64, SDValue(U64, 0), In);
1938 SDValue Out64 = DAG.getNode(ISD::BITCAST, DL, MVT::i64, In64);
1939 if (Subtarget.hasHighWord())
1940 return DAG.getTargetExtractSubreg(SystemZ::subreg_h32, DL,
1942 SDValue Shift = DAG.getNode(ISD::SRL, DL, MVT::i64, Out64,
1943 DAG.getConstant(32, MVT::i64));
1944 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Shift);
1946 llvm_unreachable("Unexpected bitcast combination");
1949 SDValue SystemZTargetLowering::lowerVASTART(SDValue Op,
1950 SelectionDAG &DAG) const {
1951 MachineFunction &MF = DAG.getMachineFunction();
1952 SystemZMachineFunctionInfo *FuncInfo =
1953 MF.getInfo<SystemZMachineFunctionInfo>();
1954 EVT PtrVT = getPointerTy();
1956 SDValue Chain = Op.getOperand(0);
1957 SDValue Addr = Op.getOperand(1);
1958 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1961 // The initial values of each field.
1962 const unsigned NumFields = 4;
1963 SDValue Fields[NumFields] = {
1964 DAG.getConstant(FuncInfo->getVarArgsFirstGPR(), PtrVT),
1965 DAG.getConstant(FuncInfo->getVarArgsFirstFPR(), PtrVT),
1966 DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT),
1967 DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), PtrVT)
1970 // Store each field into its respective slot.
1971 SDValue MemOps[NumFields];
1972 unsigned Offset = 0;
1973 for (unsigned I = 0; I < NumFields; ++I) {
1974 SDValue FieldAddr = Addr;
1976 FieldAddr = DAG.getNode(ISD::ADD, DL, PtrVT, FieldAddr,
1977 DAG.getIntPtrConstant(Offset));
1978 MemOps[I] = DAG.getStore(Chain, DL, Fields[I], FieldAddr,
1979 MachinePointerInfo(SV, Offset),
1983 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
1986 SDValue SystemZTargetLowering::lowerVACOPY(SDValue Op,
1987 SelectionDAG &DAG) const {
1988 SDValue Chain = Op.getOperand(0);
1989 SDValue DstPtr = Op.getOperand(1);
1990 SDValue SrcPtr = Op.getOperand(2);
1991 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
1992 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
1995 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr, DAG.getIntPtrConstant(32),
1996 /*Align*/8, /*isVolatile*/false, /*AlwaysInline*/false,
1997 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
2000 SDValue SystemZTargetLowering::
2001 lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const {
2002 SDValue Chain = Op.getOperand(0);
2003 SDValue Size = Op.getOperand(1);
2006 unsigned SPReg = getStackPointerRegisterToSaveRestore();
2008 // Get a reference to the stack pointer.
2009 SDValue OldSP = DAG.getCopyFromReg(Chain, DL, SPReg, MVT::i64);
2011 // Get the new stack pointer value.
2012 SDValue NewSP = DAG.getNode(ISD::SUB, DL, MVT::i64, OldSP, Size);
2014 // Copy the new stack pointer back.
2015 Chain = DAG.getCopyToReg(Chain, DL, SPReg, NewSP);
2017 // The allocated data lives above the 160 bytes allocated for the standard
2018 // frame, plus any outgoing stack arguments. We don't know how much that
2019 // amounts to yet, so emit a special ADJDYNALLOC placeholder.
2020 SDValue ArgAdjust = DAG.getNode(SystemZISD::ADJDYNALLOC, DL, MVT::i64);
2021 SDValue Result = DAG.getNode(ISD::ADD, DL, MVT::i64, NewSP, ArgAdjust);
2023 SDValue Ops[2] = { Result, Chain };
2024 return DAG.getMergeValues(Ops, DL);
2027 SDValue SystemZTargetLowering::lowerSMUL_LOHI(SDValue Op,
2028 SelectionDAG &DAG) const {
2029 EVT VT = Op.getValueType();
2033 // Just do a normal 64-bit multiplication and extract the results.
2034 // We define this so that it can be used for constant division.
2035 lowerMUL_LOHI32(DAG, DL, ISD::SIGN_EXTEND, Op.getOperand(0),
2036 Op.getOperand(1), Ops[1], Ops[0]);
2038 // Do a full 128-bit multiplication based on UMUL_LOHI64:
2040 // (ll * rl) + ((lh * rl) << 64) + ((ll * rh) << 64)
2042 // but using the fact that the upper halves are either all zeros
2045 // (ll * rl) - ((lh & rl) << 64) - ((ll & rh) << 64)
2047 // and grouping the right terms together since they are quicker than the
2050 // (ll * rl) - (((lh & rl) + (ll & rh)) << 64)
2051 SDValue C63 = DAG.getConstant(63, MVT::i64);
2052 SDValue LL = Op.getOperand(0);
2053 SDValue RL = Op.getOperand(1);
2054 SDValue LH = DAG.getNode(ISD::SRA, DL, VT, LL, C63);
2055 SDValue RH = DAG.getNode(ISD::SRA, DL, VT, RL, C63);
2056 // UMUL_LOHI64 returns the low result in the odd register and the high
2057 // result in the even register. SMUL_LOHI is defined to return the
2058 // low half first, so the results are in reverse order.
2059 lowerGR128Binary(DAG, DL, VT, SystemZ::AEXT128_64, SystemZISD::UMUL_LOHI64,
2060 LL, RL, Ops[1], Ops[0]);
2061 SDValue NegLLTimesRH = DAG.getNode(ISD::AND, DL, VT, LL, RH);
2062 SDValue NegLHTimesRL = DAG.getNode(ISD::AND, DL, VT, LH, RL);
2063 SDValue NegSum = DAG.getNode(ISD::ADD, DL, VT, NegLLTimesRH, NegLHTimesRL);
2064 Ops[1] = DAG.getNode(ISD::SUB, DL, VT, Ops[1], NegSum);
2066 return DAG.getMergeValues(Ops, DL);
2069 SDValue SystemZTargetLowering::lowerUMUL_LOHI(SDValue Op,
2070 SelectionDAG &DAG) const {
2071 EVT VT = Op.getValueType();
2075 // Just do a normal 64-bit multiplication and extract the results.
2076 // We define this so that it can be used for constant division.
2077 lowerMUL_LOHI32(DAG, DL, ISD::ZERO_EXTEND, Op.getOperand(0),
2078 Op.getOperand(1), Ops[1], Ops[0]);
2080 // UMUL_LOHI64 returns the low result in the odd register and the high
2081 // result in the even register. UMUL_LOHI is defined to return the
2082 // low half first, so the results are in reverse order.
2083 lowerGR128Binary(DAG, DL, VT, SystemZ::AEXT128_64, SystemZISD::UMUL_LOHI64,
2084 Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
2085 return DAG.getMergeValues(Ops, DL);
2088 SDValue SystemZTargetLowering::lowerSDIVREM(SDValue Op,
2089 SelectionDAG &DAG) const {
2090 SDValue Op0 = Op.getOperand(0);
2091 SDValue Op1 = Op.getOperand(1);
2092 EVT VT = Op.getValueType();
2096 // We use DSGF for 32-bit division.
2098 Op0 = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i64, Op0);
2099 Opcode = SystemZISD::SDIVREM32;
2100 } else if (DAG.ComputeNumSignBits(Op1) > 32) {
2101 Op1 = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Op1);
2102 Opcode = SystemZISD::SDIVREM32;
2104 Opcode = SystemZISD::SDIVREM64;
2106 // DSG(F) takes a 64-bit dividend, so the even register in the GR128
2107 // input is "don't care". The instruction returns the remainder in
2108 // the even register and the quotient in the odd register.
2110 lowerGR128Binary(DAG, DL, VT, SystemZ::AEXT128_64, Opcode,
2111 Op0, Op1, Ops[1], Ops[0]);
2112 return DAG.getMergeValues(Ops, DL);
2115 SDValue SystemZTargetLowering::lowerUDIVREM(SDValue Op,
2116 SelectionDAG &DAG) const {
2117 EVT VT = Op.getValueType();
2120 // DL(G) uses a double-width dividend, so we need to clear the even
2121 // register in the GR128 input. The instruction returns the remainder
2122 // in the even register and the quotient in the odd register.
2125 lowerGR128Binary(DAG, DL, VT, SystemZ::ZEXT128_32, SystemZISD::UDIVREM32,
2126 Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
2128 lowerGR128Binary(DAG, DL, VT, SystemZ::ZEXT128_64, SystemZISD::UDIVREM64,
2129 Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
2130 return DAG.getMergeValues(Ops, DL);
2133 SDValue SystemZTargetLowering::lowerOR(SDValue Op, SelectionDAG &DAG) const {
2134 assert(Op.getValueType() == MVT::i64 && "Should be 64-bit operation");
2136 // Get the known-zero masks for each operand.
2137 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1) };
2138 APInt KnownZero[2], KnownOne[2];
2139 DAG.computeKnownBits(Ops[0], KnownZero[0], KnownOne[0]);
2140 DAG.computeKnownBits(Ops[1], KnownZero[1], KnownOne[1]);
2142 // See if the upper 32 bits of one operand and the lower 32 bits of the
2143 // other are known zero. They are the low and high operands respectively.
2144 uint64_t Masks[] = { KnownZero[0].getZExtValue(),
2145 KnownZero[1].getZExtValue() };
2147 if ((Masks[0] >> 32) == 0xffffffff && uint32_t(Masks[1]) == 0xffffffff)
2149 else if ((Masks[1] >> 32) == 0xffffffff && uint32_t(Masks[0]) == 0xffffffff)
2154 SDValue LowOp = Ops[Low];
2155 SDValue HighOp = Ops[High];
2157 // If the high part is a constant, we're better off using IILH.
2158 if (HighOp.getOpcode() == ISD::Constant)
2161 // If the low part is a constant that is outside the range of LHI,
2162 // then we're better off using IILF.
2163 if (LowOp.getOpcode() == ISD::Constant) {
2164 int64_t Value = int32_t(cast<ConstantSDNode>(LowOp)->getZExtValue());
2165 if (!isInt<16>(Value))
2169 // Check whether the high part is an AND that doesn't change the
2170 // high 32 bits and just masks out low bits. We can skip it if so.
2171 if (HighOp.getOpcode() == ISD::AND &&
2172 HighOp.getOperand(1).getOpcode() == ISD::Constant) {
2173 SDValue HighOp0 = HighOp.getOperand(0);
2174 uint64_t Mask = cast<ConstantSDNode>(HighOp.getOperand(1))->getZExtValue();
2175 if (DAG.MaskedValueIsZero(HighOp0, APInt(64, ~(Mask | 0xffffffff))))
2179 // Take advantage of the fact that all GR32 operations only change the
2180 // low 32 bits by truncating Low to an i32 and inserting it directly
2181 // using a subreg. The interesting cases are those where the truncation
2184 SDValue Low32 = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, LowOp);
2185 return DAG.getTargetInsertSubreg(SystemZ::subreg_l32, DL,
2186 MVT::i64, HighOp, Low32);
2189 // Op is an atomic load. Lower it into a normal volatile load.
2190 SDValue SystemZTargetLowering::lowerATOMIC_LOAD(SDValue Op,
2191 SelectionDAG &DAG) const {
2192 auto *Node = cast<AtomicSDNode>(Op.getNode());
2193 return DAG.getExtLoad(ISD::EXTLOAD, SDLoc(Op), Op.getValueType(),
2194 Node->getChain(), Node->getBasePtr(),
2195 Node->getMemoryVT(), Node->getMemOperand());
2198 // Op is an atomic store. Lower it into a normal volatile store followed
2199 // by a serialization.
2200 SDValue SystemZTargetLowering::lowerATOMIC_STORE(SDValue Op,
2201 SelectionDAG &DAG) const {
2202 auto *Node = cast<AtomicSDNode>(Op.getNode());
2203 SDValue Chain = DAG.getTruncStore(Node->getChain(), SDLoc(Op), Node->getVal(),
2204 Node->getBasePtr(), Node->getMemoryVT(),
2205 Node->getMemOperand());
2206 return SDValue(DAG.getMachineNode(SystemZ::Serialize, SDLoc(Op), MVT::Other,
2210 // Op is an 8-, 16-bit or 32-bit ATOMIC_LOAD_* operation. Lower the first
2211 // two into the fullword ATOMIC_LOADW_* operation given by Opcode.
2212 SDValue SystemZTargetLowering::lowerATOMIC_LOAD_OP(SDValue Op,
2214 unsigned Opcode) const {
2215 auto *Node = cast<AtomicSDNode>(Op.getNode());
2217 // 32-bit operations need no code outside the main loop.
2218 EVT NarrowVT = Node->getMemoryVT();
2219 EVT WideVT = MVT::i32;
2220 if (NarrowVT == WideVT)
2223 int64_t BitSize = NarrowVT.getSizeInBits();
2224 SDValue ChainIn = Node->getChain();
2225 SDValue Addr = Node->getBasePtr();
2226 SDValue Src2 = Node->getVal();
2227 MachineMemOperand *MMO = Node->getMemOperand();
2229 EVT PtrVT = Addr.getValueType();
2231 // Convert atomic subtracts of constants into additions.
2232 if (Opcode == SystemZISD::ATOMIC_LOADW_SUB)
2233 if (auto *Const = dyn_cast<ConstantSDNode>(Src2)) {
2234 Opcode = SystemZISD::ATOMIC_LOADW_ADD;
2235 Src2 = DAG.getConstant(-Const->getSExtValue(), Src2.getValueType());
2238 // Get the address of the containing word.
2239 SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr,
2240 DAG.getConstant(-4, PtrVT));
2242 // Get the number of bits that the word must be rotated left in order
2243 // to bring the field to the top bits of a GR32.
2244 SDValue BitShift = DAG.getNode(ISD::SHL, DL, PtrVT, Addr,
2245 DAG.getConstant(3, PtrVT));
2246 BitShift = DAG.getNode(ISD::TRUNCATE, DL, WideVT, BitShift);
2248 // Get the complementing shift amount, for rotating a field in the top
2249 // bits back to its proper position.
2250 SDValue NegBitShift = DAG.getNode(ISD::SUB, DL, WideVT,
2251 DAG.getConstant(0, WideVT), BitShift);
2253 // Extend the source operand to 32 bits and prepare it for the inner loop.
2254 // ATOMIC_SWAPW uses RISBG to rotate the field left, but all other
2255 // operations require the source to be shifted in advance. (This shift
2256 // can be folded if the source is constant.) For AND and NAND, the lower
2257 // bits must be set, while for other opcodes they should be left clear.
2258 if (Opcode != SystemZISD::ATOMIC_SWAPW)
2259 Src2 = DAG.getNode(ISD::SHL, DL, WideVT, Src2,
2260 DAG.getConstant(32 - BitSize, WideVT));
2261 if (Opcode == SystemZISD::ATOMIC_LOADW_AND ||
2262 Opcode == SystemZISD::ATOMIC_LOADW_NAND)
2263 Src2 = DAG.getNode(ISD::OR, DL, WideVT, Src2,
2264 DAG.getConstant(uint32_t(-1) >> BitSize, WideVT));
2266 // Construct the ATOMIC_LOADW_* node.
2267 SDVTList VTList = DAG.getVTList(WideVT, MVT::Other);
2268 SDValue Ops[] = { ChainIn, AlignedAddr, Src2, BitShift, NegBitShift,
2269 DAG.getConstant(BitSize, WideVT) };
2270 SDValue AtomicOp = DAG.getMemIntrinsicNode(Opcode, DL, VTList, Ops,
2273 // Rotate the result of the final CS so that the field is in the lower
2274 // bits of a GR32, then truncate it.
2275 SDValue ResultShift = DAG.getNode(ISD::ADD, DL, WideVT, BitShift,
2276 DAG.getConstant(BitSize, WideVT));
2277 SDValue Result = DAG.getNode(ISD::ROTL, DL, WideVT, AtomicOp, ResultShift);
2279 SDValue RetOps[2] = { Result, AtomicOp.getValue(1) };
2280 return DAG.getMergeValues(RetOps, DL);
2283 // Op is an ATOMIC_LOAD_SUB operation. Lower 8- and 16-bit operations
2284 // into ATOMIC_LOADW_SUBs and decide whether to convert 32- and 64-bit
2285 // operations into additions.
2286 SDValue SystemZTargetLowering::lowerATOMIC_LOAD_SUB(SDValue Op,
2287 SelectionDAG &DAG) const {
2288 auto *Node = cast<AtomicSDNode>(Op.getNode());
2289 EVT MemVT = Node->getMemoryVT();
2290 if (MemVT == MVT::i32 || MemVT == MVT::i64) {
2291 // A full-width operation.
2292 assert(Op.getValueType() == MemVT && "Mismatched VTs");
2293 SDValue Src2 = Node->getVal();
2297 if (auto *Op2 = dyn_cast<ConstantSDNode>(Src2)) {
2298 // Use an addition if the operand is constant and either LAA(G) is
2299 // available or the negative value is in the range of A(G)FHI.
2300 int64_t Value = (-Op2->getAPIntValue()).getSExtValue();
2301 if (isInt<32>(Value) || Subtarget.hasInterlockedAccess1())
2302 NegSrc2 = DAG.getConstant(Value, MemVT);
2303 } else if (Subtarget.hasInterlockedAccess1())
2304 // Use LAA(G) if available.
2305 NegSrc2 = DAG.getNode(ISD::SUB, DL, MemVT, DAG.getConstant(0, MemVT),
2308 if (NegSrc2.getNode())
2309 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, DL, MemVT,
2310 Node->getChain(), Node->getBasePtr(), NegSrc2,
2311 Node->getMemOperand(), Node->getOrdering(),
2312 Node->getSynchScope());
2314 // Use the node as-is.
2318 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_SUB);
2321 // Node is an 8- or 16-bit ATOMIC_CMP_SWAP operation. Lower the first two
2322 // into a fullword ATOMIC_CMP_SWAPW operation.
2323 SDValue SystemZTargetLowering::lowerATOMIC_CMP_SWAP(SDValue Op,
2324 SelectionDAG &DAG) const {
2325 auto *Node = cast<AtomicSDNode>(Op.getNode());
2327 // We have native support for 32-bit compare and swap.
2328 EVT NarrowVT = Node->getMemoryVT();
2329 EVT WideVT = MVT::i32;
2330 if (NarrowVT == WideVT)
2333 int64_t BitSize = NarrowVT.getSizeInBits();
2334 SDValue ChainIn = Node->getOperand(0);
2335 SDValue Addr = Node->getOperand(1);
2336 SDValue CmpVal = Node->getOperand(2);
2337 SDValue SwapVal = Node->getOperand(3);
2338 MachineMemOperand *MMO = Node->getMemOperand();
2340 EVT PtrVT = Addr.getValueType();
2342 // Get the address of the containing word.
2343 SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr,
2344 DAG.getConstant(-4, PtrVT));
2346 // Get the number of bits that the word must be rotated left in order
2347 // to bring the field to the top bits of a GR32.
2348 SDValue BitShift = DAG.getNode(ISD::SHL, DL, PtrVT, Addr,
2349 DAG.getConstant(3, PtrVT));
2350 BitShift = DAG.getNode(ISD::TRUNCATE, DL, WideVT, BitShift);
2352 // Get the complementing shift amount, for rotating a field in the top
2353 // bits back to its proper position.
2354 SDValue NegBitShift = DAG.getNode(ISD::SUB, DL, WideVT,
2355 DAG.getConstant(0, WideVT), BitShift);
2357 // Construct the ATOMIC_CMP_SWAPW node.
2358 SDVTList VTList = DAG.getVTList(WideVT, MVT::Other);
2359 SDValue Ops[] = { ChainIn, AlignedAddr, CmpVal, SwapVal, BitShift,
2360 NegBitShift, DAG.getConstant(BitSize, WideVT) };
2361 SDValue AtomicOp = DAG.getMemIntrinsicNode(SystemZISD::ATOMIC_CMP_SWAPW, DL,
2362 VTList, Ops, NarrowVT, MMO);
2366 SDValue SystemZTargetLowering::lowerSTACKSAVE(SDValue Op,
2367 SelectionDAG &DAG) const {
2368 MachineFunction &MF = DAG.getMachineFunction();
2369 MF.getInfo<SystemZMachineFunctionInfo>()->setManipulatesSP(true);
2370 return DAG.getCopyFromReg(Op.getOperand(0), SDLoc(Op),
2371 SystemZ::R15D, Op.getValueType());
2374 SDValue SystemZTargetLowering::lowerSTACKRESTORE(SDValue Op,
2375 SelectionDAG &DAG) const {
2376 MachineFunction &MF = DAG.getMachineFunction();
2377 MF.getInfo<SystemZMachineFunctionInfo>()->setManipulatesSP(true);
2378 return DAG.getCopyToReg(Op.getOperand(0), SDLoc(Op),
2379 SystemZ::R15D, Op.getOperand(1));
2382 SDValue SystemZTargetLowering::lowerPREFETCH(SDValue Op,
2383 SelectionDAG &DAG) const {
2384 bool IsData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
2386 // Just preserve the chain.
2387 return Op.getOperand(0);
2389 bool IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
2390 unsigned Code = IsWrite ? SystemZ::PFD_WRITE : SystemZ::PFD_READ;
2391 auto *Node = cast<MemIntrinsicSDNode>(Op.getNode());
2394 DAG.getConstant(Code, MVT::i32),
2397 return DAG.getMemIntrinsicNode(SystemZISD::PREFETCH, SDLoc(Op),
2398 Node->getVTList(), Ops,
2399 Node->getMemoryVT(), Node->getMemOperand());
2402 SDValue SystemZTargetLowering::LowerOperation(SDValue Op,
2403 SelectionDAG &DAG) const {
2404 switch (Op.getOpcode()) {
2406 return lowerBR_CC(Op, DAG);
2407 case ISD::SELECT_CC:
2408 return lowerSELECT_CC(Op, DAG);
2410 return lowerSETCC(Op, DAG);
2411 case ISD::GlobalAddress:
2412 return lowerGlobalAddress(cast<GlobalAddressSDNode>(Op), DAG);
2413 case ISD::GlobalTLSAddress:
2414 return lowerGlobalTLSAddress(cast<GlobalAddressSDNode>(Op), DAG);
2415 case ISD::BlockAddress:
2416 return lowerBlockAddress(cast<BlockAddressSDNode>(Op), DAG);
2417 case ISD::JumpTable:
2418 return lowerJumpTable(cast<JumpTableSDNode>(Op), DAG);
2419 case ISD::ConstantPool:
2420 return lowerConstantPool(cast<ConstantPoolSDNode>(Op), DAG);
2422 return lowerBITCAST(Op, DAG);
2424 return lowerVASTART(Op, DAG);
2426 return lowerVACOPY(Op, DAG);
2427 case ISD::DYNAMIC_STACKALLOC:
2428 return lowerDYNAMIC_STACKALLOC(Op, DAG);
2429 case ISD::SMUL_LOHI:
2430 return lowerSMUL_LOHI(Op, DAG);
2431 case ISD::UMUL_LOHI:
2432 return lowerUMUL_LOHI(Op, DAG);
2434 return lowerSDIVREM(Op, DAG);
2436 return lowerUDIVREM(Op, DAG);
2438 return lowerOR(Op, DAG);
2439 case ISD::ATOMIC_SWAP:
2440 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_SWAPW);
2441 case ISD::ATOMIC_STORE:
2442 return lowerATOMIC_STORE(Op, DAG);
2443 case ISD::ATOMIC_LOAD:
2444 return lowerATOMIC_LOAD(Op, DAG);
2445 case ISD::ATOMIC_LOAD_ADD:
2446 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_ADD);
2447 case ISD::ATOMIC_LOAD_SUB:
2448 return lowerATOMIC_LOAD_SUB(Op, DAG);
2449 case ISD::ATOMIC_LOAD_AND:
2450 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_AND);
2451 case ISD::ATOMIC_LOAD_OR:
2452 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_OR);
2453 case ISD::ATOMIC_LOAD_XOR:
2454 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_XOR);
2455 case ISD::ATOMIC_LOAD_NAND:
2456 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_NAND);
2457 case ISD::ATOMIC_LOAD_MIN:
2458 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_MIN);
2459 case ISD::ATOMIC_LOAD_MAX:
2460 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_MAX);
2461 case ISD::ATOMIC_LOAD_UMIN:
2462 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_UMIN);
2463 case ISD::ATOMIC_LOAD_UMAX:
2464 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_UMAX);
2465 case ISD::ATOMIC_CMP_SWAP:
2466 return lowerATOMIC_CMP_SWAP(Op, DAG);
2467 case ISD::STACKSAVE:
2468 return lowerSTACKSAVE(Op, DAG);
2469 case ISD::STACKRESTORE:
2470 return lowerSTACKRESTORE(Op, DAG);
2472 return lowerPREFETCH(Op, DAG);
2474 llvm_unreachable("Unexpected node to lower");
2478 const char *SystemZTargetLowering::getTargetNodeName(unsigned Opcode) const {
2479 #define OPCODE(NAME) case SystemZISD::NAME: return "SystemZISD::" #NAME
2484 OPCODE(PCREL_WRAPPER);
2485 OPCODE(PCREL_OFFSET);
2491 OPCODE(SELECT_CCMASK);
2492 OPCODE(ADJDYNALLOC);
2493 OPCODE(EXTRACT_ACCESS);
2494 OPCODE(UMUL_LOHI64);
2510 OPCODE(SEARCH_STRING);
2513 OPCODE(ATOMIC_SWAPW);
2514 OPCODE(ATOMIC_LOADW_ADD);
2515 OPCODE(ATOMIC_LOADW_SUB);
2516 OPCODE(ATOMIC_LOADW_AND);
2517 OPCODE(ATOMIC_LOADW_OR);
2518 OPCODE(ATOMIC_LOADW_XOR);
2519 OPCODE(ATOMIC_LOADW_NAND);
2520 OPCODE(ATOMIC_LOADW_MIN);
2521 OPCODE(ATOMIC_LOADW_MAX);
2522 OPCODE(ATOMIC_LOADW_UMIN);
2523 OPCODE(ATOMIC_LOADW_UMAX);
2524 OPCODE(ATOMIC_CMP_SWAPW);
2531 SDValue SystemZTargetLowering::PerformDAGCombine(SDNode *N,
2532 DAGCombinerInfo &DCI) const {
2533 SelectionDAG &DAG = DCI.DAG;
2534 unsigned Opcode = N->getOpcode();
2535 if (Opcode == ISD::SIGN_EXTEND) {
2536 // Convert (sext (ashr (shl X, C1), C2)) to
2537 // (ashr (shl (anyext X), C1'), C2')), since wider shifts are as
2538 // cheap as narrower ones.
2539 SDValue N0 = N->getOperand(0);
2540 EVT VT = N->getValueType(0);
2541 if (N0.hasOneUse() && N0.getOpcode() == ISD::SRA) {
2542 auto *SraAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2543 SDValue Inner = N0.getOperand(0);
2544 if (SraAmt && Inner.hasOneUse() && Inner.getOpcode() == ISD::SHL) {
2545 if (auto *ShlAmt = dyn_cast<ConstantSDNode>(Inner.getOperand(1))) {
2546 unsigned Extra = (VT.getSizeInBits() -
2547 N0.getValueType().getSizeInBits());
2548 unsigned NewShlAmt = ShlAmt->getZExtValue() + Extra;
2549 unsigned NewSraAmt = SraAmt->getZExtValue() + Extra;
2550 EVT ShiftVT = N0.getOperand(1).getValueType();
2551 SDValue Ext = DAG.getNode(ISD::ANY_EXTEND, SDLoc(Inner), VT,
2552 Inner.getOperand(0));
2553 SDValue Shl = DAG.getNode(ISD::SHL, SDLoc(Inner), VT, Ext,
2554 DAG.getConstant(NewShlAmt, ShiftVT));
2555 return DAG.getNode(ISD::SRA, SDLoc(N0), VT, Shl,
2556 DAG.getConstant(NewSraAmt, ShiftVT));
2564 //===----------------------------------------------------------------------===//
2566 //===----------------------------------------------------------------------===//
2568 // Create a new basic block after MBB.
2569 static MachineBasicBlock *emitBlockAfter(MachineBasicBlock *MBB) {
2570 MachineFunction &MF = *MBB->getParent();
2571 MachineBasicBlock *NewMBB = MF.CreateMachineBasicBlock(MBB->getBasicBlock());
2572 MF.insert(std::next(MachineFunction::iterator(MBB)), NewMBB);
2576 // Split MBB after MI and return the new block (the one that contains
2577 // instructions after MI).
2578 static MachineBasicBlock *splitBlockAfter(MachineInstr *MI,
2579 MachineBasicBlock *MBB) {
2580 MachineBasicBlock *NewMBB = emitBlockAfter(MBB);
2581 NewMBB->splice(NewMBB->begin(), MBB,
2582 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
2583 NewMBB->transferSuccessorsAndUpdatePHIs(MBB);
2587 // Split MBB before MI and return the new block (the one that contains MI).
2588 static MachineBasicBlock *splitBlockBefore(MachineInstr *MI,
2589 MachineBasicBlock *MBB) {
2590 MachineBasicBlock *NewMBB = emitBlockAfter(MBB);
2591 NewMBB->splice(NewMBB->begin(), MBB, MI, MBB->end());
2592 NewMBB->transferSuccessorsAndUpdatePHIs(MBB);
2596 // Force base value Base into a register before MI. Return the register.
2597 static unsigned forceReg(MachineInstr *MI, MachineOperand &Base,
2598 const SystemZInstrInfo *TII) {
2600 return Base.getReg();
2602 MachineBasicBlock *MBB = MI->getParent();
2603 MachineFunction &MF = *MBB->getParent();
2604 MachineRegisterInfo &MRI = MF.getRegInfo();
2606 unsigned Reg = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
2607 BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(SystemZ::LA), Reg)
2608 .addOperand(Base).addImm(0).addReg(0);
2612 // Implement EmitInstrWithCustomInserter for pseudo Select* instruction MI.
2614 SystemZTargetLowering::emitSelect(MachineInstr *MI,
2615 MachineBasicBlock *MBB) const {
2616 const SystemZInstrInfo *TII =
2617 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
2619 unsigned DestReg = MI->getOperand(0).getReg();
2620 unsigned TrueReg = MI->getOperand(1).getReg();
2621 unsigned FalseReg = MI->getOperand(2).getReg();
2622 unsigned CCValid = MI->getOperand(3).getImm();
2623 unsigned CCMask = MI->getOperand(4).getImm();
2624 DebugLoc DL = MI->getDebugLoc();
2626 MachineBasicBlock *StartMBB = MBB;
2627 MachineBasicBlock *JoinMBB = splitBlockBefore(MI, MBB);
2628 MachineBasicBlock *FalseMBB = emitBlockAfter(StartMBB);
2631 // BRC CCMask, JoinMBB
2632 // # fallthrough to FalseMBB
2634 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2635 .addImm(CCValid).addImm(CCMask).addMBB(JoinMBB);
2636 MBB->addSuccessor(JoinMBB);
2637 MBB->addSuccessor(FalseMBB);
2640 // # fallthrough to JoinMBB
2642 MBB->addSuccessor(JoinMBB);
2645 // %Result = phi [ %FalseReg, FalseMBB ], [ %TrueReg, StartMBB ]
2648 BuildMI(*MBB, MI, DL, TII->get(SystemZ::PHI), DestReg)
2649 .addReg(TrueReg).addMBB(StartMBB)
2650 .addReg(FalseReg).addMBB(FalseMBB);
2652 MI->eraseFromParent();
2656 // Implement EmitInstrWithCustomInserter for pseudo CondStore* instruction MI.
2657 // StoreOpcode is the store to use and Invert says whether the store should
2658 // happen when the condition is false rather than true. If a STORE ON
2659 // CONDITION is available, STOCOpcode is its opcode, otherwise it is 0.
2661 SystemZTargetLowering::emitCondStore(MachineInstr *MI,
2662 MachineBasicBlock *MBB,
2663 unsigned StoreOpcode, unsigned STOCOpcode,
2664 bool Invert) const {
2665 const SystemZInstrInfo *TII =
2666 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
2668 unsigned SrcReg = MI->getOperand(0).getReg();
2669 MachineOperand Base = MI->getOperand(1);
2670 int64_t Disp = MI->getOperand(2).getImm();
2671 unsigned IndexReg = MI->getOperand(3).getReg();
2672 unsigned CCValid = MI->getOperand(4).getImm();
2673 unsigned CCMask = MI->getOperand(5).getImm();
2674 DebugLoc DL = MI->getDebugLoc();
2676 StoreOpcode = TII->getOpcodeForOffset(StoreOpcode, Disp);
2678 // Use STOCOpcode if possible. We could use different store patterns in
2679 // order to avoid matching the index register, but the performance trade-offs
2680 // might be more complicated in that case.
2681 if (STOCOpcode && !IndexReg && Subtarget.hasLoadStoreOnCond()) {
2684 BuildMI(*MBB, MI, DL, TII->get(STOCOpcode))
2685 .addReg(SrcReg).addOperand(Base).addImm(Disp)
2686 .addImm(CCValid).addImm(CCMask);
2687 MI->eraseFromParent();
2691 // Get the condition needed to branch around the store.
2695 MachineBasicBlock *StartMBB = MBB;
2696 MachineBasicBlock *JoinMBB = splitBlockBefore(MI, MBB);
2697 MachineBasicBlock *FalseMBB = emitBlockAfter(StartMBB);
2700 // BRC CCMask, JoinMBB
2701 // # fallthrough to FalseMBB
2703 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2704 .addImm(CCValid).addImm(CCMask).addMBB(JoinMBB);
2705 MBB->addSuccessor(JoinMBB);
2706 MBB->addSuccessor(FalseMBB);
2709 // store %SrcReg, %Disp(%Index,%Base)
2710 // # fallthrough to JoinMBB
2712 BuildMI(MBB, DL, TII->get(StoreOpcode))
2713 .addReg(SrcReg).addOperand(Base).addImm(Disp).addReg(IndexReg);
2714 MBB->addSuccessor(JoinMBB);
2716 MI->eraseFromParent();
2720 // Implement EmitInstrWithCustomInserter for pseudo ATOMIC_LOAD{,W}_*
2721 // or ATOMIC_SWAP{,W} instruction MI. BinOpcode is the instruction that
2722 // performs the binary operation elided by "*", or 0 for ATOMIC_SWAP{,W}.
2723 // BitSize is the width of the field in bits, or 0 if this is a partword
2724 // ATOMIC_LOADW_* or ATOMIC_SWAPW instruction, in which case the bitsize
2725 // is one of the operands. Invert says whether the field should be
2726 // inverted after performing BinOpcode (e.g. for NAND).
2728 SystemZTargetLowering::emitAtomicLoadBinary(MachineInstr *MI,
2729 MachineBasicBlock *MBB,
2732 bool Invert) const {
2733 MachineFunction &MF = *MBB->getParent();
2734 const SystemZInstrInfo *TII =
2735 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
2736 MachineRegisterInfo &MRI = MF.getRegInfo();
2737 bool IsSubWord = (BitSize < 32);
2739 // Extract the operands. Base can be a register or a frame index.
2740 // Src2 can be a register or immediate.
2741 unsigned Dest = MI->getOperand(0).getReg();
2742 MachineOperand Base = earlyUseOperand(MI->getOperand(1));
2743 int64_t Disp = MI->getOperand(2).getImm();
2744 MachineOperand Src2 = earlyUseOperand(MI->getOperand(3));
2745 unsigned BitShift = (IsSubWord ? MI->getOperand(4).getReg() : 0);
2746 unsigned NegBitShift = (IsSubWord ? MI->getOperand(5).getReg() : 0);
2747 DebugLoc DL = MI->getDebugLoc();
2749 BitSize = MI->getOperand(6).getImm();
2751 // Subword operations use 32-bit registers.
2752 const TargetRegisterClass *RC = (BitSize <= 32 ?
2753 &SystemZ::GR32BitRegClass :
2754 &SystemZ::GR64BitRegClass);
2755 unsigned LOpcode = BitSize <= 32 ? SystemZ::L : SystemZ::LG;
2756 unsigned CSOpcode = BitSize <= 32 ? SystemZ::CS : SystemZ::CSG;
2758 // Get the right opcodes for the displacement.
2759 LOpcode = TII->getOpcodeForOffset(LOpcode, Disp);
2760 CSOpcode = TII->getOpcodeForOffset(CSOpcode, Disp);
2761 assert(LOpcode && CSOpcode && "Displacement out of range");
2763 // Create virtual registers for temporary results.
2764 unsigned OrigVal = MRI.createVirtualRegister(RC);
2765 unsigned OldVal = MRI.createVirtualRegister(RC);
2766 unsigned NewVal = (BinOpcode || IsSubWord ?
2767 MRI.createVirtualRegister(RC) : Src2.getReg());
2768 unsigned RotatedOldVal = (IsSubWord ? MRI.createVirtualRegister(RC) : OldVal);
2769 unsigned RotatedNewVal = (IsSubWord ? MRI.createVirtualRegister(RC) : NewVal);
2771 // Insert a basic block for the main loop.
2772 MachineBasicBlock *StartMBB = MBB;
2773 MachineBasicBlock *DoneMBB = splitBlockBefore(MI, MBB);
2774 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
2778 // %OrigVal = L Disp(%Base)
2779 // # fall through to LoopMMB
2781 BuildMI(MBB, DL, TII->get(LOpcode), OrigVal)
2782 .addOperand(Base).addImm(Disp).addReg(0);
2783 MBB->addSuccessor(LoopMBB);
2786 // %OldVal = phi [ %OrigVal, StartMBB ], [ %Dest, LoopMBB ]
2787 // %RotatedOldVal = RLL %OldVal, 0(%BitShift)
2788 // %RotatedNewVal = OP %RotatedOldVal, %Src2
2789 // %NewVal = RLL %RotatedNewVal, 0(%NegBitShift)
2790 // %Dest = CS %OldVal, %NewVal, Disp(%Base)
2792 // # fall through to DoneMMB
2794 BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
2795 .addReg(OrigVal).addMBB(StartMBB)
2796 .addReg(Dest).addMBB(LoopMBB);
2798 BuildMI(MBB, DL, TII->get(SystemZ::RLL), RotatedOldVal)
2799 .addReg(OldVal).addReg(BitShift).addImm(0);
2801 // Perform the operation normally and then invert every bit of the field.
2802 unsigned Tmp = MRI.createVirtualRegister(RC);
2803 BuildMI(MBB, DL, TII->get(BinOpcode), Tmp)
2804 .addReg(RotatedOldVal).addOperand(Src2);
2806 // XILF with the upper BitSize bits set.
2807 BuildMI(MBB, DL, TII->get(SystemZ::XILF), RotatedNewVal)
2808 .addReg(Tmp).addImm(-1U << (32 - BitSize));
2810 // Use LCGR and add -1 to the result, which is more compact than
2811 // an XILF, XILH pair.
2812 unsigned Tmp2 = MRI.createVirtualRegister(RC);
2813 BuildMI(MBB, DL, TII->get(SystemZ::LCGR), Tmp2).addReg(Tmp);
2814 BuildMI(MBB, DL, TII->get(SystemZ::AGHI), RotatedNewVal)
2815 .addReg(Tmp2).addImm(-1);
2817 } else if (BinOpcode)
2818 // A simply binary operation.
2819 BuildMI(MBB, DL, TII->get(BinOpcode), RotatedNewVal)
2820 .addReg(RotatedOldVal).addOperand(Src2);
2822 // Use RISBG to rotate Src2 into position and use it to replace the
2823 // field in RotatedOldVal.
2824 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RotatedNewVal)
2825 .addReg(RotatedOldVal).addReg(Src2.getReg())
2826 .addImm(32).addImm(31 + BitSize).addImm(32 - BitSize);
2828 BuildMI(MBB, DL, TII->get(SystemZ::RLL), NewVal)
2829 .addReg(RotatedNewVal).addReg(NegBitShift).addImm(0);
2830 BuildMI(MBB, DL, TII->get(CSOpcode), Dest)
2831 .addReg(OldVal).addReg(NewVal).addOperand(Base).addImm(Disp);
2832 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2833 .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
2834 MBB->addSuccessor(LoopMBB);
2835 MBB->addSuccessor(DoneMBB);
2837 MI->eraseFromParent();
2841 // Implement EmitInstrWithCustomInserter for pseudo
2842 // ATOMIC_LOAD{,W}_{,U}{MIN,MAX} instruction MI. CompareOpcode is the
2843 // instruction that should be used to compare the current field with the
2844 // minimum or maximum value. KeepOldMask is the BRC condition-code mask
2845 // for when the current field should be kept. BitSize is the width of
2846 // the field in bits, or 0 if this is a partword ATOMIC_LOADW_* instruction.
2848 SystemZTargetLowering::emitAtomicLoadMinMax(MachineInstr *MI,
2849 MachineBasicBlock *MBB,
2850 unsigned CompareOpcode,
2851 unsigned KeepOldMask,
2852 unsigned BitSize) const {
2853 MachineFunction &MF = *MBB->getParent();
2854 const SystemZInstrInfo *TII =
2855 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
2856 MachineRegisterInfo &MRI = MF.getRegInfo();
2857 bool IsSubWord = (BitSize < 32);
2859 // Extract the operands. Base can be a register or a frame index.
2860 unsigned Dest = MI->getOperand(0).getReg();
2861 MachineOperand Base = earlyUseOperand(MI->getOperand(1));
2862 int64_t Disp = MI->getOperand(2).getImm();
2863 unsigned Src2 = MI->getOperand(3).getReg();
2864 unsigned BitShift = (IsSubWord ? MI->getOperand(4).getReg() : 0);
2865 unsigned NegBitShift = (IsSubWord ? MI->getOperand(5).getReg() : 0);
2866 DebugLoc DL = MI->getDebugLoc();
2868 BitSize = MI->getOperand(6).getImm();
2870 // Subword operations use 32-bit registers.
2871 const TargetRegisterClass *RC = (BitSize <= 32 ?
2872 &SystemZ::GR32BitRegClass :
2873 &SystemZ::GR64BitRegClass);
2874 unsigned LOpcode = BitSize <= 32 ? SystemZ::L : SystemZ::LG;
2875 unsigned CSOpcode = BitSize <= 32 ? SystemZ::CS : SystemZ::CSG;
2877 // Get the right opcodes for the displacement.
2878 LOpcode = TII->getOpcodeForOffset(LOpcode, Disp);
2879 CSOpcode = TII->getOpcodeForOffset(CSOpcode, Disp);
2880 assert(LOpcode && CSOpcode && "Displacement out of range");
2882 // Create virtual registers for temporary results.
2883 unsigned OrigVal = MRI.createVirtualRegister(RC);
2884 unsigned OldVal = MRI.createVirtualRegister(RC);
2885 unsigned NewVal = MRI.createVirtualRegister(RC);
2886 unsigned RotatedOldVal = (IsSubWord ? MRI.createVirtualRegister(RC) : OldVal);
2887 unsigned RotatedAltVal = (IsSubWord ? MRI.createVirtualRegister(RC) : Src2);
2888 unsigned RotatedNewVal = (IsSubWord ? MRI.createVirtualRegister(RC) : NewVal);
2890 // Insert 3 basic blocks for the loop.
2891 MachineBasicBlock *StartMBB = MBB;
2892 MachineBasicBlock *DoneMBB = splitBlockBefore(MI, MBB);
2893 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
2894 MachineBasicBlock *UseAltMBB = emitBlockAfter(LoopMBB);
2895 MachineBasicBlock *UpdateMBB = emitBlockAfter(UseAltMBB);
2899 // %OrigVal = L Disp(%Base)
2900 // # fall through to LoopMMB
2902 BuildMI(MBB, DL, TII->get(LOpcode), OrigVal)
2903 .addOperand(Base).addImm(Disp).addReg(0);
2904 MBB->addSuccessor(LoopMBB);
2907 // %OldVal = phi [ %OrigVal, StartMBB ], [ %Dest, UpdateMBB ]
2908 // %RotatedOldVal = RLL %OldVal, 0(%BitShift)
2909 // CompareOpcode %RotatedOldVal, %Src2
2910 // BRC KeepOldMask, UpdateMBB
2912 BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
2913 .addReg(OrigVal).addMBB(StartMBB)
2914 .addReg(Dest).addMBB(UpdateMBB);
2916 BuildMI(MBB, DL, TII->get(SystemZ::RLL), RotatedOldVal)
2917 .addReg(OldVal).addReg(BitShift).addImm(0);
2918 BuildMI(MBB, DL, TII->get(CompareOpcode))
2919 .addReg(RotatedOldVal).addReg(Src2);
2920 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2921 .addImm(SystemZ::CCMASK_ICMP).addImm(KeepOldMask).addMBB(UpdateMBB);
2922 MBB->addSuccessor(UpdateMBB);
2923 MBB->addSuccessor(UseAltMBB);
2926 // %RotatedAltVal = RISBG %RotatedOldVal, %Src2, 32, 31 + BitSize, 0
2927 // # fall through to UpdateMMB
2930 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RotatedAltVal)
2931 .addReg(RotatedOldVal).addReg(Src2)
2932 .addImm(32).addImm(31 + BitSize).addImm(0);
2933 MBB->addSuccessor(UpdateMBB);
2936 // %RotatedNewVal = PHI [ %RotatedOldVal, LoopMBB ],
2937 // [ %RotatedAltVal, UseAltMBB ]
2938 // %NewVal = RLL %RotatedNewVal, 0(%NegBitShift)
2939 // %Dest = CS %OldVal, %NewVal, Disp(%Base)
2941 // # fall through to DoneMMB
2943 BuildMI(MBB, DL, TII->get(SystemZ::PHI), RotatedNewVal)
2944 .addReg(RotatedOldVal).addMBB(LoopMBB)
2945 .addReg(RotatedAltVal).addMBB(UseAltMBB);
2947 BuildMI(MBB, DL, TII->get(SystemZ::RLL), NewVal)
2948 .addReg(RotatedNewVal).addReg(NegBitShift).addImm(0);
2949 BuildMI(MBB, DL, TII->get(CSOpcode), Dest)
2950 .addReg(OldVal).addReg(NewVal).addOperand(Base).addImm(Disp);
2951 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2952 .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
2953 MBB->addSuccessor(LoopMBB);
2954 MBB->addSuccessor(DoneMBB);
2956 MI->eraseFromParent();
2960 // Implement EmitInstrWithCustomInserter for pseudo ATOMIC_CMP_SWAPW
2963 SystemZTargetLowering::emitAtomicCmpSwapW(MachineInstr *MI,
2964 MachineBasicBlock *MBB) const {
2965 MachineFunction &MF = *MBB->getParent();
2966 const SystemZInstrInfo *TII =
2967 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
2968 MachineRegisterInfo &MRI = MF.getRegInfo();
2970 // Extract the operands. Base can be a register or a frame index.
2971 unsigned Dest = MI->getOperand(0).getReg();
2972 MachineOperand Base = earlyUseOperand(MI->getOperand(1));
2973 int64_t Disp = MI->getOperand(2).getImm();
2974 unsigned OrigCmpVal = MI->getOperand(3).getReg();
2975 unsigned OrigSwapVal = MI->getOperand(4).getReg();
2976 unsigned BitShift = MI->getOperand(5).getReg();
2977 unsigned NegBitShift = MI->getOperand(6).getReg();
2978 int64_t BitSize = MI->getOperand(7).getImm();
2979 DebugLoc DL = MI->getDebugLoc();
2981 const TargetRegisterClass *RC = &SystemZ::GR32BitRegClass;
2983 // Get the right opcodes for the displacement.
2984 unsigned LOpcode = TII->getOpcodeForOffset(SystemZ::L, Disp);
2985 unsigned CSOpcode = TII->getOpcodeForOffset(SystemZ::CS, Disp);
2986 assert(LOpcode && CSOpcode && "Displacement out of range");
2988 // Create virtual registers for temporary results.
2989 unsigned OrigOldVal = MRI.createVirtualRegister(RC);
2990 unsigned OldVal = MRI.createVirtualRegister(RC);
2991 unsigned CmpVal = MRI.createVirtualRegister(RC);
2992 unsigned SwapVal = MRI.createVirtualRegister(RC);
2993 unsigned StoreVal = MRI.createVirtualRegister(RC);
2994 unsigned RetryOldVal = MRI.createVirtualRegister(RC);
2995 unsigned RetryCmpVal = MRI.createVirtualRegister(RC);
2996 unsigned RetrySwapVal = MRI.createVirtualRegister(RC);
2998 // Insert 2 basic blocks for the loop.
2999 MachineBasicBlock *StartMBB = MBB;
3000 MachineBasicBlock *DoneMBB = splitBlockBefore(MI, MBB);
3001 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
3002 MachineBasicBlock *SetMBB = emitBlockAfter(LoopMBB);
3006 // %OrigOldVal = L Disp(%Base)
3007 // # fall through to LoopMMB
3009 BuildMI(MBB, DL, TII->get(LOpcode), OrigOldVal)
3010 .addOperand(Base).addImm(Disp).addReg(0);
3011 MBB->addSuccessor(LoopMBB);
3014 // %OldVal = phi [ %OrigOldVal, EntryBB ], [ %RetryOldVal, SetMBB ]
3015 // %CmpVal = phi [ %OrigCmpVal, EntryBB ], [ %RetryCmpVal, SetMBB ]
3016 // %SwapVal = phi [ %OrigSwapVal, EntryBB ], [ %RetrySwapVal, SetMBB ]
3017 // %Dest = RLL %OldVal, BitSize(%BitShift)
3018 // ^^ The low BitSize bits contain the field
3020 // %RetryCmpVal = RISBG32 %CmpVal, %Dest, 32, 63-BitSize, 0
3021 // ^^ Replace the upper 32-BitSize bits of the
3022 // comparison value with those that we loaded,
3023 // so that we can use a full word comparison.
3024 // CR %Dest, %RetryCmpVal
3026 // # Fall through to SetMBB
3028 BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
3029 .addReg(OrigOldVal).addMBB(StartMBB)
3030 .addReg(RetryOldVal).addMBB(SetMBB);
3031 BuildMI(MBB, DL, TII->get(SystemZ::PHI), CmpVal)
3032 .addReg(OrigCmpVal).addMBB(StartMBB)
3033 .addReg(RetryCmpVal).addMBB(SetMBB);
3034 BuildMI(MBB, DL, TII->get(SystemZ::PHI), SwapVal)
3035 .addReg(OrigSwapVal).addMBB(StartMBB)
3036 .addReg(RetrySwapVal).addMBB(SetMBB);
3037 BuildMI(MBB, DL, TII->get(SystemZ::RLL), Dest)
3038 .addReg(OldVal).addReg(BitShift).addImm(BitSize);
3039 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RetryCmpVal)
3040 .addReg(CmpVal).addReg(Dest).addImm(32).addImm(63 - BitSize).addImm(0);
3041 BuildMI(MBB, DL, TII->get(SystemZ::CR))
3042 .addReg(Dest).addReg(RetryCmpVal);
3043 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
3044 .addImm(SystemZ::CCMASK_ICMP)
3045 .addImm(SystemZ::CCMASK_CMP_NE).addMBB(DoneMBB);
3046 MBB->addSuccessor(DoneMBB);
3047 MBB->addSuccessor(SetMBB);
3050 // %RetrySwapVal = RISBG32 %SwapVal, %Dest, 32, 63-BitSize, 0
3051 // ^^ Replace the upper 32-BitSize bits of the new
3052 // value with those that we loaded.
3053 // %StoreVal = RLL %RetrySwapVal, -BitSize(%NegBitShift)
3054 // ^^ Rotate the new field to its proper position.
3055 // %RetryOldVal = CS %Dest, %StoreVal, Disp(%Base)
3057 // # fall through to ExitMMB
3059 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RetrySwapVal)
3060 .addReg(SwapVal).addReg(Dest).addImm(32).addImm(63 - BitSize).addImm(0);
3061 BuildMI(MBB, DL, TII->get(SystemZ::RLL), StoreVal)
3062 .addReg(RetrySwapVal).addReg(NegBitShift).addImm(-BitSize);
3063 BuildMI(MBB, DL, TII->get(CSOpcode), RetryOldVal)
3064 .addReg(OldVal).addReg(StoreVal).addOperand(Base).addImm(Disp);
3065 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
3066 .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
3067 MBB->addSuccessor(LoopMBB);
3068 MBB->addSuccessor(DoneMBB);
3070 MI->eraseFromParent();
3074 // Emit an extension from a GR32 or GR64 to a GR128. ClearEven is true
3075 // if the high register of the GR128 value must be cleared or false if
3076 // it's "don't care". SubReg is subreg_l32 when extending a GR32
3077 // and subreg_l64 when extending a GR64.
3079 SystemZTargetLowering::emitExt128(MachineInstr *MI,
3080 MachineBasicBlock *MBB,
3081 bool ClearEven, unsigned SubReg) const {
3082 MachineFunction &MF = *MBB->getParent();
3083 const SystemZInstrInfo *TII =
3084 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
3085 MachineRegisterInfo &MRI = MF.getRegInfo();
3086 DebugLoc DL = MI->getDebugLoc();
3088 unsigned Dest = MI->getOperand(0).getReg();
3089 unsigned Src = MI->getOperand(1).getReg();
3090 unsigned In128 = MRI.createVirtualRegister(&SystemZ::GR128BitRegClass);
3092 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::IMPLICIT_DEF), In128);
3094 unsigned NewIn128 = MRI.createVirtualRegister(&SystemZ::GR128BitRegClass);
3095 unsigned Zero64 = MRI.createVirtualRegister(&SystemZ::GR64BitRegClass);
3097 BuildMI(*MBB, MI, DL, TII->get(SystemZ::LLILL), Zero64)
3099 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::INSERT_SUBREG), NewIn128)
3100 .addReg(In128).addReg(Zero64).addImm(SystemZ::subreg_h64);
3103 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::INSERT_SUBREG), Dest)
3104 .addReg(In128).addReg(Src).addImm(SubReg);
3106 MI->eraseFromParent();
3111 SystemZTargetLowering::emitMemMemWrapper(MachineInstr *MI,
3112 MachineBasicBlock *MBB,
3113 unsigned Opcode) const {
3114 MachineFunction &MF = *MBB->getParent();
3115 const SystemZInstrInfo *TII =
3116 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
3117 MachineRegisterInfo &MRI = MF.getRegInfo();
3118 DebugLoc DL = MI->getDebugLoc();
3120 MachineOperand DestBase = earlyUseOperand(MI->getOperand(0));
3121 uint64_t DestDisp = MI->getOperand(1).getImm();
3122 MachineOperand SrcBase = earlyUseOperand(MI->getOperand(2));
3123 uint64_t SrcDisp = MI->getOperand(3).getImm();
3124 uint64_t Length = MI->getOperand(4).getImm();
3126 // When generating more than one CLC, all but the last will need to
3127 // branch to the end when a difference is found.
3128 MachineBasicBlock *EndMBB = (Length > 256 && Opcode == SystemZ::CLC ?
3129 splitBlockAfter(MI, MBB) : nullptr);
3131 // Check for the loop form, in which operand 5 is the trip count.
3132 if (MI->getNumExplicitOperands() > 5) {
3133 bool HaveSingleBase = DestBase.isIdenticalTo(SrcBase);
3135 uint64_t StartCountReg = MI->getOperand(5).getReg();
3136 uint64_t StartSrcReg = forceReg(MI, SrcBase, TII);
3137 uint64_t StartDestReg = (HaveSingleBase ? StartSrcReg :
3138 forceReg(MI, DestBase, TII));
3140 const TargetRegisterClass *RC = &SystemZ::ADDR64BitRegClass;
3141 uint64_t ThisSrcReg = MRI.createVirtualRegister(RC);
3142 uint64_t ThisDestReg = (HaveSingleBase ? ThisSrcReg :
3143 MRI.createVirtualRegister(RC));
3144 uint64_t NextSrcReg = MRI.createVirtualRegister(RC);
3145 uint64_t NextDestReg = (HaveSingleBase ? NextSrcReg :
3146 MRI.createVirtualRegister(RC));
3148 RC = &SystemZ::GR64BitRegClass;
3149 uint64_t ThisCountReg = MRI.createVirtualRegister(RC);
3150 uint64_t NextCountReg = MRI.createVirtualRegister(RC);
3152 MachineBasicBlock *StartMBB = MBB;
3153 MachineBasicBlock *DoneMBB = splitBlockBefore(MI, MBB);
3154 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
3155 MachineBasicBlock *NextMBB = (EndMBB ? emitBlockAfter(LoopMBB) : LoopMBB);
3158 // # fall through to LoopMMB
3159 MBB->addSuccessor(LoopMBB);
3162 // %ThisDestReg = phi [ %StartDestReg, StartMBB ],
3163 // [ %NextDestReg, NextMBB ]
3164 // %ThisSrcReg = phi [ %StartSrcReg, StartMBB ],
3165 // [ %NextSrcReg, NextMBB ]
3166 // %ThisCountReg = phi [ %StartCountReg, StartMBB ],
3167 // [ %NextCountReg, NextMBB ]
3168 // ( PFD 2, 768+DestDisp(%ThisDestReg) )
3169 // Opcode DestDisp(256,%ThisDestReg), SrcDisp(%ThisSrcReg)
3172 // The prefetch is used only for MVC. The JLH is used only for CLC.
3175 BuildMI(MBB, DL, TII->get(SystemZ::PHI), ThisDestReg)
3176 .addReg(StartDestReg).addMBB(StartMBB)
3177 .addReg(NextDestReg).addMBB(NextMBB);
3178 if (!HaveSingleBase)
3179 BuildMI(MBB, DL, TII->get(SystemZ::PHI), ThisSrcReg)
3180 .addReg(StartSrcReg).addMBB(StartMBB)
3181 .addReg(NextSrcReg).addMBB(NextMBB);
3182 BuildMI(MBB, DL, TII->get(SystemZ::PHI), ThisCountReg)
3183 .addReg(StartCountReg).addMBB(StartMBB)
3184 .addReg(NextCountReg).addMBB(NextMBB);
3185 if (Opcode == SystemZ::MVC)
3186 BuildMI(MBB, DL, TII->get(SystemZ::PFD))
3187 .addImm(SystemZ::PFD_WRITE)
3188 .addReg(ThisDestReg).addImm(DestDisp + 768).addReg(0);
3189 BuildMI(MBB, DL, TII->get(Opcode))
3190 .addReg(ThisDestReg).addImm(DestDisp).addImm(256)
3191 .addReg(ThisSrcReg).addImm(SrcDisp);
3193 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
3194 .addImm(SystemZ::CCMASK_ICMP).addImm(SystemZ::CCMASK_CMP_NE)
3196 MBB->addSuccessor(EndMBB);
3197 MBB->addSuccessor(NextMBB);
3201 // %NextDestReg = LA 256(%ThisDestReg)
3202 // %NextSrcReg = LA 256(%ThisSrcReg)
3203 // %NextCountReg = AGHI %ThisCountReg, -1
3204 // CGHI %NextCountReg, 0
3206 // # fall through to DoneMMB
3208 // The AGHI, CGHI and JLH should be converted to BRCTG by later passes.
3211 BuildMI(MBB, DL, TII->get(SystemZ::LA), NextDestReg)
3212 .addReg(ThisDestReg).addImm(256).addReg(0);
3213 if (!HaveSingleBase)
3214 BuildMI(MBB, DL, TII->get(SystemZ::LA), NextSrcReg)
3215 .addReg(ThisSrcReg).addImm(256).addReg(0);
3216 BuildMI(MBB, DL, TII->get(SystemZ::AGHI), NextCountReg)
3217 .addReg(ThisCountReg).addImm(-1);
3218 BuildMI(MBB, DL, TII->get(SystemZ::CGHI))
3219 .addReg(NextCountReg).addImm(0);
3220 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
3221 .addImm(SystemZ::CCMASK_ICMP).addImm(SystemZ::CCMASK_CMP_NE)
3223 MBB->addSuccessor(LoopMBB);
3224 MBB->addSuccessor(DoneMBB);
3226 DestBase = MachineOperand::CreateReg(NextDestReg, false);
3227 SrcBase = MachineOperand::CreateReg(NextSrcReg, false);
3231 // Handle any remaining bytes with straight-line code.
3232 while (Length > 0) {
3233 uint64_t ThisLength = std::min(Length, uint64_t(256));
3234 // The previous iteration might have created out-of-range displacements.
3235 // Apply them using LAY if so.
3236 if (!isUInt<12>(DestDisp)) {
3237 unsigned Reg = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
3238 BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(SystemZ::LAY), Reg)
3239 .addOperand(DestBase).addImm(DestDisp).addReg(0);
3240 DestBase = MachineOperand::CreateReg(Reg, false);
3243 if (!isUInt<12>(SrcDisp)) {
3244 unsigned Reg = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
3245 BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(SystemZ::LAY), Reg)
3246 .addOperand(SrcBase).addImm(SrcDisp).addReg(0);
3247 SrcBase = MachineOperand::CreateReg(Reg, false);
3250 BuildMI(*MBB, MI, DL, TII->get(Opcode))
3251 .addOperand(DestBase).addImm(DestDisp).addImm(ThisLength)
3252 .addOperand(SrcBase).addImm(SrcDisp);
3253 DestDisp += ThisLength;
3254 SrcDisp += ThisLength;
3255 Length -= ThisLength;
3256 // If there's another CLC to go, branch to the end if a difference
3258 if (EndMBB && Length > 0) {
3259 MachineBasicBlock *NextMBB = splitBlockBefore(MI, MBB);
3260 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
3261 .addImm(SystemZ::CCMASK_ICMP).addImm(SystemZ::CCMASK_CMP_NE)
3263 MBB->addSuccessor(EndMBB);
3264 MBB->addSuccessor(NextMBB);
3269 MBB->addSuccessor(EndMBB);
3271 MBB->addLiveIn(SystemZ::CC);
3274 MI->eraseFromParent();
3278 // Decompose string pseudo-instruction MI into a loop that continually performs
3279 // Opcode until CC != 3.
3281 SystemZTargetLowering::emitStringWrapper(MachineInstr *MI,
3282 MachineBasicBlock *MBB,
3283 unsigned Opcode) const {
3284 MachineFunction &MF = *MBB->getParent();
3285 const SystemZInstrInfo *TII =
3286 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
3287 MachineRegisterInfo &MRI = MF.getRegInfo();
3288 DebugLoc DL = MI->getDebugLoc();
3290 uint64_t End1Reg = MI->getOperand(0).getReg();
3291 uint64_t Start1Reg = MI->getOperand(1).getReg();
3292 uint64_t Start2Reg = MI->getOperand(2).getReg();
3293 uint64_t CharReg = MI->getOperand(3).getReg();
3295 const TargetRegisterClass *RC = &SystemZ::GR64BitRegClass;
3296 uint64_t This1Reg = MRI.createVirtualRegister(RC);
3297 uint64_t This2Reg = MRI.createVirtualRegister(RC);
3298 uint64_t End2Reg = MRI.createVirtualRegister(RC);
3300 MachineBasicBlock *StartMBB = MBB;
3301 MachineBasicBlock *DoneMBB = splitBlockBefore(MI, MBB);
3302 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
3305 // # fall through to LoopMMB
3306 MBB->addSuccessor(LoopMBB);
3309 // %This1Reg = phi [ %Start1Reg, StartMBB ], [ %End1Reg, LoopMBB ]
3310 // %This2Reg = phi [ %Start2Reg, StartMBB ], [ %End2Reg, LoopMBB ]
3312 // %End1Reg, %End2Reg = CLST %This1Reg, %This2Reg -- uses R0L
3314 // # fall through to DoneMMB
3316 // The load of R0L can be hoisted by post-RA LICM.
3319 BuildMI(MBB, DL, TII->get(SystemZ::PHI), This1Reg)
3320 .addReg(Start1Reg).addMBB(StartMBB)
3321 .addReg(End1Reg).addMBB(LoopMBB);
3322 BuildMI(MBB, DL, TII->get(SystemZ::PHI), This2Reg)
3323 .addReg(Start2Reg).addMBB(StartMBB)
3324 .addReg(End2Reg).addMBB(LoopMBB);
3325 BuildMI(MBB, DL, TII->get(TargetOpcode::COPY), SystemZ::R0L).addReg(CharReg);
3326 BuildMI(MBB, DL, TII->get(Opcode))
3327 .addReg(End1Reg, RegState::Define).addReg(End2Reg, RegState::Define)
3328 .addReg(This1Reg).addReg(This2Reg);
3329 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
3330 .addImm(SystemZ::CCMASK_ANY).addImm(SystemZ::CCMASK_3).addMBB(LoopMBB);
3331 MBB->addSuccessor(LoopMBB);
3332 MBB->addSuccessor(DoneMBB);
3334 DoneMBB->addLiveIn(SystemZ::CC);
3336 MI->eraseFromParent();
3340 MachineBasicBlock *SystemZTargetLowering::
3341 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const {
3342 switch (MI->getOpcode()) {
3343 case SystemZ::Select32Mux:
3344 case SystemZ::Select32:
3345 case SystemZ::SelectF32:
3346 case SystemZ::Select64:
3347 case SystemZ::SelectF64:
3348 case SystemZ::SelectF128:
3349 return emitSelect(MI, MBB);
3351 case SystemZ::CondStore8Mux:
3352 return emitCondStore(MI, MBB, SystemZ::STCMux, 0, false);
3353 case SystemZ::CondStore8MuxInv:
3354 return emitCondStore(MI, MBB, SystemZ::STCMux, 0, true);
3355 case SystemZ::CondStore16Mux:
3356 return emitCondStore(MI, MBB, SystemZ::STHMux, 0, false);
3357 case SystemZ::CondStore16MuxInv:
3358 return emitCondStore(MI, MBB, SystemZ::STHMux, 0, true);
3359 case SystemZ::CondStore8:
3360 return emitCondStore(MI, MBB, SystemZ::STC, 0, false);
3361 case SystemZ::CondStore8Inv:
3362 return emitCondStore(MI, MBB, SystemZ::STC, 0, true);
3363 case SystemZ::CondStore16:
3364 return emitCondStore(MI, MBB, SystemZ::STH, 0, false);
3365 case SystemZ::CondStore16Inv:
3366 return emitCondStore(MI, MBB, SystemZ::STH, 0, true);
3367 case SystemZ::CondStore32:
3368 return emitCondStore(MI, MBB, SystemZ::ST, SystemZ::STOC, false);
3369 case SystemZ::CondStore32Inv:
3370 return emitCondStore(MI, MBB, SystemZ::ST, SystemZ::STOC, true);
3371 case SystemZ::CondStore64:
3372 return emitCondStore(MI, MBB, SystemZ::STG, SystemZ::STOCG, false);
3373 case SystemZ::CondStore64Inv:
3374 return emitCondStore(MI, MBB, SystemZ::STG, SystemZ::STOCG, true);
3375 case SystemZ::CondStoreF32:
3376 return emitCondStore(MI, MBB, SystemZ::STE, 0, false);
3377 case SystemZ::CondStoreF32Inv:
3378 return emitCondStore(MI, MBB, SystemZ::STE, 0, true);
3379 case SystemZ::CondStoreF64:
3380 return emitCondStore(MI, MBB, SystemZ::STD, 0, false);
3381 case SystemZ::CondStoreF64Inv:
3382 return emitCondStore(MI, MBB, SystemZ::STD, 0, true);
3384 case SystemZ::AEXT128_64:
3385 return emitExt128(MI, MBB, false, SystemZ::subreg_l64);
3386 case SystemZ::ZEXT128_32:
3387 return emitExt128(MI, MBB, true, SystemZ::subreg_l32);
3388 case SystemZ::ZEXT128_64:
3389 return emitExt128(MI, MBB, true, SystemZ::subreg_l64);
3391 case SystemZ::ATOMIC_SWAPW:
3392 return emitAtomicLoadBinary(MI, MBB, 0, 0);
3393 case SystemZ::ATOMIC_SWAP_32:
3394 return emitAtomicLoadBinary(MI, MBB, 0, 32);
3395 case SystemZ::ATOMIC_SWAP_64:
3396 return emitAtomicLoadBinary(MI, MBB, 0, 64);
3398 case SystemZ::ATOMIC_LOADW_AR:
3399 return emitAtomicLoadBinary(MI, MBB, SystemZ::AR, 0);
3400 case SystemZ::ATOMIC_LOADW_AFI:
3401 return emitAtomicLoadBinary(MI, MBB, SystemZ::AFI, 0);
3402 case SystemZ::ATOMIC_LOAD_AR:
3403 return emitAtomicLoadBinary(MI, MBB, SystemZ::AR, 32);
3404 case SystemZ::ATOMIC_LOAD_AHI:
3405 return emitAtomicLoadBinary(MI, MBB, SystemZ::AHI, 32);
3406 case SystemZ::ATOMIC_LOAD_AFI:
3407 return emitAtomicLoadBinary(MI, MBB, SystemZ::AFI, 32);
3408 case SystemZ::ATOMIC_LOAD_AGR:
3409 return emitAtomicLoadBinary(MI, MBB, SystemZ::AGR, 64);
3410 case SystemZ::ATOMIC_LOAD_AGHI:
3411 return emitAtomicLoadBinary(MI, MBB, SystemZ::AGHI, 64);
3412 case SystemZ::ATOMIC_LOAD_AGFI:
3413 return emitAtomicLoadBinary(MI, MBB, SystemZ::AGFI, 64);
3415 case SystemZ::ATOMIC_LOADW_SR:
3416 return emitAtomicLoadBinary(MI, MBB, SystemZ::SR, 0);
3417 case SystemZ::ATOMIC_LOAD_SR:
3418 return emitAtomicLoadBinary(MI, MBB, SystemZ::SR, 32);
3419 case SystemZ::ATOMIC_LOAD_SGR:
3420 return emitAtomicLoadBinary(MI, MBB, SystemZ::SGR, 64);
3422 case SystemZ::ATOMIC_LOADW_NR:
3423 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 0);
3424 case SystemZ::ATOMIC_LOADW_NILH:
3425 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 0);
3426 case SystemZ::ATOMIC_LOAD_NR:
3427 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 32);
3428 case SystemZ::ATOMIC_LOAD_NILL:
3429 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL, 32);
3430 case SystemZ::ATOMIC_LOAD_NILH:
3431 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 32);
3432 case SystemZ::ATOMIC_LOAD_NILF:
3433 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF, 32);
3434 case SystemZ::ATOMIC_LOAD_NGR:
3435 return emitAtomicLoadBinary(MI, MBB, SystemZ::NGR, 64);
3436 case SystemZ::ATOMIC_LOAD_NILL64:
3437 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL64, 64);
3438 case SystemZ::ATOMIC_LOAD_NILH64:
3439 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH64, 64);
3440 case SystemZ::ATOMIC_LOAD_NIHL64:
3441 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHL64, 64);
3442 case SystemZ::ATOMIC_LOAD_NIHH64:
3443 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHH64, 64);
3444 case SystemZ::ATOMIC_LOAD_NILF64:
3445 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF64, 64);
3446 case SystemZ::ATOMIC_LOAD_NIHF64:
3447 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHF64, 64);
3449 case SystemZ::ATOMIC_LOADW_OR:
3450 return emitAtomicLoadBinary(MI, MBB, SystemZ::OR, 0);
3451 case SystemZ::ATOMIC_LOADW_OILH:
3452 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILH, 0);
3453 case SystemZ::ATOMIC_LOAD_OR:
3454 return emitAtomicLoadBinary(MI, MBB, SystemZ::OR, 32);
3455 case SystemZ::ATOMIC_LOAD_OILL:
3456 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILL, 32);
3457 case SystemZ::ATOMIC_LOAD_OILH:
3458 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILH, 32);
3459 case SystemZ::ATOMIC_LOAD_OILF:
3460 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILF, 32);
3461 case SystemZ::ATOMIC_LOAD_OGR:
3462 return emitAtomicLoadBinary(MI, MBB, SystemZ::OGR, 64);
3463 case SystemZ::ATOMIC_LOAD_OILL64:
3464 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILL64, 64);
3465 case SystemZ::ATOMIC_LOAD_OILH64:
3466 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILH64, 64);
3467 case SystemZ::ATOMIC_LOAD_OIHL64:
3468 return emitAtomicLoadBinary(MI, MBB, SystemZ::OIHL64, 64);
3469 case SystemZ::ATOMIC_LOAD_OIHH64:
3470 return emitAtomicLoadBinary(MI, MBB, SystemZ::OIHH64, 64);
3471 case SystemZ::ATOMIC_LOAD_OILF64:
3472 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILF64, 64);
3473 case SystemZ::ATOMIC_LOAD_OIHF64:
3474 return emitAtomicLoadBinary(MI, MBB, SystemZ::OIHF64, 64);
3476 case SystemZ::ATOMIC_LOADW_XR:
3477 return emitAtomicLoadBinary(MI, MBB, SystemZ::XR, 0);
3478 case SystemZ::ATOMIC_LOADW_XILF:
3479 return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF, 0);
3480 case SystemZ::ATOMIC_LOAD_XR:
3481 return emitAtomicLoadBinary(MI, MBB, SystemZ::XR, 32);
3482 case SystemZ::ATOMIC_LOAD_XILF:
3483 return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF, 32);
3484 case SystemZ::ATOMIC_LOAD_XGR:
3485 return emitAtomicLoadBinary(MI, MBB, SystemZ::XGR, 64);
3486 case SystemZ::ATOMIC_LOAD_XILF64:
3487 return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF64, 64);
3488 case SystemZ::ATOMIC_LOAD_XIHF64:
3489 return emitAtomicLoadBinary(MI, MBB, SystemZ::XIHF64, 64);
3491 case SystemZ::ATOMIC_LOADW_NRi:
3492 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 0, true);
3493 case SystemZ::ATOMIC_LOADW_NILHi:
3494 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 0, true);
3495 case SystemZ::ATOMIC_LOAD_NRi:
3496 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 32, true);
3497 case SystemZ::ATOMIC_LOAD_NILLi:
3498 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL, 32, true);
3499 case SystemZ::ATOMIC_LOAD_NILHi:
3500 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 32, true);
3501 case SystemZ::ATOMIC_LOAD_NILFi:
3502 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF, 32, true);
3503 case SystemZ::ATOMIC_LOAD_NGRi:
3504 return emitAtomicLoadBinary(MI, MBB, SystemZ::NGR, 64, true);
3505 case SystemZ::ATOMIC_LOAD_NILL64i:
3506 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL64, 64, true);
3507 case SystemZ::ATOMIC_LOAD_NILH64i:
3508 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH64, 64, true);
3509 case SystemZ::ATOMIC_LOAD_NIHL64i:
3510 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHL64, 64, true);
3511 case SystemZ::ATOMIC_LOAD_NIHH64i:
3512 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHH64, 64, true);
3513 case SystemZ::ATOMIC_LOAD_NILF64i:
3514 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF64, 64, true);
3515 case SystemZ::ATOMIC_LOAD_NIHF64i:
3516 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHF64, 64, true);
3518 case SystemZ::ATOMIC_LOADW_MIN:
3519 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
3520 SystemZ::CCMASK_CMP_LE, 0);
3521 case SystemZ::ATOMIC_LOAD_MIN_32:
3522 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
3523 SystemZ::CCMASK_CMP_LE, 32);
3524 case SystemZ::ATOMIC_LOAD_MIN_64:
3525 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CGR,
3526 SystemZ::CCMASK_CMP_LE, 64);
3528 case SystemZ::ATOMIC_LOADW_MAX:
3529 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
3530 SystemZ::CCMASK_CMP_GE, 0);
3531 case SystemZ::ATOMIC_LOAD_MAX_32:
3532 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
3533 SystemZ::CCMASK_CMP_GE, 32);
3534 case SystemZ::ATOMIC_LOAD_MAX_64:
3535 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CGR,
3536 SystemZ::CCMASK_CMP_GE, 64);
3538 case SystemZ::ATOMIC_LOADW_UMIN:
3539 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
3540 SystemZ::CCMASK_CMP_LE, 0);
3541 case SystemZ::ATOMIC_LOAD_UMIN_32:
3542 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
3543 SystemZ::CCMASK_CMP_LE, 32);
3544 case SystemZ::ATOMIC_LOAD_UMIN_64:
3545 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLGR,
3546 SystemZ::CCMASK_CMP_LE, 64);
3548 case SystemZ::ATOMIC_LOADW_UMAX:
3549 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
3550 SystemZ::CCMASK_CMP_GE, 0);
3551 case SystemZ::ATOMIC_LOAD_UMAX_32:
3552 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
3553 SystemZ::CCMASK_CMP_GE, 32);
3554 case SystemZ::ATOMIC_LOAD_UMAX_64:
3555 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLGR,
3556 SystemZ::CCMASK_CMP_GE, 64);
3558 case SystemZ::ATOMIC_CMP_SWAPW:
3559 return emitAtomicCmpSwapW(MI, MBB);
3560 case SystemZ::MVCSequence:
3561 case SystemZ::MVCLoop:
3562 return emitMemMemWrapper(MI, MBB, SystemZ::MVC);
3563 case SystemZ::NCSequence:
3564 case SystemZ::NCLoop:
3565 return emitMemMemWrapper(MI, MBB, SystemZ::NC);
3566 case SystemZ::OCSequence:
3567 case SystemZ::OCLoop:
3568 return emitMemMemWrapper(MI, MBB, SystemZ::OC);
3569 case SystemZ::XCSequence:
3570 case SystemZ::XCLoop:
3571 return emitMemMemWrapper(MI, MBB, SystemZ::XC);
3572 case SystemZ::CLCSequence:
3573 case SystemZ::CLCLoop:
3574 return emitMemMemWrapper(MI, MBB, SystemZ::CLC);
3575 case SystemZ::CLSTLoop:
3576 return emitStringWrapper(MI, MBB, SystemZ::CLST);
3577 case SystemZ::MVSTLoop:
3578 return emitStringWrapper(MI, MBB, SystemZ::MVST);
3579 case SystemZ::SRSTLoop:
3580 return emitStringWrapper(MI, MBB, SystemZ::SRST);
3582 llvm_unreachable("Unexpected instr type to insert");