1 //===-- SystemZISelLowering.cpp - SystemZ DAG lowering implementation -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SystemZTargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "systemz-lower"
16 #include "SystemZISelLowering.h"
17 #include "SystemZCallingConv.h"
18 #include "SystemZConstantPoolValue.h"
19 #include "SystemZMachineFunctionInfo.h"
20 #include "SystemZTargetMachine.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
28 // Classify VT as either 32 or 64 bit.
29 static bool is32Bit(EVT VT) {
30 switch (VT.getSimpleVT().SimpleTy) {
36 llvm_unreachable("Unsupported type");
40 // Return a version of MachineOperand that can be safely used before the
42 static MachineOperand earlyUseOperand(MachineOperand Op) {
48 SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm)
49 : TargetLowering(tm, new TargetLoweringObjectFileELF()),
50 Subtarget(*tm.getSubtargetImpl()), TM(tm) {
51 MVT PtrVT = getPointerTy();
53 // Set up the register classes.
54 addRegisterClass(MVT::i32, &SystemZ::GR32BitRegClass);
55 addRegisterClass(MVT::i64, &SystemZ::GR64BitRegClass);
56 addRegisterClass(MVT::f32, &SystemZ::FP32BitRegClass);
57 addRegisterClass(MVT::f64, &SystemZ::FP64BitRegClass);
58 addRegisterClass(MVT::f128, &SystemZ::FP128BitRegClass);
60 // Compute derived properties from the register classes
61 computeRegisterProperties();
63 // Set up special registers.
64 setExceptionPointerRegister(SystemZ::R6D);
65 setExceptionSelectorRegister(SystemZ::R7D);
66 setStackPointerRegisterToSaveRestore(SystemZ::R15D);
68 // TODO: It may be better to default to latency-oriented scheduling, however
69 // LLVM's current latency-oriented scheduler can't handle physreg definitions
70 // such as SystemZ has with CC, so set this to the register-pressure
71 // scheduler, because it can.
72 setSchedulingPreference(Sched::RegPressure);
74 setBooleanContents(ZeroOrOneBooleanContent);
75 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
77 // Instructions are strings of 2-byte aligned 2-byte values.
78 setMinFunctionAlignment(2);
80 // Handle operations that are handled in a similar way for all types.
81 for (unsigned I = MVT::FIRST_INTEGER_VALUETYPE;
82 I <= MVT::LAST_FP_VALUETYPE;
84 MVT VT = MVT::SimpleValueType(I);
85 if (isTypeLegal(VT)) {
86 // Expand SETCC(X, Y, COND) into SELECT_CC(X, Y, 1, 0, COND).
87 setOperationAction(ISD::SETCC, VT, Expand);
89 // Expand SELECT(C, A, B) into SELECT_CC(X, 0, A, B, NE).
90 setOperationAction(ISD::SELECT, VT, Expand);
92 // Lower SELECT_CC and BR_CC into separate comparisons and branches.
93 setOperationAction(ISD::SELECT_CC, VT, Custom);
94 setOperationAction(ISD::BR_CC, VT, Custom);
98 // Expand jump table branches as address arithmetic followed by an
100 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
102 // Expand BRCOND into a BR_CC (see above).
103 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
105 // Handle integer types.
106 for (unsigned I = MVT::FIRST_INTEGER_VALUETYPE;
107 I <= MVT::LAST_INTEGER_VALUETYPE;
109 MVT VT = MVT::SimpleValueType(I);
110 if (isTypeLegal(VT)) {
111 // Expand individual DIV and REMs into DIVREMs.
112 setOperationAction(ISD::SDIV, VT, Expand);
113 setOperationAction(ISD::UDIV, VT, Expand);
114 setOperationAction(ISD::SREM, VT, Expand);
115 setOperationAction(ISD::UREM, VT, Expand);
116 setOperationAction(ISD::SDIVREM, VT, Custom);
117 setOperationAction(ISD::UDIVREM, VT, Custom);
119 // Expand ATOMIC_LOAD and ATOMIC_STORE using ATOMIC_CMP_SWAP.
120 // FIXME: probably much too conservative.
121 setOperationAction(ISD::ATOMIC_LOAD, VT, Expand);
122 setOperationAction(ISD::ATOMIC_STORE, VT, Expand);
124 // No special instructions for these.
125 setOperationAction(ISD::CTPOP, VT, Expand);
126 setOperationAction(ISD::CTTZ, VT, Expand);
127 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
128 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
129 setOperationAction(ISD::ROTR, VT, Expand);
131 // Use *MUL_LOHI where possible instead of MULH*.
132 setOperationAction(ISD::MULHS, VT, Expand);
133 setOperationAction(ISD::MULHU, VT, Expand);
134 setOperationAction(ISD::SMUL_LOHI, VT, Custom);
135 setOperationAction(ISD::UMUL_LOHI, VT, Custom);
137 // We have instructions for signed but not unsigned FP conversion.
138 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
142 // Type legalization will convert 8- and 16-bit atomic operations into
143 // forms that operate on i32s (but still keeping the original memory VT).
144 // Lower them into full i32 operations.
145 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Custom);
146 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Custom);
147 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom);
148 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Custom);
149 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Custom);
150 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Custom);
151 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Custom);
152 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Custom);
153 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Custom);
154 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Custom);
155 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Custom);
156 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
158 // We have instructions for signed but not unsigned FP conversion.
159 // Handle unsigned 32-bit types as signed 64-bit types.
160 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Promote);
161 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
163 // We have native support for a 64-bit CTLZ, via FLOGR.
164 setOperationAction(ISD::CTLZ, MVT::i32, Promote);
165 setOperationAction(ISD::CTLZ, MVT::i64, Legal);
167 // Give LowerOperation the chance to replace 64-bit ORs with subregs.
168 setOperationAction(ISD::OR, MVT::i64, Custom);
170 // FIXME: Can we support these natively?
171 setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand);
172 setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
173 setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand);
175 // We have native instructions for i8, i16 and i32 extensions, but not i1.
176 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
177 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
178 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
179 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
181 // Handle the various types of symbolic address.
182 setOperationAction(ISD::ConstantPool, PtrVT, Custom);
183 setOperationAction(ISD::GlobalAddress, PtrVT, Custom);
184 setOperationAction(ISD::GlobalTLSAddress, PtrVT, Custom);
185 setOperationAction(ISD::BlockAddress, PtrVT, Custom);
186 setOperationAction(ISD::JumpTable, PtrVT, Custom);
188 // We need to handle dynamic allocations specially because of the
189 // 160-byte area at the bottom of the stack.
190 setOperationAction(ISD::DYNAMIC_STACKALLOC, PtrVT, Custom);
192 // Use custom expanders so that we can force the function to use
194 setOperationAction(ISD::STACKSAVE, MVT::Other, Custom);
195 setOperationAction(ISD::STACKRESTORE, MVT::Other, Custom);
197 // Handle prefetches with PFD or PFDRL.
198 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
200 // Handle floating-point types.
201 for (unsigned I = MVT::FIRST_FP_VALUETYPE;
202 I <= MVT::LAST_FP_VALUETYPE;
204 MVT VT = MVT::SimpleValueType(I);
205 if (isTypeLegal(VT)) {
206 // We can use FI for FRINT.
207 setOperationAction(ISD::FRINT, VT, Legal);
209 // We can use the extended form of FI for other rounding operations.
210 if (Subtarget.hasFPExtension()) {
211 setOperationAction(ISD::FNEARBYINT, VT, Legal);
212 setOperationAction(ISD::FFLOOR, VT, Legal);
213 setOperationAction(ISD::FCEIL, VT, Legal);
214 setOperationAction(ISD::FTRUNC, VT, Legal);
215 setOperationAction(ISD::FROUND, VT, Legal);
218 // No special instructions for these.
219 setOperationAction(ISD::FSIN, VT, Expand);
220 setOperationAction(ISD::FCOS, VT, Expand);
221 setOperationAction(ISD::FREM, VT, Expand);
225 // We have fused multiply-addition for f32 and f64 but not f128.
226 setOperationAction(ISD::FMA, MVT::f32, Legal);
227 setOperationAction(ISD::FMA, MVT::f64, Legal);
228 setOperationAction(ISD::FMA, MVT::f128, Expand);
230 // Needed so that we don't try to implement f128 constant loads using
231 // a load-and-extend of a f80 constant (in cases where the constant
232 // would fit in an f80).
233 setLoadExtAction(ISD::EXTLOAD, MVT::f80, Expand);
235 // Floating-point truncation and stores need to be done separately.
236 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
237 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
238 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
240 // We have 64-bit FPR<->GPR moves, but need special handling for
242 setOperationAction(ISD::BITCAST, MVT::i32, Custom);
243 setOperationAction(ISD::BITCAST, MVT::f32, Custom);
245 // VASTART and VACOPY need to deal with the SystemZ-specific varargs
246 // structure, but VAEND is a no-op.
247 setOperationAction(ISD::VASTART, MVT::Other, Custom);
248 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
249 setOperationAction(ISD::VAEND, MVT::Other, Expand);
251 // We want to use MVC in preference to even a single load/store pair.
252 MaxStoresPerMemcpy = 0;
253 MaxStoresPerMemcpyOptSize = 0;
255 // The main memset sequence is a byte store followed by an MVC.
256 // Two STC or MV..I stores win over that, but the kind of fused stores
257 // generated by target-independent code don't when the byte value is
258 // variable. E.g. "STC <reg>;MHI <reg>,257;STH <reg>" is not better
259 // than "STC;MVC". Handle the choice in target-specific code instead.
260 MaxStoresPerMemset = 0;
261 MaxStoresPerMemsetOptSize = 0;
265 SystemZTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
266 VT = VT.getScalarType();
271 switch (VT.getSimpleVT().SimpleTy) {
284 bool SystemZTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
285 // We can load zero using LZ?R and negative zero using LZ?R;LC?BR.
286 return Imm.isZero() || Imm.isNegZero();
289 bool SystemZTargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
291 // Unaligned accesses should never be slower than the expanded version.
292 // We check specifically for aligned accesses in the few cases where
293 // they are required.
299 bool SystemZTargetLowering::isLegalAddressingMode(const AddrMode &AM,
301 // Punt on globals for now, although they can be used in limited
302 // RELATIVE LONG cases.
306 // Require a 20-bit signed offset.
307 if (!isInt<20>(AM.BaseOffs))
310 // Indexing is OK but no scale factor can be applied.
311 return AM.Scale == 0 || AM.Scale == 1;
314 bool SystemZTargetLowering::isTruncateFree(Type *FromType, Type *ToType) const {
315 if (!FromType->isIntegerTy() || !ToType->isIntegerTy())
317 unsigned FromBits = FromType->getPrimitiveSizeInBits();
318 unsigned ToBits = ToType->getPrimitiveSizeInBits();
319 return FromBits > ToBits;
322 bool SystemZTargetLowering::isTruncateFree(EVT FromVT, EVT ToVT) const {
323 if (!FromVT.isInteger() || !ToVT.isInteger())
325 unsigned FromBits = FromVT.getSizeInBits();
326 unsigned ToBits = ToVT.getSizeInBits();
327 return FromBits > ToBits;
330 //===----------------------------------------------------------------------===//
331 // Inline asm support
332 //===----------------------------------------------------------------------===//
334 TargetLowering::ConstraintType
335 SystemZTargetLowering::getConstraintType(const std::string &Constraint) const {
336 if (Constraint.size() == 1) {
337 switch (Constraint[0]) {
338 case 'a': // Address register
339 case 'd': // Data register (equivalent to 'r')
340 case 'f': // Floating-point register
341 case 'r': // General-purpose register
342 return C_RegisterClass;
344 case 'Q': // Memory with base and unsigned 12-bit displacement
345 case 'R': // Likewise, plus an index
346 case 'S': // Memory with base and signed 20-bit displacement
347 case 'T': // Likewise, plus an index
348 case 'm': // Equivalent to 'T'.
351 case 'I': // Unsigned 8-bit constant
352 case 'J': // Unsigned 12-bit constant
353 case 'K': // Signed 16-bit constant
354 case 'L': // Signed 20-bit displacement (on all targets we support)
355 case 'M': // 0x7fffffff
362 return TargetLowering::getConstraintType(Constraint);
365 TargetLowering::ConstraintWeight SystemZTargetLowering::
366 getSingleConstraintMatchWeight(AsmOperandInfo &info,
367 const char *constraint) const {
368 ConstraintWeight weight = CW_Invalid;
369 Value *CallOperandVal = info.CallOperandVal;
370 // If we don't have a value, we can't do a match,
371 // but allow it at the lowest weight.
372 if (CallOperandVal == NULL)
374 Type *type = CallOperandVal->getType();
375 // Look at the constraint type.
376 switch (*constraint) {
378 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
381 case 'a': // Address register
382 case 'd': // Data register (equivalent to 'r')
383 case 'r': // General-purpose register
384 if (CallOperandVal->getType()->isIntegerTy())
385 weight = CW_Register;
388 case 'f': // Floating-point register
389 if (type->isFloatingPointTy())
390 weight = CW_Register;
393 case 'I': // Unsigned 8-bit constant
394 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal))
395 if (isUInt<8>(C->getZExtValue()))
396 weight = CW_Constant;
399 case 'J': // Unsigned 12-bit constant
400 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal))
401 if (isUInt<12>(C->getZExtValue()))
402 weight = CW_Constant;
405 case 'K': // Signed 16-bit constant
406 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal))
407 if (isInt<16>(C->getSExtValue()))
408 weight = CW_Constant;
411 case 'L': // Signed 20-bit displacement (on all targets we support)
412 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal))
413 if (isInt<20>(C->getSExtValue()))
414 weight = CW_Constant;
417 case 'M': // 0x7fffffff
418 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal))
419 if (C->getZExtValue() == 0x7fffffff)
420 weight = CW_Constant;
426 // Parse a "{tNNN}" register constraint for which the register type "t"
427 // has already been verified. MC is the class associated with "t" and
428 // Map maps 0-based register numbers to LLVM register numbers.
429 static std::pair<unsigned, const TargetRegisterClass *>
430 parseRegisterNumber(const std::string &Constraint,
431 const TargetRegisterClass *RC, const unsigned *Map) {
432 assert(*(Constraint.end()-1) == '}' && "Missing '}'");
433 if (isdigit(Constraint[2])) {
434 std::string Suffix(Constraint.data() + 2, Constraint.size() - 2);
435 unsigned Index = atoi(Suffix.c_str());
436 if (Index < 16 && Map[Index])
437 return std::make_pair(Map[Index], RC);
439 return std::make_pair(0u, static_cast<TargetRegisterClass*>(0));
442 std::pair<unsigned, const TargetRegisterClass *> SystemZTargetLowering::
443 getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const {
444 if (Constraint.size() == 1) {
445 // GCC Constraint Letters
446 switch (Constraint[0]) {
448 case 'd': // Data register (equivalent to 'r')
449 case 'r': // General-purpose register
451 return std::make_pair(0U, &SystemZ::GR64BitRegClass);
452 else if (VT == MVT::i128)
453 return std::make_pair(0U, &SystemZ::GR128BitRegClass);
454 return std::make_pair(0U, &SystemZ::GR32BitRegClass);
456 case 'a': // Address register
458 return std::make_pair(0U, &SystemZ::ADDR64BitRegClass);
459 else if (VT == MVT::i128)
460 return std::make_pair(0U, &SystemZ::ADDR128BitRegClass);
461 return std::make_pair(0U, &SystemZ::ADDR32BitRegClass);
463 case 'f': // Floating-point register
465 return std::make_pair(0U, &SystemZ::FP64BitRegClass);
466 else if (VT == MVT::f128)
467 return std::make_pair(0U, &SystemZ::FP128BitRegClass);
468 return std::make_pair(0U, &SystemZ::FP32BitRegClass);
471 if (Constraint[0] == '{') {
472 // We need to override the default register parsing for GPRs and FPRs
473 // because the interpretation depends on VT. The internal names of
474 // the registers are also different from the external names
475 // (F0D and F0S instead of F0, etc.).
476 if (Constraint[1] == 'r') {
478 return parseRegisterNumber(Constraint, &SystemZ::GR32BitRegClass,
479 SystemZMC::GR32Regs);
481 return parseRegisterNumber(Constraint, &SystemZ::GR128BitRegClass,
482 SystemZMC::GR128Regs);
483 return parseRegisterNumber(Constraint, &SystemZ::GR64BitRegClass,
484 SystemZMC::GR64Regs);
486 if (Constraint[1] == 'f') {
488 return parseRegisterNumber(Constraint, &SystemZ::FP32BitRegClass,
489 SystemZMC::FP32Regs);
491 return parseRegisterNumber(Constraint, &SystemZ::FP128BitRegClass,
492 SystemZMC::FP128Regs);
493 return parseRegisterNumber(Constraint, &SystemZ::FP64BitRegClass,
494 SystemZMC::FP64Regs);
497 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
500 void SystemZTargetLowering::
501 LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
502 std::vector<SDValue> &Ops,
503 SelectionDAG &DAG) const {
504 // Only support length 1 constraints for now.
505 if (Constraint.length() == 1) {
506 switch (Constraint[0]) {
507 case 'I': // Unsigned 8-bit constant
508 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
509 if (isUInt<8>(C->getZExtValue()))
510 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(),
514 case 'J': // Unsigned 12-bit constant
515 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
516 if (isUInt<12>(C->getZExtValue()))
517 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(),
521 case 'K': // Signed 16-bit constant
522 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
523 if (isInt<16>(C->getSExtValue()))
524 Ops.push_back(DAG.getTargetConstant(C->getSExtValue(),
528 case 'L': // Signed 20-bit displacement (on all targets we support)
529 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
530 if (isInt<20>(C->getSExtValue()))
531 Ops.push_back(DAG.getTargetConstant(C->getSExtValue(),
535 case 'M': // 0x7fffffff
536 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
537 if (C->getZExtValue() == 0x7fffffff)
538 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(),
543 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
546 //===----------------------------------------------------------------------===//
547 // Calling conventions
548 //===----------------------------------------------------------------------===//
550 #include "SystemZGenCallingConv.inc"
552 bool SystemZTargetLowering::allowTruncateForTailCall(Type *FromType,
553 Type *ToType) const {
554 return isTruncateFree(FromType, ToType);
557 bool SystemZTargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
558 if (!CI->isTailCall())
563 // Value is a value that has been passed to us in the location described by VA
564 // (and so has type VA.getLocVT()). Convert Value to VA.getValVT(), chaining
565 // any loads onto Chain.
566 static SDValue convertLocVTToValVT(SelectionDAG &DAG, SDLoc DL,
567 CCValAssign &VA, SDValue Chain,
569 // If the argument has been promoted from a smaller type, insert an
570 // assertion to capture this.
571 if (VA.getLocInfo() == CCValAssign::SExt)
572 Value = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Value,
573 DAG.getValueType(VA.getValVT()));
574 else if (VA.getLocInfo() == CCValAssign::ZExt)
575 Value = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Value,
576 DAG.getValueType(VA.getValVT()));
579 Value = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Value);
580 else if (VA.getLocInfo() == CCValAssign::Indirect)
581 Value = DAG.getLoad(VA.getValVT(), DL, Chain, Value,
582 MachinePointerInfo(), false, false, false, 0);
584 assert(VA.getLocInfo() == CCValAssign::Full && "Unsupported getLocInfo");
588 // Value is a value of type VA.getValVT() that we need to copy into
589 // the location described by VA. Return a copy of Value converted to
590 // VA.getValVT(). The caller is responsible for handling indirect values.
591 static SDValue convertValVTToLocVT(SelectionDAG &DAG, SDLoc DL,
592 CCValAssign &VA, SDValue Value) {
593 switch (VA.getLocInfo()) {
594 case CCValAssign::SExt:
595 return DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Value);
596 case CCValAssign::ZExt:
597 return DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Value);
598 case CCValAssign::AExt:
599 return DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Value);
600 case CCValAssign::Full:
603 llvm_unreachable("Unhandled getLocInfo()");
607 SDValue SystemZTargetLowering::
608 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
609 const SmallVectorImpl<ISD::InputArg> &Ins,
610 SDLoc DL, SelectionDAG &DAG,
611 SmallVectorImpl<SDValue> &InVals) const {
612 MachineFunction &MF = DAG.getMachineFunction();
613 MachineFrameInfo *MFI = MF.getFrameInfo();
614 MachineRegisterInfo &MRI = MF.getRegInfo();
615 SystemZMachineFunctionInfo *FuncInfo =
616 MF.getInfo<SystemZMachineFunctionInfo>();
617 const SystemZFrameLowering *TFL =
618 static_cast<const SystemZFrameLowering *>(TM.getFrameLowering());
620 // Assign locations to all of the incoming arguments.
621 SmallVector<CCValAssign, 16> ArgLocs;
622 CCState CCInfo(CallConv, IsVarArg, MF, TM, ArgLocs, *DAG.getContext());
623 CCInfo.AnalyzeFormalArguments(Ins, CC_SystemZ);
625 unsigned NumFixedGPRs = 0;
626 unsigned NumFixedFPRs = 0;
627 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
629 CCValAssign &VA = ArgLocs[I];
630 EVT LocVT = VA.getLocVT();
632 // Arguments passed in registers
633 const TargetRegisterClass *RC;
634 switch (LocVT.getSimpleVT().SimpleTy) {
636 // Integers smaller than i64 should be promoted to i64.
637 llvm_unreachable("Unexpected argument type");
640 RC = &SystemZ::GR32BitRegClass;
644 RC = &SystemZ::GR64BitRegClass;
648 RC = &SystemZ::FP32BitRegClass;
652 RC = &SystemZ::FP64BitRegClass;
656 unsigned VReg = MRI.createVirtualRegister(RC);
657 MRI.addLiveIn(VA.getLocReg(), VReg);
658 ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, LocVT);
660 assert(VA.isMemLoc() && "Argument not register or memory");
662 // Create the frame index object for this incoming parameter.
663 int FI = MFI->CreateFixedObject(LocVT.getSizeInBits() / 8,
664 VA.getLocMemOffset(), true);
666 // Create the SelectionDAG nodes corresponding to a load
667 // from this parameter. Unpromoted ints and floats are
668 // passed as right-justified 8-byte values.
669 EVT PtrVT = getPointerTy();
670 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
671 if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32)
672 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4));
673 ArgValue = DAG.getLoad(LocVT, DL, Chain, FIN,
674 MachinePointerInfo::getFixedStack(FI),
675 false, false, false, 0);
678 // Convert the value of the argument register into the value that's
680 InVals.push_back(convertLocVTToValVT(DAG, DL, VA, Chain, ArgValue));
684 // Save the number of non-varargs registers for later use by va_start, etc.
685 FuncInfo->setVarArgsFirstGPR(NumFixedGPRs);
686 FuncInfo->setVarArgsFirstFPR(NumFixedFPRs);
688 // Likewise the address (in the form of a frame index) of where the
689 // first stack vararg would be. The 1-byte size here is arbitrary.
690 int64_t StackSize = CCInfo.getNextStackOffset();
691 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize, true));
693 // ...and a similar frame index for the caller-allocated save area
694 // that will be used to store the incoming registers.
695 int64_t RegSaveOffset = TFL->getOffsetOfLocalArea();
696 unsigned RegSaveIndex = MFI->CreateFixedObject(1, RegSaveOffset, true);
697 FuncInfo->setRegSaveFrameIndex(RegSaveIndex);
699 // Store the FPR varargs in the reserved frame slots. (We store the
700 // GPRs as part of the prologue.)
701 if (NumFixedFPRs < SystemZ::NumArgFPRs) {
702 SDValue MemOps[SystemZ::NumArgFPRs];
703 for (unsigned I = NumFixedFPRs; I < SystemZ::NumArgFPRs; ++I) {
704 unsigned Offset = TFL->getRegSpillOffset(SystemZ::ArgFPRs[I]);
705 int FI = MFI->CreateFixedObject(8, RegSaveOffset + Offset, true);
706 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
707 unsigned VReg = MF.addLiveIn(SystemZ::ArgFPRs[I],
708 &SystemZ::FP64BitRegClass);
709 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f64);
710 MemOps[I] = DAG.getStore(ArgValue.getValue(1), DL, ArgValue, FIN,
711 MachinePointerInfo::getFixedStack(FI),
715 // Join the stores, which are independent of one another.
716 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
717 &MemOps[NumFixedFPRs],
718 SystemZ::NumArgFPRs - NumFixedFPRs);
725 static bool canUseSiblingCall(CCState ArgCCInfo,
726 SmallVectorImpl<CCValAssign> &ArgLocs) {
727 // Punt if there are any indirect or stack arguments, or if the call
728 // needs the call-saved argument register R6.
729 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
730 CCValAssign &VA = ArgLocs[I];
731 if (VA.getLocInfo() == CCValAssign::Indirect)
735 unsigned Reg = VA.getLocReg();
736 if (Reg == SystemZ::R6W || Reg == SystemZ::R6D)
743 SystemZTargetLowering::LowerCall(CallLoweringInfo &CLI,
744 SmallVectorImpl<SDValue> &InVals) const {
745 SelectionDAG &DAG = CLI.DAG;
747 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
748 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
749 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
750 SDValue Chain = CLI.Chain;
751 SDValue Callee = CLI.Callee;
752 bool &IsTailCall = CLI.IsTailCall;
753 CallingConv::ID CallConv = CLI.CallConv;
754 bool IsVarArg = CLI.IsVarArg;
755 MachineFunction &MF = DAG.getMachineFunction();
756 EVT PtrVT = getPointerTy();
758 // Analyze the operands of the call, assigning locations to each operand.
759 SmallVector<CCValAssign, 16> ArgLocs;
760 CCState ArgCCInfo(CallConv, IsVarArg, MF, TM, ArgLocs, *DAG.getContext());
761 ArgCCInfo.AnalyzeCallOperands(Outs, CC_SystemZ);
763 // We don't support GuaranteedTailCallOpt, only automatically-detected
765 if (IsTailCall && !canUseSiblingCall(ArgCCInfo, ArgLocs))
768 // Get a count of how many bytes are to be pushed on the stack.
769 unsigned NumBytes = ArgCCInfo.getNextStackOffset();
771 // Mark the start of the call.
773 Chain = DAG.getCALLSEQ_START(Chain, DAG.getConstant(NumBytes, PtrVT, true),
776 // Copy argument values to their designated locations.
777 SmallVector<std::pair<unsigned, SDValue>, 9> RegsToPass;
778 SmallVector<SDValue, 8> MemOpChains;
780 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
781 CCValAssign &VA = ArgLocs[I];
782 SDValue ArgValue = OutVals[I];
784 if (VA.getLocInfo() == CCValAssign::Indirect) {
785 // Store the argument in a stack slot and pass its address.
786 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
787 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
788 MemOpChains.push_back(DAG.getStore(Chain, DL, ArgValue, SpillSlot,
789 MachinePointerInfo::getFixedStack(FI),
791 ArgValue = SpillSlot;
793 ArgValue = convertValVTToLocVT(DAG, DL, VA, ArgValue);
796 // Queue up the argument copies and emit them at the end.
797 RegsToPass.push_back(std::make_pair(VA.getLocReg(), ArgValue));
799 assert(VA.isMemLoc() && "Argument not register or memory");
801 // Work out the address of the stack slot. Unpromoted ints and
802 // floats are passed as right-justified 8-byte values.
803 if (!StackPtr.getNode())
804 StackPtr = DAG.getCopyFromReg(Chain, DL, SystemZ::R15D, PtrVT);
805 unsigned Offset = SystemZMC::CallFrameSize + VA.getLocMemOffset();
806 if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32)
808 SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr,
809 DAG.getIntPtrConstant(Offset));
812 MemOpChains.push_back(DAG.getStore(Chain, DL, ArgValue, Address,
813 MachinePointerInfo(),
818 // Join the stores, which are independent of one another.
819 if (!MemOpChains.empty())
820 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
821 &MemOpChains[0], MemOpChains.size());
823 // Accept direct calls by converting symbolic call addresses to the
824 // associated Target* opcodes. Force %r1 to be used for indirect
827 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
828 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, PtrVT);
829 Callee = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Callee);
830 } else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) {
831 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), PtrVT);
832 Callee = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Callee);
833 } else if (IsTailCall) {
834 Chain = DAG.getCopyToReg(Chain, DL, SystemZ::R1D, Callee, Glue);
835 Glue = Chain.getValue(1);
836 Callee = DAG.getRegister(SystemZ::R1D, Callee.getValueType());
839 // Build a sequence of copy-to-reg nodes, chained and glued together.
840 for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I) {
841 Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[I].first,
842 RegsToPass[I].second, Glue);
843 Glue = Chain.getValue(1);
846 // The first call operand is the chain and the second is the target address.
847 SmallVector<SDValue, 8> Ops;
848 Ops.push_back(Chain);
849 Ops.push_back(Callee);
851 // Add argument registers to the end of the list so that they are
852 // known live into the call.
853 for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I)
854 Ops.push_back(DAG.getRegister(RegsToPass[I].first,
855 RegsToPass[I].second.getValueType()));
857 // Glue the call to the argument copies, if any.
862 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
864 return DAG.getNode(SystemZISD::SIBCALL, DL, NodeTys, &Ops[0], Ops.size());
865 Chain = DAG.getNode(SystemZISD::CALL, DL, NodeTys, &Ops[0], Ops.size());
866 Glue = Chain.getValue(1);
868 // Mark the end of the call, which is glued to the call itself.
869 Chain = DAG.getCALLSEQ_END(Chain,
870 DAG.getConstant(NumBytes, PtrVT, true),
871 DAG.getConstant(0, PtrVT, true),
873 Glue = Chain.getValue(1);
875 // Assign locations to each value returned by this call.
876 SmallVector<CCValAssign, 16> RetLocs;
877 CCState RetCCInfo(CallConv, IsVarArg, MF, TM, RetLocs, *DAG.getContext());
878 RetCCInfo.AnalyzeCallResult(Ins, RetCC_SystemZ);
880 // Copy all of the result registers out of their specified physreg.
881 for (unsigned I = 0, E = RetLocs.size(); I != E; ++I) {
882 CCValAssign &VA = RetLocs[I];
884 // Copy the value out, gluing the copy to the end of the call sequence.
885 SDValue RetValue = DAG.getCopyFromReg(Chain, DL, VA.getLocReg(),
886 VA.getLocVT(), Glue);
887 Chain = RetValue.getValue(1);
888 Glue = RetValue.getValue(2);
890 // Convert the value of the return register into the value that's
892 InVals.push_back(convertLocVTToValVT(DAG, DL, VA, Chain, RetValue));
899 SystemZTargetLowering::LowerReturn(SDValue Chain,
900 CallingConv::ID CallConv, bool IsVarArg,
901 const SmallVectorImpl<ISD::OutputArg> &Outs,
902 const SmallVectorImpl<SDValue> &OutVals,
903 SDLoc DL, SelectionDAG &DAG) const {
904 MachineFunction &MF = DAG.getMachineFunction();
906 // Assign locations to each returned value.
907 SmallVector<CCValAssign, 16> RetLocs;
908 CCState RetCCInfo(CallConv, IsVarArg, MF, TM, RetLocs, *DAG.getContext());
909 RetCCInfo.AnalyzeReturn(Outs, RetCC_SystemZ);
911 // Quick exit for void returns
913 return DAG.getNode(SystemZISD::RET_FLAG, DL, MVT::Other, Chain);
915 // Copy the result values into the output registers.
917 SmallVector<SDValue, 4> RetOps;
918 RetOps.push_back(Chain);
919 for (unsigned I = 0, E = RetLocs.size(); I != E; ++I) {
920 CCValAssign &VA = RetLocs[I];
921 SDValue RetValue = OutVals[I];
923 // Make the return register live on exit.
924 assert(VA.isRegLoc() && "Can only return in registers!");
926 // Promote the value as required.
927 RetValue = convertValVTToLocVT(DAG, DL, VA, RetValue);
929 // Chain and glue the copies together.
930 unsigned Reg = VA.getLocReg();
931 Chain = DAG.getCopyToReg(Chain, DL, Reg, RetValue, Glue);
932 Glue = Chain.getValue(1);
933 RetOps.push_back(DAG.getRegister(Reg, VA.getLocVT()));
936 // Update chain and glue.
939 RetOps.push_back(Glue);
941 return DAG.getNode(SystemZISD::RET_FLAG, DL, MVT::Other,
942 RetOps.data(), RetOps.size());
945 // CC is a comparison that will be implemented using an integer or
946 // floating-point comparison. Return the condition code mask for
947 // a branch on true. In the integer case, CCMASK_CMP_UO is set for
948 // unsigned comparisons and clear for signed ones. In the floating-point
949 // case, CCMASK_CMP_UO has its normal mask meaning (unordered).
950 static unsigned CCMaskForCondCode(ISD::CondCode CC) {
952 case ISD::SET##X: return SystemZ::CCMASK_CMP_##X; \
953 case ISD::SETO##X: return SystemZ::CCMASK_CMP_##X; \
954 case ISD::SETU##X: return SystemZ::CCMASK_CMP_UO | SystemZ::CCMASK_CMP_##X
958 llvm_unreachable("Invalid integer condition!");
967 case ISD::SETO: return SystemZ::CCMASK_CMP_O;
968 case ISD::SETUO: return SystemZ::CCMASK_CMP_UO;
973 // If a comparison described by IsUnsigned, CCMask, CmpOp0 and CmpOp1
974 // can be converted to a comparison against zero, adjust the operands
976 static void adjustZeroCmp(SelectionDAG &DAG, bool &IsUnsigned,
977 SDValue &CmpOp0, SDValue &CmpOp1,
982 ConstantSDNode *ConstOp1 = dyn_cast<ConstantSDNode>(CmpOp1.getNode());
986 int64_t Value = ConstOp1->getSExtValue();
987 if ((Value == -1 && CCMask == SystemZ::CCMASK_CMP_GT) ||
988 (Value == -1 && CCMask == SystemZ::CCMASK_CMP_LE) ||
989 (Value == 1 && CCMask == SystemZ::CCMASK_CMP_LT) ||
990 (Value == 1 && CCMask == SystemZ::CCMASK_CMP_GE)) {
991 CCMask ^= SystemZ::CCMASK_CMP_EQ;
992 CmpOp1 = DAG.getConstant(0, CmpOp1.getValueType());
996 // If a comparison described by IsUnsigned, CCMask, CmpOp0 and CmpOp1
997 // is suitable for CLI(Y), CHHSI or CLHHSI, adjust the operands as necessary.
998 static void adjustSubwordCmp(SelectionDAG &DAG, bool &IsUnsigned,
999 SDValue &CmpOp0, SDValue &CmpOp1,
1001 // For us to make any changes, it must a comparison between a single-use
1002 // load and a constant.
1003 if (!CmpOp0.hasOneUse() ||
1004 CmpOp0.getOpcode() != ISD::LOAD ||
1005 CmpOp1.getOpcode() != ISD::Constant)
1008 // We must have an 8- or 16-bit load.
1009 LoadSDNode *Load = cast<LoadSDNode>(CmpOp0);
1010 unsigned NumBits = Load->getMemoryVT().getStoreSizeInBits();
1011 if (NumBits != 8 && NumBits != 16)
1014 // The load must be an extending one and the constant must be within the
1015 // range of the unextended value.
1016 ConstantSDNode *Constant = cast<ConstantSDNode>(CmpOp1);
1017 uint64_t Value = Constant->getZExtValue();
1018 uint64_t Mask = (1 << NumBits) - 1;
1019 if (Load->getExtensionType() == ISD::SEXTLOAD) {
1020 int64_t SignedValue = Constant->getSExtValue();
1021 if (uint64_t(SignedValue) + (1ULL << (NumBits - 1)) > Mask)
1023 // Unsigned comparison between two sign-extended values is equivalent
1024 // to unsigned comparison between two zero-extended values.
1027 else if (CCMask == SystemZ::CCMASK_CMP_EQ ||
1028 CCMask == SystemZ::CCMASK_CMP_NE)
1029 // Any choice of IsUnsigned is OK for equality comparisons.
1030 // We could use either CHHSI or CLHHSI for 16-bit comparisons,
1031 // but since we use CLHHSI for zero extensions, it seems better
1032 // to be consistent and do the same here.
1033 Value &= Mask, IsUnsigned = true;
1034 else if (NumBits == 8) {
1035 // Try to treat the comparison as unsigned, so that we can use CLI.
1036 // Adjust CCMask and Value as necessary.
1037 if (Value == 0 && CCMask == SystemZ::CCMASK_CMP_LT)
1038 // Test whether the high bit of the byte is set.
1039 Value = 127, CCMask = SystemZ::CCMASK_CMP_GT, IsUnsigned = true;
1040 else if (Value == 0 && CCMask == SystemZ::CCMASK_CMP_GE)
1041 // Test whether the high bit of the byte is clear.
1042 Value = 128, CCMask = SystemZ::CCMASK_CMP_LT, IsUnsigned = true;
1044 // No instruction exists for this combination.
1047 } else if (Load->getExtensionType() == ISD::ZEXTLOAD) {
1050 // Signed comparison between two zero-extended values is equivalent
1051 // to unsigned comparison.
1056 // Make sure that the first operand is an i32 of the right extension type.
1057 ISD::LoadExtType ExtType = IsUnsigned ? ISD::ZEXTLOAD : ISD::SEXTLOAD;
1058 if (CmpOp0.getValueType() != MVT::i32 ||
1059 Load->getExtensionType() != ExtType)
1060 CmpOp0 = DAG.getExtLoad(ExtType, SDLoc(Load), MVT::i32,
1061 Load->getChain(), Load->getBasePtr(),
1062 Load->getPointerInfo(), Load->getMemoryVT(),
1063 Load->isVolatile(), Load->isNonTemporal(),
1064 Load->getAlignment());
1066 // Make sure that the second operand is an i32 with the right value.
1067 if (CmpOp1.getValueType() != MVT::i32 ||
1068 Value != Constant->getZExtValue())
1069 CmpOp1 = DAG.getConstant(Value, MVT::i32);
1072 // Return true if a comparison described by CCMask, CmpOp0 and CmpOp1
1073 // is an equality comparison that is better implemented using unsigned
1074 // rather than signed comparison instructions.
1075 static bool preferUnsignedComparison(SelectionDAG &DAG, SDValue CmpOp0,
1076 SDValue CmpOp1, unsigned CCMask) {
1077 // The test must be for equality or inequality.
1078 if (CCMask != SystemZ::CCMASK_CMP_EQ && CCMask != SystemZ::CCMASK_CMP_NE)
1081 if (CmpOp1.getOpcode() == ISD::Constant) {
1082 uint64_t Value = cast<ConstantSDNode>(CmpOp1)->getSExtValue();
1084 // If we're comparing with memory, prefer unsigned comparisons for
1085 // values that are in the unsigned 16-bit range but not the signed
1086 // 16-bit range. We want to use CLFHSI and CLGHSI.
1087 if (CmpOp0.hasOneUse() &&
1088 ISD::isNormalLoad(CmpOp0.getNode()) &&
1089 (Value >= 32768 && Value < 65536))
1092 // Use unsigned comparisons for values that are in the CLGFI range
1093 // but not in the CGFI range.
1094 if (CmpOp0.getValueType() == MVT::i64 && (Value >> 31) == 1)
1100 // Prefer CL for zero-extended loads.
1101 if (CmpOp1.getOpcode() == ISD::ZERO_EXTEND ||
1102 ISD::isZEXTLoad(CmpOp1.getNode()))
1105 // ...and for "in-register" zero extensions.
1106 if (CmpOp1.getOpcode() == ISD::AND && CmpOp1.getValueType() == MVT::i64) {
1107 SDValue Mask = CmpOp1.getOperand(1);
1108 if (Mask.getOpcode() == ISD::Constant &&
1109 cast<ConstantSDNode>(Mask)->getZExtValue() == 0xffffffff)
1116 // Return true if Op is either an unextended load, or a load with the
1117 // extension type given by IsUnsigned.
1118 static bool isNaturalMemoryOperand(SDValue Op, bool IsUnsigned) {
1119 LoadSDNode *Load = dyn_cast<LoadSDNode>(Op.getNode());
1121 switch (Load->getExtensionType()) {
1122 case ISD::NON_EXTLOAD:
1135 // Return true if it is better to swap comparison operands Op0 and Op1.
1136 // IsUnsigned says whether an integer comparison is signed or unsigned.
1137 static bool shouldSwapCmpOperands(SDValue Op0, SDValue Op1,
1139 // Leave f128 comparisons alone, since they have no memory forms.
1140 if (Op0.getValueType() == MVT::f128)
1143 // Always keep a floating-point constant second, since comparisons with
1144 // zero can use LOAD TEST and comparisons with other constants make a
1145 // natural memory operand.
1146 if (isa<ConstantFPSDNode>(Op1))
1149 // Never swap comparisons with zero since there are many ways to optimize
1151 ConstantSDNode *COp1 = dyn_cast<ConstantSDNode>(Op1);
1152 if (COp1 && COp1->getZExtValue() == 0)
1155 // Look for cases where Cmp0 is a single-use load and Cmp1 isn't.
1156 // In that case we generally prefer the memory to be second.
1157 if ((isNaturalMemoryOperand(Op0, IsUnsigned) && Op0.hasOneUse()) &&
1158 !(isNaturalMemoryOperand(Op1, IsUnsigned) && Op1.hasOneUse())) {
1159 // The only exceptions are when the second operand is a constant and
1160 // we can use things like CHHSI.
1164 // The memory-immediate instructions require 16-bit unsigned integers.
1165 if (isUInt<16>(COp1->getZExtValue()))
1168 // There are no comparisons between integers and signed memory bytes.
1169 // The others require 16-bit signed integers.
1170 if (cast<LoadSDNode>(Op0.getNode())->getMemoryVT() == MVT::i8 ||
1171 isInt<16>(COp1->getSExtValue()))
1179 // Return a target node that compares CmpOp0 with CmpOp1 and stores a
1180 // 2-bit result in CC. Set CCValid to the CCMASK_* of all possible
1181 // 2-bit results and CCMask to the subset of those results that are
1182 // associated with Cond.
1183 static SDValue emitCmp(SelectionDAG &DAG, SDValue CmpOp0, SDValue CmpOp1,
1184 ISD::CondCode Cond, unsigned &CCValid,
1186 bool IsUnsigned = false;
1187 CCMask = CCMaskForCondCode(Cond);
1188 if (CmpOp0.getValueType().isFloatingPoint())
1189 CCValid = SystemZ::CCMASK_FCMP;
1191 IsUnsigned = CCMask & SystemZ::CCMASK_CMP_UO;
1192 CCValid = SystemZ::CCMASK_ICMP;
1194 adjustZeroCmp(DAG, IsUnsigned, CmpOp0, CmpOp1, CCMask);
1195 adjustSubwordCmp(DAG, IsUnsigned, CmpOp0, CmpOp1, CCMask);
1196 if (preferUnsignedComparison(DAG, CmpOp0, CmpOp1, CCMask))
1200 if (shouldSwapCmpOperands(CmpOp0, CmpOp1, IsUnsigned)) {
1201 std::swap(CmpOp0, CmpOp1);
1202 CCMask = ((CCMask & SystemZ::CCMASK_CMP_EQ) |
1203 (CCMask & SystemZ::CCMASK_CMP_GT ? SystemZ::CCMASK_CMP_LT : 0) |
1204 (CCMask & SystemZ::CCMASK_CMP_LT ? SystemZ::CCMASK_CMP_GT : 0) |
1205 (CCMask & SystemZ::CCMASK_CMP_UO));
1209 return DAG.getNode((IsUnsigned ? SystemZISD::UCMP : SystemZISD::CMP),
1210 DL, MVT::Glue, CmpOp0, CmpOp1);
1213 // Implement a 32-bit *MUL_LOHI operation by extending both operands to
1214 // 64 bits. Extend is the extension type to use. Store the high part
1215 // in Hi and the low part in Lo.
1216 static void lowerMUL_LOHI32(SelectionDAG &DAG, SDLoc DL,
1217 unsigned Extend, SDValue Op0, SDValue Op1,
1218 SDValue &Hi, SDValue &Lo) {
1219 Op0 = DAG.getNode(Extend, DL, MVT::i64, Op0);
1220 Op1 = DAG.getNode(Extend, DL, MVT::i64, Op1);
1221 SDValue Mul = DAG.getNode(ISD::MUL, DL, MVT::i64, Op0, Op1);
1222 Hi = DAG.getNode(ISD::SRL, DL, MVT::i64, Mul, DAG.getConstant(32, MVT::i64));
1223 Hi = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Hi);
1224 Lo = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mul);
1227 // Lower a binary operation that produces two VT results, one in each
1228 // half of a GR128 pair. Op0 and Op1 are the VT operands to the operation,
1229 // Extend extends Op0 to a GR128, and Opcode performs the GR128 operation
1230 // on the extended Op0 and (unextended) Op1. Store the even register result
1231 // in Even and the odd register result in Odd.
1232 static void lowerGR128Binary(SelectionDAG &DAG, SDLoc DL, EVT VT,
1233 unsigned Extend, unsigned Opcode,
1234 SDValue Op0, SDValue Op1,
1235 SDValue &Even, SDValue &Odd) {
1236 SDNode *In128 = DAG.getMachineNode(Extend, DL, MVT::Untyped, Op0);
1237 SDValue Result = DAG.getNode(Opcode, DL, MVT::Untyped,
1238 SDValue(In128, 0), Op1);
1239 bool Is32Bit = is32Bit(VT);
1240 SDValue SubReg0 = DAG.getTargetConstant(SystemZ::even128(Is32Bit), VT);
1241 SDValue SubReg1 = DAG.getTargetConstant(SystemZ::odd128(Is32Bit), VT);
1242 SDNode *Reg0 = DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL,
1243 VT, Result, SubReg0);
1244 SDNode *Reg1 = DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL,
1245 VT, Result, SubReg1);
1246 Even = SDValue(Reg0, 0);
1247 Odd = SDValue(Reg1, 0);
1250 SDValue SystemZTargetLowering::lowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
1251 SDValue Chain = Op.getOperand(0);
1252 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
1253 SDValue CmpOp0 = Op.getOperand(2);
1254 SDValue CmpOp1 = Op.getOperand(3);
1255 SDValue Dest = Op.getOperand(4);
1258 unsigned CCValid, CCMask;
1259 SDValue Flags = emitCmp(DAG, CmpOp0, CmpOp1, CC, CCValid, CCMask);
1260 return DAG.getNode(SystemZISD::BR_CCMASK, DL, Op.getValueType(),
1261 Chain, DAG.getConstant(CCValid, MVT::i32),
1262 DAG.getConstant(CCMask, MVT::i32), Dest, Flags);
1265 SDValue SystemZTargetLowering::lowerSELECT_CC(SDValue Op,
1266 SelectionDAG &DAG) const {
1267 SDValue CmpOp0 = Op.getOperand(0);
1268 SDValue CmpOp1 = Op.getOperand(1);
1269 SDValue TrueOp = Op.getOperand(2);
1270 SDValue FalseOp = Op.getOperand(3);
1271 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1274 unsigned CCValid, CCMask;
1275 SDValue Flags = emitCmp(DAG, CmpOp0, CmpOp1, CC, CCValid, CCMask);
1277 SmallVector<SDValue, 5> Ops;
1278 Ops.push_back(TrueOp);
1279 Ops.push_back(FalseOp);
1280 Ops.push_back(DAG.getConstant(CCValid, MVT::i32));
1281 Ops.push_back(DAG.getConstant(CCMask, MVT::i32));
1282 Ops.push_back(Flags);
1284 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
1285 return DAG.getNode(SystemZISD::SELECT_CCMASK, DL, VTs, &Ops[0], Ops.size());
1288 SDValue SystemZTargetLowering::lowerGlobalAddress(GlobalAddressSDNode *Node,
1289 SelectionDAG &DAG) const {
1291 const GlobalValue *GV = Node->getGlobal();
1292 int64_t Offset = Node->getOffset();
1293 EVT PtrVT = getPointerTy();
1294 Reloc::Model RM = TM.getRelocationModel();
1295 CodeModel::Model CM = TM.getCodeModel();
1298 if (Subtarget.isPC32DBLSymbol(GV, RM, CM)) {
1299 // Make sure that the offset is aligned to a halfword. If it isn't,
1300 // create an "anchor" at the previous 12-bit boundary.
1301 // FIXME check whether there is a better way of handling this.
1303 Result = DAG.getTargetGlobalAddress(GV, DL, PtrVT,
1304 Offset & ~uint64_t(0xfff));
1307 Result = DAG.getTargetGlobalAddress(GV, DL, PtrVT, Offset);
1310 Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
1312 Result = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, SystemZII::MO_GOT);
1313 Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
1314 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
1315 MachinePointerInfo::getGOT(), false, false, false, 0);
1318 // If there was a non-zero offset that we didn't fold, create an explicit
1321 Result = DAG.getNode(ISD::ADD, DL, PtrVT, Result,
1322 DAG.getConstant(Offset, PtrVT));
1327 SDValue SystemZTargetLowering::lowerGlobalTLSAddress(GlobalAddressSDNode *Node,
1328 SelectionDAG &DAG) const {
1330 const GlobalValue *GV = Node->getGlobal();
1331 EVT PtrVT = getPointerTy();
1332 TLSModel::Model model = TM.getTLSModel(GV);
1334 if (model != TLSModel::LocalExec)
1335 llvm_unreachable("only local-exec TLS mode supported");
1337 // The high part of the thread pointer is in access register 0.
1338 SDValue TPHi = DAG.getNode(SystemZISD::EXTRACT_ACCESS, DL, MVT::i32,
1339 DAG.getConstant(0, MVT::i32));
1340 TPHi = DAG.getNode(ISD::ANY_EXTEND, DL, PtrVT, TPHi);
1342 // The low part of the thread pointer is in access register 1.
1343 SDValue TPLo = DAG.getNode(SystemZISD::EXTRACT_ACCESS, DL, MVT::i32,
1344 DAG.getConstant(1, MVT::i32));
1345 TPLo = DAG.getNode(ISD::ZERO_EXTEND, DL, PtrVT, TPLo);
1347 // Merge them into a single 64-bit address.
1348 SDValue TPHiShifted = DAG.getNode(ISD::SHL, DL, PtrVT, TPHi,
1349 DAG.getConstant(32, PtrVT));
1350 SDValue TP = DAG.getNode(ISD::OR, DL, PtrVT, TPHiShifted, TPLo);
1352 // Get the offset of GA from the thread pointer.
1353 SystemZConstantPoolValue *CPV =
1354 SystemZConstantPoolValue::Create(GV, SystemZCP::NTPOFF);
1356 // Force the offset into the constant pool and load it from there.
1357 SDValue CPAddr = DAG.getConstantPool(CPV, PtrVT, 8);
1358 SDValue Offset = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(),
1359 CPAddr, MachinePointerInfo::getConstantPool(),
1360 false, false, false, 0);
1362 // Add the base and offset together.
1363 return DAG.getNode(ISD::ADD, DL, PtrVT, TP, Offset);
1366 SDValue SystemZTargetLowering::lowerBlockAddress(BlockAddressSDNode *Node,
1367 SelectionDAG &DAG) const {
1369 const BlockAddress *BA = Node->getBlockAddress();
1370 int64_t Offset = Node->getOffset();
1371 EVT PtrVT = getPointerTy();
1373 SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT, Offset);
1374 Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
1378 SDValue SystemZTargetLowering::lowerJumpTable(JumpTableSDNode *JT,
1379 SelectionDAG &DAG) const {
1381 EVT PtrVT = getPointerTy();
1382 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1384 // Use LARL to load the address of the table.
1385 return DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
1388 SDValue SystemZTargetLowering::lowerConstantPool(ConstantPoolSDNode *CP,
1389 SelectionDAG &DAG) const {
1391 EVT PtrVT = getPointerTy();
1394 if (CP->isMachineConstantPoolEntry())
1395 Result = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
1396 CP->getAlignment());
1398 Result = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
1399 CP->getAlignment(), CP->getOffset());
1401 // Use LARL to load the address of the constant pool entry.
1402 return DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
1405 SDValue SystemZTargetLowering::lowerBITCAST(SDValue Op,
1406 SelectionDAG &DAG) const {
1408 SDValue In = Op.getOperand(0);
1409 EVT InVT = In.getValueType();
1410 EVT ResVT = Op.getValueType();
1412 SDValue SubReg32 = DAG.getTargetConstant(SystemZ::subreg_32bit, MVT::i64);
1413 SDValue Shift32 = DAG.getConstant(32, MVT::i64);
1414 if (InVT == MVT::i32 && ResVT == MVT::f32) {
1415 SDValue In64 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, In);
1416 SDValue Shift = DAG.getNode(ISD::SHL, DL, MVT::i64, In64, Shift32);
1417 SDValue Out64 = DAG.getNode(ISD::BITCAST, DL, MVT::f64, Shift);
1418 SDNode *Out = DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL,
1419 MVT::f32, Out64, SubReg32);
1420 return SDValue(Out, 0);
1422 if (InVT == MVT::f32 && ResVT == MVT::i32) {
1423 SDNode *U64 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, MVT::f64);
1424 SDNode *In64 = DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, DL,
1425 MVT::f64, SDValue(U64, 0), In, SubReg32);
1426 SDValue Out64 = DAG.getNode(ISD::BITCAST, DL, MVT::i64, SDValue(In64, 0));
1427 SDValue Shift = DAG.getNode(ISD::SRL, DL, MVT::i64, Out64, Shift32);
1428 SDValue Out = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Shift);
1431 llvm_unreachable("Unexpected bitcast combination");
1434 SDValue SystemZTargetLowering::lowerVASTART(SDValue Op,
1435 SelectionDAG &DAG) const {
1436 MachineFunction &MF = DAG.getMachineFunction();
1437 SystemZMachineFunctionInfo *FuncInfo =
1438 MF.getInfo<SystemZMachineFunctionInfo>();
1439 EVT PtrVT = getPointerTy();
1441 SDValue Chain = Op.getOperand(0);
1442 SDValue Addr = Op.getOperand(1);
1443 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1446 // The initial values of each field.
1447 const unsigned NumFields = 4;
1448 SDValue Fields[NumFields] = {
1449 DAG.getConstant(FuncInfo->getVarArgsFirstGPR(), PtrVT),
1450 DAG.getConstant(FuncInfo->getVarArgsFirstFPR(), PtrVT),
1451 DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT),
1452 DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), PtrVT)
1455 // Store each field into its respective slot.
1456 SDValue MemOps[NumFields];
1457 unsigned Offset = 0;
1458 for (unsigned I = 0; I < NumFields; ++I) {
1459 SDValue FieldAddr = Addr;
1461 FieldAddr = DAG.getNode(ISD::ADD, DL, PtrVT, FieldAddr,
1462 DAG.getIntPtrConstant(Offset));
1463 MemOps[I] = DAG.getStore(Chain, DL, Fields[I], FieldAddr,
1464 MachinePointerInfo(SV, Offset),
1468 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps, NumFields);
1471 SDValue SystemZTargetLowering::lowerVACOPY(SDValue Op,
1472 SelectionDAG &DAG) const {
1473 SDValue Chain = Op.getOperand(0);
1474 SDValue DstPtr = Op.getOperand(1);
1475 SDValue SrcPtr = Op.getOperand(2);
1476 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
1477 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
1480 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr, DAG.getIntPtrConstant(32),
1481 /*Align*/8, /*isVolatile*/false, /*AlwaysInline*/false,
1482 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
1485 SDValue SystemZTargetLowering::
1486 lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const {
1487 SDValue Chain = Op.getOperand(0);
1488 SDValue Size = Op.getOperand(1);
1491 unsigned SPReg = getStackPointerRegisterToSaveRestore();
1493 // Get a reference to the stack pointer.
1494 SDValue OldSP = DAG.getCopyFromReg(Chain, DL, SPReg, MVT::i64);
1496 // Get the new stack pointer value.
1497 SDValue NewSP = DAG.getNode(ISD::SUB, DL, MVT::i64, OldSP, Size);
1499 // Copy the new stack pointer back.
1500 Chain = DAG.getCopyToReg(Chain, DL, SPReg, NewSP);
1502 // The allocated data lives above the 160 bytes allocated for the standard
1503 // frame, plus any outgoing stack arguments. We don't know how much that
1504 // amounts to yet, so emit a special ADJDYNALLOC placeholder.
1505 SDValue ArgAdjust = DAG.getNode(SystemZISD::ADJDYNALLOC, DL, MVT::i64);
1506 SDValue Result = DAG.getNode(ISD::ADD, DL, MVT::i64, NewSP, ArgAdjust);
1508 SDValue Ops[2] = { Result, Chain };
1509 return DAG.getMergeValues(Ops, 2, DL);
1512 SDValue SystemZTargetLowering::lowerSMUL_LOHI(SDValue Op,
1513 SelectionDAG &DAG) const {
1514 EVT VT = Op.getValueType();
1518 // Just do a normal 64-bit multiplication and extract the results.
1519 // We define this so that it can be used for constant division.
1520 lowerMUL_LOHI32(DAG, DL, ISD::SIGN_EXTEND, Op.getOperand(0),
1521 Op.getOperand(1), Ops[1], Ops[0]);
1523 // Do a full 128-bit multiplication based on UMUL_LOHI64:
1525 // (ll * rl) + ((lh * rl) << 64) + ((ll * rh) << 64)
1527 // but using the fact that the upper halves are either all zeros
1530 // (ll * rl) - ((lh & rl) << 64) - ((ll & rh) << 64)
1532 // and grouping the right terms together since they are quicker than the
1535 // (ll * rl) - (((lh & rl) + (ll & rh)) << 64)
1536 SDValue C63 = DAG.getConstant(63, MVT::i64);
1537 SDValue LL = Op.getOperand(0);
1538 SDValue RL = Op.getOperand(1);
1539 SDValue LH = DAG.getNode(ISD::SRA, DL, VT, LL, C63);
1540 SDValue RH = DAG.getNode(ISD::SRA, DL, VT, RL, C63);
1541 // UMUL_LOHI64 returns the low result in the odd register and the high
1542 // result in the even register. SMUL_LOHI is defined to return the
1543 // low half first, so the results are in reverse order.
1544 lowerGR128Binary(DAG, DL, VT, SystemZ::AEXT128_64, SystemZISD::UMUL_LOHI64,
1545 LL, RL, Ops[1], Ops[0]);
1546 SDValue NegLLTimesRH = DAG.getNode(ISD::AND, DL, VT, LL, RH);
1547 SDValue NegLHTimesRL = DAG.getNode(ISD::AND, DL, VT, LH, RL);
1548 SDValue NegSum = DAG.getNode(ISD::ADD, DL, VT, NegLLTimesRH, NegLHTimesRL);
1549 Ops[1] = DAG.getNode(ISD::SUB, DL, VT, Ops[1], NegSum);
1551 return DAG.getMergeValues(Ops, 2, DL);
1554 SDValue SystemZTargetLowering::lowerUMUL_LOHI(SDValue Op,
1555 SelectionDAG &DAG) const {
1556 EVT VT = Op.getValueType();
1560 // Just do a normal 64-bit multiplication and extract the results.
1561 // We define this so that it can be used for constant division.
1562 lowerMUL_LOHI32(DAG, DL, ISD::ZERO_EXTEND, Op.getOperand(0),
1563 Op.getOperand(1), Ops[1], Ops[0]);
1565 // UMUL_LOHI64 returns the low result in the odd register and the high
1566 // result in the even register. UMUL_LOHI is defined to return the
1567 // low half first, so the results are in reverse order.
1568 lowerGR128Binary(DAG, DL, VT, SystemZ::AEXT128_64, SystemZISD::UMUL_LOHI64,
1569 Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
1570 return DAG.getMergeValues(Ops, 2, DL);
1573 SDValue SystemZTargetLowering::lowerSDIVREM(SDValue Op,
1574 SelectionDAG &DAG) const {
1575 SDValue Op0 = Op.getOperand(0);
1576 SDValue Op1 = Op.getOperand(1);
1577 EVT VT = Op.getValueType();
1581 // We use DSGF for 32-bit division.
1583 Op0 = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i64, Op0);
1584 Opcode = SystemZISD::SDIVREM32;
1585 } else if (DAG.ComputeNumSignBits(Op1) > 32) {
1586 Op1 = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Op1);
1587 Opcode = SystemZISD::SDIVREM32;
1589 Opcode = SystemZISD::SDIVREM64;
1591 // DSG(F) takes a 64-bit dividend, so the even register in the GR128
1592 // input is "don't care". The instruction returns the remainder in
1593 // the even register and the quotient in the odd register.
1595 lowerGR128Binary(DAG, DL, VT, SystemZ::AEXT128_64, Opcode,
1596 Op0, Op1, Ops[1], Ops[0]);
1597 return DAG.getMergeValues(Ops, 2, DL);
1600 SDValue SystemZTargetLowering::lowerUDIVREM(SDValue Op,
1601 SelectionDAG &DAG) const {
1602 EVT VT = Op.getValueType();
1605 // DL(G) uses a double-width dividend, so we need to clear the even
1606 // register in the GR128 input. The instruction returns the remainder
1607 // in the even register and the quotient in the odd register.
1610 lowerGR128Binary(DAG, DL, VT, SystemZ::ZEXT128_32, SystemZISD::UDIVREM32,
1611 Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
1613 lowerGR128Binary(DAG, DL, VT, SystemZ::ZEXT128_64, SystemZISD::UDIVREM64,
1614 Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
1615 return DAG.getMergeValues(Ops, 2, DL);
1618 SDValue SystemZTargetLowering::lowerOR(SDValue Op, SelectionDAG &DAG) const {
1619 assert(Op.getValueType() == MVT::i64 && "Should be 64-bit operation");
1621 // Get the known-zero masks for each operand.
1622 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1) };
1623 APInt KnownZero[2], KnownOne[2];
1624 DAG.ComputeMaskedBits(Ops[0], KnownZero[0], KnownOne[0]);
1625 DAG.ComputeMaskedBits(Ops[1], KnownZero[1], KnownOne[1]);
1627 // See if the upper 32 bits of one operand and the lower 32 bits of the
1628 // other are known zero. They are the low and high operands respectively.
1629 uint64_t Masks[] = { KnownZero[0].getZExtValue(),
1630 KnownZero[1].getZExtValue() };
1632 if ((Masks[0] >> 32) == 0xffffffff && uint32_t(Masks[1]) == 0xffffffff)
1634 else if ((Masks[1] >> 32) == 0xffffffff && uint32_t(Masks[0]) == 0xffffffff)
1639 SDValue LowOp = Ops[Low];
1640 SDValue HighOp = Ops[High];
1642 // If the high part is a constant, we're better off using IILH.
1643 if (HighOp.getOpcode() == ISD::Constant)
1646 // If the low part is a constant that is outside the range of LHI,
1647 // then we're better off using IILF.
1648 if (LowOp.getOpcode() == ISD::Constant) {
1649 int64_t Value = int32_t(cast<ConstantSDNode>(LowOp)->getZExtValue());
1650 if (!isInt<16>(Value))
1654 // Check whether the high part is an AND that doesn't change the
1655 // high 32 bits and just masks out low bits. We can skip it if so.
1656 if (HighOp.getOpcode() == ISD::AND &&
1657 HighOp.getOperand(1).getOpcode() == ISD::Constant) {
1658 ConstantSDNode *MaskNode = cast<ConstantSDNode>(HighOp.getOperand(1));
1659 uint64_t Mask = MaskNode->getZExtValue() | Masks[High];
1660 if ((Mask >> 32) == 0xffffffff)
1661 HighOp = HighOp.getOperand(0);
1664 // Take advantage of the fact that all GR32 operations only change the
1665 // low 32 bits by truncating Low to an i32 and inserting it directly
1666 // using a subreg. The interesting cases are those where the truncation
1669 SDValue Low32 = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, LowOp);
1670 SDValue SubReg32 = DAG.getTargetConstant(SystemZ::subreg_32bit, MVT::i64);
1671 SDNode *Result = DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, DL,
1672 MVT::i64, HighOp, Low32, SubReg32);
1673 return SDValue(Result, 0);
1676 // Op is an 8-, 16-bit or 32-bit ATOMIC_LOAD_* operation. Lower the first
1677 // two into the fullword ATOMIC_LOADW_* operation given by Opcode.
1678 SDValue SystemZTargetLowering::lowerATOMIC_LOAD(SDValue Op,
1680 unsigned Opcode) const {
1681 AtomicSDNode *Node = cast<AtomicSDNode>(Op.getNode());
1683 // 32-bit operations need no code outside the main loop.
1684 EVT NarrowVT = Node->getMemoryVT();
1685 EVT WideVT = MVT::i32;
1686 if (NarrowVT == WideVT)
1689 int64_t BitSize = NarrowVT.getSizeInBits();
1690 SDValue ChainIn = Node->getChain();
1691 SDValue Addr = Node->getBasePtr();
1692 SDValue Src2 = Node->getVal();
1693 MachineMemOperand *MMO = Node->getMemOperand();
1695 EVT PtrVT = Addr.getValueType();
1697 // Convert atomic subtracts of constants into additions.
1698 if (Opcode == SystemZISD::ATOMIC_LOADW_SUB)
1699 if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(Src2)) {
1700 Opcode = SystemZISD::ATOMIC_LOADW_ADD;
1701 Src2 = DAG.getConstant(-Const->getSExtValue(), Src2.getValueType());
1704 // Get the address of the containing word.
1705 SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr,
1706 DAG.getConstant(-4, PtrVT));
1708 // Get the number of bits that the word must be rotated left in order
1709 // to bring the field to the top bits of a GR32.
1710 SDValue BitShift = DAG.getNode(ISD::SHL, DL, PtrVT, Addr,
1711 DAG.getConstant(3, PtrVT));
1712 BitShift = DAG.getNode(ISD::TRUNCATE, DL, WideVT, BitShift);
1714 // Get the complementing shift amount, for rotating a field in the top
1715 // bits back to its proper position.
1716 SDValue NegBitShift = DAG.getNode(ISD::SUB, DL, WideVT,
1717 DAG.getConstant(0, WideVT), BitShift);
1719 // Extend the source operand to 32 bits and prepare it for the inner loop.
1720 // ATOMIC_SWAPW uses RISBG to rotate the field left, but all other
1721 // operations require the source to be shifted in advance. (This shift
1722 // can be folded if the source is constant.) For AND and NAND, the lower
1723 // bits must be set, while for other opcodes they should be left clear.
1724 if (Opcode != SystemZISD::ATOMIC_SWAPW)
1725 Src2 = DAG.getNode(ISD::SHL, DL, WideVT, Src2,
1726 DAG.getConstant(32 - BitSize, WideVT));
1727 if (Opcode == SystemZISD::ATOMIC_LOADW_AND ||
1728 Opcode == SystemZISD::ATOMIC_LOADW_NAND)
1729 Src2 = DAG.getNode(ISD::OR, DL, WideVT, Src2,
1730 DAG.getConstant(uint32_t(-1) >> BitSize, WideVT));
1732 // Construct the ATOMIC_LOADW_* node.
1733 SDVTList VTList = DAG.getVTList(WideVT, MVT::Other);
1734 SDValue Ops[] = { ChainIn, AlignedAddr, Src2, BitShift, NegBitShift,
1735 DAG.getConstant(BitSize, WideVT) };
1736 SDValue AtomicOp = DAG.getMemIntrinsicNode(Opcode, DL, VTList, Ops,
1737 array_lengthof(Ops),
1740 // Rotate the result of the final CS so that the field is in the lower
1741 // bits of a GR32, then truncate it.
1742 SDValue ResultShift = DAG.getNode(ISD::ADD, DL, WideVT, BitShift,
1743 DAG.getConstant(BitSize, WideVT));
1744 SDValue Result = DAG.getNode(ISD::ROTL, DL, WideVT, AtomicOp, ResultShift);
1746 SDValue RetOps[2] = { Result, AtomicOp.getValue(1) };
1747 return DAG.getMergeValues(RetOps, 2, DL);
1750 // Node is an 8- or 16-bit ATOMIC_CMP_SWAP operation. Lower the first two
1751 // into a fullword ATOMIC_CMP_SWAPW operation.
1752 SDValue SystemZTargetLowering::lowerATOMIC_CMP_SWAP(SDValue Op,
1753 SelectionDAG &DAG) const {
1754 AtomicSDNode *Node = cast<AtomicSDNode>(Op.getNode());
1756 // We have native support for 32-bit compare and swap.
1757 EVT NarrowVT = Node->getMemoryVT();
1758 EVT WideVT = MVT::i32;
1759 if (NarrowVT == WideVT)
1762 int64_t BitSize = NarrowVT.getSizeInBits();
1763 SDValue ChainIn = Node->getOperand(0);
1764 SDValue Addr = Node->getOperand(1);
1765 SDValue CmpVal = Node->getOperand(2);
1766 SDValue SwapVal = Node->getOperand(3);
1767 MachineMemOperand *MMO = Node->getMemOperand();
1769 EVT PtrVT = Addr.getValueType();
1771 // Get the address of the containing word.
1772 SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr,
1773 DAG.getConstant(-4, PtrVT));
1775 // Get the number of bits that the word must be rotated left in order
1776 // to bring the field to the top bits of a GR32.
1777 SDValue BitShift = DAG.getNode(ISD::SHL, DL, PtrVT, Addr,
1778 DAG.getConstant(3, PtrVT));
1779 BitShift = DAG.getNode(ISD::TRUNCATE, DL, WideVT, BitShift);
1781 // Get the complementing shift amount, for rotating a field in the top
1782 // bits back to its proper position.
1783 SDValue NegBitShift = DAG.getNode(ISD::SUB, DL, WideVT,
1784 DAG.getConstant(0, WideVT), BitShift);
1786 // Construct the ATOMIC_CMP_SWAPW node.
1787 SDVTList VTList = DAG.getVTList(WideVT, MVT::Other);
1788 SDValue Ops[] = { ChainIn, AlignedAddr, CmpVal, SwapVal, BitShift,
1789 NegBitShift, DAG.getConstant(BitSize, WideVT) };
1790 SDValue AtomicOp = DAG.getMemIntrinsicNode(SystemZISD::ATOMIC_CMP_SWAPW, DL,
1791 VTList, Ops, array_lengthof(Ops),
1796 SDValue SystemZTargetLowering::lowerSTACKSAVE(SDValue Op,
1797 SelectionDAG &DAG) const {
1798 MachineFunction &MF = DAG.getMachineFunction();
1799 MF.getInfo<SystemZMachineFunctionInfo>()->setManipulatesSP(true);
1800 return DAG.getCopyFromReg(Op.getOperand(0), SDLoc(Op),
1801 SystemZ::R15D, Op.getValueType());
1804 SDValue SystemZTargetLowering::lowerSTACKRESTORE(SDValue Op,
1805 SelectionDAG &DAG) const {
1806 MachineFunction &MF = DAG.getMachineFunction();
1807 MF.getInfo<SystemZMachineFunctionInfo>()->setManipulatesSP(true);
1808 return DAG.getCopyToReg(Op.getOperand(0), SDLoc(Op),
1809 SystemZ::R15D, Op.getOperand(1));
1812 SDValue SystemZTargetLowering::lowerPREFETCH(SDValue Op,
1813 SelectionDAG &DAG) const {
1814 bool IsData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
1816 // Just preserve the chain.
1817 return Op.getOperand(0);
1819 bool IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
1820 unsigned Code = IsWrite ? SystemZ::PFD_WRITE : SystemZ::PFD_READ;
1821 MemIntrinsicSDNode *Node = cast<MemIntrinsicSDNode>(Op.getNode());
1824 DAG.getConstant(Code, MVT::i32),
1827 return DAG.getMemIntrinsicNode(SystemZISD::PREFETCH, SDLoc(Op),
1828 Node->getVTList(), Ops, array_lengthof(Ops),
1829 Node->getMemoryVT(), Node->getMemOperand());
1832 SDValue SystemZTargetLowering::LowerOperation(SDValue Op,
1833 SelectionDAG &DAG) const {
1834 switch (Op.getOpcode()) {
1836 return lowerBR_CC(Op, DAG);
1837 case ISD::SELECT_CC:
1838 return lowerSELECT_CC(Op, DAG);
1839 case ISD::GlobalAddress:
1840 return lowerGlobalAddress(cast<GlobalAddressSDNode>(Op), DAG);
1841 case ISD::GlobalTLSAddress:
1842 return lowerGlobalTLSAddress(cast<GlobalAddressSDNode>(Op), DAG);
1843 case ISD::BlockAddress:
1844 return lowerBlockAddress(cast<BlockAddressSDNode>(Op), DAG);
1845 case ISD::JumpTable:
1846 return lowerJumpTable(cast<JumpTableSDNode>(Op), DAG);
1847 case ISD::ConstantPool:
1848 return lowerConstantPool(cast<ConstantPoolSDNode>(Op), DAG);
1850 return lowerBITCAST(Op, DAG);
1852 return lowerVASTART(Op, DAG);
1854 return lowerVACOPY(Op, DAG);
1855 case ISD::DYNAMIC_STACKALLOC:
1856 return lowerDYNAMIC_STACKALLOC(Op, DAG);
1857 case ISD::SMUL_LOHI:
1858 return lowerSMUL_LOHI(Op, DAG);
1859 case ISD::UMUL_LOHI:
1860 return lowerUMUL_LOHI(Op, DAG);
1862 return lowerSDIVREM(Op, DAG);
1864 return lowerUDIVREM(Op, DAG);
1866 return lowerOR(Op, DAG);
1867 case ISD::ATOMIC_SWAP:
1868 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_SWAPW);
1869 case ISD::ATOMIC_LOAD_ADD:
1870 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_ADD);
1871 case ISD::ATOMIC_LOAD_SUB:
1872 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_SUB);
1873 case ISD::ATOMIC_LOAD_AND:
1874 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_AND);
1875 case ISD::ATOMIC_LOAD_OR:
1876 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_OR);
1877 case ISD::ATOMIC_LOAD_XOR:
1878 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_XOR);
1879 case ISD::ATOMIC_LOAD_NAND:
1880 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_NAND);
1881 case ISD::ATOMIC_LOAD_MIN:
1882 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_MIN);
1883 case ISD::ATOMIC_LOAD_MAX:
1884 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_MAX);
1885 case ISD::ATOMIC_LOAD_UMIN:
1886 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_UMIN);
1887 case ISD::ATOMIC_LOAD_UMAX:
1888 return lowerATOMIC_LOAD(Op, DAG, SystemZISD::ATOMIC_LOADW_UMAX);
1889 case ISD::ATOMIC_CMP_SWAP:
1890 return lowerATOMIC_CMP_SWAP(Op, DAG);
1891 case ISD::STACKSAVE:
1892 return lowerSTACKSAVE(Op, DAG);
1893 case ISD::STACKRESTORE:
1894 return lowerSTACKRESTORE(Op, DAG);
1896 return lowerPREFETCH(Op, DAG);
1898 llvm_unreachable("Unexpected node to lower");
1902 const char *SystemZTargetLowering::getTargetNodeName(unsigned Opcode) const {
1903 #define OPCODE(NAME) case SystemZISD::NAME: return "SystemZISD::" #NAME
1908 OPCODE(PCREL_WRAPPER);
1912 OPCODE(SELECT_CCMASK);
1913 OPCODE(ADJDYNALLOC);
1914 OPCODE(EXTRACT_ACCESS);
1915 OPCODE(UMUL_LOHI64);
1923 OPCODE(SEARCH_STRING);
1925 OPCODE(ATOMIC_SWAPW);
1926 OPCODE(ATOMIC_LOADW_ADD);
1927 OPCODE(ATOMIC_LOADW_SUB);
1928 OPCODE(ATOMIC_LOADW_AND);
1929 OPCODE(ATOMIC_LOADW_OR);
1930 OPCODE(ATOMIC_LOADW_XOR);
1931 OPCODE(ATOMIC_LOADW_NAND);
1932 OPCODE(ATOMIC_LOADW_MIN);
1933 OPCODE(ATOMIC_LOADW_MAX);
1934 OPCODE(ATOMIC_LOADW_UMIN);
1935 OPCODE(ATOMIC_LOADW_UMAX);
1936 OPCODE(ATOMIC_CMP_SWAPW);
1943 //===----------------------------------------------------------------------===//
1945 //===----------------------------------------------------------------------===//
1947 // Create a new basic block after MBB.
1948 static MachineBasicBlock *emitBlockAfter(MachineBasicBlock *MBB) {
1949 MachineFunction &MF = *MBB->getParent();
1950 MachineBasicBlock *NewMBB = MF.CreateMachineBasicBlock(MBB->getBasicBlock());
1951 MF.insert(llvm::next(MachineFunction::iterator(MBB)), NewMBB);
1955 // Split MBB after MI and return the new block (the one that contains
1956 // instructions after MI).
1957 static MachineBasicBlock *splitBlockAfter(MachineInstr *MI,
1958 MachineBasicBlock *MBB) {
1959 MachineBasicBlock *NewMBB = emitBlockAfter(MBB);
1960 NewMBB->splice(NewMBB->begin(), MBB,
1961 llvm::next(MachineBasicBlock::iterator(MI)),
1963 NewMBB->transferSuccessorsAndUpdatePHIs(MBB);
1967 // Implement EmitInstrWithCustomInserter for pseudo Select* instruction MI.
1969 SystemZTargetLowering::emitSelect(MachineInstr *MI,
1970 MachineBasicBlock *MBB) const {
1971 const SystemZInstrInfo *TII = TM.getInstrInfo();
1973 unsigned DestReg = MI->getOperand(0).getReg();
1974 unsigned TrueReg = MI->getOperand(1).getReg();
1975 unsigned FalseReg = MI->getOperand(2).getReg();
1976 unsigned CCValid = MI->getOperand(3).getImm();
1977 unsigned CCMask = MI->getOperand(4).getImm();
1978 DebugLoc DL = MI->getDebugLoc();
1980 MachineBasicBlock *StartMBB = MBB;
1981 MachineBasicBlock *JoinMBB = splitBlockAfter(MI, MBB);
1982 MachineBasicBlock *FalseMBB = emitBlockAfter(StartMBB);
1985 // BRC CCMask, JoinMBB
1986 // # fallthrough to FalseMBB
1988 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
1989 .addImm(CCValid).addImm(CCMask).addMBB(JoinMBB);
1990 MBB->addSuccessor(JoinMBB);
1991 MBB->addSuccessor(FalseMBB);
1994 // # fallthrough to JoinMBB
1996 MBB->addSuccessor(JoinMBB);
1999 // %Result = phi [ %FalseReg, FalseMBB ], [ %TrueReg, StartMBB ]
2002 BuildMI(*MBB, MBB->begin(), DL, TII->get(SystemZ::PHI), DestReg)
2003 .addReg(TrueReg).addMBB(StartMBB)
2004 .addReg(FalseReg).addMBB(FalseMBB);
2006 MI->eraseFromParent();
2010 // Implement EmitInstrWithCustomInserter for pseudo CondStore* instruction MI.
2011 // StoreOpcode is the store to use and Invert says whether the store should
2012 // happen when the condition is false rather than true. If a STORE ON
2013 // CONDITION is available, STOCOpcode is its opcode, otherwise it is 0.
2015 SystemZTargetLowering::emitCondStore(MachineInstr *MI,
2016 MachineBasicBlock *MBB,
2017 unsigned StoreOpcode, unsigned STOCOpcode,
2018 bool Invert) const {
2019 const SystemZInstrInfo *TII = TM.getInstrInfo();
2021 unsigned SrcReg = MI->getOperand(0).getReg();
2022 MachineOperand Base = MI->getOperand(1);
2023 int64_t Disp = MI->getOperand(2).getImm();
2024 unsigned IndexReg = MI->getOperand(3).getReg();
2025 unsigned CCValid = MI->getOperand(4).getImm();
2026 unsigned CCMask = MI->getOperand(5).getImm();
2027 DebugLoc DL = MI->getDebugLoc();
2029 StoreOpcode = TII->getOpcodeForOffset(StoreOpcode, Disp);
2031 // Use STOCOpcode if possible. We could use different store patterns in
2032 // order to avoid matching the index register, but the performance trade-offs
2033 // might be more complicated in that case.
2034 if (STOCOpcode && !IndexReg && TM.getSubtargetImpl()->hasLoadStoreOnCond()) {
2037 BuildMI(*MBB, MI, DL, TII->get(STOCOpcode))
2038 .addReg(SrcReg).addOperand(Base).addImm(Disp)
2039 .addImm(CCValid).addImm(CCMask);
2040 MI->eraseFromParent();
2044 // Get the condition needed to branch around the store.
2048 MachineBasicBlock *StartMBB = MBB;
2049 MachineBasicBlock *JoinMBB = splitBlockAfter(MI, MBB);
2050 MachineBasicBlock *FalseMBB = emitBlockAfter(StartMBB);
2053 // BRC CCMask, JoinMBB
2054 // # fallthrough to FalseMBB
2056 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2057 .addImm(CCValid).addImm(CCMask).addMBB(JoinMBB);
2058 MBB->addSuccessor(JoinMBB);
2059 MBB->addSuccessor(FalseMBB);
2062 // store %SrcReg, %Disp(%Index,%Base)
2063 // # fallthrough to JoinMBB
2065 BuildMI(MBB, DL, TII->get(StoreOpcode))
2066 .addReg(SrcReg).addOperand(Base).addImm(Disp).addReg(IndexReg);
2067 MBB->addSuccessor(JoinMBB);
2069 MI->eraseFromParent();
2073 // Implement EmitInstrWithCustomInserter for pseudo ATOMIC_LOAD{,W}_*
2074 // or ATOMIC_SWAP{,W} instruction MI. BinOpcode is the instruction that
2075 // performs the binary operation elided by "*", or 0 for ATOMIC_SWAP{,W}.
2076 // BitSize is the width of the field in bits, or 0 if this is a partword
2077 // ATOMIC_LOADW_* or ATOMIC_SWAPW instruction, in which case the bitsize
2078 // is one of the operands. Invert says whether the field should be
2079 // inverted after performing BinOpcode (e.g. for NAND).
2081 SystemZTargetLowering::emitAtomicLoadBinary(MachineInstr *MI,
2082 MachineBasicBlock *MBB,
2085 bool Invert) const {
2086 const SystemZInstrInfo *TII = TM.getInstrInfo();
2087 MachineFunction &MF = *MBB->getParent();
2088 MachineRegisterInfo &MRI = MF.getRegInfo();
2089 bool IsSubWord = (BitSize < 32);
2091 // Extract the operands. Base can be a register or a frame index.
2092 // Src2 can be a register or immediate.
2093 unsigned Dest = MI->getOperand(0).getReg();
2094 MachineOperand Base = earlyUseOperand(MI->getOperand(1));
2095 int64_t Disp = MI->getOperand(2).getImm();
2096 MachineOperand Src2 = earlyUseOperand(MI->getOperand(3));
2097 unsigned BitShift = (IsSubWord ? MI->getOperand(4).getReg() : 0);
2098 unsigned NegBitShift = (IsSubWord ? MI->getOperand(5).getReg() : 0);
2099 DebugLoc DL = MI->getDebugLoc();
2101 BitSize = MI->getOperand(6).getImm();
2103 // Subword operations use 32-bit registers.
2104 const TargetRegisterClass *RC = (BitSize <= 32 ?
2105 &SystemZ::GR32BitRegClass :
2106 &SystemZ::GR64BitRegClass);
2107 unsigned LOpcode = BitSize <= 32 ? SystemZ::L : SystemZ::LG;
2108 unsigned CSOpcode = BitSize <= 32 ? SystemZ::CS : SystemZ::CSG;
2110 // Get the right opcodes for the displacement.
2111 LOpcode = TII->getOpcodeForOffset(LOpcode, Disp);
2112 CSOpcode = TII->getOpcodeForOffset(CSOpcode, Disp);
2113 assert(LOpcode && CSOpcode && "Displacement out of range");
2115 // Create virtual registers for temporary results.
2116 unsigned OrigVal = MRI.createVirtualRegister(RC);
2117 unsigned OldVal = MRI.createVirtualRegister(RC);
2118 unsigned NewVal = (BinOpcode || IsSubWord ?
2119 MRI.createVirtualRegister(RC) : Src2.getReg());
2120 unsigned RotatedOldVal = (IsSubWord ? MRI.createVirtualRegister(RC) : OldVal);
2121 unsigned RotatedNewVal = (IsSubWord ? MRI.createVirtualRegister(RC) : NewVal);
2123 // Insert a basic block for the main loop.
2124 MachineBasicBlock *StartMBB = MBB;
2125 MachineBasicBlock *DoneMBB = splitBlockAfter(MI, MBB);
2126 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
2130 // %OrigVal = L Disp(%Base)
2131 // # fall through to LoopMMB
2133 BuildMI(MBB, DL, TII->get(LOpcode), OrigVal)
2134 .addOperand(Base).addImm(Disp).addReg(0);
2135 MBB->addSuccessor(LoopMBB);
2138 // %OldVal = phi [ %OrigVal, StartMBB ], [ %Dest, LoopMBB ]
2139 // %RotatedOldVal = RLL %OldVal, 0(%BitShift)
2140 // %RotatedNewVal = OP %RotatedOldVal, %Src2
2141 // %NewVal = RLL %RotatedNewVal, 0(%NegBitShift)
2142 // %Dest = CS %OldVal, %NewVal, Disp(%Base)
2144 // # fall through to DoneMMB
2146 BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
2147 .addReg(OrigVal).addMBB(StartMBB)
2148 .addReg(Dest).addMBB(LoopMBB);
2150 BuildMI(MBB, DL, TII->get(SystemZ::RLL), RotatedOldVal)
2151 .addReg(OldVal).addReg(BitShift).addImm(0);
2153 // Perform the operation normally and then invert every bit of the field.
2154 unsigned Tmp = MRI.createVirtualRegister(RC);
2155 BuildMI(MBB, DL, TII->get(BinOpcode), Tmp)
2156 .addReg(RotatedOldVal).addOperand(Src2);
2158 // XILF with the upper BitSize bits set.
2159 BuildMI(MBB, DL, TII->get(SystemZ::XILF32), RotatedNewVal)
2160 .addReg(Tmp).addImm(uint32_t(~0 << (32 - BitSize)));
2161 else if (BitSize == 32)
2162 // XILF with every bit set.
2163 BuildMI(MBB, DL, TII->get(SystemZ::XILF32), RotatedNewVal)
2164 .addReg(Tmp).addImm(~uint32_t(0));
2166 // Use LCGR and add -1 to the result, which is more compact than
2167 // an XILF, XILH pair.
2168 unsigned Tmp2 = MRI.createVirtualRegister(RC);
2169 BuildMI(MBB, DL, TII->get(SystemZ::LCGR), Tmp2).addReg(Tmp);
2170 BuildMI(MBB, DL, TII->get(SystemZ::AGHI), RotatedNewVal)
2171 .addReg(Tmp2).addImm(-1);
2173 } else if (BinOpcode)
2174 // A simply binary operation.
2175 BuildMI(MBB, DL, TII->get(BinOpcode), RotatedNewVal)
2176 .addReg(RotatedOldVal).addOperand(Src2);
2178 // Use RISBG to rotate Src2 into position and use it to replace the
2179 // field in RotatedOldVal.
2180 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RotatedNewVal)
2181 .addReg(RotatedOldVal).addReg(Src2.getReg())
2182 .addImm(32).addImm(31 + BitSize).addImm(32 - BitSize);
2184 BuildMI(MBB, DL, TII->get(SystemZ::RLL), NewVal)
2185 .addReg(RotatedNewVal).addReg(NegBitShift).addImm(0);
2186 BuildMI(MBB, DL, TII->get(CSOpcode), Dest)
2187 .addReg(OldVal).addReg(NewVal).addOperand(Base).addImm(Disp);
2188 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2189 .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
2190 MBB->addSuccessor(LoopMBB);
2191 MBB->addSuccessor(DoneMBB);
2193 MI->eraseFromParent();
2197 // Implement EmitInstrWithCustomInserter for pseudo
2198 // ATOMIC_LOAD{,W}_{,U}{MIN,MAX} instruction MI. CompareOpcode is the
2199 // instruction that should be used to compare the current field with the
2200 // minimum or maximum value. KeepOldMask is the BRC condition-code mask
2201 // for when the current field should be kept. BitSize is the width of
2202 // the field in bits, or 0 if this is a partword ATOMIC_LOADW_* instruction.
2204 SystemZTargetLowering::emitAtomicLoadMinMax(MachineInstr *MI,
2205 MachineBasicBlock *MBB,
2206 unsigned CompareOpcode,
2207 unsigned KeepOldMask,
2208 unsigned BitSize) const {
2209 const SystemZInstrInfo *TII = TM.getInstrInfo();
2210 MachineFunction &MF = *MBB->getParent();
2211 MachineRegisterInfo &MRI = MF.getRegInfo();
2212 bool IsSubWord = (BitSize < 32);
2214 // Extract the operands. Base can be a register or a frame index.
2215 unsigned Dest = MI->getOperand(0).getReg();
2216 MachineOperand Base = earlyUseOperand(MI->getOperand(1));
2217 int64_t Disp = MI->getOperand(2).getImm();
2218 unsigned Src2 = MI->getOperand(3).getReg();
2219 unsigned BitShift = (IsSubWord ? MI->getOperand(4).getReg() : 0);
2220 unsigned NegBitShift = (IsSubWord ? MI->getOperand(5).getReg() : 0);
2221 DebugLoc DL = MI->getDebugLoc();
2223 BitSize = MI->getOperand(6).getImm();
2225 // Subword operations use 32-bit registers.
2226 const TargetRegisterClass *RC = (BitSize <= 32 ?
2227 &SystemZ::GR32BitRegClass :
2228 &SystemZ::GR64BitRegClass);
2229 unsigned LOpcode = BitSize <= 32 ? SystemZ::L : SystemZ::LG;
2230 unsigned CSOpcode = BitSize <= 32 ? SystemZ::CS : SystemZ::CSG;
2232 // Get the right opcodes for the displacement.
2233 LOpcode = TII->getOpcodeForOffset(LOpcode, Disp);
2234 CSOpcode = TII->getOpcodeForOffset(CSOpcode, Disp);
2235 assert(LOpcode && CSOpcode && "Displacement out of range");
2237 // Create virtual registers for temporary results.
2238 unsigned OrigVal = MRI.createVirtualRegister(RC);
2239 unsigned OldVal = MRI.createVirtualRegister(RC);
2240 unsigned NewVal = MRI.createVirtualRegister(RC);
2241 unsigned RotatedOldVal = (IsSubWord ? MRI.createVirtualRegister(RC) : OldVal);
2242 unsigned RotatedAltVal = (IsSubWord ? MRI.createVirtualRegister(RC) : Src2);
2243 unsigned RotatedNewVal = (IsSubWord ? MRI.createVirtualRegister(RC) : NewVal);
2245 // Insert 3 basic blocks for the loop.
2246 MachineBasicBlock *StartMBB = MBB;
2247 MachineBasicBlock *DoneMBB = splitBlockAfter(MI, MBB);
2248 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
2249 MachineBasicBlock *UseAltMBB = emitBlockAfter(LoopMBB);
2250 MachineBasicBlock *UpdateMBB = emitBlockAfter(UseAltMBB);
2254 // %OrigVal = L Disp(%Base)
2255 // # fall through to LoopMMB
2257 BuildMI(MBB, DL, TII->get(LOpcode), OrigVal)
2258 .addOperand(Base).addImm(Disp).addReg(0);
2259 MBB->addSuccessor(LoopMBB);
2262 // %OldVal = phi [ %OrigVal, StartMBB ], [ %Dest, UpdateMBB ]
2263 // %RotatedOldVal = RLL %OldVal, 0(%BitShift)
2264 // CompareOpcode %RotatedOldVal, %Src2
2265 // BRC KeepOldMask, UpdateMBB
2267 BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
2268 .addReg(OrigVal).addMBB(StartMBB)
2269 .addReg(Dest).addMBB(UpdateMBB);
2271 BuildMI(MBB, DL, TII->get(SystemZ::RLL), RotatedOldVal)
2272 .addReg(OldVal).addReg(BitShift).addImm(0);
2273 BuildMI(MBB, DL, TII->get(CompareOpcode))
2274 .addReg(RotatedOldVal).addReg(Src2);
2275 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2276 .addImm(SystemZ::CCMASK_ICMP).addImm(KeepOldMask).addMBB(UpdateMBB);
2277 MBB->addSuccessor(UpdateMBB);
2278 MBB->addSuccessor(UseAltMBB);
2281 // %RotatedAltVal = RISBG %RotatedOldVal, %Src2, 32, 31 + BitSize, 0
2282 // # fall through to UpdateMMB
2285 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RotatedAltVal)
2286 .addReg(RotatedOldVal).addReg(Src2)
2287 .addImm(32).addImm(31 + BitSize).addImm(0);
2288 MBB->addSuccessor(UpdateMBB);
2291 // %RotatedNewVal = PHI [ %RotatedOldVal, LoopMBB ],
2292 // [ %RotatedAltVal, UseAltMBB ]
2293 // %NewVal = RLL %RotatedNewVal, 0(%NegBitShift)
2294 // %Dest = CS %OldVal, %NewVal, Disp(%Base)
2296 // # fall through to DoneMMB
2298 BuildMI(MBB, DL, TII->get(SystemZ::PHI), RotatedNewVal)
2299 .addReg(RotatedOldVal).addMBB(LoopMBB)
2300 .addReg(RotatedAltVal).addMBB(UseAltMBB);
2302 BuildMI(MBB, DL, TII->get(SystemZ::RLL), NewVal)
2303 .addReg(RotatedNewVal).addReg(NegBitShift).addImm(0);
2304 BuildMI(MBB, DL, TII->get(CSOpcode), Dest)
2305 .addReg(OldVal).addReg(NewVal).addOperand(Base).addImm(Disp);
2306 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2307 .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
2308 MBB->addSuccessor(LoopMBB);
2309 MBB->addSuccessor(DoneMBB);
2311 MI->eraseFromParent();
2315 // Implement EmitInstrWithCustomInserter for pseudo ATOMIC_CMP_SWAPW
2318 SystemZTargetLowering::emitAtomicCmpSwapW(MachineInstr *MI,
2319 MachineBasicBlock *MBB) const {
2320 const SystemZInstrInfo *TII = TM.getInstrInfo();
2321 MachineFunction &MF = *MBB->getParent();
2322 MachineRegisterInfo &MRI = MF.getRegInfo();
2324 // Extract the operands. Base can be a register or a frame index.
2325 unsigned Dest = MI->getOperand(0).getReg();
2326 MachineOperand Base = earlyUseOperand(MI->getOperand(1));
2327 int64_t Disp = MI->getOperand(2).getImm();
2328 unsigned OrigCmpVal = MI->getOperand(3).getReg();
2329 unsigned OrigSwapVal = MI->getOperand(4).getReg();
2330 unsigned BitShift = MI->getOperand(5).getReg();
2331 unsigned NegBitShift = MI->getOperand(6).getReg();
2332 int64_t BitSize = MI->getOperand(7).getImm();
2333 DebugLoc DL = MI->getDebugLoc();
2335 const TargetRegisterClass *RC = &SystemZ::GR32BitRegClass;
2337 // Get the right opcodes for the displacement.
2338 unsigned LOpcode = TII->getOpcodeForOffset(SystemZ::L, Disp);
2339 unsigned CSOpcode = TII->getOpcodeForOffset(SystemZ::CS, Disp);
2340 assert(LOpcode && CSOpcode && "Displacement out of range");
2342 // Create virtual registers for temporary results.
2343 unsigned OrigOldVal = MRI.createVirtualRegister(RC);
2344 unsigned OldVal = MRI.createVirtualRegister(RC);
2345 unsigned CmpVal = MRI.createVirtualRegister(RC);
2346 unsigned SwapVal = MRI.createVirtualRegister(RC);
2347 unsigned StoreVal = MRI.createVirtualRegister(RC);
2348 unsigned RetryOldVal = MRI.createVirtualRegister(RC);
2349 unsigned RetryCmpVal = MRI.createVirtualRegister(RC);
2350 unsigned RetrySwapVal = MRI.createVirtualRegister(RC);
2352 // Insert 2 basic blocks for the loop.
2353 MachineBasicBlock *StartMBB = MBB;
2354 MachineBasicBlock *DoneMBB = splitBlockAfter(MI, MBB);
2355 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
2356 MachineBasicBlock *SetMBB = emitBlockAfter(LoopMBB);
2360 // %OrigOldVal = L Disp(%Base)
2361 // # fall through to LoopMMB
2363 BuildMI(MBB, DL, TII->get(LOpcode), OrigOldVal)
2364 .addOperand(Base).addImm(Disp).addReg(0);
2365 MBB->addSuccessor(LoopMBB);
2368 // %OldVal = phi [ %OrigOldVal, EntryBB ], [ %RetryOldVal, SetMBB ]
2369 // %CmpVal = phi [ %OrigCmpVal, EntryBB ], [ %RetryCmpVal, SetMBB ]
2370 // %SwapVal = phi [ %OrigSwapVal, EntryBB ], [ %RetrySwapVal, SetMBB ]
2371 // %Dest = RLL %OldVal, BitSize(%BitShift)
2372 // ^^ The low BitSize bits contain the field
2374 // %RetryCmpVal = RISBG32 %CmpVal, %Dest, 32, 63-BitSize, 0
2375 // ^^ Replace the upper 32-BitSize bits of the
2376 // comparison value with those that we loaded,
2377 // so that we can use a full word comparison.
2378 // CR %Dest, %RetryCmpVal
2380 // # Fall through to SetMBB
2382 BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
2383 .addReg(OrigOldVal).addMBB(StartMBB)
2384 .addReg(RetryOldVal).addMBB(SetMBB);
2385 BuildMI(MBB, DL, TII->get(SystemZ::PHI), CmpVal)
2386 .addReg(OrigCmpVal).addMBB(StartMBB)
2387 .addReg(RetryCmpVal).addMBB(SetMBB);
2388 BuildMI(MBB, DL, TII->get(SystemZ::PHI), SwapVal)
2389 .addReg(OrigSwapVal).addMBB(StartMBB)
2390 .addReg(RetrySwapVal).addMBB(SetMBB);
2391 BuildMI(MBB, DL, TII->get(SystemZ::RLL), Dest)
2392 .addReg(OldVal).addReg(BitShift).addImm(BitSize);
2393 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RetryCmpVal)
2394 .addReg(CmpVal).addReg(Dest).addImm(32).addImm(63 - BitSize).addImm(0);
2395 BuildMI(MBB, DL, TII->get(SystemZ::CR))
2396 .addReg(Dest).addReg(RetryCmpVal);
2397 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2398 .addImm(SystemZ::CCMASK_ICMP)
2399 .addImm(SystemZ::CCMASK_CMP_NE).addMBB(DoneMBB);
2400 MBB->addSuccessor(DoneMBB);
2401 MBB->addSuccessor(SetMBB);
2404 // %RetrySwapVal = RISBG32 %SwapVal, %Dest, 32, 63-BitSize, 0
2405 // ^^ Replace the upper 32-BitSize bits of the new
2406 // value with those that we loaded.
2407 // %StoreVal = RLL %RetrySwapVal, -BitSize(%NegBitShift)
2408 // ^^ Rotate the new field to its proper position.
2409 // %RetryOldVal = CS %Dest, %StoreVal, Disp(%Base)
2411 // # fall through to ExitMMB
2413 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RetrySwapVal)
2414 .addReg(SwapVal).addReg(Dest).addImm(32).addImm(63 - BitSize).addImm(0);
2415 BuildMI(MBB, DL, TII->get(SystemZ::RLL), StoreVal)
2416 .addReg(RetrySwapVal).addReg(NegBitShift).addImm(-BitSize);
2417 BuildMI(MBB, DL, TII->get(CSOpcode), RetryOldVal)
2418 .addReg(OldVal).addReg(StoreVal).addOperand(Base).addImm(Disp);
2419 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2420 .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
2421 MBB->addSuccessor(LoopMBB);
2422 MBB->addSuccessor(DoneMBB);
2424 MI->eraseFromParent();
2428 // Emit an extension from a GR32 or GR64 to a GR128. ClearEven is true
2429 // if the high register of the GR128 value must be cleared or false if
2430 // it's "don't care". SubReg is subreg_odd32 when extending a GR32
2431 // and subreg_odd when extending a GR64.
2433 SystemZTargetLowering::emitExt128(MachineInstr *MI,
2434 MachineBasicBlock *MBB,
2435 bool ClearEven, unsigned SubReg) const {
2436 const SystemZInstrInfo *TII = TM.getInstrInfo();
2437 MachineFunction &MF = *MBB->getParent();
2438 MachineRegisterInfo &MRI = MF.getRegInfo();
2439 DebugLoc DL = MI->getDebugLoc();
2441 unsigned Dest = MI->getOperand(0).getReg();
2442 unsigned Src = MI->getOperand(1).getReg();
2443 unsigned In128 = MRI.createVirtualRegister(&SystemZ::GR128BitRegClass);
2445 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::IMPLICIT_DEF), In128);
2447 unsigned NewIn128 = MRI.createVirtualRegister(&SystemZ::GR128BitRegClass);
2448 unsigned Zero64 = MRI.createVirtualRegister(&SystemZ::GR64BitRegClass);
2450 BuildMI(*MBB, MI, DL, TII->get(SystemZ::LLILL), Zero64)
2452 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::INSERT_SUBREG), NewIn128)
2453 .addReg(In128).addReg(Zero64).addImm(SystemZ::subreg_high);
2456 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::INSERT_SUBREG), Dest)
2457 .addReg(In128).addReg(Src).addImm(SubReg);
2459 MI->eraseFromParent();
2464 SystemZTargetLowering::emitMemMemWrapper(MachineInstr *MI,
2465 MachineBasicBlock *MBB,
2466 unsigned Opcode) const {
2467 const SystemZInstrInfo *TII = TM.getInstrInfo();
2468 DebugLoc DL = MI->getDebugLoc();
2470 MachineOperand DestBase = MI->getOperand(0);
2471 uint64_t DestDisp = MI->getOperand(1).getImm();
2472 MachineOperand SrcBase = MI->getOperand(2);
2473 uint64_t SrcDisp = MI->getOperand(3).getImm();
2474 uint64_t Length = MI->getOperand(4).getImm();
2476 BuildMI(*MBB, MI, DL, TII->get(Opcode))
2477 .addOperand(DestBase).addImm(DestDisp).addImm(Length)
2478 .addOperand(SrcBase).addImm(SrcDisp);
2480 MI->eraseFromParent();
2484 // Decompose string pseudo-instruction MI into a loop that continually performs
2485 // Opcode until CC != 3.
2487 SystemZTargetLowering::emitStringWrapper(MachineInstr *MI,
2488 MachineBasicBlock *MBB,
2489 unsigned Opcode) const {
2490 const SystemZInstrInfo *TII = TM.getInstrInfo();
2491 MachineFunction &MF = *MBB->getParent();
2492 MachineRegisterInfo &MRI = MF.getRegInfo();
2493 DebugLoc DL = MI->getDebugLoc();
2495 uint64_t End1Reg = MI->getOperand(0).getReg();
2496 uint64_t Start1Reg = MI->getOperand(1).getReg();
2497 uint64_t Start2Reg = MI->getOperand(2).getReg();
2498 uint64_t CharReg = MI->getOperand(3).getReg();
2500 const TargetRegisterClass *RC = &SystemZ::GR64BitRegClass;
2501 uint64_t This1Reg = MRI.createVirtualRegister(RC);
2502 uint64_t This2Reg = MRI.createVirtualRegister(RC);
2503 uint64_t End2Reg = MRI.createVirtualRegister(RC);
2505 MachineBasicBlock *StartMBB = MBB;
2506 MachineBasicBlock *DoneMBB = splitBlockAfter(MI, MBB);
2507 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
2510 // # fall through to LoopMMB
2511 MBB->addSuccessor(LoopMBB);
2514 // %This1Reg = phi [ %Start1Reg, StartMBB ], [ %End1Reg, LoopMBB ]
2515 // %This2Reg = phi [ %Start2Reg, StartMBB ], [ %End2Reg, LoopMBB ]
2517 // %End1Reg, %End2Reg = CLST %This1Reg, %This2Reg -- uses R0W
2519 // # fall through to DoneMMB
2521 // The load of R0W can be hoisted by post-RA LICM.
2524 BuildMI(MBB, DL, TII->get(SystemZ::PHI), This1Reg)
2525 .addReg(Start1Reg).addMBB(StartMBB)
2526 .addReg(End1Reg).addMBB(LoopMBB);
2527 BuildMI(MBB, DL, TII->get(SystemZ::PHI), This2Reg)
2528 .addReg(Start2Reg).addMBB(StartMBB)
2529 .addReg(End2Reg).addMBB(LoopMBB);
2530 BuildMI(MBB, DL, TII->get(TargetOpcode::COPY), SystemZ::R0W).addReg(CharReg);
2531 BuildMI(MBB, DL, TII->get(Opcode))
2532 .addReg(End1Reg, RegState::Define).addReg(End2Reg, RegState::Define)
2533 .addReg(This1Reg).addReg(This2Reg);
2534 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2535 .addImm(SystemZ::CCMASK_ANY).addImm(SystemZ::CCMASK_3).addMBB(LoopMBB);
2536 MBB->addSuccessor(LoopMBB);
2537 MBB->addSuccessor(DoneMBB);
2539 DoneMBB->addLiveIn(SystemZ::CC);
2541 MI->eraseFromParent();
2545 MachineBasicBlock *SystemZTargetLowering::
2546 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const {
2547 switch (MI->getOpcode()) {
2548 case SystemZ::Select32:
2549 case SystemZ::SelectF32:
2550 case SystemZ::Select64:
2551 case SystemZ::SelectF64:
2552 case SystemZ::SelectF128:
2553 return emitSelect(MI, MBB);
2555 case SystemZ::CondStore8_32:
2556 return emitCondStore(MI, MBB, SystemZ::STC32, 0, false);
2557 case SystemZ::CondStore8_32Inv:
2558 return emitCondStore(MI, MBB, SystemZ::STC32, 0, true);
2559 case SystemZ::CondStore16_32:
2560 return emitCondStore(MI, MBB, SystemZ::STH32, 0, false);
2561 case SystemZ::CondStore16_32Inv:
2562 return emitCondStore(MI, MBB, SystemZ::STH32, 0, true);
2563 case SystemZ::CondStore32_32:
2564 return emitCondStore(MI, MBB, SystemZ::ST32, SystemZ::STOC32, false);
2565 case SystemZ::CondStore32_32Inv:
2566 return emitCondStore(MI, MBB, SystemZ::ST32, SystemZ::STOC32, true);
2567 case SystemZ::CondStore8:
2568 return emitCondStore(MI, MBB, SystemZ::STC, 0, false);
2569 case SystemZ::CondStore8Inv:
2570 return emitCondStore(MI, MBB, SystemZ::STC, 0, true);
2571 case SystemZ::CondStore16:
2572 return emitCondStore(MI, MBB, SystemZ::STH, 0, false);
2573 case SystemZ::CondStore16Inv:
2574 return emitCondStore(MI, MBB, SystemZ::STH, 0, true);
2575 case SystemZ::CondStore32:
2576 return emitCondStore(MI, MBB, SystemZ::ST, SystemZ::STOC, false);
2577 case SystemZ::CondStore32Inv:
2578 return emitCondStore(MI, MBB, SystemZ::ST, SystemZ::STOC, true);
2579 case SystemZ::CondStore64:
2580 return emitCondStore(MI, MBB, SystemZ::STG, SystemZ::STOCG, false);
2581 case SystemZ::CondStore64Inv:
2582 return emitCondStore(MI, MBB, SystemZ::STG, SystemZ::STOCG, true);
2583 case SystemZ::CondStoreF32:
2584 return emitCondStore(MI, MBB, SystemZ::STE, 0, false);
2585 case SystemZ::CondStoreF32Inv:
2586 return emitCondStore(MI, MBB, SystemZ::STE, 0, true);
2587 case SystemZ::CondStoreF64:
2588 return emitCondStore(MI, MBB, SystemZ::STD, 0, false);
2589 case SystemZ::CondStoreF64Inv:
2590 return emitCondStore(MI, MBB, SystemZ::STD, 0, true);
2592 case SystemZ::AEXT128_64:
2593 return emitExt128(MI, MBB, false, SystemZ::subreg_low);
2594 case SystemZ::ZEXT128_32:
2595 return emitExt128(MI, MBB, true, SystemZ::subreg_low32);
2596 case SystemZ::ZEXT128_64:
2597 return emitExt128(MI, MBB, true, SystemZ::subreg_low);
2599 case SystemZ::ATOMIC_SWAPW:
2600 return emitAtomicLoadBinary(MI, MBB, 0, 0);
2601 case SystemZ::ATOMIC_SWAP_32:
2602 return emitAtomicLoadBinary(MI, MBB, 0, 32);
2603 case SystemZ::ATOMIC_SWAP_64:
2604 return emitAtomicLoadBinary(MI, MBB, 0, 64);
2606 case SystemZ::ATOMIC_LOADW_AR:
2607 return emitAtomicLoadBinary(MI, MBB, SystemZ::AR, 0);
2608 case SystemZ::ATOMIC_LOADW_AFI:
2609 return emitAtomicLoadBinary(MI, MBB, SystemZ::AFI, 0);
2610 case SystemZ::ATOMIC_LOAD_AR:
2611 return emitAtomicLoadBinary(MI, MBB, SystemZ::AR, 32);
2612 case SystemZ::ATOMIC_LOAD_AHI:
2613 return emitAtomicLoadBinary(MI, MBB, SystemZ::AHI, 32);
2614 case SystemZ::ATOMIC_LOAD_AFI:
2615 return emitAtomicLoadBinary(MI, MBB, SystemZ::AFI, 32);
2616 case SystemZ::ATOMIC_LOAD_AGR:
2617 return emitAtomicLoadBinary(MI, MBB, SystemZ::AGR, 64);
2618 case SystemZ::ATOMIC_LOAD_AGHI:
2619 return emitAtomicLoadBinary(MI, MBB, SystemZ::AGHI, 64);
2620 case SystemZ::ATOMIC_LOAD_AGFI:
2621 return emitAtomicLoadBinary(MI, MBB, SystemZ::AGFI, 64);
2623 case SystemZ::ATOMIC_LOADW_SR:
2624 return emitAtomicLoadBinary(MI, MBB, SystemZ::SR, 0);
2625 case SystemZ::ATOMIC_LOAD_SR:
2626 return emitAtomicLoadBinary(MI, MBB, SystemZ::SR, 32);
2627 case SystemZ::ATOMIC_LOAD_SGR:
2628 return emitAtomicLoadBinary(MI, MBB, SystemZ::SGR, 64);
2630 case SystemZ::ATOMIC_LOADW_NR:
2631 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 0);
2632 case SystemZ::ATOMIC_LOADW_NILH:
2633 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH32, 0);
2634 case SystemZ::ATOMIC_LOAD_NR:
2635 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 32);
2636 case SystemZ::ATOMIC_LOAD_NILL32:
2637 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL32, 32);
2638 case SystemZ::ATOMIC_LOAD_NILH32:
2639 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH32, 32);
2640 case SystemZ::ATOMIC_LOAD_NILF32:
2641 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF32, 32);
2642 case SystemZ::ATOMIC_LOAD_NGR:
2643 return emitAtomicLoadBinary(MI, MBB, SystemZ::NGR, 64);
2644 case SystemZ::ATOMIC_LOAD_NILL:
2645 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL, 64);
2646 case SystemZ::ATOMIC_LOAD_NILH:
2647 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 64);
2648 case SystemZ::ATOMIC_LOAD_NIHL:
2649 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHL, 64);
2650 case SystemZ::ATOMIC_LOAD_NIHH:
2651 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHH, 64);
2652 case SystemZ::ATOMIC_LOAD_NILF:
2653 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF, 64);
2654 case SystemZ::ATOMIC_LOAD_NIHF:
2655 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHF, 64);
2657 case SystemZ::ATOMIC_LOADW_OR:
2658 return emitAtomicLoadBinary(MI, MBB, SystemZ::OR, 0);
2659 case SystemZ::ATOMIC_LOADW_OILH:
2660 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILH32, 0);
2661 case SystemZ::ATOMIC_LOAD_OR:
2662 return emitAtomicLoadBinary(MI, MBB, SystemZ::OR, 32);
2663 case SystemZ::ATOMIC_LOAD_OILL32:
2664 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILL32, 32);
2665 case SystemZ::ATOMIC_LOAD_OILH32:
2666 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILH32, 32);
2667 case SystemZ::ATOMIC_LOAD_OILF32:
2668 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILF32, 32);
2669 case SystemZ::ATOMIC_LOAD_OGR:
2670 return emitAtomicLoadBinary(MI, MBB, SystemZ::OGR, 64);
2671 case SystemZ::ATOMIC_LOAD_OILL:
2672 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILL, 64);
2673 case SystemZ::ATOMIC_LOAD_OILH:
2674 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILH, 64);
2675 case SystemZ::ATOMIC_LOAD_OIHL:
2676 return emitAtomicLoadBinary(MI, MBB, SystemZ::OIHL, 64);
2677 case SystemZ::ATOMIC_LOAD_OIHH:
2678 return emitAtomicLoadBinary(MI, MBB, SystemZ::OIHH, 64);
2679 case SystemZ::ATOMIC_LOAD_OILF:
2680 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILF, 64);
2681 case SystemZ::ATOMIC_LOAD_OIHF:
2682 return emitAtomicLoadBinary(MI, MBB, SystemZ::OIHF, 64);
2684 case SystemZ::ATOMIC_LOADW_XR:
2685 return emitAtomicLoadBinary(MI, MBB, SystemZ::XR, 0);
2686 case SystemZ::ATOMIC_LOADW_XILF:
2687 return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF32, 0);
2688 case SystemZ::ATOMIC_LOAD_XR:
2689 return emitAtomicLoadBinary(MI, MBB, SystemZ::XR, 32);
2690 case SystemZ::ATOMIC_LOAD_XILF32:
2691 return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF32, 32);
2692 case SystemZ::ATOMIC_LOAD_XGR:
2693 return emitAtomicLoadBinary(MI, MBB, SystemZ::XGR, 64);
2694 case SystemZ::ATOMIC_LOAD_XILF:
2695 return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF, 64);
2696 case SystemZ::ATOMIC_LOAD_XIHF:
2697 return emitAtomicLoadBinary(MI, MBB, SystemZ::XIHF, 64);
2699 case SystemZ::ATOMIC_LOADW_NRi:
2700 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 0, true);
2701 case SystemZ::ATOMIC_LOADW_NILHi:
2702 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH32, 0, true);
2703 case SystemZ::ATOMIC_LOAD_NRi:
2704 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 32, true);
2705 case SystemZ::ATOMIC_LOAD_NILL32i:
2706 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL32, 32, true);
2707 case SystemZ::ATOMIC_LOAD_NILH32i:
2708 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH32, 32, true);
2709 case SystemZ::ATOMIC_LOAD_NILF32i:
2710 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF32, 32, true);
2711 case SystemZ::ATOMIC_LOAD_NGRi:
2712 return emitAtomicLoadBinary(MI, MBB, SystemZ::NGR, 64, true);
2713 case SystemZ::ATOMIC_LOAD_NILLi:
2714 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL, 64, true);
2715 case SystemZ::ATOMIC_LOAD_NILHi:
2716 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 64, true);
2717 case SystemZ::ATOMIC_LOAD_NIHLi:
2718 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHL, 64, true);
2719 case SystemZ::ATOMIC_LOAD_NIHHi:
2720 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHH, 64, true);
2721 case SystemZ::ATOMIC_LOAD_NILFi:
2722 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF, 64, true);
2723 case SystemZ::ATOMIC_LOAD_NIHFi:
2724 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHF, 64, true);
2726 case SystemZ::ATOMIC_LOADW_MIN:
2727 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
2728 SystemZ::CCMASK_CMP_LE, 0);
2729 case SystemZ::ATOMIC_LOAD_MIN_32:
2730 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
2731 SystemZ::CCMASK_CMP_LE, 32);
2732 case SystemZ::ATOMIC_LOAD_MIN_64:
2733 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CGR,
2734 SystemZ::CCMASK_CMP_LE, 64);
2736 case SystemZ::ATOMIC_LOADW_MAX:
2737 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
2738 SystemZ::CCMASK_CMP_GE, 0);
2739 case SystemZ::ATOMIC_LOAD_MAX_32:
2740 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
2741 SystemZ::CCMASK_CMP_GE, 32);
2742 case SystemZ::ATOMIC_LOAD_MAX_64:
2743 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CGR,
2744 SystemZ::CCMASK_CMP_GE, 64);
2746 case SystemZ::ATOMIC_LOADW_UMIN:
2747 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
2748 SystemZ::CCMASK_CMP_LE, 0);
2749 case SystemZ::ATOMIC_LOAD_UMIN_32:
2750 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
2751 SystemZ::CCMASK_CMP_LE, 32);
2752 case SystemZ::ATOMIC_LOAD_UMIN_64:
2753 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLGR,
2754 SystemZ::CCMASK_CMP_LE, 64);
2756 case SystemZ::ATOMIC_LOADW_UMAX:
2757 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
2758 SystemZ::CCMASK_CMP_GE, 0);
2759 case SystemZ::ATOMIC_LOAD_UMAX_32:
2760 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
2761 SystemZ::CCMASK_CMP_GE, 32);
2762 case SystemZ::ATOMIC_LOAD_UMAX_64:
2763 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLGR,
2764 SystemZ::CCMASK_CMP_GE, 64);
2766 case SystemZ::ATOMIC_CMP_SWAPW:
2767 return emitAtomicCmpSwapW(MI, MBB);
2768 case SystemZ::MVCWrapper:
2769 return emitMemMemWrapper(MI, MBB, SystemZ::MVC);
2770 case SystemZ::CLCWrapper:
2771 return emitMemMemWrapper(MI, MBB, SystemZ::CLC);
2772 case SystemZ::CLSTLoop:
2773 return emitStringWrapper(MI, MBB, SystemZ::CLST);
2774 case SystemZ::MVSTLoop:
2775 return emitStringWrapper(MI, MBB, SystemZ::MVST);
2776 case SystemZ::SRSTLoop:
2777 return emitStringWrapper(MI, MBB, SystemZ::SRST);
2779 llvm_unreachable("Unexpected instr type to insert");