1 //===-- SystemZISelLowering.cpp - SystemZ DAG Lowering Implementation -----==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SystemZTargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "systemz-lower"
16 #include "SystemZISelLowering.h"
18 #include "SystemZTargetMachine.h"
19 #include "SystemZSubtarget.h"
20 #include "llvm/DerivedTypes.h"
21 #include "llvm/Function.h"
22 #include "llvm/Intrinsics.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/GlobalVariable.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/CodeGen/CallingConvLower.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/PseudoSourceValue.h"
32 #include "llvm/CodeGen/SelectionDAGISel.h"
33 #include "llvm/CodeGen/ValueTypes.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Target/TargetOptions.h"
36 #include "llvm/ADT/VectorExtras.h"
39 SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm) :
40 TargetLowering(tm), Subtarget(*tm.getSubtargetImpl()), TM(tm) {
42 RegInfo = TM.getRegisterInfo();
44 // Set up the register classes.
45 addRegisterClass(MVT::i32, SystemZ::GR32RegisterClass);
46 addRegisterClass(MVT::i64, SystemZ::GR64RegisterClass);
47 addRegisterClass(MVT::v2i32,SystemZ::GR64PRegisterClass);
48 addRegisterClass(MVT::v2i64,SystemZ::GR128RegisterClass);
51 addRegisterClass(MVT::f32, SystemZ::FP32RegisterClass);
52 addRegisterClass(MVT::f64, SystemZ::FP64RegisterClass);
54 addLegalFPImmediate(APFloat(+0.0)); // lzer
55 addLegalFPImmediate(APFloat(+0.0f)); // lzdr
56 addLegalFPImmediate(APFloat(-0.0)); // lzer + lner
57 addLegalFPImmediate(APFloat(-0.0f)); // lzdr + lndr
60 // Compute derived properties from the register classes
61 computeRegisterProperties();
63 // Set shifts properties
64 setShiftAmountFlavor(Extend);
65 setShiftAmountType(MVT::i64);
67 // Provide all sorts of operation actions
68 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
69 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
70 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
72 setLoadExtAction(ISD::SEXTLOAD, MVT::f32, Expand);
73 setLoadExtAction(ISD::ZEXTLOAD, MVT::f32, Expand);
74 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
76 setLoadExtAction(ISD::SEXTLOAD, MVT::f64, Expand);
77 setLoadExtAction(ISD::ZEXTLOAD, MVT::f64, Expand);
78 setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand);
80 setStackPointerRegisterToSaveRestore(SystemZ::R15D);
81 setSchedulingPreference(SchedulingForLatency);
82 setBooleanContents(ZeroOrOneBooleanContent);
84 setOperationAction(ISD::RET, MVT::Other, Custom);
86 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
87 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
88 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
89 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
90 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
91 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
92 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
93 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
94 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
95 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
96 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
98 setOperationAction(ISD::SDIV, MVT::i32, Expand);
99 setOperationAction(ISD::UDIV, MVT::i32, Expand);
100 setOperationAction(ISD::SDIV, MVT::i64, Expand);
101 setOperationAction(ISD::UDIV, MVT::i64, Expand);
102 setOperationAction(ISD::SREM, MVT::i32, Expand);
103 setOperationAction(ISD::UREM, MVT::i32, Expand);
104 setOperationAction(ISD::SREM, MVT::i64, Expand);
105 setOperationAction(ISD::UREM, MVT::i64, Expand);
107 // FIXME: Can we lower these 2 efficiently?
108 setOperationAction(ISD::SETCC, MVT::i32, Expand);
109 setOperationAction(ISD::SETCC, MVT::i64, Expand);
110 setOperationAction(ISD::SETCC, MVT::f32, Expand);
111 setOperationAction(ISD::SETCC, MVT::f64, Expand);
112 setOperationAction(ISD::SELECT, MVT::i32, Expand);
113 setOperationAction(ISD::SELECT, MVT::i64, Expand);
114 setOperationAction(ISD::SELECT, MVT::f32, Expand);
115 setOperationAction(ISD::SELECT, MVT::f64, Expand);
116 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
117 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
118 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
119 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
121 // Funny enough: we don't have 64-bit signed versions of these stuff, but have
123 setOperationAction(ISD::MULHS, MVT::i64, Expand);
124 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
126 // Lower some FP stuff
127 setOperationAction(ISD::FSIN, MVT::f32, Expand);
128 setOperationAction(ISD::FSIN, MVT::f64, Expand);
129 setOperationAction(ISD::FCOS, MVT::f32, Expand);
130 setOperationAction(ISD::FCOS, MVT::f64, Expand);
132 // We have only 64-bit bitconverts
133 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Promote);
134 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Promote);
136 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
137 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
138 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
139 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
141 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
144 SDValue SystemZTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
145 switch (Op.getOpcode()) {
146 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
147 case ISD::RET: return LowerRET(Op, DAG);
148 case ISD::CALL: return LowerCALL(Op, DAG);
149 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
150 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
151 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
152 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
153 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
155 assert(0 && "unimplemented operand");
160 //===----------------------------------------------------------------------===//
161 // Calling Convention Implementation
162 //===----------------------------------------------------------------------===//
164 #include "SystemZGenCallingConv.inc"
166 SDValue SystemZTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op,
168 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
171 assert(0 && "Unsupported calling convention");
173 case CallingConv::Fast:
174 return LowerCCCArguments(Op, DAG);
178 SDValue SystemZTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
179 CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
180 unsigned CallingConv = TheCall->getCallingConv();
181 switch (CallingConv) {
183 assert(0 && "Unsupported calling convention");
184 case CallingConv::Fast:
186 return LowerCCCCallTo(Op, DAG, CallingConv);
190 /// LowerCCCArguments - transform physical registers into virtual registers and
191 /// generate load operations for arguments places on the stack.
192 // FIXME: struct return stuff
194 SDValue SystemZTargetLowering::LowerCCCArguments(SDValue Op,
196 MachineFunction &MF = DAG.getMachineFunction();
197 MachineFrameInfo *MFI = MF.getFrameInfo();
198 MachineRegisterInfo &RegInfo = MF.getRegInfo();
199 SDValue Root = Op.getOperand(0);
200 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
201 unsigned CC = MF.getFunction()->getCallingConv();
202 DebugLoc dl = Op.getDebugLoc();
204 // Assign locations to all of the incoming arguments.
205 SmallVector<CCValAssign, 16> ArgLocs;
206 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
207 CCInfo.AnalyzeFormalArguments(Op.getNode(), CC_SystemZ);
209 assert(!isVarArg && "Varargs not supported yet");
211 SmallVector<SDValue, 16> ArgValues;
212 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
214 CCValAssign &VA = ArgLocs[i];
215 MVT LocVT = VA.getLocVT();
217 // Arguments passed in registers
218 TargetRegisterClass *RC;
219 switch (LocVT.getSimpleVT()) {
221 cerr << "LowerFORMAL_ARGUMENTS Unhandled argument type: "
222 << LocVT.getSimpleVT()
226 RC = SystemZ::GR64RegisterClass;
229 RC = SystemZ::FP32RegisterClass;
232 RC = SystemZ::FP64RegisterClass;
236 unsigned VReg = RegInfo.createVirtualRegister(RC);
237 RegInfo.addLiveIn(VA.getLocReg(), VReg);
238 ArgValue = DAG.getCopyFromReg(Root, dl, VReg, LocVT);
241 assert(VA.isMemLoc());
243 // Create the nodes corresponding to a load from this parameter slot.
244 // Create the frame index object for this incoming parameter...
245 int FI = MFI->CreateFixedObject(LocVT.getSizeInBits()/8,
246 VA.getLocMemOffset());
248 // Create the SelectionDAG nodes corresponding to a load
249 // from this parameter
250 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
251 ArgValue = DAG.getLoad(LocVT, dl, Root, FIN,
252 PseudoSourceValue::getFixedStack(FI), 0);
255 // If this is an 8/16/32-bit value, it is really passed promoted to 64
256 // bits. Insert an assert[sz]ext to capture this, then truncate to the
258 if (VA.getLocInfo() == CCValAssign::SExt)
259 ArgValue = DAG.getNode(ISD::AssertSext, dl, LocVT, ArgValue,
260 DAG.getValueType(VA.getValVT()));
261 else if (VA.getLocInfo() == CCValAssign::ZExt)
262 ArgValue = DAG.getNode(ISD::AssertZext, dl, LocVT, ArgValue,
263 DAG.getValueType(VA.getValVT()));
265 if (VA.getLocInfo() != CCValAssign::Full)
266 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
268 ArgValues.push_back(ArgValue);
271 ArgValues.push_back(Root);
273 // Return the new list of results.
274 return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
275 &ArgValues[0], ArgValues.size()).getValue(Op.getResNo());
278 /// LowerCCCCallTo - functions arguments are copied from virtual regs to
279 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
281 SDValue SystemZTargetLowering::LowerCCCCallTo(SDValue Op, SelectionDAG &DAG,
283 CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
284 SDValue Chain = TheCall->getChain();
285 SDValue Callee = TheCall->getCallee();
286 bool isVarArg = TheCall->isVarArg();
287 DebugLoc dl = Op.getDebugLoc();
288 MachineFunction &MF = DAG.getMachineFunction();
290 // Offset to first argument stack slot.
291 const unsigned FirstArgOffset = 160;
293 // Analyze operands of the call, assigning locations to each operand.
294 SmallVector<CCValAssign, 16> ArgLocs;
295 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
297 CCInfo.AnalyzeCallOperands(TheCall, CC_SystemZ);
299 // Get a count of how many bytes are to be pushed on the stack.
300 unsigned NumBytes = CCInfo.getNextStackOffset();
302 Chain = DAG.getCALLSEQ_START(Chain ,DAG.getConstant(NumBytes,
303 getPointerTy(), true));
305 SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
306 SmallVector<SDValue, 12> MemOpChains;
309 // Walk the register/memloc assignments, inserting copies/loads.
310 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
311 CCValAssign &VA = ArgLocs[i];
313 // Arguments start after the 5 first operands of ISD::CALL
314 SDValue Arg = TheCall->getArg(i);
316 // Promote the value if needed.
317 switch (VA.getLocInfo()) {
318 default: assert(0 && "Unknown loc info!");
319 case CCValAssign::Full: break;
320 case CCValAssign::SExt:
321 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
323 case CCValAssign::ZExt:
324 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
326 case CCValAssign::AExt:
327 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
331 // Arguments that can be passed on register must be kept at RegsToPass
334 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
336 assert(VA.isMemLoc());
338 if (StackPtr.getNode() == 0)
340 DAG.getCopyFromReg(Chain, dl,
341 (RegInfo->hasFP(MF) ?
342 SystemZ::R11D : SystemZ::R15D),
345 unsigned Offset = FirstArgOffset + VA.getLocMemOffset();
346 SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(),
348 DAG.getIntPtrConstant(Offset));
350 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
351 PseudoSourceValue::getStack(), Offset));
355 // Transform all store nodes into one single node because all store nodes are
356 // independent of each other.
357 if (!MemOpChains.empty())
358 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
359 &MemOpChains[0], MemOpChains.size());
361 // Build a sequence of copy-to-reg nodes chained together with token chain and
362 // flag operands which copy the outgoing args into registers. The InFlag in
363 // necessary since all emited instructions must be stuck together.
365 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
366 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
367 RegsToPass[i].second, InFlag);
368 InFlag = Chain.getValue(1);
371 // If the callee is a GlobalAddress node (quite common, every direct call is)
372 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
373 // Likewise ExternalSymbol -> TargetExternalSymbol.
374 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
375 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
376 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
377 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), getPointerTy());
379 // Returns a chain & a flag for retval copy to use.
380 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
381 SmallVector<SDValue, 8> Ops;
382 Ops.push_back(Chain);
383 Ops.push_back(Callee);
385 // Add argument registers to the end of the list so that they are
386 // known live into the call.
387 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
388 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
389 RegsToPass[i].second.getValueType()));
391 if (InFlag.getNode())
392 Ops.push_back(InFlag);
394 Chain = DAG.getNode(SystemZISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
395 InFlag = Chain.getValue(1);
397 // Create the CALLSEQ_END node.
398 Chain = DAG.getCALLSEQ_END(Chain,
399 DAG.getConstant(NumBytes, getPointerTy(), true),
400 DAG.getConstant(0, getPointerTy(), true),
402 InFlag = Chain.getValue(1);
404 // Handle result values, copying them out of physregs into vregs that we
406 return SDValue(LowerCallResult(Chain, InFlag, TheCall, CC, DAG),
410 /// LowerCallResult - Lower the result values of an ISD::CALL into the
411 /// appropriate copies out of appropriate physical registers. This assumes that
412 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
413 /// being lowered. Returns a SDNode with the same number of values as the
416 SystemZTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
418 unsigned CallingConv,
420 bool isVarArg = TheCall->isVarArg();
421 DebugLoc dl = TheCall->getDebugLoc();
423 // Assign locations to each value returned by this call.
424 SmallVector<CCValAssign, 16> RVLocs;
425 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
427 CCInfo.AnalyzeCallResult(TheCall, RetCC_SystemZ);
428 SmallVector<SDValue, 8> ResultVals;
430 // Copy all of the result registers out of their specified physreg.
431 for (unsigned i = 0; i != RVLocs.size(); ++i) {
432 CCValAssign &VA = RVLocs[i];
434 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
435 VA.getLocVT(), InFlag).getValue(1);
436 SDValue RetValue = Chain.getValue(0);
437 InFlag = Chain.getValue(2);
439 // If this is an 8/16/32-bit value, it is really passed promoted to 64
440 // bits. Insert an assert[sz]ext to capture this, then truncate to the
442 if (VA.getLocInfo() == CCValAssign::SExt)
443 RetValue = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), RetValue,
444 DAG.getValueType(VA.getValVT()));
445 else if (VA.getLocInfo() == CCValAssign::ZExt)
446 RetValue = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), RetValue,
447 DAG.getValueType(VA.getValVT()));
449 if (VA.getLocInfo() != CCValAssign::Full)
450 RetValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), RetValue);
452 ResultVals.push_back(RetValue);
455 ResultVals.push_back(Chain);
457 // Merge everything together with a MERGE_VALUES node.
458 return DAG.getNode(ISD::MERGE_VALUES, dl, TheCall->getVTList(),
459 &ResultVals[0], ResultVals.size()).getNode();
463 SDValue SystemZTargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) {
464 // CCValAssign - represent the assignment of the return value to a location
465 SmallVector<CCValAssign, 16> RVLocs;
466 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
467 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
468 DebugLoc dl = Op.getDebugLoc();
470 // CCState - Info about the registers and stack slot.
471 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
473 // Analize return values of ISD::RET
474 CCInfo.AnalyzeReturn(Op.getNode(), RetCC_SystemZ);
476 // If this is the first return lowered for this function, add the regs to the
477 // liveout set for the function.
478 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
479 for (unsigned i = 0; i != RVLocs.size(); ++i)
480 if (RVLocs[i].isRegLoc())
481 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
484 // The chain is always operand #0
485 SDValue Chain = Op.getOperand(0);
488 // Copy the result values into the output registers.
489 for (unsigned i = 0; i != RVLocs.size(); ++i) {
490 CCValAssign &VA = RVLocs[i];
491 SDValue ResValue = Op.getOperand(i*2+1);
492 assert(VA.isRegLoc() && "Can only return in registers!");
494 // If this is an 8/16/32-bit value, it is really should be passed promoted
496 if (VA.getLocInfo() == CCValAssign::SExt)
497 ResValue = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ResValue);
498 else if (VA.getLocInfo() == CCValAssign::ZExt)
499 ResValue = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ResValue);
500 else if (VA.getLocInfo() == CCValAssign::AExt)
501 ResValue = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ResValue);
503 // ISD::RET => ret chain, (regnum1,val1), ...
504 // So i*2+1 index only the regnums
505 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ResValue, Flag);
507 // Guarantee that all emitted copies are stuck together,
508 // avoiding something bad.
509 Flag = Chain.getValue(1);
513 return DAG.getNode(SystemZISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
516 return DAG.getNode(SystemZISD::RET_FLAG, dl, MVT::Other, Chain);
519 SDValue SystemZTargetLowering::EmitCmp(SDValue LHS, SDValue RHS,
520 ISD::CondCode CC, SDValue &SystemZCC,
522 // FIXME: Emit a test if RHS is zero
524 bool isUnsigned = false;
525 SystemZCC::CondCodes TCC;
527 default: assert(0 && "Invalid integer condition!");
533 TCC = SystemZCC::NLH;
549 if (LHS.getValueType().isFloatingPoint()) {
553 isUnsigned = true; // FALLTHROUGH
559 if (LHS.getValueType().isFloatingPoint()) {
563 isUnsigned = true; // FALLTHROUGH
569 if (LHS.getValueType().isFloatingPoint()) {
570 TCC = SystemZCC::NLE;
573 isUnsigned = true; // FALLTHROUGH
579 if (LHS.getValueType().isFloatingPoint()) {
580 TCC = SystemZCC::NHE;
583 isUnsigned = true; // FALLTHROUGH
590 SystemZCC = DAG.getConstant(TCC, MVT::i32);
592 DebugLoc dl = LHS.getDebugLoc();
593 return DAG.getNode((isUnsigned ? SystemZISD::UCMP : SystemZISD::CMP),
594 dl, MVT::Flag, LHS, RHS);
598 SDValue SystemZTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) {
599 SDValue Chain = Op.getOperand(0);
600 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
601 SDValue LHS = Op.getOperand(2);
602 SDValue RHS = Op.getOperand(3);
603 SDValue Dest = Op.getOperand(4);
604 DebugLoc dl = Op.getDebugLoc();
607 SDValue Flag = EmitCmp(LHS, RHS, CC, SystemZCC, DAG);
608 return DAG.getNode(SystemZISD::BRCOND, dl, Op.getValueType(),
609 Chain, Dest, SystemZCC, Flag);
612 SDValue SystemZTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
613 SDValue LHS = Op.getOperand(0);
614 SDValue RHS = Op.getOperand(1);
615 SDValue TrueV = Op.getOperand(2);
616 SDValue FalseV = Op.getOperand(3);
617 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
618 DebugLoc dl = Op.getDebugLoc();
621 SDValue Flag = EmitCmp(LHS, RHS, CC, SystemZCC, DAG);
623 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
624 SmallVector<SDValue, 4> Ops;
625 Ops.push_back(TrueV);
626 Ops.push_back(FalseV);
627 Ops.push_back(SystemZCC);
630 return DAG.getNode(SystemZISD::SELECT, dl, VTs, &Ops[0], Ops.size());
633 SDValue SystemZTargetLowering::LowerGlobalAddress(SDValue Op,
635 DebugLoc dl = Op.getDebugLoc();
636 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
637 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
639 bool IsPic = getTargetMachine().getRelocationModel() == Reloc::PIC_;
640 bool ExtraLoadRequired =
641 Subtarget.GVRequiresExtraLoad(GV, getTargetMachine(), false);
644 if (!IsPic && !ExtraLoadRequired) {
645 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
648 unsigned char OpFlags = 0;
649 if (ExtraLoadRequired)
650 OpFlags = SystemZII::MO_GOTENT;
652 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), 0, OpFlags);
655 Result = DAG.getNode(SystemZISD::PCRelativeWrapper, dl,
656 getPointerTy(), Result);
658 if (ExtraLoadRequired)
659 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
660 PseudoSourceValue::getGOT(), 0);
662 // If there was a non-zero offset that we didn't fold, create an explicit
665 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
666 DAG.getConstant(Offset, getPointerTy()));
672 SDValue SystemZTargetLowering::LowerJumpTable(SDValue Op,
674 DebugLoc dl = Op.getDebugLoc();
675 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
676 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy());
678 return DAG.getNode(SystemZISD::PCRelativeWrapper, dl, getPointerTy(), Result);
683 // FIXME: This is just dirty hack. We need to lower cpool properly
684 SDValue SystemZTargetLowering::LowerConstantPool(SDValue Op,
686 DebugLoc dl = Op.getDebugLoc();
687 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
689 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
693 return DAG.getNode(SystemZISD::PCRelativeWrapper, dl, getPointerTy(), Result);
696 const char *SystemZTargetLowering::getTargetNodeName(unsigned Opcode) const {
698 case SystemZISD::RET_FLAG: return "SystemZISD::RET_FLAG";
699 case SystemZISD::CALL: return "SystemZISD::CALL";
700 case SystemZISD::BRCOND: return "SystemZISD::BRCOND";
701 case SystemZISD::CMP: return "SystemZISD::CMP";
702 case SystemZISD::UCMP: return "SystemZISD::UCMP";
703 case SystemZISD::SELECT: return "SystemZISD::SELECT";
704 case SystemZISD::PCRelativeWrapper: return "SystemZISD::PCRelativeWrapper";
705 default: return NULL;
709 //===----------------------------------------------------------------------===//
710 // Other Lowering Code
711 //===----------------------------------------------------------------------===//
714 SystemZTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
715 MachineBasicBlock *BB) const {
716 const SystemZInstrInfo &TII = *TM.getInstrInfo();
717 DebugLoc dl = MI->getDebugLoc();
718 assert((MI->getOpcode() == SystemZ::Select32 ||
719 MI->getOpcode() == SystemZ::SelectF32 ||
720 MI->getOpcode() == SystemZ::Select64 ||
721 MI->getOpcode() == SystemZ::SelectF64) &&
722 "Unexpected instr type to insert");
724 // To "insert" a SELECT instruction, we actually have to insert the diamond
725 // control-flow pattern. The incoming instruction knows the destination vreg
726 // to set, the condition code register to branch on, the true/false values to
727 // select between, and a branch opcode to use.
728 const BasicBlock *LLVM_BB = BB->getBasicBlock();
729 MachineFunction::iterator I = BB;
737 // fallthrough --> copy0MBB
738 MachineBasicBlock *thisMBB = BB;
739 MachineFunction *F = BB->getParent();
740 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
741 MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
742 SystemZCC::CondCodes CC = (SystemZCC::CondCodes)MI->getOperand(3).getImm();
743 BuildMI(BB, dl, TII.getBrCond(CC)).addMBB(copy1MBB);
744 F->insert(I, copy0MBB);
745 F->insert(I, copy1MBB);
746 // Update machine-CFG edges by transferring all successors of the current
747 // block to the new block which will contain the Phi node for the select.
748 copy1MBB->transferSuccessors(BB);
749 // Next, add the true and fallthrough blocks as its successors.
750 BB->addSuccessor(copy0MBB);
751 BB->addSuccessor(copy1MBB);
755 // # fallthrough to copy1MBB
758 // Update machine-CFG edges
759 BB->addSuccessor(copy1MBB);
762 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
765 BuildMI(BB, dl, TII.get(SystemZ::PHI),
766 MI->getOperand(0).getReg())
767 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
768 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
770 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.