1 //==-- SystemZISelDAGToDAG.cpp - A dag to dag inst selector for SystemZ ---===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the SystemZ target.
12 //===----------------------------------------------------------------------===//
15 #include "SystemZISelLowering.h"
16 #include "SystemZTargetMachine.h"
17 #include "llvm/DerivedTypes.h"
18 #include "llvm/Function.h"
19 #include "llvm/Intrinsics.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/Constants.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAG.h"
27 #include "llvm/CodeGen/SelectionDAGISel.h"
28 #include "llvm/Target/TargetLowering.h"
29 #include "llvm/Support/Compiler.h"
30 #include "llvm/Support/Debug.h"
33 /// SystemZDAGToDAGISel - SystemZ specific code to select SystemZ machine
34 /// instructions for SelectionDAG operations.
37 class SystemZDAGToDAGISel : public SelectionDAGISel {
38 SystemZTargetLowering &Lowering;
39 const SystemZSubtarget &Subtarget;
42 SystemZDAGToDAGISel(SystemZTargetMachine &TM, CodeGenOpt::Level OptLevel)
43 : SelectionDAGISel(TM, OptLevel),
44 Lowering(*TM.getTargetLowering()),
45 Subtarget(*TM.getSubtargetImpl()) { }
47 virtual void InstructionSelect();
49 virtual const char *getPassName() const {
50 return "SystemZ DAG->DAG Pattern Instruction Selection";
53 /// getI16Imm - Return a target constant with the specified value, of type
55 inline SDValue getI16Imm(uint64_t Imm) {
56 return CurDAG->getTargetConstant(Imm, MVT::i16);
59 /// getI32Imm - Return a target constant with the specified value, of type
61 inline SDValue getI32Imm(uint64_t Imm) {
62 return CurDAG->getTargetConstant(Imm, MVT::i32);
65 // Include the pieces autogenerated from the target description.
66 #include "SystemZGenDAGISel.inc"
69 SDNode *Select(SDValue Op);
70 bool SelectAddrRI(const SDValue& Op, SDValue& Addr,
71 SDValue &Base, SDValue &Disp);
77 } // end anonymous namespace
79 /// createSystemZISelDag - This pass converts a legalized DAG into a
80 /// SystemZ-specific DAG, ready for instruction scheduling.
82 FunctionPass *llvm::createSystemZISelDag(SystemZTargetMachine &TM,
83 CodeGenOpt::Level OptLevel) {
84 return new SystemZDAGToDAGISel(TM, OptLevel);
87 /// isImmSExt20 - This method tests to see if the node is either a 32-bit
88 /// or 64-bit immediate, and if the value can be accurately represented as a
89 /// sign extension from a 20-bit value. If so, this returns true and the
91 static bool isImmSExt20(SDNode *N, int32_t &Imm) {
92 if (N->getOpcode() != ISD::Constant)
95 Imm = (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
97 if (Imm >= -524288 && Imm <= 524287) {
98 if (N->getValueType(0) == MVT::i32)
99 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
101 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
107 static bool isImmSExt20(SDValue Op, int32_t &Imm) {
108 return isImmSExt20(Op.getNode(), Imm);
111 /// Returns true if the address can be represented by a base register plus
112 /// a signed 20-bit displacement [r+imm].
113 bool SystemZDAGToDAGISel::SelectAddrRI(const SDValue& Op, SDValue& Addr,
114 SDValue &Base, SDValue &Disp) {
115 // FIXME dl should come from parent load or store, not from address
116 DebugLoc dl = Addr.getDebugLoc();
117 MVT VT = Addr.getValueType();
119 if (Addr.getOpcode() == ISD::ADD) {
121 if (isImmSExt20(Addr.getOperand(1), Imm)) {
122 Disp = CurDAG->getTargetConstant(Imm, MVT::i32);
123 if (FrameIndexSDNode *FI =
124 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
125 Base = CurDAG->getTargetFrameIndex(FI->getIndex(), VT);
127 Base = Addr.getOperand(0);
129 return true; // [r+i]
131 } else if (Addr.getOpcode() == ISD::OR) {
133 if (isImmSExt20(Addr.getOperand(1), Imm)) {
134 // If this is an or of disjoint bitfields, we can codegen this as an add
135 // (for better address arithmetic) if the LHS and RHS of the OR are
136 // provably disjoint.
137 APInt LHSKnownZero, LHSKnownOne;
138 CurDAG->ComputeMaskedBits(Addr.getOperand(0),
139 APInt::getAllOnesValue(Addr.getOperand(0)
140 .getValueSizeInBits()),
141 LHSKnownZero, LHSKnownOne);
143 if ((LHSKnownZero.getZExtValue()|~(uint64_t)Imm) == ~0ULL) {
144 // If all of the bits are known zero on the LHS or RHS, the add won't
146 Base = Addr.getOperand(0);
147 Disp = CurDAG->getTargetConstant(Imm, MVT::i32);
151 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr)) {
152 // Loading from a constant address.
154 // If this address fits entirely in a 20-bit sext immediate field, codegen
157 if (isImmSExt20(CN, Imm)) {
158 Disp = CurDAG->getTargetConstant(Imm, MVT::i32);
159 Base = CurDAG->getRegister(SystemZ::R0D, MVT::i64);
164 Disp = CurDAG->getTargetConstant(0, MVT::i32);
165 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Addr))
166 Base = CurDAG->getTargetFrameIndex(FI->getIndex(), VT);
169 return true; // [r+0]
173 /// InstructionSelect - This callback is invoked by
174 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
175 void SystemZDAGToDAGISel::InstructionSelect() {
178 // Codegen the basic block.
180 DOUT << "===== Instruction selection begins:\n";
185 DOUT << "===== Instruction selection ends:\n";
188 CurDAG->RemoveDeadNodes();
191 SDNode *SystemZDAGToDAGISel::Select(SDValue Op) {
192 SDNode *Node = Op.getNode();
193 DebugLoc dl = Op.getDebugLoc();
195 // Dump information about the Node being selected
197 DOUT << std::string(Indent, ' ') << "Selecting: ";
198 DEBUG(Node->dump(CurDAG));
203 // If we have a custom node, we already have selected!
204 if (Node->isMachineOpcode()) {
206 DOUT << std::string(Indent-2, ' ') << "== ";
207 DEBUG(Node->dump(CurDAG));
214 // Select the default instruction
215 SDNode *ResNode = SelectCode(Op);
218 DOUT << std::string(Indent-2, ' ') << "=> ";
219 if (ResNode == NULL || ResNode == Op.getNode())
220 DEBUG(Op.getNode()->dump(CurDAG));
222 DEBUG(ResNode->dump(CurDAG));