1 //==-- SystemZISelDAGToDAG.cpp - A dag to dag inst selector for SystemZ ---===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the SystemZ target.
12 //===----------------------------------------------------------------------===//
15 #include "SystemZTargetMachine.h"
16 #include "llvm/DerivedTypes.h"
17 #include "llvm/Function.h"
18 #include "llvm/Intrinsics.h"
19 #include "llvm/CallingConv.h"
20 #include "llvm/Constants.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/SelectionDAG.h"
26 #include "llvm/CodeGen/SelectionDAGISel.h"
27 #include "llvm/Target/TargetLowering.h"
28 #include "llvm/Support/Compiler.h"
29 #include "llvm/Support/Debug.h"
30 #include "llvm/Support/raw_ostream.h"
34 /// SystemZRRIAddressMode - This corresponds to rriaddr, but uses SDValue's
35 /// instead of register numbers for the leaves of the matched tree.
36 struct SystemZRRIAddressMode {
42 struct { // This is really a union, discriminated by BaseType!
51 SystemZRRIAddressMode(bool RI = false)
52 : BaseType(RegBase), IndexReg(), Disp(0), isRI(RI) {
56 errs() << "SystemZRRIAddressMode " << this << '\n';
57 if (BaseType == RegBase) {
58 errs() << "Base.Reg ";
59 if (Base.Reg.getNode() != 0)
60 Base.Reg.getNode()->dump();
65 errs() << " Base.FrameIndex " << Base.FrameIndex << '\n';
68 errs() << "IndexReg ";
69 if (IndexReg.getNode() != 0) IndexReg.getNode()->dump();
72 errs() << " Disp " << Disp << '\n';
77 /// SystemZDAGToDAGISel - SystemZ specific code to select SystemZ machine
78 /// instructions for SelectionDAG operations.
81 class SystemZDAGToDAGISel : public SelectionDAGISel {
82 const SystemZTargetLowering &Lowering;
83 const SystemZSubtarget &Subtarget;
85 void getAddressOperandsRI(const SystemZRRIAddressMode &AM,
86 SDValue &Base, SDValue &Disp);
87 void getAddressOperands(const SystemZRRIAddressMode &AM,
88 SDValue &Base, SDValue &Disp,
92 SystemZDAGToDAGISel(SystemZTargetMachine &TM, CodeGenOpt::Level OptLevel)
93 : SelectionDAGISel(TM, OptLevel),
94 Lowering(*TM.getTargetLowering()),
95 Subtarget(*TM.getSubtargetImpl()) { }
97 virtual const char *getPassName() const {
98 return "SystemZ DAG->DAG Pattern Instruction Selection";
101 /// getI8Imm - Return a target constant with the specified value, of type
103 inline SDValue getI8Imm(uint64_t Imm) {
104 return CurDAG->getTargetConstant(Imm, MVT::i8);
107 /// getI16Imm - Return a target constant with the specified value, of type
109 inline SDValue getI16Imm(uint64_t Imm) {
110 return CurDAG->getTargetConstant(Imm, MVT::i16);
113 /// getI32Imm - Return a target constant with the specified value, of type
115 inline SDValue getI32Imm(uint64_t Imm) {
116 return CurDAG->getTargetConstant(Imm, MVT::i32);
119 // Include the pieces autogenerated from the target description.
120 #include "SystemZGenDAGISel.inc"
123 bool SelectAddrRI12Only(SDNode *Op, SDValue& Addr,
124 SDValue &Base, SDValue &Disp);
125 bool SelectAddrRI12(SDNode *Op, SDValue& Addr,
126 SDValue &Base, SDValue &Disp,
127 bool is12BitOnly = false);
128 bool SelectAddrRI(SDNode *Op, SDValue& Addr,
129 SDValue &Base, SDValue &Disp);
130 bool SelectAddrRRI12(SDNode *Op, SDValue Addr,
131 SDValue &Base, SDValue &Disp, SDValue &Index);
132 bool SelectAddrRRI20(SDNode *Op, SDValue Addr,
133 SDValue &Base, SDValue &Disp, SDValue &Index);
134 bool SelectLAAddr(SDNode *Op, SDValue Addr,
135 SDValue &Base, SDValue &Disp, SDValue &Index);
137 SDNode *Select(SDNode *Node);
139 bool TryFoldLoad(SDNode *P, SDValue N,
140 SDValue &Base, SDValue &Disp, SDValue &Index);
142 bool MatchAddress(SDValue N, SystemZRRIAddressMode &AM,
143 bool is12Bit, unsigned Depth = 0);
144 bool MatchAddressBase(SDValue N, SystemZRRIAddressMode &AM);
145 bool MatchAddressRI(SDValue N, SystemZRRIAddressMode &AM,
148 } // end anonymous namespace
150 /// createSystemZISelDag - This pass converts a legalized DAG into a
151 /// SystemZ-specific DAG, ready for instruction scheduling.
153 FunctionPass *llvm::createSystemZISelDag(SystemZTargetMachine &TM,
154 CodeGenOpt::Level OptLevel) {
155 return new SystemZDAGToDAGISel(TM, OptLevel);
158 /// isImmSExt20 - This method tests to see if the node is either a 32-bit
159 /// or 64-bit immediate, and if the value can be accurately represented as a
160 /// sign extension from a 20-bit value. If so, this returns true and the
162 static bool isImmSExt20(int64_t Val, int64_t &Imm) {
163 if (Val >= -524288 && Val <= 524287) {
170 /// isImmZExt12 - This method tests to see if the node is either a 32-bit
171 /// or 64-bit immediate, and if the value can be accurately represented as a
172 /// zero extension from a 12-bit value. If so, this returns true and the
174 static bool isImmZExt12(int64_t Val, int64_t &Imm) {
175 if (Val >= 0 && Val <= 0xFFF) {
182 /// MatchAddress - Add the specified node to the specified addressing mode,
183 /// returning true if it cannot be done. This just pattern matches for the
185 bool SystemZDAGToDAGISel::MatchAddress(SDValue N, SystemZRRIAddressMode &AM,
186 bool is12Bit, unsigned Depth) {
187 DebugLoc dl = N.getDebugLoc();
188 DEBUG(errs() << "MatchAddress: "; AM.dump());
191 return MatchAddressBase(N, AM);
193 // FIXME: We can perform better here. If we have something like
194 // (shift (add A, imm), N), we can try to reassociate stuff and fold shift of
195 // imm into addressing mode.
196 switch (N.getOpcode()) {
198 case ISD::Constant: {
199 int64_t Val = cast<ConstantSDNode>(N)->getSExtValue();
201 bool Match = (is12Bit ?
202 isImmZExt12(AM.Disp + Val, Imm) :
203 isImmSExt20(AM.Disp + Val, Imm));
211 case ISD::FrameIndex:
212 if (AM.BaseType == SystemZRRIAddressMode::RegBase &&
213 AM.Base.Reg.getNode() == 0) {
214 AM.BaseType = SystemZRRIAddressMode::FrameIndexBase;
215 AM.Base.FrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
221 // Given A-B, if A can be completely folded into the address and
222 // the index field with the index field unused, use -B as the index.
223 // This is a win if a has multiple parts that can be folded into
224 // the address. Also, this saves a mov if the base register has
225 // other uses, since it avoids a two-address sub instruction, however
226 // it costs an additional mov if the index register has other uses.
228 // Test if the LHS of the sub can be folded.
229 SystemZRRIAddressMode Backup = AM;
230 if (MatchAddress(N.getNode()->getOperand(0), AM, is12Bit, Depth+1)) {
234 // Test if the index field is free for use.
235 if (AM.IndexReg.getNode() || AM.isRI) {
240 // If the base is a register with multiple uses, this transformation may
241 // save a mov. Otherwise it's probably better not to do it.
242 if (AM.BaseType == SystemZRRIAddressMode::RegBase &&
243 (!AM.Base.Reg.getNode() || AM.Base.Reg.getNode()->hasOneUse())) {
248 // Ok, the transformation is legal and appears profitable. Go for it.
249 SDValue RHS = N.getNode()->getOperand(1);
250 SDValue Zero = CurDAG->getConstant(0, N.getValueType());
251 SDValue Neg = CurDAG->getNode(ISD::SUB, dl, N.getValueType(), Zero, RHS);
254 // Insert the new nodes into the topological ordering.
255 if (Zero.getNode()->getNodeId() == -1 ||
256 Zero.getNode()->getNodeId() > N.getNode()->getNodeId()) {
257 CurDAG->RepositionNode(N.getNode(), Zero.getNode());
258 Zero.getNode()->setNodeId(N.getNode()->getNodeId());
260 if (Neg.getNode()->getNodeId() == -1 ||
261 Neg.getNode()->getNodeId() > N.getNode()->getNodeId()) {
262 CurDAG->RepositionNode(N.getNode(), Neg.getNode());
263 Neg.getNode()->setNodeId(N.getNode()->getNodeId());
269 SystemZRRIAddressMode Backup = AM;
270 if (!MatchAddress(N.getNode()->getOperand(0), AM, is12Bit, Depth+1) &&
271 !MatchAddress(N.getNode()->getOperand(1), AM, is12Bit, Depth+1))
274 if (!MatchAddress(N.getNode()->getOperand(1), AM, is12Bit, Depth+1) &&
275 !MatchAddress(N.getNode()->getOperand(0), AM, is12Bit, Depth+1))
279 // If we couldn't fold both operands into the address at the same time,
280 // see if we can just put each operand into a register and fold at least
283 AM.BaseType == SystemZRRIAddressMode::RegBase &&
284 !AM.Base.Reg.getNode() && !AM.IndexReg.getNode()) {
285 AM.Base.Reg = N.getNode()->getOperand(0);
286 AM.IndexReg = N.getNode()->getOperand(1);
293 // Handle "X | C" as "X + C" iff X is known to have C bits clear.
294 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
295 SystemZRRIAddressMode Backup = AM;
296 int64_t Offset = CN->getSExtValue();
298 bool MatchOffset = (is12Bit ?
299 isImmZExt12(AM.Disp + Offset, Imm) :
300 isImmSExt20(AM.Disp + Offset, Imm));
301 // The resultant disp must fit in 12 or 20-bits.
303 // LHS should be an addr mode.
304 !MatchAddress(N.getOperand(0), AM, is12Bit, Depth+1) &&
305 // Check to see if the LHS & C is zero.
306 CurDAG->MaskedValueIsZero(N.getOperand(0), CN->getAPIntValue())) {
315 return MatchAddressBase(N, AM);
318 /// MatchAddressBase - Helper for MatchAddress. Add the specified node to the
319 /// specified addressing mode without any further recursion.
320 bool SystemZDAGToDAGISel::MatchAddressBase(SDValue N,
321 SystemZRRIAddressMode &AM) {
322 // Is the base register already occupied?
323 if (AM.BaseType != SystemZRRIAddressMode::RegBase || AM.Base.Reg.getNode()) {
324 // If so, check to see if the index register is set.
325 if (AM.IndexReg.getNode() == 0 && !AM.isRI) {
330 // Otherwise, we cannot select it.
334 // Default, generate it as a register.
335 AM.BaseType = SystemZRRIAddressMode::RegBase;
340 void SystemZDAGToDAGISel::getAddressOperandsRI(const SystemZRRIAddressMode &AM,
341 SDValue &Base, SDValue &Disp) {
342 if (AM.BaseType == SystemZRRIAddressMode::RegBase)
345 Base = CurDAG->getTargetFrameIndex(AM.Base.FrameIndex, TLI.getPointerTy());
346 Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i64);
349 void SystemZDAGToDAGISel::getAddressOperands(const SystemZRRIAddressMode &AM,
350 SDValue &Base, SDValue &Disp,
352 getAddressOperandsRI(AM, Base, Disp);
356 /// Returns true if the address can be represented by a base register plus
357 /// an unsigned 12-bit displacement [r+imm].
358 bool SystemZDAGToDAGISel::SelectAddrRI12Only(SDNode *Op, SDValue& Addr,
359 SDValue &Base, SDValue &Disp) {
360 return SelectAddrRI12(Op, Addr, Base, Disp, /*is12BitOnly*/true);
363 bool SystemZDAGToDAGISel::SelectAddrRI12(SDNode *Op, SDValue& Addr,
364 SDValue &Base, SDValue &Disp,
366 SystemZRRIAddressMode AM20(/*isRI*/true), AM12(/*isRI*/true);
369 if (!Addr.hasOneUse()) {
370 unsigned Opcode = Addr.getOpcode();
371 if (Opcode != ISD::Constant && Opcode != ISD::FrameIndex) {
372 // If we are able to fold N into addressing mode, then we'll allow it even
373 // if N has multiple uses. In general, addressing computation is used as
374 // addresses by all of its uses. But watch out for CopyToReg uses, that
375 // means the address computation is liveout. It will be computed by a LA
376 // so we want to avoid computing the address twice.
377 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
378 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
379 if (UI->getOpcode() == ISD::CopyToReg) {
380 MatchAddressBase(Addr, AM12);
387 if (!Done && MatchAddress(Addr, AM12, /* is12Bit */ true))
390 // Check, whether we can match stuff using 20-bit displacements
391 if (!Done && !is12BitOnly &&
392 !MatchAddress(Addr, AM20, /* is12Bit */ false))
393 if (AM12.Disp == 0 && AM20.Disp != 0)
396 DEBUG(errs() << "MatchAddress (final): "; AM12.dump());
398 EVT VT = Addr.getValueType();
399 if (AM12.BaseType == SystemZRRIAddressMode::RegBase) {
400 if (!AM12.Base.Reg.getNode())
401 AM12.Base.Reg = CurDAG->getRegister(0, VT);
404 assert(AM12.IndexReg.getNode() == 0 && "Invalid reg-imm address mode!");
406 getAddressOperandsRI(AM12, Base, Disp);
411 /// Returns true if the address can be represented by a base register plus
412 /// a signed 20-bit displacement [r+imm].
413 bool SystemZDAGToDAGISel::SelectAddrRI(SDNode *Op, SDValue& Addr,
414 SDValue &Base, SDValue &Disp) {
415 SystemZRRIAddressMode AM(/*isRI*/true);
418 if (!Addr.hasOneUse()) {
419 unsigned Opcode = Addr.getOpcode();
420 if (Opcode != ISD::Constant && Opcode != ISD::FrameIndex) {
421 // If we are able to fold N into addressing mode, then we'll allow it even
422 // if N has multiple uses. In general, addressing computation is used as
423 // addresses by all of its uses. But watch out for CopyToReg uses, that
424 // means the address computation is liveout. It will be computed by a LA
425 // so we want to avoid computing the address twice.
426 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
427 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
428 if (UI->getOpcode() == ISD::CopyToReg) {
429 MatchAddressBase(Addr, AM);
436 if (!Done && MatchAddress(Addr, AM, /* is12Bit */ false))
439 DEBUG(errs() << "MatchAddress (final): "; AM.dump());
441 EVT VT = Addr.getValueType();
442 if (AM.BaseType == SystemZRRIAddressMode::RegBase) {
443 if (!AM.Base.Reg.getNode())
444 AM.Base.Reg = CurDAG->getRegister(0, VT);
447 assert(AM.IndexReg.getNode() == 0 && "Invalid reg-imm address mode!");
449 getAddressOperandsRI(AM, Base, Disp);
454 /// Returns true if the address can be represented by a base register plus
455 /// index register plus an unsigned 12-bit displacement [base + idx + imm].
456 bool SystemZDAGToDAGISel::SelectAddrRRI12(SDNode *Op, SDValue Addr,
457 SDValue &Base, SDValue &Disp, SDValue &Index) {
458 SystemZRRIAddressMode AM20, AM12;
461 if (!Addr.hasOneUse()) {
462 unsigned Opcode = Addr.getOpcode();
463 if (Opcode != ISD::Constant && Opcode != ISD::FrameIndex) {
464 // If we are able to fold N into addressing mode, then we'll allow it even
465 // if N has multiple uses. In general, addressing computation is used as
466 // addresses by all of its uses. But watch out for CopyToReg uses, that
467 // means the address computation is liveout. It will be computed by a LA
468 // so we want to avoid computing the address twice.
469 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
470 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
471 if (UI->getOpcode() == ISD::CopyToReg) {
472 MatchAddressBase(Addr, AM12);
479 if (!Done && MatchAddress(Addr, AM12, /* is12Bit */ true))
482 // Check, whether we can match stuff using 20-bit displacements
483 if (!Done && !MatchAddress(Addr, AM20, /* is12Bit */ false))
484 if (AM12.Disp == 0 && AM20.Disp != 0)
487 DEBUG(errs() << "MatchAddress (final): "; AM12.dump());
489 EVT VT = Addr.getValueType();
490 if (AM12.BaseType == SystemZRRIAddressMode::RegBase) {
491 if (!AM12.Base.Reg.getNode())
492 AM12.Base.Reg = CurDAG->getRegister(0, VT);
495 if (!AM12.IndexReg.getNode())
496 AM12.IndexReg = CurDAG->getRegister(0, VT);
498 getAddressOperands(AM12, Base, Disp, Index);
503 /// Returns true if the address can be represented by a base register plus
504 /// index register plus a signed 20-bit displacement [base + idx + imm].
505 bool SystemZDAGToDAGISel::SelectAddrRRI20(SDNode *Op, SDValue Addr,
506 SDValue &Base, SDValue &Disp, SDValue &Index) {
507 SystemZRRIAddressMode AM;
510 if (!Addr.hasOneUse()) {
511 unsigned Opcode = Addr.getOpcode();
512 if (Opcode != ISD::Constant && Opcode != ISD::FrameIndex) {
513 // If we are able to fold N into addressing mode, then we'll allow it even
514 // if N has multiple uses. In general, addressing computation is used as
515 // addresses by all of its uses. But watch out for CopyToReg uses, that
516 // means the address computation is liveout. It will be computed by a LA
517 // so we want to avoid computing the address twice.
518 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
519 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
520 if (UI->getOpcode() == ISD::CopyToReg) {
521 MatchAddressBase(Addr, AM);
528 if (!Done && MatchAddress(Addr, AM, /* is12Bit */ false))
531 DEBUG(errs() << "MatchAddress (final): "; AM.dump());
533 EVT VT = Addr.getValueType();
534 if (AM.BaseType == SystemZRRIAddressMode::RegBase) {
535 if (!AM.Base.Reg.getNode())
536 AM.Base.Reg = CurDAG->getRegister(0, VT);
539 if (!AM.IndexReg.getNode())
540 AM.IndexReg = CurDAG->getRegister(0, VT);
542 getAddressOperands(AM, Base, Disp, Index);
547 /// SelectLAAddr - it calls SelectAddr and determines if the maximal addressing
548 /// mode it matches can be cost effectively emitted as an LA/LAY instruction.
549 bool SystemZDAGToDAGISel::SelectLAAddr(SDNode *Op, SDValue Addr,
550 SDValue &Base, SDValue &Disp, SDValue &Index) {
551 SystemZRRIAddressMode AM;
553 if (MatchAddress(Addr, AM, false))
556 EVT VT = Addr.getValueType();
557 unsigned Complexity = 0;
558 if (AM.BaseType == SystemZRRIAddressMode::RegBase)
559 if (AM.Base.Reg.getNode())
562 AM.Base.Reg = CurDAG->getRegister(0, VT);
563 else if (AM.BaseType == SystemZRRIAddressMode::FrameIndexBase)
566 if (AM.IndexReg.getNode())
569 AM.IndexReg = CurDAG->getRegister(0, VT);
571 if (AM.Disp && (AM.Base.Reg.getNode() || AM.IndexReg.getNode()))
574 if (Complexity > 2) {
575 getAddressOperands(AM, Base, Disp, Index);
582 bool SystemZDAGToDAGISel::TryFoldLoad(SDNode *P, SDValue N,
583 SDValue &Base, SDValue &Disp, SDValue &Index) {
584 if (ISD::isNON_EXTLoad(N.getNode()) &&
585 IsLegalToFold(N, P, P, OptLevel))
586 return SelectAddrRRI20(P, N.getOperand(1), Base, Disp, Index);
590 SDNode *SystemZDAGToDAGISel::Select(SDNode *Node) {
591 EVT NVT = Node->getValueType(0);
592 DebugLoc dl = Node->getDebugLoc();
593 unsigned Opcode = Node->getOpcode();
595 // Dump information about the Node being selected
596 DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n");
598 // If we have a custom node, we already have selected!
599 if (Node->isMachineOpcode()) {
600 DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
601 return NULL; // Already selected.
608 SDValue N0 = Node->getOperand(0);
609 SDValue N1 = Node->getOperand(1);
612 bool is32Bit = false;
613 switch (NVT.getSimpleVT().SimpleTy) {
614 default: assert(0 && "Unsupported VT!");
616 Opc = SystemZ::SDIVREM32r; MOpc = SystemZ::SDIVREM32m;
621 Opc = SystemZ::SDIVREM64r; MOpc = SystemZ::SDIVREM64m;
626 SDValue Tmp0, Tmp1, Tmp2;
627 bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2);
629 // Prepare the dividend
632 Dividend = CurDAG->getMachineNode(SystemZ::MOVSX64rr32, dl, MVT::i64, N0);
634 Dividend = N0.getNode();
636 // Insert prepared dividend into suitable 'subreg'
637 SDNode *Tmp = CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
640 CurDAG->getMachineNode(TargetOpcode::INSERT_SUBREG, dl, ResVT,
641 SDValue(Tmp, 0), SDValue(Dividend, 0),
642 CurDAG->getTargetConstant(SystemZ::subreg_odd, MVT::i32));
645 SDValue DivVal = SDValue(Dividend, 0);
647 SDValue Ops[] = { DivVal, Tmp0, Tmp1, Tmp2, N1.getOperand(0) };
648 Result = CurDAG->getMachineNode(MOpc, dl, ResVT, MVT::Other,
649 Ops, array_lengthof(Ops));
651 ReplaceUses(N1.getValue(1), SDValue(Result, 1));
653 Result = CurDAG->getMachineNode(Opc, dl, ResVT, SDValue(Dividend, 0), N1);
656 // Copy the division (odd subreg) result, if it is needed.
657 if (!SDValue(Node, 0).use_empty()) {
658 unsigned SubRegIdx = (is32Bit ?
659 SystemZ::subreg_odd32 : SystemZ::subreg_odd);
660 SDNode *Div = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
663 CurDAG->getTargetConstant(SubRegIdx,
666 ReplaceUses(SDValue(Node, 0), SDValue(Div, 0));
667 DEBUG(errs() << "=> "; Result->dump(CurDAG); errs() << "\n");
670 // Copy the remainder (even subreg) result, if it is needed.
671 if (!SDValue(Node, 1).use_empty()) {
672 unsigned SubRegIdx = (is32Bit ?
673 SystemZ::subreg_32bit : SystemZ::subreg_even);
674 SDNode *Rem = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
677 CurDAG->getTargetConstant(SubRegIdx,
680 ReplaceUses(SDValue(Node, 1), SDValue(Rem, 0));
681 DEBUG(errs() << "=> "; Result->dump(CurDAG); errs() << "\n");
687 unsigned Opc, MOpc, ClrOpc;
688 SDValue N0 = Node->getOperand(0);
689 SDValue N1 = Node->getOperand(1);
692 bool is32Bit = false;
693 switch (NVT.getSimpleVT().SimpleTy) {
694 default: assert(0 && "Unsupported VT!");
696 Opc = SystemZ::UDIVREM32r; MOpc = SystemZ::UDIVREM32m;
697 ClrOpc = SystemZ::MOV64Pr0_even;
702 Opc = SystemZ::UDIVREM64r; MOpc = SystemZ::UDIVREM64m;
703 ClrOpc = SystemZ::MOV128r0_even;
708 SDValue Tmp0, Tmp1, Tmp2;
709 bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2);
711 // Prepare the dividend
712 SDNode *Dividend = N0.getNode();
714 // Insert prepared dividend into suitable 'subreg'
715 SDNode *Tmp = CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
718 unsigned SubRegIdx = (is32Bit ?
719 SystemZ::subreg_odd32 : SystemZ::subreg_odd);
721 CurDAG->getMachineNode(TargetOpcode::INSERT_SUBREG, dl, ResVT,
722 SDValue(Tmp, 0), SDValue(Dividend, 0),
723 CurDAG->getTargetConstant(SubRegIdx, MVT::i32));
726 // Zero out even subreg
727 Dividend = CurDAG->getMachineNode(ClrOpc, dl, ResVT, SDValue(Dividend, 0));
729 SDValue DivVal = SDValue(Dividend, 0);
732 SDValue Ops[] = { DivVal, Tmp0, Tmp1, Tmp2, N1.getOperand(0) };
733 Result = CurDAG->getMachineNode(MOpc, dl, ResVT, MVT::Other,
734 Ops, array_lengthof(Ops));
736 ReplaceUses(N1.getValue(1), SDValue(Result, 1));
738 Result = CurDAG->getMachineNode(Opc, dl, ResVT, DivVal, N1);
741 // Copy the division (odd subreg) result, if it is needed.
742 if (!SDValue(Node, 0).use_empty()) {
743 unsigned SubRegIdx = (is32Bit ?
744 SystemZ::subreg_odd32 : SystemZ::subreg_odd);
745 SDNode *Div = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
748 CurDAG->getTargetConstant(SubRegIdx,
750 ReplaceUses(SDValue(Node, 0), SDValue(Div, 0));
751 DEBUG(errs() << "=> "; Result->dump(CurDAG); errs() << "\n");
754 // Copy the remainder (even subreg) result, if it is needed.
755 if (!SDValue(Node, 1).use_empty()) {
756 unsigned SubRegIdx = (is32Bit ?
757 SystemZ::subreg_32bit : SystemZ::subreg_even);
758 SDNode *Rem = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
761 CurDAG->getTargetConstant(SubRegIdx,
763 ReplaceUses(SDValue(Node, 1), SDValue(Rem, 0));
764 DEBUG(errs() << "=> "; Result->dump(CurDAG); errs() << "\n");
771 // Select the default instruction
772 SDNode *ResNode = SelectCode(Node);
774 DEBUG(errs() << "=> ";
775 if (ResNode == NULL || ResNode == Node)
778 ResNode->dump(CurDAG);