1 //===-- SystemZISelDAGToDAG.cpp - A dag to dag inst selector for SystemZ --===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the SystemZ target.
12 //===----------------------------------------------------------------------===//
14 #include "SystemZTargetMachine.h"
15 #include "llvm/Analysis/AliasAnalysis.h"
16 #include "llvm/CodeGen/SelectionDAGISel.h"
17 #include "llvm/Support/Debug.h"
18 #include "llvm/Support/raw_ostream.h"
23 // Used to build addressing modes.
24 struct SystemZAddressingMode {
25 // The shape of the address.
30 // base+displacement+index for load and store operands
33 // base+displacement+index for load address operands
36 // base+displacement+index+ADJDYNALLOC
41 // The type of displacement. The enum names here correspond directly
42 // to the definitions in SystemZOperand.td. We could split them into
43 // flags -- single/pair, 128-bit, etc. -- but it hardly seems worth it.
53 // The parts of the address. The address is equivalent to:
55 // Base + Disp + Index + (IncludesDynAlloc ? ADJDYNALLOC : 0)
59 bool IncludesDynAlloc;
61 SystemZAddressingMode(AddrForm form, DispRange dr)
62 : Form(form), DR(dr), Base(), Disp(0), Index(),
63 IncludesDynAlloc(false) {}
65 // True if the address can have an index register.
66 bool hasIndexField() { return Form != FormBD; }
68 // True if the address can (and must) include ADJDYNALLOC.
69 bool isDynAlloc() { return Form == FormBDXDynAlloc; }
72 errs() << "SystemZAddressingMode " << this << '\n';
75 if (Base.getNode() != 0)
76 Base.getNode()->dump();
80 if (hasIndexField()) {
82 if (Index.getNode() != 0)
83 Index.getNode()->dump();
88 errs() << " Disp " << Disp;
90 errs() << " + ADJDYNALLOC";
95 // Return a mask with Count low bits set.
96 static uint64_t allOnes(unsigned int Count) {
97 return Count == 0 ? 0 : (uint64_t(1) << (Count - 1) << 1) - 1;
100 // Represents operands 2 to 5 of the ROTATE AND ... SELECTED BITS operation
101 // given by Opcode. The operands are: Input (R2), Start (I3), End (I4) and
102 // Rotate (I5). The combined operand value is effectively:
104 // (or (rotl Input, Rotate), ~Mask)
108 // (and (rotl Input, Rotate), Mask)
110 // otherwise. The value has BitSize bits.
111 struct RxSBGOperands {
112 RxSBGOperands(unsigned Op, SDValue N)
113 : Opcode(Op), BitSize(N.getValueType().getSizeInBits()),
114 Mask(allOnes(BitSize)), Input(N), Start(64 - BitSize), End(63),
126 class SystemZDAGToDAGISel : public SelectionDAGISel {
127 const SystemZTargetLowering &Lowering;
128 const SystemZSubtarget &Subtarget;
130 // Used by SystemZOperands.td to create integer constants.
131 inline SDValue getImm(const SDNode *Node, uint64_t Imm) {
132 return CurDAG->getTargetConstant(Imm, Node->getValueType(0));
135 const SystemZTargetMachine &getTargetMachine() const {
136 return static_cast<const SystemZTargetMachine &>(TM);
139 const SystemZInstrInfo *getInstrInfo() const {
140 return getTargetMachine().getInstrInfo();
143 // Try to fold more of the base or index of AM into AM, where IsBase
144 // selects between the base and index.
145 bool expandAddress(SystemZAddressingMode &AM, bool IsBase);
147 // Try to describe N in AM, returning true on success.
148 bool selectAddress(SDValue N, SystemZAddressingMode &AM);
150 // Extract individual target operands from matched address AM.
151 void getAddressOperands(const SystemZAddressingMode &AM, EVT VT,
152 SDValue &Base, SDValue &Disp);
153 void getAddressOperands(const SystemZAddressingMode &AM, EVT VT,
154 SDValue &Base, SDValue &Disp, SDValue &Index);
156 // Try to match Addr as a FormBD address with displacement type DR.
157 // Return true on success, storing the base and displacement in
158 // Base and Disp respectively.
159 bool selectBDAddr(SystemZAddressingMode::DispRange DR, SDValue Addr,
160 SDValue &Base, SDValue &Disp);
162 // Try to match Addr as a FormBDX address with displacement type DR.
163 // Return true on success and if the result had no index. Store the
164 // base and displacement in Base and Disp respectively.
165 bool selectMVIAddr(SystemZAddressingMode::DispRange DR, SDValue Addr,
166 SDValue &Base, SDValue &Disp);
168 // Try to match Addr as a FormBDX* address of form Form with
169 // displacement type DR. Return true on success, storing the base,
170 // displacement and index in Base, Disp and Index respectively.
171 bool selectBDXAddr(SystemZAddressingMode::AddrForm Form,
172 SystemZAddressingMode::DispRange DR, SDValue Addr,
173 SDValue &Base, SDValue &Disp, SDValue &Index);
175 // PC-relative address matching routines used by SystemZOperands.td.
176 bool selectPCRelAddress(SDValue Addr, SDValue &Target) {
177 if (Addr.getOpcode() == SystemZISD::PCREL_WRAPPER) {
178 Target = Addr.getOperand(0);
184 // BD matching routines used by SystemZOperands.td.
185 bool selectBDAddr12Only(SDValue Addr, SDValue &Base, SDValue &Disp) {
186 return selectBDAddr(SystemZAddressingMode::Disp12Only, Addr, Base, Disp);
188 bool selectBDAddr12Pair(SDValue Addr, SDValue &Base, SDValue &Disp) {
189 return selectBDAddr(SystemZAddressingMode::Disp12Pair, Addr, Base, Disp);
191 bool selectBDAddr20Only(SDValue Addr, SDValue &Base, SDValue &Disp) {
192 return selectBDAddr(SystemZAddressingMode::Disp20Only, Addr, Base, Disp);
194 bool selectBDAddr20Pair(SDValue Addr, SDValue &Base, SDValue &Disp) {
195 return selectBDAddr(SystemZAddressingMode::Disp20Pair, Addr, Base, Disp);
198 // MVI matching routines used by SystemZOperands.td.
199 bool selectMVIAddr12Pair(SDValue Addr, SDValue &Base, SDValue &Disp) {
200 return selectMVIAddr(SystemZAddressingMode::Disp12Pair, Addr, Base, Disp);
202 bool selectMVIAddr20Pair(SDValue Addr, SDValue &Base, SDValue &Disp) {
203 return selectMVIAddr(SystemZAddressingMode::Disp20Pair, Addr, Base, Disp);
206 // BDX matching routines used by SystemZOperands.td.
207 bool selectBDXAddr12Only(SDValue Addr, SDValue &Base, SDValue &Disp,
209 return selectBDXAddr(SystemZAddressingMode::FormBDXNormal,
210 SystemZAddressingMode::Disp12Only,
211 Addr, Base, Disp, Index);
213 bool selectBDXAddr12Pair(SDValue Addr, SDValue &Base, SDValue &Disp,
215 return selectBDXAddr(SystemZAddressingMode::FormBDXNormal,
216 SystemZAddressingMode::Disp12Pair,
217 Addr, Base, Disp, Index);
219 bool selectDynAlloc12Only(SDValue Addr, SDValue &Base, SDValue &Disp,
221 return selectBDXAddr(SystemZAddressingMode::FormBDXDynAlloc,
222 SystemZAddressingMode::Disp12Only,
223 Addr, Base, Disp, Index);
225 bool selectBDXAddr20Only(SDValue Addr, SDValue &Base, SDValue &Disp,
227 return selectBDXAddr(SystemZAddressingMode::FormBDXNormal,
228 SystemZAddressingMode::Disp20Only,
229 Addr, Base, Disp, Index);
231 bool selectBDXAddr20Only128(SDValue Addr, SDValue &Base, SDValue &Disp,
233 return selectBDXAddr(SystemZAddressingMode::FormBDXNormal,
234 SystemZAddressingMode::Disp20Only128,
235 Addr, Base, Disp, Index);
237 bool selectBDXAddr20Pair(SDValue Addr, SDValue &Base, SDValue &Disp,
239 return selectBDXAddr(SystemZAddressingMode::FormBDXNormal,
240 SystemZAddressingMode::Disp20Pair,
241 Addr, Base, Disp, Index);
243 bool selectLAAddr12Pair(SDValue Addr, SDValue &Base, SDValue &Disp,
245 return selectBDXAddr(SystemZAddressingMode::FormBDXLA,
246 SystemZAddressingMode::Disp12Pair,
247 Addr, Base, Disp, Index);
249 bool selectLAAddr20Pair(SDValue Addr, SDValue &Base, SDValue &Disp,
251 return selectBDXAddr(SystemZAddressingMode::FormBDXLA,
252 SystemZAddressingMode::Disp20Pair,
253 Addr, Base, Disp, Index);
256 // Check whether (or Op (and X InsertMask)) is effectively an insertion
257 // of X into bits InsertMask of some Y != Op. Return true if so and
259 bool detectOrAndInsertion(SDValue &Op, uint64_t InsertMask);
261 // Try to update RxSBG so that only the bits of RxSBG.Input in Mask are used.
262 // Return true on success.
263 bool refineRxSBGMask(RxSBGOperands &RxSBG, uint64_t Mask);
265 // Try to fold some of RxSBG.Input into other fields of RxSBG.
266 // Return true on success.
267 bool expandRxSBG(RxSBGOperands &RxSBG);
269 // Return an undefined i64 value.
270 SDValue getUNDEF64(SDLoc DL);
272 // Convert N to VT, if it isn't already.
273 SDValue convertTo(SDLoc DL, EVT VT, SDValue N);
275 // Try to implement AND or shift node N using RISBG with the zero flag set.
276 // Return the selected node on success, otherwise return null.
277 SDNode *tryRISBGZero(SDNode *N);
279 // Try to use RISBG or Opcode to implement OR or XOR node N.
280 // Return the selected node on success, otherwise return null.
281 SDNode *tryRxSBG(SDNode *N, unsigned Opcode);
283 // If Op0 is null, then Node is a constant that can be loaded using:
285 // (Opcode UpperVal LowerVal)
287 // If Op0 is nonnull, then Node can be implemented using:
289 // (Opcode (Opcode Op0 UpperVal) LowerVal)
290 SDNode *splitLargeImmediate(unsigned Opcode, SDNode *Node, SDValue Op0,
291 uint64_t UpperVal, uint64_t LowerVal);
293 // N is a (store (load Y), X) pattern. Return true if it can use an MVC
295 bool storeLoadCanUseMVC(SDNode *N) const;
297 // N is a (store (op (load A[0]), (load A[1])), X) pattern. Return true
298 // if A[1 - I] == X and if N can use a block operation like NC from A[I]
300 bool storeLoadCanUseBlockBinary(SDNode *N, unsigned I) const;
303 SystemZDAGToDAGISel(SystemZTargetMachine &TM, CodeGenOpt::Level OptLevel)
304 : SelectionDAGISel(TM, OptLevel),
305 Lowering(*TM.getTargetLowering()),
306 Subtarget(*TM.getSubtargetImpl()) { }
308 // Override MachineFunctionPass.
309 virtual const char *getPassName() const LLVM_OVERRIDE {
310 return "SystemZ DAG->DAG Pattern Instruction Selection";
313 // Override SelectionDAGISel.
314 virtual SDNode *Select(SDNode *Node) LLVM_OVERRIDE;
315 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
317 std::vector<SDValue> &OutOps)
320 // Include the pieces autogenerated from the target description.
321 #include "SystemZGenDAGISel.inc"
323 } // end anonymous namespace
325 FunctionPass *llvm::createSystemZISelDag(SystemZTargetMachine &TM,
326 CodeGenOpt::Level OptLevel) {
327 return new SystemZDAGToDAGISel(TM, OptLevel);
330 // Return true if Val should be selected as a displacement for an address
331 // with range DR. Here we're interested in the range of both the instruction
332 // described by DR and of any pairing instruction.
333 static bool selectDisp(SystemZAddressingMode::DispRange DR, int64_t Val) {
335 case SystemZAddressingMode::Disp12Only:
336 return isUInt<12>(Val);
338 case SystemZAddressingMode::Disp12Pair:
339 case SystemZAddressingMode::Disp20Only:
340 case SystemZAddressingMode::Disp20Pair:
341 return isInt<20>(Val);
343 case SystemZAddressingMode::Disp20Only128:
344 return isInt<20>(Val) && isInt<20>(Val + 8);
346 llvm_unreachable("Unhandled displacement range");
349 // Change the base or index in AM to Value, where IsBase selects
350 // between the base and index.
351 static void changeComponent(SystemZAddressingMode &AM, bool IsBase,
359 // The base or index of AM is equivalent to Value + ADJDYNALLOC,
360 // where IsBase selects between the base and index. Try to fold the
361 // ADJDYNALLOC into AM.
362 static bool expandAdjDynAlloc(SystemZAddressingMode &AM, bool IsBase,
364 if (AM.isDynAlloc() && !AM.IncludesDynAlloc) {
365 changeComponent(AM, IsBase, Value);
366 AM.IncludesDynAlloc = true;
372 // The base of AM is equivalent to Base + Index. Try to use Index as
373 // the index register.
374 static bool expandIndex(SystemZAddressingMode &AM, SDValue Base,
376 if (AM.hasIndexField() && !AM.Index.getNode()) {
384 // The base or index of AM is equivalent to Op0 + Op1, where IsBase selects
385 // between the base and index. Try to fold Op1 into AM's displacement.
386 static bool expandDisp(SystemZAddressingMode &AM, bool IsBase,
387 SDValue Op0, ConstantSDNode *Op1) {
388 // First try adjusting the displacement.
389 int64_t TestDisp = AM.Disp + Op1->getSExtValue();
390 if (selectDisp(AM.DR, TestDisp)) {
391 changeComponent(AM, IsBase, Op0);
396 // We could consider forcing the displacement into a register and
397 // using it as an index, but it would need to be carefully tuned.
401 bool SystemZDAGToDAGISel::expandAddress(SystemZAddressingMode &AM,
403 SDValue N = IsBase ? AM.Base : AM.Index;
404 unsigned Opcode = N.getOpcode();
405 if (Opcode == ISD::TRUNCATE) {
407 Opcode = N.getOpcode();
409 if (Opcode == ISD::ADD || CurDAG->isBaseWithConstantOffset(N)) {
410 SDValue Op0 = N.getOperand(0);
411 SDValue Op1 = N.getOperand(1);
413 unsigned Op0Code = Op0->getOpcode();
414 unsigned Op1Code = Op1->getOpcode();
416 if (Op0Code == SystemZISD::ADJDYNALLOC)
417 return expandAdjDynAlloc(AM, IsBase, Op1);
418 if (Op1Code == SystemZISD::ADJDYNALLOC)
419 return expandAdjDynAlloc(AM, IsBase, Op0);
421 if (Op0Code == ISD::Constant)
422 return expandDisp(AM, IsBase, Op1, cast<ConstantSDNode>(Op0));
423 if (Op1Code == ISD::Constant)
424 return expandDisp(AM, IsBase, Op0, cast<ConstantSDNode>(Op1));
426 if (IsBase && expandIndex(AM, Op0, Op1))
432 // Return true if an instruction with displacement range DR should be
433 // used for displacement value Val. selectDisp(DR, Val) must already hold.
434 static bool isValidDisp(SystemZAddressingMode::DispRange DR, int64_t Val) {
435 assert(selectDisp(DR, Val) && "Invalid displacement");
437 case SystemZAddressingMode::Disp12Only:
438 case SystemZAddressingMode::Disp20Only:
439 case SystemZAddressingMode::Disp20Only128:
442 case SystemZAddressingMode::Disp12Pair:
443 // Use the other instruction if the displacement is too large.
444 return isUInt<12>(Val);
446 case SystemZAddressingMode::Disp20Pair:
447 // Use the other instruction if the displacement is small enough.
448 return !isUInt<12>(Val);
450 llvm_unreachable("Unhandled displacement range");
453 // Return true if Base + Disp + Index should be performed by LA(Y).
454 static bool shouldUseLA(SDNode *Base, int64_t Disp, SDNode *Index) {
455 // Don't use LA(Y) for constants.
459 // Always use LA(Y) for frame addresses, since we know that the destination
460 // register is almost always (perhaps always) going to be different from
461 // the frame register.
462 if (Base->getOpcode() == ISD::FrameIndex)
466 // Always use LA(Y) if there is a base, displacement and index.
470 // Always use LA if the displacement is small enough. It should always
471 // be no worse than AGHI (and better if it avoids a move).
472 if (isUInt<12>(Disp))
475 // For similar reasons, always use LAY if the constant is too big for AGHI.
476 // LAY should be no worse than AGFI.
477 if (!isInt<16>(Disp))
480 // Don't use LA for plain registers.
484 // Don't use LA for plain addition if the index operand is only used
485 // once. It should be a natural two-operand addition in that case.
486 if (Index->hasOneUse())
489 // Prefer addition if the second operation is sign-extended, in the
490 // hope of using AGF.
491 unsigned IndexOpcode = Index->getOpcode();
492 if (IndexOpcode == ISD::SIGN_EXTEND ||
493 IndexOpcode == ISD::SIGN_EXTEND_INREG)
497 // Don't use LA for two-operand addition if either operand is only
498 // used once. The addition instructions are better in that case.
499 if (Base->hasOneUse())
505 // Return true if Addr is suitable for AM, updating AM if so.
506 bool SystemZDAGToDAGISel::selectAddress(SDValue Addr,
507 SystemZAddressingMode &AM) {
508 // Start out assuming that the address will need to be loaded separately,
509 // then try to extend it as much as we can.
512 // First try treating the address as a constant.
513 if (Addr.getOpcode() == ISD::Constant &&
514 expandDisp(AM, true, SDValue(), cast<ConstantSDNode>(Addr)))
517 // Otherwise try expanding each component.
518 while (expandAddress(AM, true) ||
519 (AM.Index.getNode() && expandAddress(AM, false)))
522 // Reject cases where it isn't profitable to use LA(Y).
523 if (AM.Form == SystemZAddressingMode::FormBDXLA &&
524 !shouldUseLA(AM.Base.getNode(), AM.Disp, AM.Index.getNode()))
527 // Reject cases where the other instruction in a pair should be used.
528 if (!isValidDisp(AM.DR, AM.Disp))
531 // Make sure that ADJDYNALLOC is included where necessary.
532 if (AM.isDynAlloc() && !AM.IncludesDynAlloc)
539 // Insert a node into the DAG at least before Pos. This will reposition
540 // the node as needed, and will assign it a node ID that is <= Pos's ID.
541 // Note that this does *not* preserve the uniqueness of node IDs!
542 // The selection DAG must no longer depend on their uniqueness when this
544 static void insertDAGNode(SelectionDAG *DAG, SDNode *Pos, SDValue N) {
545 if (N.getNode()->getNodeId() == -1 ||
546 N.getNode()->getNodeId() > Pos->getNodeId()) {
547 DAG->RepositionNode(Pos, N.getNode());
548 N.getNode()->setNodeId(Pos->getNodeId());
552 void SystemZDAGToDAGISel::getAddressOperands(const SystemZAddressingMode &AM,
553 EVT VT, SDValue &Base,
557 // Register 0 means "no base". This is mostly useful for shifts.
558 Base = CurDAG->getRegister(0, VT);
559 else if (Base.getOpcode() == ISD::FrameIndex) {
560 // Lower a FrameIndex to a TargetFrameIndex.
561 int64_t FrameIndex = cast<FrameIndexSDNode>(Base)->getIndex();
562 Base = CurDAG->getTargetFrameIndex(FrameIndex, VT);
563 } else if (Base.getValueType() != VT) {
564 // Truncate values from i64 to i32, for shifts.
565 assert(VT == MVT::i32 && Base.getValueType() == MVT::i64 &&
566 "Unexpected truncation");
568 SDValue Trunc = CurDAG->getNode(ISD::TRUNCATE, DL, VT, Base);
569 insertDAGNode(CurDAG, Base.getNode(), Trunc);
573 // Lower the displacement to a TargetConstant.
574 Disp = CurDAG->getTargetConstant(AM.Disp, VT);
577 void SystemZDAGToDAGISel::getAddressOperands(const SystemZAddressingMode &AM,
578 EVT VT, SDValue &Base,
579 SDValue &Disp, SDValue &Index) {
580 getAddressOperands(AM, VT, Base, Disp);
583 if (!Index.getNode())
584 // Register 0 means "no index".
585 Index = CurDAG->getRegister(0, VT);
588 bool SystemZDAGToDAGISel::selectBDAddr(SystemZAddressingMode::DispRange DR,
589 SDValue Addr, SDValue &Base,
591 SystemZAddressingMode AM(SystemZAddressingMode::FormBD, DR);
592 if (!selectAddress(Addr, AM))
595 getAddressOperands(AM, Addr.getValueType(), Base, Disp);
599 bool SystemZDAGToDAGISel::selectMVIAddr(SystemZAddressingMode::DispRange DR,
600 SDValue Addr, SDValue &Base,
602 SystemZAddressingMode AM(SystemZAddressingMode::FormBDXNormal, DR);
603 if (!selectAddress(Addr, AM) || AM.Index.getNode())
606 getAddressOperands(AM, Addr.getValueType(), Base, Disp);
610 bool SystemZDAGToDAGISel::selectBDXAddr(SystemZAddressingMode::AddrForm Form,
611 SystemZAddressingMode::DispRange DR,
612 SDValue Addr, SDValue &Base,
613 SDValue &Disp, SDValue &Index) {
614 SystemZAddressingMode AM(Form, DR);
615 if (!selectAddress(Addr, AM))
618 getAddressOperands(AM, Addr.getValueType(), Base, Disp, Index);
622 bool SystemZDAGToDAGISel::detectOrAndInsertion(SDValue &Op,
623 uint64_t InsertMask) {
624 // We're only interested in cases where the insertion is into some operand
625 // of Op, rather than into Op itself. The only useful case is an AND.
626 if (Op.getOpcode() != ISD::AND)
629 // We need a constant mask.
630 ConstantSDNode *MaskNode =
631 dyn_cast<ConstantSDNode>(Op.getOperand(1).getNode());
635 // It's not an insertion of Op.getOperand(0) if the two masks overlap.
636 uint64_t AndMask = MaskNode->getZExtValue();
637 if (InsertMask & AndMask)
640 // It's only an insertion if all bits are covered or are known to be zero.
641 // The inner check covers all cases but is more expensive.
642 uint64_t Used = allOnes(Op.getValueType().getSizeInBits());
643 if (Used != (AndMask | InsertMask)) {
644 APInt KnownZero, KnownOne;
645 CurDAG->ComputeMaskedBits(Op.getOperand(0), KnownZero, KnownOne);
646 if (Used != (AndMask | InsertMask | KnownZero.getZExtValue()))
650 Op = Op.getOperand(0);
654 bool SystemZDAGToDAGISel::refineRxSBGMask(RxSBGOperands &RxSBG, uint64_t Mask) {
655 const SystemZInstrInfo *TII = getInstrInfo();
656 if (RxSBG.Rotate != 0)
657 Mask = (Mask << RxSBG.Rotate) | (Mask >> (64 - RxSBG.Rotate));
659 if (TII->isRxSBGMask(Mask, RxSBG.BitSize, RxSBG.Start, RxSBG.End)) {
666 // RxSBG.Input is a shift of Count bits in the direction given by IsLeft.
667 // Return true if the result depends on the signs or zeros that are
669 static bool shiftedInBitsMatter(RxSBGOperands &RxSBG, uint64_t Count,
671 // Work out which bits of the shift result are zeros or sign copies.
672 uint64_t ShiftedIn = allOnes(Count);
674 ShiftedIn <<= RxSBG.BitSize - Count;
676 // Rotate that mask in the same way as RxSBG.Input is rotated.
677 if (RxSBG.Rotate != 0)
678 ShiftedIn = ((ShiftedIn << RxSBG.Rotate) |
679 (ShiftedIn >> (64 - RxSBG.Rotate)));
681 // Fail if any of the zero or sign bits are used.
682 return (ShiftedIn & RxSBG.Mask) != 0;
685 bool SystemZDAGToDAGISel::expandRxSBG(RxSBGOperands &RxSBG) {
686 SDValue N = RxSBG.Input;
687 unsigned Opcode = N.getOpcode();
690 if (RxSBG.Opcode == SystemZ::RNSBG)
693 ConstantSDNode *MaskNode =
694 dyn_cast<ConstantSDNode>(N.getOperand(1).getNode());
698 SDValue Input = N.getOperand(0);
699 uint64_t Mask = MaskNode->getZExtValue();
700 if (!refineRxSBGMask(RxSBG, Mask)) {
701 // If some bits of Input are already known zeros, those bits will have
702 // been removed from the mask. See if adding them back in makes the
704 APInt KnownZero, KnownOne;
705 CurDAG->ComputeMaskedBits(Input, KnownZero, KnownOne);
706 Mask |= KnownZero.getZExtValue();
707 if (!refineRxSBGMask(RxSBG, Mask))
715 if (RxSBG.Opcode != SystemZ::RNSBG)
718 ConstantSDNode *MaskNode =
719 dyn_cast<ConstantSDNode>(N.getOperand(1).getNode());
723 SDValue Input = N.getOperand(0);
724 uint64_t Mask = ~MaskNode->getZExtValue();
725 if (!refineRxSBGMask(RxSBG, Mask)) {
726 // If some bits of Input are already known ones, those bits will have
727 // been removed from the mask. See if adding them back in makes the
729 APInt KnownZero, KnownOne;
730 CurDAG->ComputeMaskedBits(Input, KnownZero, KnownOne);
731 Mask &= ~KnownOne.getZExtValue();
732 if (!refineRxSBGMask(RxSBG, Mask))
740 // Any 64-bit rotate left can be merged into the RxSBG.
741 if (RxSBG.BitSize != 64)
743 ConstantSDNode *CountNode
744 = dyn_cast<ConstantSDNode>(N.getOperand(1).getNode());
748 RxSBG.Rotate = (RxSBG.Rotate + CountNode->getZExtValue()) & 63;
749 RxSBG.Input = N.getOperand(0);
754 ConstantSDNode *CountNode =
755 dyn_cast<ConstantSDNode>(N.getOperand(1).getNode());
759 uint64_t Count = CountNode->getZExtValue();
760 if (Count < 1 || Count >= RxSBG.BitSize)
763 if (RxSBG.Opcode == SystemZ::RNSBG) {
764 // Treat (shl X, count) as (rotl X, size-count) as long as the bottom
765 // count bits from RxSBG.Input are ignored.
766 if (shiftedInBitsMatter(RxSBG, Count, true))
769 // Treat (shl X, count) as (and (rotl X, count), ~0<<count).
770 if (!refineRxSBGMask(RxSBG, allOnes(RxSBG.BitSize - Count) << Count))
774 RxSBG.Rotate = (RxSBG.Rotate + Count) & 63;
775 RxSBG.Input = N.getOperand(0);
781 ConstantSDNode *CountNode =
782 dyn_cast<ConstantSDNode>(N.getOperand(1).getNode());
786 uint64_t Count = CountNode->getZExtValue();
787 if (Count < 1 || Count >= RxSBG.BitSize)
790 if (RxSBG.Opcode == SystemZ::RNSBG || Opcode == ISD::SRA) {
791 // Treat (srl|sra X, count) as (rotl X, size-count) as long as the top
792 // count bits from RxSBG.Input are ignored.
793 if (shiftedInBitsMatter(RxSBG, Count, false))
796 // Treat (srl X, count), mask) as (and (rotl X, size-count), ~0>>count),
797 // which is similar to SLL above.
798 if (!refineRxSBGMask(RxSBG, allOnes(RxSBG.BitSize - Count)))
802 RxSBG.Rotate = (RxSBG.Rotate - Count) & 63;
803 RxSBG.Input = N.getOperand(0);
811 SDValue SystemZDAGToDAGISel::getUNDEF64(SDLoc DL) {
812 SDNode *N = CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, MVT::i64);
813 return SDValue(N, 0);
816 SDValue SystemZDAGToDAGISel::convertTo(SDLoc DL, EVT VT, SDValue N) {
817 if (N.getValueType() == MVT::i32 && VT == MVT::i64) {
818 SDValue Index = CurDAG->getTargetConstant(SystemZ::subreg_32bit, MVT::i64);
819 SDNode *Insert = CurDAG->getMachineNode(TargetOpcode::INSERT_SUBREG,
820 DL, VT, getUNDEF64(DL), N, Index);
821 return SDValue(Insert, 0);
823 if (N.getValueType() == MVT::i64 && VT == MVT::i32) {
824 SDValue Index = CurDAG->getTargetConstant(SystemZ::subreg_32bit, MVT::i64);
825 SDNode *Extract = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
827 return SDValue(Extract, 0);
829 assert(N.getValueType() == VT && "Unexpected value types");
833 SDNode *SystemZDAGToDAGISel::tryRISBGZero(SDNode *N) {
834 EVT VT = N->getValueType(0);
835 RxSBGOperands RISBG(SystemZ::RISBG, SDValue(N, 0));
837 while (expandRxSBG(RISBG))
842 // Prefer to use normal shift instructions over RISBG, since they can handle
843 // all cases and are sometimes shorter.
844 if (N->getOpcode() != ISD::AND)
847 // Prefer register extensions like LLC over RISBG. Also prefer to start
848 // out with normal ANDs if one instruction would be enough. We can convert
849 // these ANDs into an RISBG later if a three-address instruction is useful.
850 if (VT == MVT::i32 ||
851 RISBG.Mask == 0xff ||
852 RISBG.Mask == 0xffff ||
853 SystemZ::isImmLF(~RISBG.Mask) ||
854 SystemZ::isImmHF(~RISBG.Mask)) {
855 // Force the new mask into the DAG, since it may include known-one bits.
856 ConstantSDNode *MaskN = cast<ConstantSDNode>(N->getOperand(1).getNode());
857 if (MaskN->getZExtValue() != RISBG.Mask) {
858 SDValue NewMask = CurDAG->getConstant(RISBG.Mask, VT);
859 N = CurDAG->UpdateNodeOperands(N, N->getOperand(0), NewMask);
860 return SelectCode(N);
867 getUNDEF64(SDLoc(N)),
868 convertTo(SDLoc(N), MVT::i64, RISBG.Input),
869 CurDAG->getTargetConstant(RISBG.Start, MVT::i32),
870 CurDAG->getTargetConstant(RISBG.End | 128, MVT::i32),
871 CurDAG->getTargetConstant(RISBG.Rotate, MVT::i32)
873 N = CurDAG->getMachineNode(SystemZ::RISBG, SDLoc(N), MVT::i64, Ops);
874 return convertTo(SDLoc(N), VT, SDValue(N, 0)).getNode();
877 SDNode *SystemZDAGToDAGISel::tryRxSBG(SDNode *N, unsigned Opcode) {
878 // Try treating each operand of N as the second operand of the RxSBG
879 // and see which goes deepest.
880 RxSBGOperands RxSBG[] = {
881 RxSBGOperands(Opcode, N->getOperand(0)),
882 RxSBGOperands(Opcode, N->getOperand(1))
884 unsigned Count[] = { 0, 0 };
885 for (unsigned I = 0; I < 2; ++I)
886 while (expandRxSBG(RxSBG[I]))
889 // Do nothing if neither operand is suitable.
890 if (Count[0] == 0 && Count[1] == 0)
893 // Pick the deepest second operand.
894 unsigned I = Count[0] > Count[1] ? 0 : 1;
895 SDValue Op0 = N->getOperand(I ^ 1);
897 // Prefer IC for character insertions from memory.
898 if (Opcode == SystemZ::ROSBG && (RxSBG[I].Mask & 0xff) == 0)
899 if (LoadSDNode *Load = dyn_cast<LoadSDNode>(Op0.getNode()))
900 if (Load->getMemoryVT() == MVT::i8)
903 // See whether we can avoid an AND in the first operand by converting
905 if (Opcode == SystemZ::ROSBG && detectOrAndInsertion(Op0, RxSBG[I].Mask))
906 Opcode = SystemZ::RISBG;
908 EVT VT = N->getValueType(0);
910 convertTo(SDLoc(N), MVT::i64, Op0),
911 convertTo(SDLoc(N), MVT::i64, RxSBG[I].Input),
912 CurDAG->getTargetConstant(RxSBG[I].Start, MVT::i32),
913 CurDAG->getTargetConstant(RxSBG[I].End, MVT::i32),
914 CurDAG->getTargetConstant(RxSBG[I].Rotate, MVT::i32)
916 N = CurDAG->getMachineNode(Opcode, SDLoc(N), MVT::i64, Ops);
917 return convertTo(SDLoc(N), VT, SDValue(N, 0)).getNode();
920 SDNode *SystemZDAGToDAGISel::splitLargeImmediate(unsigned Opcode, SDNode *Node,
921 SDValue Op0, uint64_t UpperVal,
923 EVT VT = Node->getValueType(0);
925 SDValue Upper = CurDAG->getConstant(UpperVal, VT);
927 Upper = CurDAG->getNode(Opcode, DL, VT, Op0, Upper);
928 Upper = SDValue(Select(Upper.getNode()), 0);
930 SDValue Lower = CurDAG->getConstant(LowerVal, VT);
931 SDValue Or = CurDAG->getNode(Opcode, DL, VT, Upper, Lower);
935 // Return true if Load and Store:
936 // - are loads and stores of the same size;
937 // - do not partially overlap; and
938 // - can be decomposed into what are logically individual character accesses
939 // without changing the semantics.
940 static bool canUseBlockOperation(StoreSDNode *Store, LoadSDNode *Load,
942 // Check that the two memory operands have the same size.
943 if (Load->getMemoryVT() != Store->getMemoryVT())
946 // Volatility stops an access from being decomposed.
947 if (Load->isVolatile() || Store->isVolatile())
950 // There's no chance of overlap if the load is invariant.
951 if (Load->isInvariant())
954 // If both operands are aligned, they must be equal or not overlap.
955 uint64_t Size = Load->getMemoryVT().getStoreSize();
956 if (Load->getAlignment() >= Size && Store->getAlignment() >= Size)
959 // Otherwise we need to check whether there's an alias.
960 const Value *V1 = Load->getSrcValue();
961 const Value *V2 = Store->getSrcValue();
965 int64_t End1 = Load->getSrcValueOffset() + Size;
966 int64_t End2 = Store->getSrcValueOffset() + Size;
967 return !AA->alias(AliasAnalysis::Location(V1, End1, Load->getTBAAInfo()),
968 AliasAnalysis::Location(V2, End2, Store->getTBAAInfo()));
971 bool SystemZDAGToDAGISel::storeLoadCanUseMVC(SDNode *N) const {
972 StoreSDNode *Store = cast<StoreSDNode>(N);
973 LoadSDNode *Load = cast<LoadSDNode>(Store->getValue());
975 // Prefer not to use MVC if either address can use ... RELATIVE LONG
977 uint64_t Size = Load->getMemoryVT().getStoreSize();
978 if (Size > 1 && Size <= 8) {
979 // Prefer LHRL, LRL and LGRL.
980 if (Load->getBasePtr().getOpcode() == SystemZISD::PCREL_WRAPPER)
982 // Prefer STHRL, STRL and STGRL.
983 if (Store->getBasePtr().getOpcode() == SystemZISD::PCREL_WRAPPER)
987 return canUseBlockOperation(Store, Load, AA);
990 bool SystemZDAGToDAGISel::storeLoadCanUseBlockBinary(SDNode *N,
992 StoreSDNode *StoreA = cast<StoreSDNode>(N);
993 LoadSDNode *LoadA = cast<LoadSDNode>(StoreA->getValue().getOperand(1 - I));
994 LoadSDNode *LoadB = cast<LoadSDNode>(StoreA->getValue().getOperand(I));
995 if (LoadA->isVolatile() ||
996 LoadA->getMemoryVT() != StoreA->getMemoryVT() ||
997 LoadA->getBasePtr() != StoreA->getBasePtr())
999 return canUseBlockOperation(StoreA, LoadB, AA);
1002 SDNode *SystemZDAGToDAGISel::Select(SDNode *Node) {
1003 // Dump information about the Node being selected
1004 DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n");
1006 // If we have a custom node, we already have selected!
1007 if (Node->isMachineOpcode()) {
1008 DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
1012 unsigned Opcode = Node->getOpcode();
1013 SDNode *ResNode = 0;
1016 if (Node->getOperand(1).getOpcode() != ISD::Constant)
1017 ResNode = tryRxSBG(Node, SystemZ::ROSBG);
1021 if (Node->getOperand(1).getOpcode() != ISD::Constant)
1022 ResNode = tryRxSBG(Node, SystemZ::RXSBG);
1025 // If this is a 64-bit operation in which both 32-bit halves are nonzero,
1026 // split the operation into two.
1027 if (!ResNode && Node->getValueType(0) == MVT::i64)
1028 if (ConstantSDNode *Op1 = dyn_cast<ConstantSDNode>(Node->getOperand(1))) {
1029 uint64_t Val = Op1->getZExtValue();
1030 if (!SystemZ::isImmLF(Val) && !SystemZ::isImmHF(Val))
1031 Node = splitLargeImmediate(Opcode, Node, Node->getOperand(0),
1032 Val - uint32_t(Val), uint32_t(Val));
1037 if (Node->getOperand(1).getOpcode() != ISD::Constant)
1038 ResNode = tryRxSBG(Node, SystemZ::RNSBG);
1044 ResNode = tryRISBGZero(Node);
1048 // If this is a 64-bit constant that is out of the range of LLILF,
1049 // LLIHF and LGFI, split it into two 32-bit pieces.
1050 if (Node->getValueType(0) == MVT::i64) {
1051 uint64_t Val = cast<ConstantSDNode>(Node)->getZExtValue();
1052 if (!SystemZ::isImmLF(Val) && !SystemZ::isImmHF(Val) && !isInt<32>(Val))
1053 Node = splitLargeImmediate(ISD::OR, Node, SDValue(),
1054 Val - uint32_t(Val), uint32_t(Val));
1058 case ISD::ATOMIC_LOAD_SUB:
1059 // Try to convert subtractions of constants to additions.
1060 if (ConstantSDNode *Op2 = dyn_cast<ConstantSDNode>(Node->getOperand(2))) {
1061 uint64_t Value = -Op2->getZExtValue();
1062 EVT VT = Node->getValueType(0);
1063 if (VT == MVT::i32 || isInt<32>(Value)) {
1064 SDValue Ops[] = { Node->getOperand(0), Node->getOperand(1),
1065 CurDAG->getConstant(int32_t(Value), VT) };
1066 Node = CurDAG->MorphNodeTo(Node, ISD::ATOMIC_LOAD_ADD,
1067 Node->getVTList(), Ops, array_lengthof(Ops));
1072 case SystemZISD::SELECT_CCMASK: {
1073 SDValue Op0 = Node->getOperand(0);
1074 SDValue Op1 = Node->getOperand(1);
1075 // Prefer to put any load first, so that it can be matched as a
1076 // conditional load.
1077 if (Op1.getOpcode() == ISD::LOAD && Op0.getOpcode() != ISD::LOAD) {
1078 SDValue CCValid = Node->getOperand(2);
1079 SDValue CCMask = Node->getOperand(3);
1080 uint64_t ConstCCValid =
1081 cast<ConstantSDNode>(CCValid.getNode())->getZExtValue();
1082 uint64_t ConstCCMask =
1083 cast<ConstantSDNode>(CCMask.getNode())->getZExtValue();
1084 // Invert the condition.
1085 CCMask = CurDAG->getConstant(ConstCCValid ^ ConstCCMask,
1086 CCMask.getValueType());
1087 SDValue Op4 = Node->getOperand(4);
1088 Node = CurDAG->UpdateNodeOperands(Node, Op1, Op0, CCValid, CCMask, Op4);
1094 // Select the default instruction
1096 ResNode = SelectCode(Node);
1098 DEBUG(errs() << "=> ";
1099 if (ResNode == NULL || ResNode == Node)
1102 ResNode->dump(CurDAG);
1108 bool SystemZDAGToDAGISel::
1109 SelectInlineAsmMemoryOperand(const SDValue &Op,
1110 char ConstraintCode,
1111 std::vector<SDValue> &OutOps) {
1112 assert(ConstraintCode == 'm' && "Unexpected constraint code");
1113 // Accept addresses with short displacements, which are compatible
1114 // with Q, R, S and T. But keep the index operand for future expansion.
1115 SDValue Base, Disp, Index;
1116 if (!selectBDXAddr(SystemZAddressingMode::FormBD,
1117 SystemZAddressingMode::Disp12Only,
1118 Op, Base, Disp, Index))
1120 OutOps.push_back(Base);
1121 OutOps.push_back(Disp);
1122 OutOps.push_back(Index);