1 //===-- SparcRegInfo.cpp - Sparc Target Register Information --------------===//
3 // This file contains implementation of Sparc specific helper methods
4 // used for register allocation.
6 //===----------------------------------------------------------------------===//
8 #include "SparcInternals.h"
9 #include "SparcRegClassInfo.h"
10 #include "llvm/Target/Sparc.h"
11 #include "llvm/CodeGen/MachineCodeForMethod.h"
12 #include "llvm/CodeGen/PhyRegAlloc.h"
13 #include "llvm/CodeGen/MachineInstr.h"
14 #include "llvm/Analysis/LiveVar/MethodLiveVarInfo.h"
15 #include "llvm/iTerminators.h"
16 #include "llvm/iOther.h"
17 #include "llvm/DerivedTypes.h"
21 UltraSparcRegInfo::UltraSparcRegInfo(const UltraSparc &tgt)
22 : MachineRegInfo(tgt), UltraSparcInfo(&tgt), NumOfIntArgRegs(6),
23 NumOfFloatArgRegs(32), InvalidRegNum(1000) {
25 MachineRegClassArr.push_back(new SparcIntRegClass(IntRegClassID));
26 MachineRegClassArr.push_back(new SparcFloatRegClass(FloatRegClassID));
27 MachineRegClassArr.push_back(new SparcIntCCRegClass(IntCCRegClassID));
28 MachineRegClassArr.push_back(new SparcFloatCCRegClass(FloatCCRegClassID));
30 assert(SparcFloatRegOrder::StartOfNonVolatileRegs == 32 &&
31 "32 Float regs are used for float arg passing");
35 // getZeroRegNum - returns the register that contains always zero.
36 // this is the unified register number
38 int UltraSparcRegInfo::getZeroRegNum() const {
39 return this->getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
40 SparcIntRegOrder::g0);
43 // getCallAddressReg - returns the reg used for pushing the address when a
44 // method is called. This can be used for other purposes between calls
46 unsigned UltraSparcRegInfo::getCallAddressReg() const {
47 return this->getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
48 SparcIntRegOrder::o7);
51 // Returns the register containing the return address.
52 // It should be made sure that this register contains the return
53 // value when a return instruction is reached.
55 unsigned UltraSparcRegInfo::getReturnAddressReg() const {
56 return this->getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
57 SparcIntRegOrder::i7);
60 // given the unified register number, this gives the name
61 // for generating assembly code or debugging.
63 const std::string UltraSparcRegInfo::getUnifiedRegName(int reg) const {
65 return SparcIntRegOrder::getRegName(reg);
66 else if ( reg < (64 + 32) )
67 return SparcFloatRegOrder::getRegName( reg - 32);
68 else if( reg < (64+32+4) )
69 return SparcFloatCCRegOrder::getRegName( reg -32 - 64);
70 else if( reg < (64+32+4+2) ) // two names: %xcc and %ccr
71 return SparcIntCCRegOrder::getRegName( reg -32 - 64 - 4);
72 else if (reg== InvalidRegNum) //****** TODO: Remove */
75 assert(0 && "Invalid register number");
79 // Get unified reg number for frame pointer
80 unsigned UltraSparcRegInfo::getFramePointer() const {
81 return this->getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
82 SparcIntRegOrder::i6);
85 // Get unified reg number for stack pointer
86 unsigned UltraSparcRegInfo::getStackPointer() const {
87 return this->getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
88 SparcIntRegOrder::o6);
93 //---------------------------------------------------------------------------
94 // Finds the return value of a sparc specific call instruction
95 //---------------------------------------------------------------------------
98 UltraSparcRegInfo::getCallInstRetVal(const MachineInstr *CallMI) const {
99 unsigned OpCode = CallMI->getOpCode();
100 unsigned NumOfImpRefs = CallMI->getNumImplicitRefs();
102 if (OpCode == CALL) {
104 // The one before the last implicit operand is the return value of
107 if( NumOfImpRefs > 1 )
108 if (CallMI->implicitRefIsDefined(NumOfImpRefs-2))
109 return CallMI->getImplicitRef(NumOfImpRefs-2);
111 } else if (OpCode == JMPLCALL) {
113 // The last implicit operand is the return value of a JMPL
116 if (CallMI->implicitRefIsDefined(NumOfImpRefs-1))
117 return CallMI->getImplicitRef(NumOfImpRefs-1);
119 assert(0 && "OpCode must be CALL/JMPL for a call instr");
126 UltraSparcRegInfo::getCallInstIndirectAddrVal(const MachineInstr *CallMI) const
128 return (CallMI->getOpCode() == JMPLCALL)?
129 CallMI->getOperand(0).getVRegValue() : NULL;
133 //---------------------------------------------------------------------------
134 // Finds the return address of a call sparc specific call instruction
135 //---------------------------------------------------------------------------
137 UltraSparcRegInfo::getCallInstRetAddr(const MachineInstr *CallMI) const {
138 unsigned OpCode = CallMI->getOpCode();
140 if (OpCode == CALL) {
141 unsigned NumOfImpRefs = CallMI->getNumImplicitRefs();
143 assert( NumOfImpRefs && "CALL instr must have at least on ImpRef");
145 // The last implicit operand is the return address of a CALL instr
147 return CallMI->getImplicitRef(NumOfImpRefs-1);
149 } else if(OpCode == JMPLCALL) {
150 MachineOperand &MO = (MachineOperand &)CallMI->getOperand(2);
151 return MO.getVRegValue();
154 assert(0 && "OpCode must be CALL/JMPL for a call instr");
158 // The following 3 methods are used to find the RegType (see enum above)
159 // of a LiveRange, Value and using the unified RegClassID
161 int UltraSparcRegInfo::getRegType(const LiveRange *LR) const {
162 switch (LR->getRegClass()->getID()) {
163 case IntRegClassID: return IntRegType;
164 case FloatRegClassID: {
165 const Type *Typ = LR->getType();
166 if (Typ == Type::FloatTy)
167 return FPSingleRegType;
168 else if (Typ == Type::DoubleTy)
169 return FPDoubleRegType;
170 assert(0 && "Unknown type in FloatRegClass");
172 case IntCCRegClassID: return IntCCRegType;
173 case FloatCCRegClassID: return FloatCCRegType;
174 default: assert( 0 && "Unknown reg class ID");
179 int UltraSparcRegInfo::getRegType(const Value *Val) const {
182 switch (getRegClassIDOfValue(Val)) {
183 case IntRegClassID: return IntRegType;
184 case FloatRegClassID:
185 Typ = Val->getType()->getPrimitiveID();
186 if (Typ == Type::FloatTyID)
187 return FPSingleRegType;
188 else if (Typ == Type::DoubleTyID)
189 return FPDoubleRegType;
190 assert(0 && "Unknown type in FloatRegClass");
192 case IntCCRegClassID: return IntCCRegType;
193 case FloatCCRegClassID: return FloatCCRegType ;
194 default: assert(0 && "Unknown reg class ID");
199 int UltraSparcRegInfo::getRegType(int reg) const {
202 else if (reg < (32 + 32))
203 return FPSingleRegType;
204 else if (reg < (64 + 32))
205 return FPDoubleRegType;
206 else if (reg < (64+32+4))
207 return FloatCCRegType;
208 else if (reg < (64+32+4+2))
211 assert(0 && "Invalid register number in getRegType");
219 //---------------------------------------------------------------------------
220 // Finds the # of actual arguments of the call instruction
221 //---------------------------------------------------------------------------
223 UltraSparcRegInfo::getCallInstNumArgs(const MachineInstr *CallMI) const {
225 unsigned OpCode = CallMI->getOpCode();
226 unsigned NumOfImpRefs = CallMI->getNumImplicitRefs();
228 if (OpCode == CALL) {
229 switch (NumOfImpRefs) {
230 case 0: assert(0 && "A CALL inst must have at least one ImpRef (RetAddr)");
232 default: // two or more implicit refs
233 if (CallMI->implicitRefIsDefined(NumOfImpRefs-2))
234 return NumOfImpRefs - 2;
236 return NumOfImpRefs - 1;
238 } else if (OpCode == JMPLCALL) {
240 // The last implicit operand is the return value of a JMPL instr
241 if( NumOfImpRefs > 0 ) {
242 if (CallMI->implicitRefIsDefined(NumOfImpRefs-1))
243 return NumOfImpRefs - 1;
251 assert(0 && "OpCode must be CALL/JMPL for a call instr");
257 //---------------------------------------------------------------------------
258 // Finds whether a call is an indirect call
259 //---------------------------------------------------------------------------
260 bool UltraSparcRegInfo::isVarArgCall(const MachineInstr *CallMI) const {
262 assert ( (UltraSparcInfo->getInstrInfo()).isCall(CallMI->getOpCode()) );
264 const MachineOperand & calleeOp = CallMI->getOperand(0);
265 Value *calleeVal = calleeOp.getVRegValue();
267 PointerType *PT = cast<PointerType>(calleeVal->getType());
268 return cast<FunctionType>(PT->getElementType())->isVarArg();
274 //---------------------------------------------------------------------------
275 // Suggests a register for the ret address in the RET machine instruction.
276 // We always suggest %i7 by convention.
277 //---------------------------------------------------------------------------
278 void UltraSparcRegInfo::suggestReg4RetAddr(const MachineInstr *RetMI,
279 LiveRangeInfo& LRI) const {
281 assert( (RetMI->getNumOperands() >= 2)
282 && "JMPL/RETURN must have 3 and 2 operands respectively");
284 MachineOperand & MO = ( MachineOperand &) RetMI->getOperand(0);
286 // return address is always mapped to i7
288 MO.setRegForValue( getUnifiedRegNum( IntRegClassID, SparcIntRegOrder::i7) );
290 // Possible Optimization:
291 // Instead of setting the color, we can suggest one. In that case,
292 // we have to test later whether it received the suggested color.
293 // In that case, a LR has to be created at the start of method.
294 // It has to be done as follows (remove the setRegVal above):
296 // const Value *RetAddrVal = MO.getVRegValue();
297 // assert( RetAddrVal && "LR for ret address must be created at start");
298 // LiveRange * RetAddrLR = LRI.getLiveRangeForValue( RetAddrVal);
299 // RetAddrLR->setSuggestedColor(getUnifiedRegNum( IntRegClassID,
300 // SparcIntRegOrdr::i7) );
304 //---------------------------------------------------------------------------
305 // Suggests a register for the ret address in the JMPL/CALL machine instr.
306 // Sparc ABI dictates that %o7 be used for this purpose.
307 //---------------------------------------------------------------------------
308 void UltraSparcRegInfo::suggestReg4CallAddr(const MachineInstr * CallMI,
310 std::vector<RegClass *> RCList) const {
313 const Value *RetAddrVal = getCallInstRetAddr( CallMI );
315 // RetAddrVal cannot be NULL (asserted in getCallInstRetAddr)
316 // create a new LR for the return address and color it
318 LiveRange * RetAddrLR = new LiveRange();
319 RetAddrLR->insert( RetAddrVal );
320 unsigned RegClassID = getRegClassIDOfValue( RetAddrVal );
321 RetAddrLR->setRegClass( RCList[RegClassID] );
322 RetAddrLR->setColor(getUnifiedRegNum(IntRegClassID,SparcIntRegOrder::o7));
323 LRI.addLRToMap( RetAddrVal, RetAddrLR);
330 //---------------------------------------------------------------------------
331 // This method will suggest colors to incoming args to a method.
332 // According to the Sparc ABI, the first 6 incoming args are in
333 // %i0 - %i5 (if they are integer) OR in %f0 - %f31 (if they are float).
334 // If the arg is passed on stack due to the lack of regs, NOTHING will be
335 // done - it will be colored (or spilled) as a normal live range.
336 //---------------------------------------------------------------------------
337 void UltraSparcRegInfo::suggestRegs4MethodArgs(const Function *Meth,
338 LiveRangeInfo& LRI) const
341 // get the argument list
342 const Function::ArgumentListType& ArgList = Meth->getArgumentList();
343 // get an iterator to arg list
344 Function::ArgumentListType::const_iterator ArgIt = ArgList.begin();
347 for( unsigned argNo=0; ArgIt != ArgList.end() ; ++ArgIt, ++argNo) {
350 LiveRange *const LR = LRI.getLiveRangeForValue((const Value *) *ArgIt);
351 assert( LR && "No live range found for method arg");
353 unsigned RegType = getRegType( LR );
356 // if the arg is in int class - allocate a reg for an int arg
358 if( RegType == IntRegType ) {
360 if( argNo < NumOfIntArgRegs) {
361 LR->setSuggestedColor( SparcIntRegOrder::i0 + argNo );
364 // Do NOTHING as this will be colored as a normal value.
365 if (DEBUG_RA) cerr << " Int Regr not suggested for method arg\n";
369 else if( RegType==FPSingleRegType && (argNo*2+1) < NumOfFloatArgRegs)
370 LR->setSuggestedColor( SparcFloatRegOrder::f0 + (argNo * 2 + 1) );
373 else if( RegType == FPDoubleRegType && (argNo*2) < NumOfFloatArgRegs)
374 LR->setSuggestedColor( SparcFloatRegOrder::f0 + (argNo * 2) );
381 //---------------------------------------------------------------------------
382 // This method is called after graph coloring to move incoming args to
383 // the correct hardware registers if they did not receive the correct
384 // (suggested) color through graph coloring.
385 //---------------------------------------------------------------------------
386 void UltraSparcRegInfo::colorMethodArgs(const Function *Meth,
388 AddedInstrns *FirstAI) const {
390 // get the argument list
391 const Function::ArgumentListType& ArgList = Meth->getArgumentList();
392 // get an iterator to arg list
393 Function::ArgumentListType::const_iterator ArgIt = ArgList.begin();
398 for( unsigned argNo=0; ArgIt != ArgList.end() ; ++ArgIt, ++argNo) {
401 LiveRange *LR = LRI.getLiveRangeForValue(*ArgIt);
402 assert( LR && "No live range found for method arg");
405 unsigned RegType = getRegType( LR );
406 unsigned RegClassID = (LR->getRegClass())->getID();
408 // Find whether this argument is coming in a register (if not, on stack)
409 // Also find the correct register that the argument must go (UniArgReg)
411 bool isArgInReg = false;
412 unsigned UniArgReg = InvalidRegNum; // reg that LR MUST be colored with
414 if( (RegType== IntRegType && argNo < NumOfIntArgRegs)) {
416 UniArgReg = getUnifiedRegNum( RegClassID, SparcIntRegOrder::i0 + argNo );
418 else if(RegType == FPSingleRegType && argNo < NumOfFloatArgRegs) {
420 UniArgReg = getUnifiedRegNum( RegClassID,
421 SparcFloatRegOrder::f0 + argNo*2 + 1 ) ;
423 else if(RegType == FPDoubleRegType && argNo < NumOfFloatArgRegs) {
425 UniArgReg = getUnifiedRegNum(RegClassID, SparcFloatRegOrder::f0+argNo*2);
429 if( LR->hasColor() ) { // if this arg received a register
431 unsigned UniLRReg = getUnifiedRegNum( RegClassID, LR->getColor() );
433 // if LR received the correct color, nothing to do
435 if( UniLRReg == UniArgReg )
438 // We are here because the LR did not receive the suggested
439 // but LR received another register.
440 // Now we have to copy the %i reg (or stack pos of arg)
441 // to the register the LR was colored with.
443 // if the arg is coming in UniArgReg register, it MUST go into
444 // the UniLRReg register
447 AdMI = cpReg2RegMI( UniArgReg, UniLRReg, RegType );
451 // Now the arg is coming on stack. Since the LR recieved a register,
452 // we just have to load the arg on stack into that register
454 const MachineFrameInfo& frameInfo = target.getFrameInfo();
455 assert(frameInfo.argsOnStackHaveFixedSize());
457 bool growUp; // find the offset of arg in stack frame
459 frameInfo.getFirstIncomingArgOffset(MachineCodeForMethod::get(Meth),
462 growUp? firstArg + argNo * frameInfo.getSizeOfEachArgOnStack()
463 : firstArg - argNo * frameInfo.getSizeOfEachArgOnStack();
465 AdMI = cpMem2RegMI(getFramePointer(), offsetFromFP,
469 FirstAI->InstrnsBefore.push_back( AdMI );
471 } // if LR received a color
475 // Now, the LR did not receive a color. But it has a stack offset for
477 // So, if the arg is coming in UniArgReg register, we can just move
478 // that on to the stack pos of LR
481 cpReg2MemMI(UniArgReg, getFramePointer(),
482 LR->getSpillOffFromFP(), RegType );
484 FirstAI->InstrnsBefore.push_back( AdMI );
489 // Now the arg is coming on stack. Since the LR did NOT
490 // recieved a register as well, it is allocated a stack position. We
491 // can simply change the stack poistion of the LR. We can do this,
492 // since this method is called before any other method that makes
493 // uses of the stack pos of the LR (e.g., updateMachineInstr)
495 const MachineFrameInfo& frameInfo = target.getFrameInfo();
496 assert(frameInfo.argsOnStackHaveFixedSize());
499 int firstArg = frameInfo.getFirstIncomingArgOffset(MachineCodeForMethod::get(Meth), growUp);
501 growUp? firstArg + argNo * frameInfo.getSizeOfEachArgOnStack()
502 : firstArg - argNo * frameInfo.getSizeOfEachArgOnStack();
504 LR->modifySpillOffFromFP( offsetFromFP );
509 } // for each incoming argument
515 //---------------------------------------------------------------------------
516 // This method is called before graph coloring to suggest colors to the
517 // outgoing call args and the return value of the call.
518 //---------------------------------------------------------------------------
519 void UltraSparcRegInfo::suggestRegs4CallArgs(const MachineInstr *CallMI,
521 std::vector<RegClass *> RCList) const {
523 assert ( (UltraSparcInfo->getInstrInfo()).isCall(CallMI->getOpCode()) );
525 suggestReg4CallAddr(CallMI, LRI, RCList);
528 // First color the return value of the call instruction. The return value
529 // will be in %o0 if the value is an integer type, or in %f0 if the
530 // value is a float type.
532 // the return value cannot have a LR in machine instruction since it is
533 // only defined by the call instruction
535 // if type is not void, create a new live range and set its
536 // register class and add to LRI
539 const Value *RetVal = getCallInstRetVal( CallMI );
543 assert ((!LRI.getLiveRangeForValue(RetVal)) &&
544 "LR for ret Value of call already definded!");
546 // create a new LR for the return value
547 LiveRange *RetValLR = new LiveRange();
548 RetValLR->insert(RetVal);
549 unsigned RegClassID = getRegClassIDOfValue(RetVal);
550 RetValLR->setRegClass(RCList[RegClassID]);
551 LRI.addLRToMap(RetVal, RetValLR);
553 // now suggest a register depending on the register class of ret arg
555 if( RegClassID == IntRegClassID )
556 RetValLR->setSuggestedColor(SparcIntRegOrder::o0);
557 else if (RegClassID == FloatRegClassID )
558 RetValLR->setSuggestedColor(SparcFloatRegOrder::f0 );
559 else assert( 0 && "Unknown reg class for return value of call\n");
563 // Now suggest colors for arguments (operands) of the call instruction.
564 // Colors are suggested only if the arg number is smaller than the
565 // the number of registers allocated for argument passing.
566 // Now, go thru call args - implicit operands of the call MI
568 unsigned NumOfCallArgs = getCallInstNumArgs( CallMI );
570 for(unsigned argNo=0, i=0; i < NumOfCallArgs; ++i, ++argNo ) {
572 const Value *CallArg = CallMI->getImplicitRef(i);
574 // get the LR of call operand (parameter)
575 LiveRange *const LR = LRI.getLiveRangeForValue(CallArg);
577 // not possible to have a null LR since all args (even consts)
578 // must be defined before
580 cerr << " ERROR: In call instr, no LR for arg: " << RAV(CallArg) << "\n";
581 assert(0 && "NO LR for call arg");
584 unsigned RegType = getRegType( LR );
586 // if the arg is in int class - allocate a reg for an int arg
587 if( RegType == IntRegType ) {
589 if( argNo < NumOfIntArgRegs)
590 LR->setSuggestedColor( SparcIntRegOrder::o0 + argNo );
593 // Do NOTHING as this will be colored as a normal value.
594 cerr << " Regr not suggested for int call arg\n";
597 else if( RegType == FPSingleRegType && (argNo*2 +1)< NumOfFloatArgRegs)
598 LR->setSuggestedColor( SparcFloatRegOrder::f0 + (argNo * 2 + 1) );
601 else if( RegType == FPDoubleRegType && (argNo*2) < NumOfFloatArgRegs)
602 LR->setSuggestedColor( SparcFloatRegOrder::f0 + (argNo * 2) );
605 } // for all call arguments
610 //---------------------------------------------------------------------------
611 // After graph coloring, we have call this method to see whehter the return
612 // value and the call args received the correct colors. If not, we have
613 // to instert copy instructions.
614 //---------------------------------------------------------------------------
616 void UltraSparcRegInfo::colorCallArgs(const MachineInstr *CallMI,
618 AddedInstrns *CallAI,
620 const BasicBlock *BB) const {
622 assert ( (UltraSparcInfo->getInstrInfo()).isCall(CallMI->getOpCode()) );
624 // Reset the optional args area in the stack frame
625 // since that is reused for each call
627 PRA.mcInfo.resetOptionalArgs(target);
629 // First color the return value of the call.
630 // If there is a LR for the return value, it means this
631 // method returns a value
635 const Value *RetVal = getCallInstRetVal( CallMI );
638 LiveRange *RetValLR = LRI.getLiveRangeForValue( RetVal );
641 cerr << "\nNo LR for:" << RAV(RetVal) << "\n";
642 assert(0 && "ERR:No LR for non-void return value");
645 unsigned RegClassID = (RetValLR->getRegClass())->getID();
646 bool recvCorrectColor = false;
648 unsigned CorrectCol; // correct color for ret value
649 if(RegClassID == IntRegClassID)
650 CorrectCol = SparcIntRegOrder::o0;
651 else if(RegClassID == FloatRegClassID)
652 CorrectCol = SparcFloatRegOrder::f0;
654 assert( 0 && "Unknown RegClass");
658 // if the LR received the correct color, NOTHING to do
660 if( RetValLR->hasColor() )
661 if( RetValLR->getColor() == CorrectCol )
662 recvCorrectColor = true;
665 // if we didn't receive the correct color for some reason,
666 // put copy instruction
668 if( !recvCorrectColor ) {
670 unsigned RegType = getRegType( RetValLR );
672 // the reg that LR must be colored with
673 unsigned UniRetReg = getUnifiedRegNum( RegClassID, CorrectCol);
675 if( RetValLR->hasColor() ) {
678 UniRetLRReg=getUnifiedRegNum(RegClassID,RetValLR->getColor());
680 // the return value is coming in UniRetReg but has to go into
683 AdMI = cpReg2RegMI( UniRetReg, UniRetLRReg, RegType );
688 // if the LR did NOT receive a color, we have to move the return
689 // value coming in UniRetReg to the stack pos of spilled LR
691 AdMI = cpReg2MemMI(UniRetReg, getFramePointer(),
692 RetValLR->getSpillOffFromFP(), RegType );
695 CallAI->InstrnsAfter.push_back( AdMI );
697 } // the LR didn't receive the suggested color
699 } // if there a return value
702 //-------------------------------------------
703 // Now color all args of the call instruction
704 //-------------------------------------------
706 std::vector<MachineInstr *> AddedInstrnsBefore;
708 unsigned NumOfCallArgs = getCallInstNumArgs( CallMI );
710 bool VarArgCall = isVarArgCall( CallMI );
712 if(VarArgCall) cerr << "\nVar arg call found!!\n";
714 for(unsigned argNo=0, i=0; i < NumOfCallArgs; ++i, ++argNo ) {
716 const Value *CallArg = CallMI->getImplicitRef(i);
718 // get the LR of call operand (parameter)
719 LiveRange *const LR = LRI.getLiveRangeForValue(CallArg);
721 unsigned RegType = getRegType( CallArg );
722 unsigned RegClassID = getRegClassIDOfValue( CallArg);
724 // find whether this argument is coming in a register (if not, on stack)
726 bool isArgInReg = false;
727 unsigned UniArgReg = InvalidRegNum; // reg that LR must be colored with
729 if( (RegType== IntRegType && argNo < NumOfIntArgRegs)) {
731 UniArgReg = getUnifiedRegNum(RegClassID, SparcIntRegOrder::o0 + argNo );
733 else if(RegType == FPSingleRegType && argNo < NumOfFloatArgRegs) {
737 UniArgReg = getUnifiedRegNum(RegClassID,
738 SparcFloatRegOrder::f0 + (argNo*2 + 1) );
740 // a variable argument call - must pass float arg in %o's
741 if( argNo < NumOfIntArgRegs)
742 UniArgReg=getUnifiedRegNum(IntRegClassID,SparcIntRegOrder::o0+argNo);
748 else if(RegType == FPDoubleRegType && argNo < NumOfFloatArgRegs) {
752 UniArgReg =getUnifiedRegNum(RegClassID,SparcFloatRegOrder::f0+argNo*2);
754 // a variable argument call - must pass float arg in %o's
755 if( argNo < NumOfIntArgRegs)
756 UniArgReg=getUnifiedRegNum(IntRegClassID,SparcIntRegOrder::o0+argNo);
762 // not possible to have a null LR since all args (even consts)
763 // must be defined before
765 cerr << " ERROR: In call instr, no LR for arg: " << RAV(CallArg) << "\n";
766 assert(0 && "NO LR for call arg");
770 if (LR->hasColor()) {
771 unsigned UniLRReg = getUnifiedRegNum( RegClassID, LR->getColor() );
773 // if LR received the correct color, nothing to do
774 if( UniLRReg == UniArgReg )
777 // We are here because though the LR is allocated a register, it
778 // was not allocated the suggested register. So, we have to copy %ix reg
779 // (or stack pos of arg) to the register it was colored with
781 // the LR is colored with UniLRReg but has to go into UniArgReg
782 // to pass it as an argument
786 if( VarArgCall && RegClassID == FloatRegClassID ) {
789 // for a variable argument call, the float reg must go in a %o reg.
790 // We have to move a float reg to an int reg via memory.
791 // The store instruction will be directly added to
792 // CallAI->InstrnsBefore since it does not need reordering
794 int TmpOff = PRA.mcInfo.pushTempValue(target,
795 getSpilledRegSize(RegType));
797 AdMI = cpReg2MemMI(UniLRReg, getFramePointer(), TmpOff, RegType );
798 CallAI->InstrnsBefore.push_back( AdMI );
800 AdMI = cpMem2RegMI(getFramePointer(), TmpOff, UniArgReg, IntRegType);
801 AddedInstrnsBefore.push_back( AdMI );
805 AdMI = cpReg2RegMI(UniLRReg, UniArgReg, RegType );
806 AddedInstrnsBefore.push_back( AdMI );
810 // Now, we have to pass the arg on stack. Since LR received a register
811 // we just have to move that register to the stack position where
812 // the argument must be passed
814 int argOffset = PRA.mcInfo.allocateOptionalArg(target, LR->getType());
816 AdMI = cpReg2MemMI(UniLRReg, getStackPointer(), argOffset, RegType );
818 // Now add the instruction. We can directly add to
819 // CallAI->InstrnsBefore since we are just saving a reg on stack
821 CallAI->InstrnsBefore.push_back( AdMI );
823 //cerr << "\nCaution: Passing a reg on stack";
827 } else { // LR is not colored (i.e., spilled)
831 // Now the LR did NOT recieve a register but has a stack poistion.
832 // Since, the outgoing arg goes in a register we just have to insert
833 // a load instruction to load the LR to outgoing register
835 if( VarArgCall && RegClassID == FloatRegClassID )
836 AdMI = cpMem2RegMI(getFramePointer(), LR->getSpillOffFromFP(),
837 UniArgReg, IntRegType );
839 AdMI = cpMem2RegMI(getFramePointer(), LR->getSpillOffFromFP(),
840 UniArgReg, RegType );
842 cerr << "\nCaution: Loading a spilled val to a reg as a call arg";
843 AddedInstrnsBefore.push_back( AdMI ); // Now add the instruction
847 // Now, we have to pass the arg on stack. Since LR also did NOT
848 // receive a register we have to move an argument in memory to
849 // outgoing parameter on stack.
851 // Optoimize: Optimize when reverse pointers in MahineInstr are
853 // call PRA.getUnusedRegAtMI(....) to get an unused reg. Only if this
854 // fails, then use the following code. Currently, we cannot call the
855 // above method since we cannot find LVSetBefore without the BB
857 int TReg = PRA.getUniRegNotUsedByThisInst( LR->getRegClass(), CallMI );
859 int TmpOff = PRA.mcInfo.pushTempValue(target,
860 getSpilledRegSize(getRegType(LR)) );
863 int argOffset = PRA.mcInfo.allocateOptionalArg(target, LR->getType());
865 MachineInstr *Ad1, *Ad2, *Ad3, *Ad4;
868 // (1) Save TReg on stack
869 // (2) Load LR value into TReg from stack pos of LR
870 // (3) Store Treg on outgoing Arg pos on stack
871 // (4) Load the old value of TReg from stack to TReg (restore it)
873 Ad1 = cpReg2MemMI(TReg, getFramePointer(), TmpOff, RegType );
874 Ad2 = cpMem2RegMI(getFramePointer(), LR->getSpillOffFromFP(),
876 Ad3 = cpReg2MemMI(TReg, getStackPointer(), argOffset, RegType );
877 Ad4 = cpMem2RegMI(getFramePointer(), TmpOff, TReg, RegType );
879 // We directly add to CallAI->InstrnsBefore instead of adding to
880 // AddedInstrnsBefore since these instructions must not be
883 CallAI->InstrnsBefore.push_back( Ad1 );
884 CallAI->InstrnsBefore.push_back( Ad2 );
885 CallAI->InstrnsBefore.push_back( Ad3 );
886 CallAI->InstrnsBefore.push_back( Ad4 );
888 cerr << "\nCaution: Call arg moved from stack2stack for: " << *CallMI ;
891 } // for each parameter in call instruction
894 // if we added any instruction before the call instruction, verify
895 // that they are in the proper order and if not, reorder them
897 if (!AddedInstrnsBefore.empty()) {
900 cerr << "\nCalling reorder with instrns: \n";
901 for(unsigned i=0; i < AddedInstrnsBefore.size(); i++)
902 cerr << *(AddedInstrnsBefore[i]);
905 std::vector<MachineInstr *> TmpVec;
906 OrderAddedInstrns(AddedInstrnsBefore, TmpVec, PRA);
909 cerr << "\nAfter reordering instrns: \n";
910 for(unsigned i = 0; i < TmpVec.size(); i++)
914 // copy the results back from TmpVec to InstrnsBefore
915 for(unsigned i=0; i < TmpVec.size(); i++)
916 CallAI->InstrnsBefore.push_back( TmpVec[i] );
920 // now insert caller saving code for this call instruction
922 insertCallerSavingCode(CallMI, BB, PRA);
924 // Reset optional args area again to be safe
925 PRA.mcInfo.resetOptionalArgs(target);
928 //---------------------------------------------------------------------------
929 // This method is called for an LLVM return instruction to identify which
930 // values will be returned from this method and to suggest colors.
931 //---------------------------------------------------------------------------
932 void UltraSparcRegInfo::suggestReg4RetValue(const MachineInstr *RetMI,
933 LiveRangeInfo &LRI) const {
935 assert( (UltraSparcInfo->getInstrInfo()).isReturn( RetMI->getOpCode() ) );
937 suggestReg4RetAddr(RetMI, LRI);
939 // if there is an implicit ref, that has to be the ret value
940 if( RetMI->getNumImplicitRefs() > 0 ) {
942 // The first implicit operand is the return value of a return instr
943 const Value *RetVal = RetMI->getImplicitRef(0);
945 LiveRange *const LR = LRI.getLiveRangeForValue( RetVal );
948 cerr << "\nNo LR for:" << RAV(RetVal) << "\n";
949 assert(0 && "No LR for return value of non-void method");
952 unsigned RegClassID = (LR->getRegClass())->getID();
954 if (RegClassID == IntRegClassID)
955 LR->setSuggestedColor(SparcIntRegOrder::i0);
956 else if (RegClassID == FloatRegClassID)
957 LR->setSuggestedColor(SparcFloatRegOrder::f0);
963 //---------------------------------------------------------------------------
964 // Colors the return value of a method to %i0 or %f0, if possible. If it is
965 // not possilbe to directly color the LR, insert a copy instruction to move
966 // the LR to %i0 or %f0. When the LR is spilled, instead of the copy, we
967 // have to put a load instruction.
968 //---------------------------------------------------------------------------
969 void UltraSparcRegInfo::colorRetValue(const MachineInstr *RetMI,
971 AddedInstrns *RetAI) const {
973 assert((UltraSparcInfo->getInstrInfo()).isReturn( RetMI->getOpCode()));
975 // if there is an implicit ref, that has to be the ret value
976 if(RetMI->getNumImplicitRefs() > 0) {
978 // The first implicit operand is the return value of a return instr
979 const Value *RetVal = RetMI->getImplicitRef(0);
981 LiveRange *LR = LRI.getLiveRangeForValue(RetVal);
984 cerr << "\nNo LR for:" << RAV(RetVal) << "\n";
985 // assert( LR && "No LR for return value of non-void method");
989 unsigned RegClassID = getRegClassIDOfValue(RetVal);
990 unsigned RegType = getRegType( RetVal );
993 if(RegClassID == IntRegClassID)
994 CorrectCol = SparcIntRegOrder::i0;
995 else if(RegClassID == FloatRegClassID)
996 CorrectCol = SparcFloatRegOrder::f0;
998 assert (0 && "Unknown RegClass");
1002 // if the LR received the correct color, NOTHING to do
1004 if (LR->hasColor() && LR->getColor() == CorrectCol)
1007 unsigned UniRetReg = getUnifiedRegNum(RegClassID, CorrectCol);
1009 if (LR->hasColor()) {
1011 // We are here because the LR was allocted a regiter
1012 // It may be the suggested register or not
1014 // copy the LR of retun value to i0 or f0
1016 unsigned UniLRReg =getUnifiedRegNum( RegClassID, LR->getColor());
1018 // the LR received UniLRReg but must be colored with UniRetReg
1019 // to pass as the return value
1020 RetAI->InstrnsBefore.push_back(cpReg2RegMI(UniLRReg, UniRetReg, RegType));
1022 else { // if the LR is spilled
1023 MachineInstr *AdMI = cpMem2RegMI(getFramePointer(),
1024 LR->getSpillOffFromFP(),
1025 UniRetReg, RegType);
1026 RetAI->InstrnsBefore.push_back(AdMI);
1027 cerr << "\nCopied the return value from stack\n";
1030 } // if there is a return value
1035 //---------------------------------------------------------------------------
1036 // Copy from a register to register. Register number must be the unified
1038 //---------------------------------------------------------------------------
1040 MachineInstr * UltraSparcRegInfo::cpReg2RegMI(unsigned SrcReg, unsigned DestReg,
1041 int RegType) const {
1043 assert( ((int)SrcReg != InvalidRegNum) && ((int)DestReg != InvalidRegNum) &&
1044 "Invalid Register");
1046 MachineInstr * MI = NULL;
1052 case FloatCCRegType:
1053 MI = new MachineInstr(ADD, 3);
1054 MI->SetMachineOperandReg(0, SrcReg, false);
1055 MI->SetMachineOperandReg(1, this->getZeroRegNum(), false);
1056 MI->SetMachineOperandReg(2, DestReg, true);
1059 case FPSingleRegType:
1060 MI = new MachineInstr(FMOVS, 2);
1061 MI->SetMachineOperandReg(0, SrcReg, false);
1062 MI->SetMachineOperandReg(1, DestReg, true);
1065 case FPDoubleRegType:
1066 MI = new MachineInstr(FMOVD, 2);
1067 MI->SetMachineOperandReg(0, SrcReg, false);
1068 MI->SetMachineOperandReg(1, DestReg, true);
1072 assert(0 && "Unknow RegType");
1079 //---------------------------------------------------------------------------
1080 // Copy from a register to memory (i.e., Store). Register number must
1081 // be the unified register number
1082 //---------------------------------------------------------------------------
1085 MachineInstr * UltraSparcRegInfo::cpReg2MemMI(unsigned SrcReg,
1086 unsigned DestPtrReg,
1087 int Offset, int RegType) const {
1088 MachineInstr * MI = NULL;
1091 case FloatCCRegType:
1092 MI = new MachineInstr(STX, 3);
1093 MI->SetMachineOperandReg(0, SrcReg, false);
1094 MI->SetMachineOperandReg(1, DestPtrReg, false);
1095 MI->SetMachineOperandConst(2, MachineOperand:: MO_SignExtendedImmed,
1099 case FPSingleRegType:
1100 MI = new MachineInstr(ST, 3);
1101 MI->SetMachineOperandReg(0, SrcReg, false);
1102 MI->SetMachineOperandReg(1, DestPtrReg, false);
1103 MI->SetMachineOperandConst(2, MachineOperand:: MO_SignExtendedImmed,
1107 case FPDoubleRegType:
1108 MI = new MachineInstr(STD, 3);
1109 MI->SetMachineOperandReg(0, SrcReg, false);
1110 MI->SetMachineOperandReg(1, DestPtrReg, false);
1111 MI->SetMachineOperandConst(2, MachineOperand:: MO_SignExtendedImmed,
1116 assert( 0 && "Cannot directly store %ccr to memory");
1119 assert(0 && "Unknow RegType in cpReg2MemMI");
1126 //---------------------------------------------------------------------------
1127 // Copy from memory to a reg (i.e., Load) Register number must be the unified
1129 //---------------------------------------------------------------------------
1132 MachineInstr * UltraSparcRegInfo::cpMem2RegMI(unsigned SrcPtrReg,
1135 int RegType) const {
1136 MachineInstr * MI = NULL;
1139 case FloatCCRegType:
1140 MI = new MachineInstr(LDX, 3);
1141 MI->SetMachineOperandReg(0, SrcPtrReg, false);
1142 MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed,
1144 MI->SetMachineOperandReg(2, DestReg, true);
1147 case FPSingleRegType:
1148 MI = new MachineInstr(LD, 3);
1149 MI->SetMachineOperandReg(0, SrcPtrReg, false);
1150 MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed,
1152 MI->SetMachineOperandReg(2, DestReg, true);
1156 case FPDoubleRegType:
1157 MI = new MachineInstr(LDD, 3);
1158 MI->SetMachineOperandReg(0, SrcPtrReg, false);
1159 MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed,
1161 MI->SetMachineOperandReg(2, DestReg, true);
1165 assert( 0 && "Cannot directly load into %ccr from memory");
1168 assert(0 && "Unknown RegType in cpMem2RegMI");
1178 //---------------------------------------------------------------------------
1179 // Generate a copy instruction to copy a value to another. Temporarily
1180 // used by PhiElimination code.
1181 //---------------------------------------------------------------------------
1184 MachineInstr *UltraSparcRegInfo::cpValue2Value(Value *Src, Value *Dest) const {
1185 int RegType = getRegType( Src );
1187 assert( (RegType==getRegType(Src)) && "Src & Dest are diff types");
1189 MachineInstr * MI = NULL;
1193 MI = new MachineInstr(ADD, 3);
1194 MI->SetMachineOperandVal(0, MachineOperand:: MO_VirtualRegister, Src, false);
1195 MI->SetMachineOperandReg(1, this->getZeroRegNum(), false);
1196 MI->SetMachineOperandVal(2, MachineOperand:: MO_VirtualRegister, Dest, true);
1199 case FPSingleRegType:
1200 MI = new MachineInstr(FMOVS, 2);
1201 MI->SetMachineOperandVal(0, MachineOperand:: MO_VirtualRegister, Src, false);
1202 MI->SetMachineOperandVal(1, MachineOperand:: MO_VirtualRegister, Dest, true);
1206 case FPDoubleRegType:
1207 MI = new MachineInstr(FMOVD, 2);
1208 MI->SetMachineOperandVal(0, MachineOperand:: MO_VirtualRegister, Src, false);
1209 MI->SetMachineOperandVal(1, MachineOperand:: MO_VirtualRegister, Dest, true);
1213 assert(0 && "Unknow RegType in CpValu2Value");
1224 //----------------------------------------------------------------------------
1225 // This method inserts caller saving/restoring instructons before/after
1226 // a call machine instruction. The caller saving/restoring instructions are
1229 // ** caller saving instructions
1230 // other instructions inserted for the call by ColorCallArg
1232 // other instructions inserted for the call ColorCallArg
1233 // ** caller restoring instructions
1235 //----------------------------------------------------------------------------
1238 void UltraSparcRegInfo::insertCallerSavingCode(const MachineInstr *MInst,
1239 const BasicBlock *BB,
1240 PhyRegAlloc &PRA) const {
1242 // has set to record which registers were saved/restored
1244 std::hash_set<unsigned> PushedRegSet;
1246 // Now find the LR of the return value of the call
1247 // The last *implicit operand* is the return value of a call
1248 // Insert it to to he PushedRegSet since we must not save that register
1249 // and restore it after the call.
1250 // We do this because, we look at the LV set *after* the instruction
1251 // to determine, which LRs must be saved across calls. The return value
1252 // of the call is live in this set - but we must not save/restore it.
1255 const Value *RetVal = getCallInstRetVal( MInst );
1258 LiveRange *RetValLR = PRA.LRI.getLiveRangeForValue( RetVal );
1259 assert(RetValLR && "No LR for RetValue of call");
1261 if (RetValLR->hasColor())
1262 PushedRegSet.insert(
1263 getUnifiedRegNum((RetValLR->getRegClass())->getID(),
1264 RetValLR->getColor() ) );
1268 const ValueSet &LVSetAft = PRA.LVI->getLiveVarSetAfterMInst(MInst, BB);
1269 ValueSet::const_iterator LIt = LVSetAft.begin();
1271 // for each live var in live variable set after machine inst
1272 for( ; LIt != LVSetAft.end(); ++LIt) {
1274 // get the live range corresponding to live var
1275 LiveRange *const LR = PRA.LRI.getLiveRangeForValue(*LIt );
1277 // LR can be null if it is a const since a const
1278 // doesn't have a dominating def - see Assumptions above
1281 if( LR->hasColor() ) {
1283 unsigned RCID = (LR->getRegClass())->getID();
1284 unsigned Color = LR->getColor();
1286 if ( isRegVolatile(RCID, Color) ) {
1288 // if the value is in both LV sets (i.e., live before and after
1289 // the call machine instruction)
1291 unsigned Reg = getUnifiedRegNum(RCID, Color);
1293 if( PushedRegSet.find(Reg) == PushedRegSet.end() ) {
1295 // if we haven't already pushed that register
1297 unsigned RegType = getRegType( LR );
1299 // Now get two instructions - to push on stack and pop from stack
1300 // and add them to InstrnsBefore and InstrnsAfter of the
1304 int StackOff = PRA.mcInfo.pushTempValue(target,
1305 getSpilledRegSize(RegType));
1308 MachineInstr *AdIBefCC=NULL, *AdIAftCC=NULL, *AdICpCC;
1309 MachineInstr *AdIBef=NULL, *AdIAft=NULL;
1311 //---- Insert code for pushing the reg on stack ----------
1313 if( RegType == IntCCRegType ) {
1315 // Handle IntCCRegType specially since we cannot directly
1316 // push %ccr on to the stack
1318 const ValueSet &LVSetBef =
1319 PRA.LVI->getLiveVarSetBeforeMInst(MInst, BB);
1321 // get a free INTEGER register
1323 PRA.getUsableUniRegAtMI(PRA.getRegClassByID(IntRegClassID) /*LR->getRegClass()*/,
1324 IntRegType, MInst, &LVSetBef, AdIBefCC, AdIAftCC);
1326 // insert the instructions in reverse order since we are
1327 // adding them to the front of InstrnsBefore
1330 PRA.AddedInstrMap[MInst]->InstrnsBefore.push_front(AdIAftCC);
1332 AdICpCC = cpCCR2IntMI(FreeIntReg);
1333 PRA.AddedInstrMap[MInst]->InstrnsBefore.push_front(AdICpCC);
1336 PRA.AddedInstrMap[MInst]->InstrnsBefore.push_front(AdIBefCC);
1339 cerr << "\n!! Inserted caller saving (push) inst for %ccr:";
1340 if(AdIBefCC) cerr << "\t" << *(AdIBefCC);
1341 cerr << "\t" << *AdICpCC;
1342 if(AdIAftCC) cerr << "\t" << *(AdIAftCC);
1346 // for any other register type, just add the push inst
1347 AdIBef = cpReg2MemMI(Reg, getFramePointer(), StackOff, RegType );
1348 PRA.AddedInstrMap[MInst]->InstrnsBefore.push_front(AdIBef);
1352 //---- Insert code for popping the reg from the stack ----------
1354 if (RegType == IntCCRegType) {
1356 // Handle IntCCRegType specially since we cannot directly
1357 // pop %ccr on from the stack
1359 // get a free INT register
1361 PRA.getUsableUniRegAtMI(PRA.getRegClassByID(IntRegClassID) /* LR->getRegClass()*/,
1362 IntRegType, MInst, &LVSetAft, AdIBefCC, AdIAftCC);
1365 PRA.AddedInstrMap[MInst]->InstrnsAfter.push_back(AdIBefCC);
1367 AdICpCC = cpInt2CCRMI(FreeIntReg);
1368 PRA.AddedInstrMap[MInst]->InstrnsAfter.push_back(AdICpCC);
1371 PRA.AddedInstrMap[MInst]->InstrnsAfter.push_back(AdIAftCC);
1375 cerr << "\n!! Inserted caller saving (pop) inst for %ccr:";
1376 if(AdIBefCC) cerr << "\t" << *(AdIBefCC);
1377 cerr << "\t" << *AdICpCC;
1378 if(AdIAftCC) cerr << "\t" << *(AdIAftCC);
1382 // for any other register type, just add the pop inst
1383 AdIAft = cpMem2RegMI(getFramePointer(), StackOff, Reg, RegType );
1384 PRA.AddedInstrMap[MInst]->InstrnsAfter.push_back(AdIAft);
1387 PushedRegSet.insert(Reg);
1390 cerr << "\nFor call inst:" << *MInst;
1391 cerr << " -inserted caller saving instrs:\n\t ";
1392 if( RegType == IntCCRegType ) {
1393 if(AdIBefCC) cerr << *AdIBefCC << "\t";
1394 if(AdIAftCC) cerr << *AdIAftCC;
1397 if(AdIBef) cerr << *AdIBef << "\t";
1398 if(AdIAft) cerr << *AdIAft;
1401 } // if not already pushed
1403 } // if LR has a volatile color
1405 } // if LR has color
1407 } // if there is a LR for Var
1409 } // for each value in the LV set after instruction
1413 //---------------------------------------------------------------------------
1414 // Copies %ccr into an integer register. IntReg is the UNIFIED register
1416 //---------------------------------------------------------------------------
1418 MachineInstr * UltraSparcRegInfo::cpCCR2IntMI(unsigned IntReg) const {
1419 MachineInstr * MI = new MachineInstr(RDCCR, 2);
1420 MI->SetMachineOperandReg(0, this->getUnifiedRegNum(UltraSparcRegInfo::IntCCRegClassID,
1421 SparcIntCCRegOrder::ccr),
1423 MI->SetMachineOperandReg(1, IntReg, true);
1427 //---------------------------------------------------------------------------
1428 // Copies an integer register into %ccr. IntReg is the UNIFIED register
1430 //---------------------------------------------------------------------------
1432 MachineInstr *UltraSparcRegInfo::cpInt2CCRMI(unsigned IntReg) const {
1433 MachineInstr *MI = new MachineInstr(WRCCR, 3);
1434 MI->SetMachineOperandReg(0, IntReg, false);
1435 MI->SetMachineOperandReg(1, this->getZeroRegNum(), false);
1436 MI->SetMachineOperandReg(2, this->getUnifiedRegNum(UltraSparcRegInfo::IntCCRegClassID, SparcIntCCRegOrder::ccr),
1444 //---------------------------------------------------------------------------
1445 // Print the register assigned to a LR
1446 //---------------------------------------------------------------------------
1448 void UltraSparcRegInfo::printReg(const LiveRange *LR) {
1449 unsigned RegClassID = (LR->getRegClass())->getID();
1450 cerr << " *Node " << (LR->getUserIGNode())->getIndex();
1452 if (!LR->hasColor()) {
1453 cerr << " - could not find a color\n";
1457 // if a color is found
1459 cerr << " colored with color "<< LR->getColor();
1461 if (RegClassID == IntRegClassID) {
1462 cerr<< " [" << SparcIntRegOrder::getRegName(LR->getColor()) << "]\n";
1464 } else if (RegClassID == FloatRegClassID) {
1465 cerr << "[" << SparcFloatRegOrder::getRegName(LR->getColor());
1466 if( LR->getType() == Type::DoubleTy)
1467 cerr << "+" << SparcFloatRegOrder::getRegName(LR->getColor()+1);
1472 //---------------------------------------------------------------------------
1473 // This method examines instructions inserted by RegAlloc code before a
1474 // machine instruction to detect invalid orders that destroy values before
1475 // they are used. If it detects such conditions, it reorders the instructions.
1477 // The unordered instructions come in the UnordVec. These instructions are
1478 // instructions inserted by RegAlloc. All such instruction MUST have
1479 // their USES BEFORE THE DEFS after reordering.
1481 // The UnordVec & OrdVec must be DISTINCT. The OrdVec must be empty when
1482 // this method is called.
1484 // This method uses two vectors for efficiency in accessing
1486 // Since instructions are inserted in RegAlloc, this assumes that the
1487 // first operand is the source reg and the last operand is the dest reg.
1489 // All the uses are before THE def to a register
1492 //---------------------------------------------------------------------------
1493 void UltraSparcRegInfo::OrderAddedInstrns(std::vector<MachineInstr *> &UnordVec,
1494 std::vector<MachineInstr *> &OrdVec,
1495 PhyRegAlloc &PRA) const{
1498 Problem: We can have instructions inserted by RegAlloc like
1500 2. add %oy %g0 %oz, where z!=x or z==x
1502 This is wrong since %oy used by 2 is overwritten by 1
1505 We re-order the instructions so that the uses are before the defs
1510 for each instruction 'DefInst' in the UnOrdVec
1511 for each instruction 'UseInst' that follows the DefInst
1512 if the reg defined by DefInst is used by UseInst
1513 mark DefInst as not movable in this iteration
1514 If DefInst is not marked as not-movable, move DefInst to OrdVec
1515 while all instructions in DefInst are moved to OrdVec
1517 For moving, we call the move2OrdVec(). It checks whether there is a def
1518 in it for the uses in the instruction to be added to OrdVec. If there
1519 are no preceding defs, it just appends the instruction. If there is a
1520 preceding def, it puts two instructions to save the reg on stack before
1521 the load and puts a restore at use.
1526 bool DebugPrint = false;
1529 CouldMoveAll = true;
1530 std::vector<MachineInstr *>::iterator DefIt = UnordVec.begin();
1532 for( ; DefIt != UnordVec.end(); ++DefIt ) {
1534 // for each instruction in the UnordVec do ...
1536 MachineInstr *DefInst = *DefIt;
1538 if( DefInst == NULL) continue;
1540 //cerr << "\nInst in UnordVec = " << *DefInst;
1542 // last operand is the def (unless for a store which has no def reg)
1543 MachineOperand& DefOp = DefInst->getOperand(DefInst->getNumOperands()-1);
1545 if( DefOp.opIsDef() &&
1546 DefOp.getOperandType() == MachineOperand::MO_MachineRegister) {
1548 // If the operand in DefInst is a def ...
1550 bool DefEqUse = false;
1552 std::vector<MachineInstr *>::iterator UseIt = DefIt;
1555 for( ; UseIt != UnordVec.end(); ++UseIt ) {
1557 MachineInstr *UseInst = *UseIt;
1558 if( UseInst == NULL) continue;
1560 // for each inst (UseInst) that is below the DefInst do ...
1561 MachineOperand& UseOp = UseInst->getOperand(0);
1563 if( ! UseOp.opIsDef() &&
1564 UseOp.getOperandType() == MachineOperand::MO_MachineRegister) {
1566 // if use is a register ...
1568 if( DefOp.getMachineRegNum() == UseOp.getMachineRegNum() ) {
1570 // if Def and this use are the same, it means that this use
1571 // is destroyed by a def before it is used
1573 // cerr << "\nCouldn't move " << *DefInst;
1576 CouldMoveAll = false;
1579 } // if two registers are equal
1581 } // if use is a register
1583 }// for all use instructions
1587 // after examining all the instructions that follow the DefInst
1588 // if there are no dependencies, we can move it to the OrdVec
1590 // cerr << "Moved to Ord: " << *DefInst;
1592 moveInst2OrdVec(OrdVec, DefInst, PRA);
1594 //OrdVec.push_back(DefInst);
1596 // mark the pos of DefInst with NULL to indicate that it is
1601 } // if Def is a machine register
1603 } // for all instructions in the UnordVec
1606 } while(!CouldMoveAll);
1609 cerr << "\nAdded instructions were reordered to:\n";
1610 for(unsigned int i=0; i < OrdVec.size(); i++)
1611 cerr << *(OrdVec[i]);
1619 void UltraSparcRegInfo::moveInst2OrdVec(std::vector<MachineInstr *> &OrdVec,
1620 MachineInstr *UnordInst,
1621 PhyRegAlloc &PRA) const {
1622 MachineOperand& UseOp = UnordInst->getOperand(0);
1624 if( ! UseOp.opIsDef() &&
1625 UseOp.getOperandType() == MachineOperand::MO_MachineRegister) {
1627 // for the use of UnordInst, see whether there is a defining instr
1628 // before in the OrdVec
1629 bool DefEqUse = false;
1631 std::vector<MachineInstr *>::iterator OrdIt = OrdVec.begin();
1633 for( ; OrdIt != OrdVec.end(); ++OrdIt ) {
1635 MachineInstr *OrdInst = *OrdIt ;
1637 MachineOperand& DefOp =
1638 OrdInst->getOperand(OrdInst->getNumOperands()-1);
1640 if( DefOp.opIsDef() &&
1641 DefOp.getOperandType() == MachineOperand::MO_MachineRegister) {
1643 //cerr << "\nDefining Ord Inst: " << *OrdInst;
1645 if( DefOp.getMachineRegNum() == UseOp.getMachineRegNum() ) {
1647 // we are here because there is a preceding def in the OrdVec
1648 // for the use in this intr we are going to insert. This
1649 // happened because the original code was like:
1650 // 1. add %ox %g0 %oy
1651 // 2. add %oy %g0 %ox
1652 // In Round1, we added 2 to OrdVec but 1 remained in UnordVec
1653 // Now we are processing %ox of 1.
1656 const int UReg = DefOp.getMachineRegNum();
1657 const int RegType = getRegType(UReg);
1658 MachineInstr *AdIBef, *AdIAft;
1660 const int StackOff = PRA.mcInfo.pushTempValue(target,
1661 getSpilledRegSize(RegType));
1663 // Save the UReg (%ox) on stack before it's destroyed
1664 AdIBef=cpReg2MemMI(UReg, getFramePointer(), StackOff, RegType);
1665 OrdIt = OrdVec.insert( OrdIt, AdIBef);
1666 OrdIt++; // points to current instr we processed
1668 // Load directly into DReg (%oy)
1669 MachineOperand& DOp=
1670 (UnordInst->getOperand(UnordInst->getNumOperands()-1));
1671 assert(DOp.opIsDef() && "Last operand is not the def");
1672 const int DReg = DOp.getMachineRegNum();
1674 AdIAft=cpMem2RegMI(getFramePointer(), StackOff, DReg, RegType);
1675 OrdVec.push_back(AdIAft);
1677 cerr << "\nFixed CIRCULAR references by reordering";
1680 cerr << "\nBefore CIRCULAR Reordering:\n";
1684 cerr << "\nAfter CIRCULAR Reordering - All Inst so far:\n";
1685 for(unsigned i=0; i < OrdVec.size(); i++)
1686 cerr << *(OrdVec[i]);
1689 // Do not copy the UseInst to OrdVec
1693 }// if two registers are equal
1695 } // if Def is a register
1697 } // for each instr in OrdVec
1701 // We didn't find a def in the OrdVec, so just append this inst
1702 OrdVec.push_back( UnordInst );
1703 //cerr << "Reordered Inst (Moved Dn): " << *UnordInst;
1706 }// if the operand in UnordInst is a use