1 //===-- SparcRegInfo.cpp - Sparc Target Register Information --------------===//
3 // This file contains implementation of Sparc specific helper methods
4 // used for register allocation.
6 //===----------------------------------------------------------------------===//
8 #include "SparcInternals.h"
9 #include "SparcRegClassInfo.h"
10 #include "llvm/CodeGen/MachineFunction.h"
11 #include "llvm/CodeGen/MachineFunctionInfo.h"
12 #include "llvm/CodeGen/InstrSelection.h"
13 #include "llvm/CodeGen/MachineInstrBuilder.h"
14 #include "llvm/CodeGen/MachineCodeForInstruction.h"
15 #include "llvm/CodeGen/MachineInstrAnnot.h"
16 #include "llvm/CodeGen/LiveRangeInfo.h"
17 #include "llvm/CodeGen/LiveRange.h"
18 #include "llvm/iTerminators.h"
19 #include "llvm/iOther.h"
20 #include "llvm/Function.h"
21 #include "llvm/DerivedTypes.h"
27 UltraSparcRegInfo::UltraSparcRegInfo(const UltraSparc &tgt)
28 : TargetRegInfo(tgt), NumOfIntArgRegs(6), NumOfFloatArgRegs(32)
30 MachineRegClassArr.push_back(new SparcIntRegClass(IntRegClassID));
31 MachineRegClassArr.push_back(new SparcFloatRegClass(FloatRegClassID));
32 MachineRegClassArr.push_back(new SparcIntCCRegClass(IntCCRegClassID));
33 MachineRegClassArr.push_back(new SparcFloatCCRegClass(FloatCCRegClassID));
34 MachineRegClassArr.push_back(new SparcSpecialRegClass(SpecialRegClassID));
36 assert(SparcFloatRegClass::StartOfNonVolatileRegs == 32 &&
37 "32 Float regs are used for float arg passing");
41 // getZeroRegNum - returns the register that contains always zero.
42 // this is the unified register number
44 int UltraSparcRegInfo::getZeroRegNum() const {
45 return getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
46 SparcIntRegClass::g0);
49 // getCallAddressReg - returns the reg used for pushing the address when a
50 // method is called. This can be used for other purposes between calls
52 unsigned UltraSparcRegInfo::getCallAddressReg() const {
53 return getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
54 SparcIntRegClass::o7);
57 // Returns the register containing the return address.
58 // It should be made sure that this register contains the return
59 // value when a return instruction is reached.
61 unsigned UltraSparcRegInfo::getReturnAddressReg() const {
62 return getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
63 SparcIntRegClass::i7);
66 // Register get name implementations...
68 // Int register names in same order as enum in class SparcIntRegClass
69 static const char * const IntRegNames[] = {
70 "o0", "o1", "o2", "o3", "o4", "o5", "o7",
71 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
72 "i0", "i1", "i2", "i3", "i4", "i5",
74 "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
78 const char * const SparcIntRegClass::getRegName(unsigned reg) const {
79 assert(reg < NumOfAllRegs);
80 return IntRegNames[reg];
83 static const char * const FloatRegNames[] = {
84 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9",
85 "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19",
86 "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29",
87 "f30", "f31", "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
88 "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", "f48", "f49",
89 "f50", "f51", "f52", "f53", "f54", "f55", "f56", "f57", "f58", "f59",
90 "f60", "f61", "f62", "f63"
93 const char * const SparcFloatRegClass::getRegName(unsigned reg) const {
94 assert (reg < NumOfAllRegs);
95 return FloatRegNames[reg];
99 static const char * const IntCCRegNames[] = {
103 const char * const SparcIntCCRegClass::getRegName(unsigned reg) const {
105 return IntCCRegNames[reg];
108 static const char * const FloatCCRegNames[] = {
109 "fcc0", "fcc1", "fcc2", "fcc3"
112 const char * const SparcFloatCCRegClass::getRegName(unsigned reg) const {
114 return FloatCCRegNames[reg];
117 static const char * const SpecialRegNames[] = {
121 const char * const SparcSpecialRegClass::getRegName(unsigned reg) const {
123 return SpecialRegNames[reg];
126 // Get unified reg number for frame pointer
127 unsigned UltraSparcRegInfo::getFramePointer() const {
128 return getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
129 SparcIntRegClass::i6);
132 // Get unified reg number for stack pointer
133 unsigned UltraSparcRegInfo::getStackPointer() const {
134 return getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
135 SparcIntRegClass::o6);
139 //---------------------------------------------------------------------------
140 // Finds whether a call is an indirect call
141 //---------------------------------------------------------------------------
144 isVarArgsFunction(const Type *funcType) {
145 return cast<FunctionType>(cast<PointerType>(funcType)
146 ->getElementType())->isVarArg();
150 isVarArgsCall(const MachineInstr *CallMI) {
151 Value* callee = CallMI->getOperand(0).getVRegValue();
152 // const Type* funcType = isa<Function>(callee)? callee->getType()
153 // : cast<PointerType>(callee->getType())->getElementType();
154 const Type* funcType = callee->getType();
155 return isVarArgsFunction(funcType);
159 // Get the register number for the specified argument #argNo,
162 // getInvalidRegNum(), if there is no int register available for the arg.
163 // regNum, otherwise (this is NOT the unified reg. num).
164 // regClassId is set to the register class ID.
167 UltraSparcRegInfo::regNumForIntArg(bool inCallee, bool isVarArgsCall,
168 unsigned argNo, unsigned& regClassId) const
170 regClassId = IntRegClassID;
171 if (argNo >= NumOfIntArgRegs)
172 return getInvalidRegNum();
174 return argNo + (inCallee? SparcIntRegClass::i0 : SparcIntRegClass::o0);
177 // Get the register number for the specified FP argument #argNo,
178 // Use INT regs for FP args if this is a varargs call.
181 // getInvalidRegNum(), if there is no int register available for the arg.
182 // regNum, otherwise (this is NOT the unified reg. num).
183 // regClassId is set to the register class ID.
186 UltraSparcRegInfo::regNumForFPArg(unsigned regType,
187 bool inCallee, bool isVarArgsCall,
188 unsigned argNo, unsigned& regClassId) const
191 return regNumForIntArg(inCallee, isVarArgsCall, argNo, regClassId);
194 regClassId = FloatRegClassID;
195 if (regType == FPSingleRegType)
196 return (argNo*2+1 >= NumOfFloatArgRegs)?
197 getInvalidRegNum() : SparcFloatRegClass::f0 + (argNo * 2 + 1);
198 else if (regType == FPDoubleRegType)
199 return (argNo*2 >= NumOfFloatArgRegs)?
200 getInvalidRegNum() : SparcFloatRegClass::f0 + (argNo * 2);
202 assert(0 && "Illegal FP register type");
208 //---------------------------------------------------------------------------
209 // Finds the return address of a call sparc specific call instruction
210 //---------------------------------------------------------------------------
212 // The following 4 methods are used to find the RegType (SparcInternals.h)
213 // of a LiveRange, a Value, and for a given register unified reg number.
215 int UltraSparcRegInfo::getRegTypeForClassAndType(unsigned regClassID,
216 const Type* type) const
218 switch (regClassID) {
219 case IntRegClassID: return IntRegType;
220 case FloatRegClassID:
221 if (type == Type::FloatTy) return FPSingleRegType;
222 else if (type == Type::DoubleTy) return FPDoubleRegType;
223 assert(0 && "Unknown type in FloatRegClass"); return 0;
224 case IntCCRegClassID: return IntCCRegType;
225 case FloatCCRegClassID: return FloatCCRegType;
226 case SpecialRegClassID: return SpecialRegType;
227 default: assert( 0 && "Unknown reg class ID"); return 0;
231 int UltraSparcRegInfo::getRegTypeForDataType(const Type* type) const
233 return getRegTypeForClassAndType(getRegClassIDOfType(type), type);
236 int UltraSparcRegInfo::getRegTypeForLR(const LiveRange *LR) const
238 return getRegTypeForClassAndType(LR->getRegClassID(), LR->getType());
241 int UltraSparcRegInfo::getRegType(int unifiedRegNum) const
243 if (unifiedRegNum < 32)
245 else if (unifiedRegNum < (32 + 32))
246 return FPSingleRegType;
247 else if (unifiedRegNum < (64 + 32))
248 return FPDoubleRegType;
249 else if (unifiedRegNum < (64+32+4))
250 return FloatCCRegType;
251 else if (unifiedRegNum < (64+32+4+2))
254 assert(0 && "Invalid unified register number in getRegType");
259 // To find the register class used for a specified Type
261 unsigned UltraSparcRegInfo::getRegClassIDOfType(const Type *type,
262 bool isCCReg) const {
263 Type::PrimitiveID ty = type->getPrimitiveID();
266 // FIXME: Comparing types like this isn't very safe...
267 if ((ty && ty <= Type::LongTyID) || (ty == Type::LabelTyID) ||
268 (ty == Type::FunctionTyID) || (ty == Type::PointerTyID) )
269 res = IntRegClassID; // sparc int reg (ty=0: void)
270 else if (ty <= Type::DoubleTyID)
271 res = FloatRegClassID; // sparc float reg class
273 //std::cerr << "TypeID: " << ty << "\n";
274 assert(0 && "Cannot resolve register class for type");
279 return res + 2; // corresponding condition code register
284 unsigned UltraSparcRegInfo::getRegClassIDOfRegType(int regType) const {
286 case IntRegType: return IntRegClassID;
287 case FPSingleRegType:
288 case FPDoubleRegType: return FloatRegClassID;
289 case IntCCRegType: return IntCCRegClassID;
290 case FloatCCRegType: return FloatCCRegClassID;
292 assert(0 && "Invalid register type in getRegClassIDOfRegType");
297 //---------------------------------------------------------------------------
298 // Suggests a register for the ret address in the RET machine instruction.
299 // We always suggest %i7 by convention.
300 //---------------------------------------------------------------------------
301 void UltraSparcRegInfo::suggestReg4RetAddr(MachineInstr *RetMI,
302 LiveRangeInfo& LRI) const {
304 assert(target.getInstrInfo().isReturn(RetMI->getOpCode()));
306 // return address is always mapped to i7 so set it immediately
307 RetMI->SetRegForOperand(0, getUnifiedRegNum(IntRegClassID,
308 SparcIntRegClass::i7));
310 // Possible Optimization:
311 // Instead of setting the color, we can suggest one. In that case,
312 // we have to test later whether it received the suggested color.
313 // In that case, a LR has to be created at the start of method.
314 // It has to be done as follows (remove the setRegVal above):
316 // MachineOperand & MO = RetMI->getOperand(0);
317 // const Value *RetAddrVal = MO.getVRegValue();
318 // assert( RetAddrVal && "LR for ret address must be created at start");
319 // LiveRange * RetAddrLR = LRI.getLiveRangeForValue( RetAddrVal);
320 // RetAddrLR->setSuggestedColor(getUnifiedRegNum( IntRegClassID,
321 // SparcIntRegOrdr::i7) );
325 //---------------------------------------------------------------------------
326 // Suggests a register for the ret address in the JMPL/CALL machine instr.
327 // Sparc ABI dictates that %o7 be used for this purpose.
328 //---------------------------------------------------------------------------
330 UltraSparcRegInfo::suggestReg4CallAddr(MachineInstr * CallMI,
331 LiveRangeInfo& LRI) const
333 CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
334 const Value *RetAddrVal = argDesc->getReturnAddrReg();
335 assert(RetAddrVal && "INTERNAL ERROR: Return address value is required");
337 // A LR must already exist for the return address.
338 LiveRange *RetAddrLR = LRI.getLiveRangeForValue(RetAddrVal);
339 assert(RetAddrLR && "INTERNAL ERROR: No LR for return address of call!");
341 unsigned RegClassID = RetAddrLR->getRegClassID();
342 RetAddrLR->setColor(getUnifiedRegNum(IntRegClassID, SparcIntRegClass::o7));
347 //---------------------------------------------------------------------------
348 // This method will suggest colors to incoming args to a method.
349 // According to the Sparc ABI, the first 6 incoming args are in
350 // %i0 - %i5 (if they are integer) OR in %f0 - %f31 (if they are float).
351 // If the arg is passed on stack due to the lack of regs, NOTHING will be
352 // done - it will be colored (or spilled) as a normal live range.
353 //---------------------------------------------------------------------------
354 void UltraSparcRegInfo::suggestRegs4MethodArgs(const Function *Meth,
355 LiveRangeInfo& LRI) const
357 // Check if this is a varArgs function. needed for choosing regs.
358 bool isVarArgs = isVarArgsFunction(Meth->getType());
360 // Count the arguments, *ignoring* whether they are int or FP args.
361 // Use this common arg numbering to pick the right int or fp register.
363 for(Function::const_aiterator I = Meth->abegin(), E = Meth->aend();
364 I != E; ++I, ++argNo) {
365 LiveRange *LR = LRI.getLiveRangeForValue(I);
366 assert(LR && "No live range found for method arg");
368 unsigned regType = getRegTypeForLR(LR);
369 unsigned regClassIDOfArgReg = BadRegClass; // for chosen reg (unused)
371 int regNum = (regType == IntRegType)
372 ? regNumForIntArg(/*inCallee*/ true, isVarArgs, argNo, regClassIDOfArgReg)
373 : regNumForFPArg(regType, /*inCallee*/ true, isVarArgs, argNo,
376 if (regNum != getInvalidRegNum())
377 LR->setSuggestedColor(regNum);
382 //---------------------------------------------------------------------------
383 // This method is called after graph coloring to move incoming args to
384 // the correct hardware registers if they did not receive the correct
385 // (suggested) color through graph coloring.
386 //---------------------------------------------------------------------------
387 void UltraSparcRegInfo::colorMethodArgs(const Function *Meth,
389 std::vector<MachineInstr*>& InstrnsBefore,
390 std::vector<MachineInstr*>& InstrnsAfter) const {
392 // check if this is a varArgs function. needed for choosing regs.
393 bool isVarArgs = isVarArgsFunction(Meth->getType());
397 // for each argument. count INT and FP arguments separately.
398 unsigned argNo=0, intArgNo=0, fpArgNo=0;
399 for(Function::const_aiterator I = Meth->abegin(), E = Meth->aend();
400 I != E; ++I, ++argNo) {
402 LiveRange *LR = LRI.getLiveRangeForValue(I);
403 assert( LR && "No live range found for method arg");
405 unsigned regType = getRegTypeForLR(LR);
406 unsigned RegClassID = LR->getRegClassID();
408 // Find whether this argument is coming in a register (if not, on stack)
409 // Also find the correct register the argument must use (UniArgReg)
411 bool isArgInReg = false;
412 unsigned UniArgReg = getInvalidRegNum(); // reg that LR MUST be colored with
413 unsigned regClassIDOfArgReg = BadRegClass; // reg class of chosen reg
415 int regNum = (regType == IntRegType)
416 ? regNumForIntArg(/*inCallee*/ true, isVarArgs,
417 argNo, regClassIDOfArgReg)
418 : regNumForFPArg(regType, /*inCallee*/ true, isVarArgs,
419 argNo, regClassIDOfArgReg);
421 if(regNum != getInvalidRegNum()) {
423 UniArgReg = getUnifiedRegNum( regClassIDOfArgReg, regNum);
426 if( ! LR->isMarkedForSpill() ) { // if this arg received a register
428 unsigned UniLRReg = getUnifiedRegNum( RegClassID, LR->getColor() );
430 // if LR received the correct color, nothing to do
432 if( UniLRReg == UniArgReg )
435 // We are here because the LR did not receive the suggested
436 // but LR received another register.
437 // Now we have to copy the %i reg (or stack pos of arg)
438 // to the register the LR was colored with.
440 // if the arg is coming in UniArgReg register, it MUST go into
441 // the UniLRReg register
444 if( regClassIDOfArgReg != RegClassID ) {
445 assert(0 && "This could should work but it is not tested yet");
447 // It is a variable argument call: the float reg must go in a %o reg.
448 // We have to move an int reg to a float reg via memory.
451 RegClassID == FloatRegClassID &&
452 regClassIDOfArgReg == IntRegClassID &&
453 "This should only be an Int register for an FP argument");
455 int TmpOff = MachineFunction::get(Meth).getInfo()->pushTempValue(
456 getSpilledRegSize(regType));
457 cpReg2MemMI(InstrnsBefore,
458 UniArgReg, getFramePointer(), TmpOff, IntRegType);
460 cpMem2RegMI(InstrnsBefore,
461 getFramePointer(), TmpOff, UniLRReg, regType);
464 cpReg2RegMI(InstrnsBefore, UniArgReg, UniLRReg, regType);
469 // Now the arg is coming on stack. Since the LR recieved a register,
470 // we just have to load the arg on stack into that register
472 const TargetFrameInfo& frameInfo = target.getFrameInfo();
474 frameInfo.getIncomingArgOffset(MachineFunction::get(Meth),
477 // float arguments on stack are right justified so adjust the offset!
478 // int arguments are also right justified but they are always loaded as
479 // a full double-word so the offset does not need to be adjusted.
480 if (regType == FPSingleRegType) {
481 unsigned argSize = target.getTargetData().getTypeSize(LR->getType());
482 unsigned slotSize = frameInfo.getSizeOfEachArgOnStack();
483 assert(argSize <= slotSize && "Insufficient slot size!");
484 offsetFromFP += slotSize - argSize;
487 cpMem2RegMI(InstrnsBefore,
488 getFramePointer(), offsetFromFP, UniLRReg, regType);
491 } // if LR received a color
495 // Now, the LR did not receive a color. But it has a stack offset for
497 // So, if the arg is coming in UniArgReg register, we can just move
498 // that on to the stack pos of LR
502 if( regClassIDOfArgReg != RegClassID ) {
504 "FP arguments to a varargs function should be explicitly "
505 "copied to/from int registers by instruction selection!");
507 // It must be a float arg for a variable argument call, which
508 // must come in a %o reg. Move the int reg to the stack.
510 assert(isVarArgs && regClassIDOfArgReg == IntRegClassID &&
511 "This should only be an Int register for an FP argument");
513 cpReg2MemMI(InstrnsBefore, UniArgReg,
514 getFramePointer(), LR->getSpillOffFromFP(), IntRegType);
517 cpReg2MemMI(InstrnsBefore, UniArgReg,
518 getFramePointer(), LR->getSpillOffFromFP(), regType);
524 // Now the arg is coming on stack. Since the LR did NOT
525 // recieved a register as well, it is allocated a stack position. We
526 // can simply change the stack position of the LR. We can do this,
527 // since this method is called before any other method that makes
528 // uses of the stack pos of the LR (e.g., updateMachineInstr)
530 const TargetFrameInfo& frameInfo = target.getFrameInfo();
532 frameInfo.getIncomingArgOffset(MachineFunction::get(Meth),
535 // FP arguments on stack are right justified so adjust offset!
536 // int arguments are also right justified but they are always loaded as
537 // a full double-word so the offset does not need to be adjusted.
538 if (regType == FPSingleRegType) {
539 unsigned argSize = target.getTargetData().getTypeSize(LR->getType());
540 unsigned slotSize = frameInfo.getSizeOfEachArgOnStack();
541 assert(argSize <= slotSize && "Insufficient slot size!");
542 offsetFromFP += slotSize - argSize;
545 LR->modifySpillOffFromFP( offsetFromFP );
550 } // for each incoming argument
556 //---------------------------------------------------------------------------
557 // This method is called before graph coloring to suggest colors to the
558 // outgoing call args and the return value of the call.
559 //---------------------------------------------------------------------------
560 void UltraSparcRegInfo::suggestRegs4CallArgs(MachineInstr *CallMI,
561 LiveRangeInfo& LRI) const {
562 assert ( (target.getInstrInfo()).isCall(CallMI->getOpCode()) );
564 CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
566 suggestReg4CallAddr(CallMI, LRI);
568 // First color the return value of the call instruction, if any.
569 // The return value will be in %o0 if the value is an integer type,
570 // or in %f0 if the value is a float type.
572 if (const Value *RetVal = argDesc->getReturnValue()) {
573 LiveRange *RetValLR = LRI.getLiveRangeForValue(RetVal);
574 assert(RetValLR && "No LR for return Value of call!");
576 unsigned RegClassID = RetValLR->getRegClassID();
578 // now suggest a register depending on the register class of ret arg
579 if( RegClassID == IntRegClassID )
580 RetValLR->setSuggestedColor(SparcIntRegClass::o0);
581 else if (RegClassID == FloatRegClassID )
582 RetValLR->setSuggestedColor(SparcFloatRegClass::f0 );
583 else assert( 0 && "Unknown reg class for return value of call\n");
586 // Now suggest colors for arguments (operands) of the call instruction.
587 // Colors are suggested only if the arg number is smaller than the
588 // the number of registers allocated for argument passing.
589 // Now, go thru call args - implicit operands of the call MI
591 unsigned NumOfCallArgs = argDesc->getNumArgs();
593 for(unsigned argNo=0, i=0, intArgNo=0, fpArgNo=0;
594 i < NumOfCallArgs; ++i, ++argNo) {
596 const Value *CallArg = argDesc->getArgInfo(i).getArgVal();
598 // get the LR of call operand (parameter)
599 LiveRange *const LR = LRI.getLiveRangeForValue(CallArg);
601 continue; // no live ranges for constants and labels
603 unsigned regType = getRegTypeForLR(LR);
604 unsigned regClassIDOfArgReg = BadRegClass; // chosen reg class (unused)
606 // Choose a register for this arg depending on whether it is
607 // an INT or FP value. Here we ignore whether or not it is a
608 // varargs calls, because FP arguments will be explicitly copied
609 // to an integer Value and handled under (argCopy != NULL) below.
610 int regNum = (regType == IntRegType)
611 ? regNumForIntArg(/*inCallee*/ false, /*isVarArgs*/ false,
612 argNo, regClassIDOfArgReg)
613 : regNumForFPArg(regType, /*inCallee*/ false, /*isVarArgs*/ false,
614 argNo, regClassIDOfArgReg);
616 // If a register could be allocated, use it.
617 // If not, do NOTHING as this will be colored as a normal value.
618 if(regNum != getInvalidRegNum())
619 LR->setSuggestedColor(regNum);
620 } // for all call arguments
624 //---------------------------------------------------------------------------
625 // this method is called for an LLVM return instruction to identify which
626 // values will be returned from this method and to suggest colors.
627 //---------------------------------------------------------------------------
628 void UltraSparcRegInfo::suggestReg4RetValue(MachineInstr *RetMI,
629 LiveRangeInfo& LRI) const {
631 assert( (target.getInstrInfo()).isReturn( RetMI->getOpCode() ) );
633 suggestReg4RetAddr(RetMI, LRI);
635 // To find the return value (if any), we can get the LLVM return instr.
636 // from the return address register, which is the first operand
637 Value* tmpI = RetMI->getOperand(0).getVRegValue();
638 ReturnInst* retI=cast<ReturnInst>(cast<TmpInstruction>(tmpI)->getOperand(0));
639 if (const Value *RetVal = retI->getReturnValue())
640 if (LiveRange *const LR = LRI.getLiveRangeForValue(RetVal))
641 LR->setSuggestedColor(LR->getRegClassID() == IntRegClassID
642 ? (unsigned) SparcIntRegClass::i0
643 : (unsigned) SparcFloatRegClass::f0);
646 //---------------------------------------------------------------------------
647 // Check if a specified register type needs a scratch register to be
648 // copied to/from memory. If it does, the reg. type that must be used
649 // for scratch registers is returned in scratchRegType.
651 // Only the int CC register needs such a scratch register.
652 // The FP CC registers can (and must) be copied directly to/from memory.
653 //---------------------------------------------------------------------------
656 UltraSparcRegInfo::regTypeNeedsScratchReg(int RegType,
657 int& scratchRegType) const
659 if (RegType == IntCCRegType)
661 scratchRegType = IntRegType;
667 //---------------------------------------------------------------------------
668 // Copy from a register to register. Register number must be the unified
670 //---------------------------------------------------------------------------
673 UltraSparcRegInfo::cpReg2RegMI(std::vector<MachineInstr*>& mvec,
677 assert( ((int)SrcReg != getInvalidRegNum()) &&
678 ((int)DestReg != getInvalidRegNum()) &&
681 MachineInstr * MI = NULL;
686 if (getRegType(DestReg) == IntRegType) {
687 // copy intCC reg to int reg
688 MI = (BuildMI(V9::RDCCR, 2)
689 .addMReg(getUnifiedRegNum(UltraSparcRegInfo::IntCCRegClassID,
690 SparcIntCCRegClass::ccr))
691 .addMReg(DestReg,MOTy::Def));
693 // copy int reg to intCC reg
694 assert(getRegType(SrcReg) == IntRegType
695 && "Can only copy CC reg to/from integer reg");
696 MI = (BuildMI(V9::WRCCRr, 3)
698 .addMReg(SparcIntRegClass::g0)
699 .addMReg(getUnifiedRegNum(UltraSparcRegInfo::IntCCRegClassID,
700 SparcIntCCRegClass::ccr), MOTy::Def));
705 assert(0 && "Cannot copy FPCC register to any other register");
709 MI = BuildMI(V9::ADDr, 3).addMReg(SrcReg).addMReg(getZeroRegNum())
710 .addMReg(DestReg, MOTy::Def);
713 case FPSingleRegType:
714 MI = BuildMI(V9::FMOVS, 2).addMReg(SrcReg).addMReg(DestReg, MOTy::Def);
717 case FPDoubleRegType:
718 MI = BuildMI(V9::FMOVD, 2).addMReg(SrcReg).addMReg(DestReg, MOTy::Def);
722 assert(0 && "Unknown RegType");
730 //---------------------------------------------------------------------------
731 // Copy from a register to memory (i.e., Store). Register number must
732 // be the unified register number
733 //---------------------------------------------------------------------------
737 UltraSparcRegInfo::cpReg2MemMI(std::vector<MachineInstr*>& mvec,
740 int Offset, int RegType,
741 int scratchReg) const {
742 MachineInstr * MI = NULL;
745 // If the Offset will not fit in the signed-immediate field, find an
746 // unused register to hold the offset value. This takes advantage of
747 // the fact that all the opcodes used below have the same size immed. field.
748 // Use the register allocator, PRA, to find an unused reg. at this MI.
750 if (RegType != IntCCRegType) // does not use offset below
751 if (! target.getInstrInfo().constantFitsInImmedField(V9::LDXi, Offset)) {
752 #ifdef CAN_FIND_FREE_REGISTER_TRANSPARENTLY
753 RegClass* RC = PRA.getRegClassByID(this->getRegClassIDOfRegType(RegType));
754 OffReg = PRA.getUnusedUniRegAtMI(RC, RegType, MInst, LVSetBef);
756 // Default to using register g2 for holding large offsets
757 OffReg = getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
758 SparcIntRegClass::g4);
760 assert(OffReg >= 0 && "FIXME: cpReg2MemMI cannot find an unused reg.");
761 mvec.push_back(BuildMI(V9::SETSW, 2).addZImm(Offset).addReg(OffReg));
766 if (target.getInstrInfo().constantFitsInImmedField(V9::STXi, Offset))
767 MI = BuildMI(V9::STXi,3).addMReg(SrcReg).addMReg(PtrReg).addSImm(Offset);
769 MI = BuildMI(V9::STXr,3).addMReg(SrcReg).addMReg(PtrReg).addMReg(OffReg);
772 case FPSingleRegType:
773 if (target.getInstrInfo().constantFitsInImmedField(V9::STFi, Offset))
774 MI = BuildMI(V9::STFi, 3).addMReg(SrcReg).addMReg(PtrReg).addSImm(Offset);
776 MI = BuildMI(V9::STFr, 3).addMReg(SrcReg).addMReg(PtrReg).addMReg(OffReg);
779 case FPDoubleRegType:
780 if (target.getInstrInfo().constantFitsInImmedField(V9::STDFi, Offset))
781 MI = BuildMI(V9::STDFi,3).addMReg(SrcReg).addMReg(PtrReg).addSImm(Offset);
783 MI = BuildMI(V9::STDFr,3).addMReg(SrcReg).addMReg(PtrReg).addSImm(OffReg);
787 assert(scratchReg >= 0 && "Need scratch reg to store %ccr to memory");
788 assert(getRegType(scratchReg) ==IntRegType && "Invalid scratch reg");
789 MI = (BuildMI(V9::RDCCR, 2)
790 .addMReg(getUnifiedRegNum(UltraSparcRegInfo::IntCCRegClassID,
791 SparcIntCCRegClass::ccr))
792 .addMReg(scratchReg, MOTy::Def));
795 cpReg2MemMI(mvec, scratchReg, PtrReg, Offset, IntRegType);
798 case FloatCCRegType: {
799 unsigned fsrReg = getUnifiedRegNum(UltraSparcRegInfo::SpecialRegClassID,
800 SparcSpecialRegClass::fsr);
801 if (target.getInstrInfo().constantFitsInImmedField(V9::STXFSRi, Offset))
802 MI=BuildMI(V9::STXFSRi,3).addMReg(fsrReg).addMReg(PtrReg).addSImm(Offset);
804 MI=BuildMI(V9::STXFSRr,3).addMReg(fsrReg).addMReg(PtrReg).addMReg(OffReg);
808 assert(0 && "Unknown RegType in cpReg2MemMI");
814 //---------------------------------------------------------------------------
815 // Copy from memory to a reg (i.e., Load) Register number must be the unified
817 //---------------------------------------------------------------------------
821 UltraSparcRegInfo::cpMem2RegMI(std::vector<MachineInstr*>& mvec,
826 int scratchReg) const {
827 MachineInstr * MI = NULL;
830 // If the Offset will not fit in the signed-immediate field, find an
831 // unused register to hold the offset value. This takes advantage of
832 // the fact that all the opcodes used below have the same size immed. field.
833 // Use the register allocator, PRA, to find an unused reg. at this MI.
835 if (RegType != IntCCRegType) // does not use offset below
836 if (! target.getInstrInfo().constantFitsInImmedField(V9::LDXi, Offset)) {
837 #ifdef CAN_FIND_FREE_REGISTER_TRANSPARENTLY
838 RegClass* RC = PRA.getRegClassByID(this->getRegClassIDOfRegType(RegType));
839 OffReg = PRA.getUnusedUniRegAtMI(RC, RegType, MInst, LVSetBef);
841 // Default to using register g2 for holding large offsets
842 OffReg = getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
843 SparcIntRegClass::g4);
845 assert(OffReg >= 0 && "FIXME: cpReg2MemMI cannot find an unused reg.");
846 mvec.push_back(BuildMI(V9::SETSW, 2).addZImm(Offset).addReg(OffReg));
851 if (target.getInstrInfo().constantFitsInImmedField(V9::LDXi, Offset))
852 MI = BuildMI(V9::LDXi, 3).addMReg(PtrReg).addSImm(Offset).addMReg(DestReg,
855 MI = BuildMI(V9::LDXr, 3).addMReg(PtrReg).addMReg(OffReg).addMReg(DestReg,
859 case FPSingleRegType:
860 if (target.getInstrInfo().constantFitsInImmedField(V9::LDFi, Offset))
861 MI = BuildMI(V9::LDFi, 3).addMReg(PtrReg).addSImm(Offset).addMReg(DestReg,
864 MI = BuildMI(V9::LDFr, 3).addMReg(PtrReg).addMReg(OffReg).addMReg(DestReg,
868 case FPDoubleRegType:
869 if (target.getInstrInfo().constantFitsInImmedField(V9::LDDFi, Offset))
870 MI= BuildMI(V9::LDDFi, 3).addMReg(PtrReg).addSImm(Offset).addMReg(DestReg,
873 MI= BuildMI(V9::LDDFr, 3).addMReg(PtrReg).addMReg(OffReg).addMReg(DestReg,
878 assert(scratchReg >= 0 && "Need scratch reg to load %ccr from memory");
879 assert(getRegType(scratchReg) ==IntRegType && "Invalid scratch reg");
880 cpMem2RegMI(mvec, PtrReg, Offset, scratchReg, IntRegType);
881 MI = (BuildMI(V9::WRCCRr, 3)
883 .addMReg(SparcIntRegClass::g0)
884 .addMReg(getUnifiedRegNum(UltraSparcRegInfo::IntCCRegClassID,
885 SparcIntCCRegClass::ccr), MOTy::Def));
888 case FloatCCRegType: {
889 unsigned fsrRegNum = getUnifiedRegNum(UltraSparcRegInfo::SpecialRegClassID,
890 SparcSpecialRegClass::fsr);
891 if (target.getInstrInfo().constantFitsInImmedField(V9::LDXFSRi, Offset))
892 MI = BuildMI(V9::LDXFSRi, 3).addMReg(PtrReg).addSImm(Offset)
893 .addMReg(fsrRegNum, MOTy::UseAndDef);
895 MI = BuildMI(V9::LDXFSRr, 3).addMReg(PtrReg).addMReg(OffReg)
896 .addMReg(fsrRegNum, MOTy::UseAndDef);
900 assert(0 && "Unknown RegType in cpMem2RegMI");
906 //---------------------------------------------------------------------------
907 // Generate a copy instruction to copy a value to another. Temporarily
908 // used by PhiElimination code.
909 //---------------------------------------------------------------------------
913 UltraSparcRegInfo::cpValue2Value(Value *Src, Value *Dest,
914 std::vector<MachineInstr*>& mvec) const {
915 int RegType = getRegTypeForDataType(Src->getType());
916 MachineInstr * MI = NULL;
920 MI = BuildMI(V9::ADDr, 3).addReg(Src).addMReg(getZeroRegNum())
923 case FPSingleRegType:
924 MI = BuildMI(V9::FMOVS, 2).addReg(Src).addRegDef(Dest);
926 case FPDoubleRegType:
927 MI = BuildMI(V9::FMOVD, 2).addReg(Src).addRegDef(Dest);
930 assert(0 && "Unknow RegType in CpValu2Value");
938 //---------------------------------------------------------------------------
939 // Print the register assigned to a LR
940 //---------------------------------------------------------------------------
942 void UltraSparcRegInfo::printReg(const LiveRange *LR) const {
943 unsigned RegClassID = LR->getRegClassID();
944 std::cerr << " Node ";
946 if (!LR->hasColor()) {
947 std::cerr << " - could not find a color\n";
951 // if a color is found
953 std::cerr << " colored with color "<< LR->getColor();
955 unsigned uRegName = getUnifiedRegNum(RegClassID, LR->getColor());
958 std::cerr<< getUnifiedRegName(uRegName);
959 if (RegClassID == FloatRegClassID && LR->getType() == Type::DoubleTy)
960 std::cerr << "+" << getUnifiedRegName(uRegName+1);