1 /* Title: SparcRegClassInfo.h -*- C++ -*-
2 Author: Ruchira Sasanka
4 Purpose: Contains the description of integer register class of Sparc
8 #ifndef SPARC_REG_INFO_CLASS_H
9 #define SPARC_REG_INFO_CLASS_H
11 #include "llvm/Target/MachineRegInfo.h"
12 #include "llvm/CodeGen/IGNode.h"
14 //-----------------------------------------------------------------------------
15 // Integer Register Class
16 //-----------------------------------------------------------------------------
18 // Int register names in same order as enum in class SparcIntRegOrder
20 static const std::string IntRegNames[] =
22 "o0", "o1", "o2", "o3", "o4", "o5", "o7",
23 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
24 "i0", "i1", "i2", "i3", "i4", "i5",
26 "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
31 class SparcIntRegOrder{
35 enum RegsInPrefOrder // colors possible for a LR (in preferred order)
37 // --- following colors are volatile across function calls
38 // %g0 can't be used for coloring - always 0
41 o0, o1, o2, o3, o4, o5, o7, // %o0-%o5,
44 // all %0's can get modified by a call
46 // --- following colors are NON-volatile across function calls
48 l0, l1, l2, l3, l4, l5, l6, l7, // %l0-%l7
49 i0, i1, i2, i3, i4, i5, // %i0-%i5: i's need not be preserved
51 // %i6 is the fp - so not allocated
52 // %i7 is the ret address by convention - can be used for others
54 // max # of colors reg coloring can allocate (NumOfAvailRegs)
56 // --- following colors are not available for allocation within this phase
57 // --- but can appear for pre-colored ranges
59 i6, i7, g0, g1, g2, g3, g4, g5, g6, g7, o6
61 //*** NOTE: If we decide to use some %g regs, they are volatile
63 // Move the %g regs from the end of the enumeration to just above the
64 // enumeration of %o0 (change StartOfAllRegs below)
65 // change isRegVloatile method below
66 // Also change IntRegNames above.
70 // max # of colors reg coloring can allocate
71 static unsigned int const NumOfAvailRegs = i6;
73 static unsigned int const StartOfNonVolatileRegs = l0;
74 static unsigned int const StartOfAllRegs = o0;
75 static unsigned int const NumOfAllRegs = o6 + 1;
78 static const std::string getRegName(const unsigned reg) {
79 assert( reg < NumOfAllRegs );
80 return IntRegNames[reg];
83 static unsigned int getRegNumInCallersWindow(const unsigned reg) {
84 if (reg <= l7 || reg == o6) {
85 assert(0 && "registers o0-o7 and l0-l7 are not visible in caller");
89 return reg - (i0 - o0);
90 assert((reg >= g0 || reg <= g7) && "Unrecognized integer register number");
97 class SparcIntRegClass : public MachineRegClassInfo
101 SparcIntRegClass(unsigned ID)
102 : MachineRegClassInfo(ID,
103 SparcIntRegOrder::NumOfAvailRegs,
104 SparcIntRegOrder::NumOfAllRegs)
107 void colorIGNode(IGNode * Node, bool IsColorUsedArr[] ) const;
109 inline bool isRegVolatile(const int Reg) const {
110 return (Reg < (int) SparcIntRegOrder::StartOfNonVolatileRegs);
118 //-----------------------------------------------------------------------------
119 // Float Register Class
120 //-----------------------------------------------------------------------------
122 static const std::string FloatRegNames[] =
124 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9",
125 "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19",
126 "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29",
127 "f30", "f31", "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
128 "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", "f48", "f49",
129 "f50", "f51", "f52", "f53", "f54", "f55", "f56", "f57", "f58", "f59",
130 "f60", "f61", "f62", "f63"
134 class SparcFloatRegOrder{
138 enum RegsInPrefOrder {
140 f0, f1, f2, f3, f4, f5, f6, f7, f8, f9,
141 f10, f11, f12, f13, f14, f15, f16, f17, f18, f19,
142 f20, f21, f22, f23, f24, f25, f26, f27, f28, f29,
143 f30, f31, f32, f33, f34, f35, f36, f37, f38, f39,
144 f40, f41, f42, f43, f44, f45, f46, f47, f48, f49,
145 f50, f51, f52, f53, f54, f55, f56, f57, f58, f59,
150 // there are 64 regs alltogether but only 32 regs can be allocated at
153 static unsigned int const NumOfAvailRegs = 32;
154 static unsigned int const NumOfAllRegs = 64;
156 static unsigned int const StartOfNonVolatileRegs = f32;
157 static unsigned int const StartOfAllRegs = f0;
160 static const std::string getRegName(const unsigned reg) {
161 assert( reg < NumOfAllRegs );
162 return FloatRegNames[reg];
170 class SparcFloatRegClass : public MachineRegClassInfo
174 int findFloatColor(const LiveRange *const LR, unsigned Start,
175 unsigned End, bool IsColorUsedArr[] ) const;
179 SparcFloatRegClass(unsigned ID)
180 : MachineRegClassInfo(ID,
181 SparcFloatRegOrder::NumOfAvailRegs,
182 SparcFloatRegOrder::NumOfAllRegs)
185 void colorIGNode(IGNode * Node, bool IsColorUsedArr[] ) const;
187 // according to Sparc 64 ABI, all %fp regs are volatile
188 inline bool isRegVolatile(const int Reg) const { return true; }
196 //-----------------------------------------------------------------------------
197 // Int CC Register Class
198 // Only one integer cc register is available. However, this register is
199 // referred to as %xcc when instructions like subcc are executed but
200 // referred to as %ccr (i.e., %xcc + %icc") when this register is moved
201 // into an integer register using RD or WR instrcutions. So, two ids are
202 // allocated for two names.
203 //-----------------------------------------------------------------------------
206 static const std::string IntCCRegNames[] =
212 class SparcIntCCRegOrder{
216 enum RegsInPrefOrder {
218 xcc, ccr // only one is available - see the note above
221 static const std::string getRegName(const unsigned reg) {
223 return IntCCRegNames[reg];
230 class SparcIntCCRegClass : public MachineRegClassInfo
234 SparcIntCCRegClass(unsigned ID)
235 : MachineRegClassInfo(ID, 1, 2) { }
237 inline void colorIGNode(IGNode * Node, bool IsColorUsedArr[] ) const {
238 Node->setColor(0); // only one int cc reg is available
241 // according to Sparc 64 ABI, %ccr is volatile
243 inline bool isRegVolatile(const int Reg) const { return true; }
250 //-----------------------------------------------------------------------------
251 // Float CC Register Class
252 // Only 4 Float CC registers are available
253 //-----------------------------------------------------------------------------
256 static const std::string FloatCCRegNames[] =
258 "fcc0", "fcc1", "fcc2", "fcc3"
262 class SparcFloatCCRegOrder{
266 enum RegsInPrefOrder {
268 fcc0, fcc1, fcc2, fcc3
271 static const std::string getRegName(const unsigned reg) {
273 return FloatCCRegNames[reg];
280 class SparcFloatCCRegClass : public MachineRegClassInfo
284 SparcFloatCCRegClass(unsigned ID)
285 : MachineRegClassInfo(ID, 4, 4) { }
287 void colorIGNode(IGNode * Node, bool IsColorUsedArr[] ) const {
289 for(c=0; c < 4 && IsColorUsedArr[c] ; ++c) ; // find color
290 assert( (c < 4) && "Can allocate only 4 float cc registers");
295 // according to Sparc 64 ABI, all %fp CC regs are volatile
297 inline bool isRegVolatile(const int Reg) const { return true; }