1 //***************************************************************************
6 // This file defines stuff that is to be private to the Sparc
7 // backend, but is shared among different portions of the backend.
8 //**************************************************************************/
11 #ifndef SPARC_INTERNALS_H
12 #define SPARC_INTERNALS_H
14 #include "llvm/Target/TargetMachine.h"
15 #include "llvm/Target/MachineSchedInfo.h"
16 #include "llvm/Target/MachineFrameInfo.h"
17 #include "llvm/Target/MachineCacheInfo.h"
18 #include "llvm/Target/MachineRegInfo.h"
19 #include "llvm/Type.h"
20 #include <sys/types.h>
27 Pass *createPrologEpilogCodeInserter(TargetMachine &TM);
29 // OpCodeMask definitions for the Sparc V9
31 const OpCodeMask Immed = 0x00002000; // immed or reg operand?
32 const OpCodeMask Annul = 0x20000000; // annul delay instr?
33 const OpCodeMask PredictTaken = 0x00080000; // predict branch taken?
36 enum SparcInstrSchedClass {
37 SPARC_NONE, /* Instructions with no scheduling restrictions */
38 SPARC_IEUN, /* Integer class that can use IEU0 or IEU1 */
39 SPARC_IEU0, /* Integer class IEU0 */
40 SPARC_IEU1, /* Integer class IEU1 */
41 SPARC_FPM, /* FP Multiply or Divide instructions */
42 SPARC_FPA, /* All other FP instructions */
43 SPARC_CTI, /* Control-transfer instructions */
44 SPARC_LD, /* Load instructions */
45 SPARC_ST, /* Store instructions */
46 SPARC_SINGLE, /* Instructions that must issue by themselves */
48 SPARC_INV, /* This should stay at the end for the next value */
49 SPARC_NUM_SCHED_CLASSES = SPARC_INV
53 //---------------------------------------------------------------------------
54 // enum SparcMachineOpCode.
55 // const MachineInstrDescriptor SparcMachineInstrDesc[]
58 // Description of UltraSparc machine instructions.
60 //---------------------------------------------------------------------------
62 enum SparcMachineOpCode {
63 #define I(ENUM, OPCODESTRING, NUMOPERANDS, RESULTPOS, MAXIMM, IMMSE, \
64 NUMDELAYSLOTS, LATENCY, SCHEDCLASS, INSTFLAGS) \
66 #include "SparcInstr.def"
68 // End-of-array marker
70 NUM_REAL_OPCODES = PHI, // number of valid opcodes
71 NUM_TOTAL_OPCODES = INVALID_OPCODE
75 // Array of machine instruction descriptions...
76 extern const MachineInstrDescriptor SparcMachineInstrDesc[];
79 //---------------------------------------------------------------------------
80 // class UltraSparcInstrInfo
83 // Information about individual instructions.
84 // Most information is stored in the SparcMachineInstrDesc array above.
85 // Other information is computed on demand, and most such functions
86 // default to member functions in base class MachineInstrInfo.
87 //---------------------------------------------------------------------------
89 class UltraSparcInstrInfo : public MachineInstrInfo {
91 /*ctor*/ UltraSparcInstrInfo(const TargetMachine& tgt);
94 // All immediate constants are in position 1 except the
95 // store instructions.
97 virtual int getImmedConstantPos(MachineOpCode opCode) const {
99 if (this->maxImmedConstant(opCode, ignore) != 0)
101 assert(! this->isStore((MachineOpCode) STB - 1)); // 1st store opcode
102 assert(! this->isStore((MachineOpCode) STXFSR+1));// last store opcode
103 return (opCode >= STB && opCode <= STXFSR)? 2 : 1;
109 virtual bool hasResultInterlock (MachineOpCode opCode) const
111 // All UltraSPARC instructions have interlocks (note that delay slots
112 // are not considered here).
113 // However, instructions that use the result of an FCMP produce a
114 // 9-cycle stall if they are issued less than 3 cycles after the FCMP.
115 // Force the compiler to insert a software interlock (i.e., gap of
116 // 2 other groups, including NOPs if necessary).
117 return (opCode == FCMPS || opCode == FCMPD || opCode == FCMPQ);
120 //-------------------------------------------------------------------------
121 // Code generation support for creating individual machine instructions
122 //-------------------------------------------------------------------------
124 // Create an instruction sequence to put the constant `val' into
125 // the virtual register `dest'. `val' may be a Constant or a
126 // GlobalValue, viz., the constant address of a global variable or function.
127 // The generated instructions are returned in `mvec'.
128 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
129 // Any stack space required is allocated via mcff.
131 virtual void CreateCodeToLoadConst(const TargetMachine& target,
135 std::vector<MachineInstr*>& mvec,
136 MachineCodeForInstruction& mcfi) const;
138 // Create an instruction sequence to copy an integer value `val'
139 // to a floating point value `dest' by copying to memory and back.
140 // val must be an integral type. dest must be a Float or Double.
141 // The generated instructions are returned in `mvec'.
142 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
143 // Any stack space required is allocated via mcff.
145 virtual void CreateCodeToCopyIntToFloat(const TargetMachine& target,
149 std::vector<MachineInstr*>& mvec,
150 MachineCodeForInstruction& mcfi) const;
152 // Similarly, create an instruction sequence to copy an FP value
153 // `val' to an integer value `dest' by copying to memory and back.
154 // The generated instructions are returned in `mvec'.
155 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
156 // Any stack space required is allocated via mcff.
158 virtual void CreateCodeToCopyFloatToInt(const TargetMachine& target,
162 std::vector<MachineInstr*>& mvec,
163 MachineCodeForInstruction& mcfi) const;
165 // Create instruction(s) to copy src to dest, for arbitrary types
166 // The generated instructions are returned in `mvec'.
167 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
168 // Any stack space required is allocated via mcff.
170 virtual void CreateCopyInstructionsByType(const TargetMachine& target,
174 std::vector<MachineInstr*>& mvec,
175 MachineCodeForInstruction& mcfi) const;
177 // Create instruction sequence to produce a sign-extended register value
178 // from an arbitrary sized value (sized in bits, not bytes).
179 // Any stack space required is allocated via mcff.
181 virtual void CreateSignExtensionInstructions(const TargetMachine& target,
183 Value* unsignedSrcVal,
184 unsigned int srcSizeInBits,
186 std::vector<MachineInstr*>& mvec,
187 MachineCodeForInstruction& mcfi) const;
191 //----------------------------------------------------------------------------
192 // class UltraSparcRegInfo
194 // This class implements the virtual class MachineRegInfo for Sparc.
196 //----------------------------------------------------------------------------
198 class UltraSparcRegInfo : public MachineRegInfo {
199 // The actual register classes in the Sparc
202 IntRegClassID, // Integer
203 FloatRegClassID, // Float (both single/double)
204 IntCCRegClassID, // Int Condition Code
205 FloatCCRegClassID // Float Condition code
209 // Type of registers available in Sparc. There can be several reg types
210 // in the same class. For instace, the float reg class has Single/Double
221 // **** WARNING: If the above enum order is changed, also modify
222 // getRegisterClassOfValue method below since it assumes this particular
223 // order for efficiency.
226 // reverse pointer to get info about the ultra sparc machine
228 const UltraSparc *const UltraSparcInfo;
230 // Number of registers used for passing int args (usually 6: %o0 - %o5)
232 unsigned const NumOfIntArgRegs;
234 // Number of registers used for passing float args (usually 32: %f0 - %f31)
236 unsigned const NumOfFloatArgRegs;
238 // An out of bound register number that can be used to initialize register
239 // numbers. Useful for error detection.
241 int const InvalidRegNum;
244 // ======================== Private Methods =============================
246 // The following methods are used to color special live ranges (e.g.
247 // function args and return values etc.) with specific hardware registers
248 // as required. See SparcRegInfo.cpp for the implementation.
250 void suggestReg4RetAddr(MachineInstr *RetMI,
251 LiveRangeInfo &LRI) const;
253 void suggestReg4CallAddr(MachineInstr *CallMI, LiveRangeInfo &LRI,
254 std::vector<RegClass *> RCList) const;
256 void InitializeOutgoingArg(MachineInstr* CallMI, AddedInstrns *CallAI,
257 PhyRegAlloc &PRA, LiveRange* LR,
258 unsigned regType, unsigned RegClassID,
259 int UniArgReg, unsigned int argNo,
260 std::vector<MachineInstr *>& AddedInstrnsBefore)
263 // The following 4 methods are used to find the RegType (see enum above)
264 // for a reg class and a given primitive type, a LiveRange, a Value,
265 // or a particular machine register.
266 // The fifth function gives the reg class of the given RegType.
268 int getRegType(unsigned regClassID, const Type* type) const;
269 int getRegType(const LiveRange *LR) const;
270 int getRegType(const Value *Val) const;
271 int getRegType(int unifiedRegNum) const;
273 // Used to generate a copy instruction based on the register class of
276 MachineInstr *cpValue2RegMI(Value *Val, unsigned DestReg,
280 // The following 2 methods are used to order the instructions addeed by
281 // the register allocator in association with function calling. See
282 // SparcRegInfo.cpp for more details
284 void moveInst2OrdVec(std::vector<MachineInstr *> &OrdVec,
285 MachineInstr *UnordInst,
286 PhyRegAlloc &PRA) const;
288 void OrderAddedInstrns(std::vector<MachineInstr *> &UnordVec,
289 std::vector<MachineInstr *> &OrdVec,
290 PhyRegAlloc &PRA) const;
293 // Compute which register can be used for an argument, if any
295 int regNumForIntArg(bool inCallee, bool isVarArgsCall,
296 unsigned argNo, unsigned intArgNo, unsigned fpArgNo,
297 unsigned& regClassId) const;
299 int regNumForFPArg(unsigned RegType, bool inCallee, bool isVarArgsCall,
300 unsigned argNo, unsigned intArgNo, unsigned fpArgNo,
301 unsigned& regClassId) const;
304 UltraSparcRegInfo(const UltraSparc &tgt);
306 // To get complete machine information structure using the machine register
309 inline const UltraSparc &getUltraSparcInfo() const {
310 return *UltraSparcInfo;
313 // To find the register class used for a specified Type
315 unsigned getRegClassIDOfType(const Type *type,
316 bool isCCReg = false) const;
318 // To find the register class of a Value
320 inline unsigned getRegClassIDOfValue(const Value *Val,
321 bool isCCReg = false) const {
322 return getRegClassIDOfType(Val->getType(), isCCReg);
325 // To find the register class to which a specified register belongs
327 unsigned getRegClassIDOfReg(int unifiedRegNum) const;
328 unsigned getRegClassIDOfRegType(int regType) const;
330 // getZeroRegNum - returns the register that contains always zero this is the
331 // unified register number
333 virtual int getZeroRegNum() const;
335 // getCallAddressReg - returns the reg used for pushing the address when a
336 // function is called. This can be used for other purposes between calls
338 unsigned getCallAddressReg() const;
340 // Returns the register containing the return address.
341 // It should be made sure that this register contains the return
342 // value when a return instruction is reached.
344 unsigned getReturnAddressReg() const;
346 // Number of registers used for passing int args (usually 6: %o0 - %o5)
347 // and float args (usually 32: %f0 - %f31)
349 unsigned const GetNumOfIntArgRegs() const { return NumOfIntArgRegs; }
350 unsigned const GetNumOfFloatArgRegs() const { return NumOfFloatArgRegs; }
352 // The following methods are used to color special live ranges (e.g.
353 // function args and return values etc.) with specific hardware registers
354 // as required. See SparcRegInfo.cpp for the implementation for Sparc.
356 void suggestRegs4MethodArgs(const Function *Meth,
357 LiveRangeInfo& LRI) const;
359 void suggestRegs4CallArgs(MachineInstr *CallMI,
361 std::vector<RegClass *> RCL) const;
363 void suggestReg4RetValue(MachineInstr *RetMI,
364 LiveRangeInfo& LRI) const;
366 void colorMethodArgs(const Function *Meth, LiveRangeInfo &LRI,
367 AddedInstrns *FirstAI) const;
369 void colorCallArgs(MachineInstr *CallMI, LiveRangeInfo &LRI,
370 AddedInstrns *CallAI, PhyRegAlloc &PRA,
371 const BasicBlock *BB) const;
373 void colorRetValue(MachineInstr *RetI, LiveRangeInfo& LRI,
374 AddedInstrns *RetAI) const;
377 // method used for printing a register for debugging purposes
379 static void printReg(const LiveRange *LR);
381 // Each register class has a seperate space for register IDs. To convert
382 // a regId in a register class to a common Id, or vice versa,
383 // we use the folloing methods.
385 // This method provides a unique number for each register
386 inline int getUnifiedRegNum(unsigned regClassID, int reg) const {
388 if (regClassID == IntRegClassID) {
389 assert(reg < 32 && "Invalid reg. number");
392 else if (regClassID == FloatRegClassID) {
393 assert(reg < 64 && "Invalid reg. number");
394 return reg + 32; // we have 32 int regs
396 else if (regClassID == FloatCCRegClassID) {
397 assert(reg < 4 && "Invalid reg. number");
398 return reg + 32 + 64; // 32 int, 64 float
400 else if (regClassID == IntCCRegClassID ) {
401 assert(reg == 0 && "Invalid reg. number");
402 return reg + 4+ 32 + 64; // only one int CC reg
404 else if (reg==InvalidRegNum) {
405 return InvalidRegNum;
408 assert(0 && "Invalid register class");
412 // This method converts the unified number to the number in its class,
413 // and returns the class ID in regClassID.
414 inline int getClassRegNum(int ureg, unsigned& regClassID) const {
415 if (ureg < 32) { regClassID = IntRegClassID; return ureg; }
416 else if (ureg < 32+64) { regClassID = FloatRegClassID; return ureg-32; }
417 else if (ureg < 4 +96) { regClassID = FloatCCRegClassID; return ureg-96; }
418 else if (ureg < 1 +100) { regClassID = IntCCRegClassID; return ureg-100;}
419 else if (ureg == InvalidRegNum) { return InvalidRegNum; }
420 else { assert(0 && "Invalid unified register number"); }
423 // Returns the assembly-language name of the specified machine register.
425 virtual const std::string getUnifiedRegName(int reg) const;
428 // returns the # of bytes of stack space allocated for each register
429 // type. For Sparc, currently we allocate 8 bytes on stack for all
430 // register types. We can optimize this later if necessary to save stack
431 // space (However, should make sure that stack alignment is correct)
433 inline int getSpilledRegSize(int RegType) const {
438 // To obtain the return value and the indirect call address (if any)
439 // contained in a CALL machine instruction
441 const Value * getCallInstRetVal(const MachineInstr *CallMI) const;
442 const Value * getCallInstIndirectAddrVal(const MachineInstr *CallMI) const;
444 // The following methods are used to generate "copy" machine instructions
445 // for an architecture.
447 // The function regTypeNeedsScratchReg() can be used to check whether a
448 // scratch register is needed to copy a register of type `regType' to
449 // or from memory. If so, such a scratch register can be provided by
450 // the caller (e.g., if it knows which regsiters are free); otherwise
451 // an arbitrary one will be chosen and spilled by the copy instructions.
453 bool regTypeNeedsScratchReg(int RegType,
454 int& scratchRegClassId) const;
456 void cpReg2RegMI(std::vector<MachineInstr*>& mvec,
457 unsigned SrcReg, unsigned DestReg,
460 void cpReg2MemMI(std::vector<MachineInstr*>& mvec,
461 unsigned SrcReg, unsigned DestPtrReg,
462 int Offset, int RegType, int scratchReg = -1) const;
464 void cpMem2RegMI(std::vector<MachineInstr*>& mvec,
465 unsigned SrcPtrReg, int Offset, unsigned DestReg,
466 int RegType, int scratchReg = -1) const;
468 void cpValue2Value(Value *Src, Value *Dest,
469 std::vector<MachineInstr*>& mvec) const;
471 // To see whether a register is a volatile (i.e., whehter it must be
472 // preserved acorss calls)
474 inline bool isRegVolatile(int RegClassID, int Reg) const {
475 return MachineRegClassArr[RegClassID]->isRegVolatile(Reg);
479 virtual unsigned getFramePointer() const;
480 virtual unsigned getStackPointer() const;
482 virtual int getInvalidRegNum() const {
483 return InvalidRegNum;
486 // This method inserts the caller saving code for call instructions
488 void insertCallerSavingCode(std::vector<MachineInstr*>& instrnsBefore,
489 std::vector<MachineInstr*>& instrnsAfter,
491 const BasicBlock *BB, PhyRegAlloc &PRA ) const;
497 //---------------------------------------------------------------------------
498 // class UltraSparcSchedInfo
501 // Interface to instruction scheduling information for UltraSPARC.
502 // The parameter values above are based on UltraSPARC IIi.
503 //---------------------------------------------------------------------------
506 class UltraSparcSchedInfo: public MachineSchedInfo {
508 UltraSparcSchedInfo(const TargetMachine &tgt);
510 virtual void initializeResources();
514 //---------------------------------------------------------------------------
515 // class UltraSparcFrameInfo
518 // Interface to stack frame layout info for the UltraSPARC.
519 // Starting offsets for each area of the stack frame are aligned at
520 // a multiple of getStackFrameSizeAlignment().
521 //---------------------------------------------------------------------------
523 class UltraSparcFrameInfo: public MachineFrameInfo {
525 UltraSparcFrameInfo(const TargetMachine &tgt) : MachineFrameInfo(tgt) {}
528 int getStackFrameSizeAlignment() const { return StackFrameSizeAlignment;}
529 int getMinStackFrameSize() const { return MinStackFrameSize; }
530 int getNumFixedOutgoingArgs() const { return NumFixedOutgoingArgs; }
531 int getSizeOfEachArgOnStack() const { return SizeOfEachArgOnStack; }
532 bool argsOnStackHaveFixedSize() const { return true; }
535 // These methods compute offsets using the frame contents for a
536 // particular function. The frame contents are obtained from the
537 // MachineCodeInfoForMethod object for the given function.
539 int getFirstIncomingArgOffset (MachineCodeForMethod& mcInfo,
542 growUp = true; // arguments area grows upwards
543 return FirstIncomingArgOffsetFromFP;
545 int getFirstOutgoingArgOffset (MachineCodeForMethod& mcInfo,
548 growUp = true; // arguments area grows upwards
549 return FirstOutgoingArgOffsetFromSP;
551 int getFirstOptionalOutgoingArgOffset(MachineCodeForMethod& mcInfo,
554 growUp = true; // arguments area grows upwards
555 return FirstOptionalOutgoingArgOffsetFromSP;
558 int getFirstAutomaticVarOffset (MachineCodeForMethod& mcInfo,
560 int getRegSpillAreaOffset (MachineCodeForMethod& mcInfo,
562 int getTmpAreaOffset (MachineCodeForMethod& mcInfo,
564 int getDynamicAreaOffset (MachineCodeForMethod& mcInfo,
568 // These methods specify the base register used for each stack area
569 // (generally FP or SP)
571 virtual int getIncomingArgBaseRegNum() const {
572 return (int) target.getRegInfo().getFramePointer();
574 virtual int getOutgoingArgBaseRegNum() const {
575 return (int) target.getRegInfo().getStackPointer();
577 virtual int getOptionalOutgoingArgBaseRegNum() const {
578 return (int) target.getRegInfo().getStackPointer();
580 virtual int getAutomaticVarBaseRegNum() const {
581 return (int) target.getRegInfo().getFramePointer();
583 virtual int getRegSpillAreaBaseRegNum() const {
584 return (int) target.getRegInfo().getFramePointer();
586 virtual int getDynamicAreaBaseRegNum() const {
587 return (int) target.getRegInfo().getStackPointer();
591 // All stack addresses must be offset by 0x7ff (2047) on Sparc V9.
592 static const int OFFSET = (int) 0x7ff;
593 static const int StackFrameSizeAlignment = 16;
594 static const int MinStackFrameSize = 176;
595 static const int NumFixedOutgoingArgs = 6;
596 static const int SizeOfEachArgOnStack = 8;
597 static const int StaticAreaOffsetFromFP = 0 + OFFSET;
598 static const int FirstIncomingArgOffsetFromFP = 128 + OFFSET;
599 static const int FirstOptionalIncomingArgOffsetFromFP = 176 + OFFSET;
600 static const int FirstOutgoingArgOffsetFromSP = 128 + OFFSET;
601 static const int FirstOptionalOutgoingArgOffsetFromSP = 176 + OFFSET;
605 //---------------------------------------------------------------------------
606 // class UltraSparcCacheInfo
609 // Interface to cache parameters for the UltraSPARC.
610 // Just use defaults for now.
611 //---------------------------------------------------------------------------
613 class UltraSparcCacheInfo: public MachineCacheInfo {
615 UltraSparcCacheInfo(const TargetMachine &T) : MachineCacheInfo(T) {}
619 //---------------------------------------------------------------------------
620 // class UltraSparcMachine
623 // Primary interface to machine description for the UltraSPARC.
624 // Primarily just initializes machine-dependent parameters in
625 // class TargetMachine, and creates machine-dependent subclasses
626 // for classes such as InstrInfo, SchedInfo and RegInfo.
627 //---------------------------------------------------------------------------
629 class UltraSparc : public TargetMachine {
631 UltraSparcInstrInfo instrInfo;
632 UltraSparcSchedInfo schedInfo;
633 UltraSparcRegInfo regInfo;
634 UltraSparcFrameInfo frameInfo;
635 UltraSparcCacheInfo cacheInfo;
639 virtual const MachineInstrInfo &getInstrInfo() const { return instrInfo; }
640 virtual const MachineSchedInfo &getSchedInfo() const { return schedInfo; }
641 virtual const MachineRegInfo &getRegInfo() const { return regInfo; }
642 virtual const MachineFrameInfo &getFrameInfo() const { return frameInfo; }
643 virtual const MachineCacheInfo &getCacheInfo() const { return cacheInfo; }
646 // addPassesToEmitAssembly - Add passes to the specified pass manager to get
647 // assembly langage code emited. For sparc, we have to do ...
649 virtual void addPassesToEmitAssembly(PassManager &PM, std::ostream &Out);
652 Pass *getFunctionAsmPrinterPass(PassManager &PM, std::ostream &Out);
653 Pass *getModuleAsmPrinterPass(PassManager &PM, std::ostream &Out);
654 Pass *getEmitBytecodeToAsmPass(std::ostream &Out);