2 //***************************************************************************
4 // SparcInstrSelection.cpp
7 // BURS instruction selection for SPARC V9 architecture.
10 // 7/02/01 - Vikram Adve - Created
11 //**************************************************************************/
13 #include "SparcInternals.h"
14 #include "SparcInstrSelectionSupport.h"
15 #include "llvm/CodeGen/InstrSelectionSupport.h"
16 #include "llvm/CodeGen/MachineInstr.h"
17 #include "llvm/CodeGen/InstrForest.h"
18 #include "llvm/CodeGen/InstrSelection.h"
19 #include "llvm/Support/MathExtras.h"
20 #include "llvm/DerivedTypes.h"
21 #include "llvm/iTerminators.h"
22 #include "llvm/iMemory.h"
23 #include "llvm/iOther.h"
24 #include "llvm/BasicBlock.h"
25 #include "llvm/Method.h"
26 #include "llvm/ConstPoolVals.h"
29 //******************** Internal Data Declarations ************************/
32 //************************* Forward Declarations ***************************/
35 static void SetMemOperands_Internal (MachineInstr* minstr,
36 const InstructionNode* vmInstrNode,
38 Value* arrayOffsetVal,
39 const vector<ConstPoolVal*>& idxVec,
40 const TargetMachine& target);
43 //************************ Internal Functions ******************************/
46 static inline MachineOpCode
47 ChooseBprInstruction(const InstructionNode* instrNode)
51 Instruction* setCCInstr =
52 ((InstructionNode*) instrNode->leftChild())->getInstruction();
54 switch(setCCInstr->getOpcode())
56 case Instruction::SetEQ: opCode = BRZ; break;
57 case Instruction::SetNE: opCode = BRNZ; break;
58 case Instruction::SetLE: opCode = BRLEZ; break;
59 case Instruction::SetGE: opCode = BRGEZ; break;
60 case Instruction::SetLT: opCode = BRLZ; break;
61 case Instruction::SetGT: opCode = BRGZ; break;
63 assert(0 && "Unrecognized VM instruction!");
64 opCode = INVALID_OPCODE;
72 static inline MachineOpCode
73 ChooseBpccInstruction(const InstructionNode* instrNode,
74 const BinaryOperator* setCCInstr)
76 MachineOpCode opCode = INVALID_OPCODE;
78 bool isSigned = setCCInstr->getOperand(0)->getType()->isSigned();
82 switch(setCCInstr->getOpcode())
84 case Instruction::SetEQ: opCode = BE; break;
85 case Instruction::SetNE: opCode = BNE; break;
86 case Instruction::SetLE: opCode = BLE; break;
87 case Instruction::SetGE: opCode = BGE; break;
88 case Instruction::SetLT: opCode = BL; break;
89 case Instruction::SetGT: opCode = BG; break;
91 assert(0 && "Unrecognized VM instruction!");
97 switch(setCCInstr->getOpcode())
99 case Instruction::SetEQ: opCode = BE; break;
100 case Instruction::SetNE: opCode = BNE; break;
101 case Instruction::SetLE: opCode = BLEU; break;
102 case Instruction::SetGE: opCode = BCC; break;
103 case Instruction::SetLT: opCode = BCS; break;
104 case Instruction::SetGT: opCode = BGU; break;
106 assert(0 && "Unrecognized VM instruction!");
114 static inline MachineOpCode
115 ChooseBFpccInstruction(const InstructionNode* instrNode,
116 const BinaryOperator* setCCInstr)
118 MachineOpCode opCode = INVALID_OPCODE;
120 switch(setCCInstr->getOpcode())
122 case Instruction::SetEQ: opCode = FBE; break;
123 case Instruction::SetNE: opCode = FBNE; break;
124 case Instruction::SetLE: opCode = FBLE; break;
125 case Instruction::SetGE: opCode = FBGE; break;
126 case Instruction::SetLT: opCode = FBL; break;
127 case Instruction::SetGT: opCode = FBG; break;
129 assert(0 && "Unrecognized VM instruction!");
137 static inline MachineOpCode
138 ChooseBccInstruction(const InstructionNode* instrNode,
141 InstructionNode* setCCNode = (InstructionNode*) instrNode->leftChild();
142 BinaryOperator* setCCInstr = (BinaryOperator*) setCCNode->getInstruction();
143 const Type* setCCType = setCCInstr->getOperand(0)->getType();
145 isFPBranch = (setCCType == Type::FloatTy || setCCType == Type::DoubleTy);
148 return ChooseBFpccInstruction(instrNode, setCCInstr);
150 return ChooseBpccInstruction(instrNode, setCCInstr);
154 static inline MachineOpCode
155 ChooseMovFpccInstruction(const InstructionNode* instrNode)
157 MachineOpCode opCode = INVALID_OPCODE;
159 switch(instrNode->getInstruction()->getOpcode())
161 case Instruction::SetEQ: opCode = MOVFE; break;
162 case Instruction::SetNE: opCode = MOVFNE; break;
163 case Instruction::SetLE: opCode = MOVFLE; break;
164 case Instruction::SetGE: opCode = MOVFGE; break;
165 case Instruction::SetLT: opCode = MOVFL; break;
166 case Instruction::SetGT: opCode = MOVFG; break;
168 assert(0 && "Unrecognized VM instruction!");
176 // Assumes that SUBcc v1, v2 -> v3 has been executed.
177 // In most cases, we want to clear v3 and then follow it by instruction
179 // Set mustClearReg=false if v3 need not be cleared before conditional move.
180 // Set valueToMove=0 if we want to conditionally move 0 instead of 1
181 // (i.e., we want to test inverse of a condition)
182 // (The latter two cases do not seem to arise because SetNE needs nothing.)
185 ChooseMovpccAfterSub(const InstructionNode* instrNode,
189 MachineOpCode opCode = INVALID_OPCODE;
193 switch(instrNode->getInstruction()->getOpcode())
195 case Instruction::SetEQ: opCode = MOVE; break;
196 case Instruction::SetLE: opCode = MOVLE; break;
197 case Instruction::SetGE: opCode = MOVGE; break;
198 case Instruction::SetLT: opCode = MOVL; break;
199 case Instruction::SetGT: opCode = MOVG; break;
200 case Instruction::SetNE: assert(0 && "No move required!"); break;
201 default: assert(0 && "Unrecognized VM instr!"); break;
207 static inline MachineOpCode
208 ChooseConvertToFloatInstr(const InstructionNode* instrNode,
211 MachineOpCode opCode = INVALID_OPCODE;
213 switch(instrNode->getOpLabel())
216 if (opType == Type::SByteTy || opType == Type::ShortTy || opType == Type::IntTy)
218 else if (opType == Type::LongTy)
220 else if (opType == Type::DoubleTy)
222 else if (opType == Type::FloatTy)
225 assert(0 && "Cannot convert this type to FLOAT on SPARC");
229 if (opType == Type::SByteTy || opType == Type::ShortTy || opType == Type::IntTy)
231 else if (opType == Type::LongTy)
233 else if (opType == Type::FloatTy)
235 else if (opType == Type::DoubleTy)
238 assert(0 && "Cannot convert this type to DOUBLE on SPARC");
248 static inline MachineOpCode
249 ChooseConvertToIntInstr(const InstructionNode* instrNode,
252 MachineOpCode opCode = INVALID_OPCODE;;
254 int instrType = (int) instrNode->getOpLabel();
256 if (instrType == ToSByteTy || instrType == ToShortTy || instrType == ToIntTy)
258 switch (opType->getPrimitiveID())
260 case Type::FloatTyID: opCode = FSTOI; break;
261 case Type::DoubleTyID: opCode = FDTOI; break;
263 assert(0 && "Non-numeric non-bool type cannot be converted to Int");
267 else if (instrType == ToLongTy)
269 switch (opType->getPrimitiveID())
271 case Type::FloatTyID: opCode = FSTOX; break;
272 case Type::DoubleTyID: opCode = FDTOX; break;
274 assert(0 && "Non-numeric non-bool type cannot be converted to Long");
279 assert(0 && "Should not get here, Mo!");
285 static inline MachineOpCode
286 ChooseAddInstructionByType(const Type* resultType)
288 MachineOpCode opCode = INVALID_OPCODE;
290 if (resultType->isIntegral() ||
291 isa<PointerType>(resultType) ||
292 isa<MethodType>(resultType) ||
293 resultType->isLabelType() ||
294 resultType == Type::BoolTy)
299 switch(resultType->getPrimitiveID())
301 case Type::FloatTyID: opCode = FADDS; break;
302 case Type::DoubleTyID: opCode = FADDD; break;
303 default: assert(0 && "Invalid type for ADD instruction"); break;
310 static inline MachineOpCode
311 ChooseAddInstruction(const InstructionNode* instrNode)
313 return ChooseAddInstructionByType(instrNode->getInstruction()->getType());
317 static inline MachineInstr*
318 CreateMovFloatInstruction(const InstructionNode* instrNode,
319 const Type* resultType)
321 MachineInstr* minstr = new MachineInstr((resultType == Type::FloatTy)
323 minstr->SetMachineOperand(0, MachineOperand::MO_VirtualRegister,
324 instrNode->leftChild()->getValue());
325 minstr->SetMachineOperand(1, MachineOperand::MO_VirtualRegister,
326 instrNode->getValue());
330 static inline MachineInstr*
331 CreateAddConstInstruction(const InstructionNode* instrNode)
333 MachineInstr* minstr = NULL;
335 Value* constOp = ((InstrTreeNode*) instrNode->rightChild())->getValue();
336 assert(isa<ConstPoolVal>(constOp));
338 // Cases worth optimizing are:
339 // (1) Add with 0 for float or double: use an FMOV of appropriate type,
340 // instead of an FADD (1 vs 3 cycles). There is no integer MOV.
342 const Type* resultType = instrNode->getInstruction()->getType();
344 if (resultType == Type::FloatTy ||
345 resultType == Type::DoubleTy)
347 double dval = ((ConstPoolFP*) constOp)->getValue();
349 minstr = CreateMovFloatInstruction(instrNode, resultType);
356 static inline MachineOpCode
357 ChooseSubInstruction(const InstructionNode* instrNode)
359 MachineOpCode opCode = INVALID_OPCODE;
361 const Type* resultType = instrNode->getInstruction()->getType();
363 if (resultType->isIntegral() ||
364 resultType->isPointerType())
369 switch(resultType->getPrimitiveID())
371 case Type::FloatTyID: opCode = FSUBS; break;
372 case Type::DoubleTyID: opCode = FSUBD; break;
373 default: assert(0 && "Invalid type for SUB instruction"); break;
380 static inline MachineInstr*
381 CreateSubConstInstruction(const InstructionNode* instrNode)
383 MachineInstr* minstr = NULL;
385 Value* constOp = ((InstrTreeNode*) instrNode->rightChild())->getValue();
386 assert(isa<ConstPoolVal>(constOp));
388 // Cases worth optimizing are:
389 // (1) Sub with 0 for float or double: use an FMOV of appropriate type,
390 // instead of an FSUB (1 vs 3 cycles). There is no integer MOV.
392 const Type* resultType = instrNode->getInstruction()->getType();
394 if (resultType == Type::FloatTy ||
395 resultType == Type::DoubleTy)
397 double dval = ((ConstPoolFP*) constOp)->getValue();
399 minstr = CreateMovFloatInstruction(instrNode, resultType);
406 static inline MachineOpCode
407 ChooseFcmpInstruction(const InstructionNode* instrNode)
409 MachineOpCode opCode = INVALID_OPCODE;
411 Value* operand = ((InstrTreeNode*) instrNode->leftChild())->getValue();
412 switch(operand->getType()->getPrimitiveID()) {
413 case Type::FloatTyID: opCode = FCMPS; break;
414 case Type::DoubleTyID: opCode = FCMPD; break;
415 default: assert(0 && "Invalid type for FCMP instruction"); break;
422 // Assumes that leftArg and rightArg are both cast instructions.
425 BothFloatToDouble(const InstructionNode* instrNode)
427 InstrTreeNode* leftArg = instrNode->leftChild();
428 InstrTreeNode* rightArg = instrNode->rightChild();
429 InstrTreeNode* leftArgArg = leftArg->leftChild();
430 InstrTreeNode* rightArgArg = rightArg->leftChild();
431 assert(leftArg->getValue()->getType() == rightArg->getValue()->getType());
433 // Check if both arguments are floats cast to double
434 return (leftArg->getValue()->getType() == Type::DoubleTy &&
435 leftArgArg->getValue()->getType() == Type::FloatTy &&
436 rightArgArg->getValue()->getType() == Type::FloatTy);
440 static inline MachineOpCode
441 ChooseMulInstruction(const InstructionNode* instrNode,
444 MachineOpCode opCode = INVALID_OPCODE;
446 if (checkCasts && BothFloatToDouble(instrNode))
448 return opCode = FSMULD;
450 // else fall through and use the regular multiply instructions
452 const Type* resultType = instrNode->getInstruction()->getType();
454 if (resultType->isIntegral())
459 switch(resultType->getPrimitiveID())
461 case Type::FloatTyID: opCode = FMULS; break;
462 case Type::DoubleTyID: opCode = FMULD; break;
463 default: assert(0 && "Invalid type for MUL instruction"); break;
470 static inline MachineInstr*
471 CreateIntNegInstruction(TargetMachine& target,
474 MachineInstr* minstr = new MachineInstr(SUB);
475 minstr->SetMachineOperand(0, target.getRegInfo().getZeroRegNum());
476 minstr->SetMachineOperand(1, MachineOperand::MO_VirtualRegister, vreg);
477 minstr->SetMachineOperand(2, MachineOperand::MO_VirtualRegister, vreg);
482 static inline MachineInstr*
483 CreateMulConstInstruction(TargetMachine &target,
484 const InstructionNode* instrNode,
485 MachineInstr*& getMinstr2)
487 MachineInstr* minstr = NULL;
489 bool needNeg = false;
491 Value* constOp = ((InstrTreeNode*) instrNode->rightChild())->getValue();
492 assert(isa<ConstPoolVal>(constOp));
494 // Cases worth optimizing are:
495 // (1) Multiply by 0 or 1 for any type: replace with copy (ADD or FMOV)
496 // (2) Multiply by 2^x for integer types: replace with Shift
498 const Type* resultType = instrNode->getInstruction()->getType();
500 if (resultType->isIntegral() || resultType->isPointerType())
504 int64_t C = GetConstantValueAsSignedInt(constOp, isValidConst);
507 bool needNeg = false;
514 if (C == 0 || C == 1)
516 minstr = new MachineInstr(ADD);
519 minstr->SetMachineOperand(0,
520 target.getRegInfo().getZeroRegNum());
522 minstr->SetMachineOperand(0,MachineOperand::MO_VirtualRegister,
523 instrNode->leftChild()->getValue());
524 minstr->SetMachineOperand(1,target.getRegInfo().getZeroRegNum());
526 else if (IsPowerOf2(C, pow))
528 minstr = new MachineInstr((resultType == Type::LongTy)
530 minstr->SetMachineOperand(0, MachineOperand::MO_VirtualRegister,
531 instrNode->leftChild()->getValue());
532 minstr->SetMachineOperand(1, MachineOperand::MO_UnextendedImmed,
536 if (minstr && needNeg)
537 { // insert <reg = SUB 0, reg> after the instr to flip the sign
538 getMinstr2 = CreateIntNegInstruction(target,
539 instrNode->getValue());
545 if (resultType == Type::FloatTy ||
546 resultType == Type::DoubleTy)
549 double dval = ((ConstPoolFP*) constOp)->getValue();
555 minstr = new MachineInstr((resultType == Type::FloatTy)
557 minstr->SetMachineOperand(0,
558 target.getRegInfo().getZeroRegNum());
560 else if (fabs(dval) == 1)
562 bool needNeg = (dval < 0);
564 MachineOpCode opCode = needNeg
565 ? (resultType == Type::FloatTy? FNEGS : FNEGD)
566 : (resultType == Type::FloatTy? FMOVS : FMOVD);
568 minstr = new MachineInstr(opCode);
569 minstr->SetMachineOperand(0,
570 MachineOperand::MO_VirtualRegister,
571 instrNode->leftChild()->getValue());
578 minstr->SetMachineOperand(2, MachineOperand::MO_VirtualRegister,
579 instrNode->getValue());
585 static inline MachineOpCode
586 ChooseDivInstruction(TargetMachine &target,
587 const InstructionNode* instrNode)
589 MachineOpCode opCode = INVALID_OPCODE;
591 const Type* resultType = instrNode->getInstruction()->getType();
593 if (resultType->isIntegral())
594 opCode = resultType->isSigned()? SDIVX : UDIVX;
596 switch(resultType->getPrimitiveID())
598 case Type::FloatTyID: opCode = FDIVS; break;
599 case Type::DoubleTyID: opCode = FDIVD; break;
600 default: assert(0 && "Invalid type for DIV instruction"); break;
607 static inline MachineInstr*
608 CreateDivConstInstruction(TargetMachine &target,
609 const InstructionNode* instrNode,
610 MachineInstr*& getMinstr2)
612 MachineInstr* minstr = NULL;
615 Value* constOp = ((InstrTreeNode*) instrNode->rightChild())->getValue();
616 assert(isa<ConstPoolVal>(constOp));
618 // Cases worth optimizing are:
619 // (1) Divide by 1 for any type: replace with copy (ADD or FMOV)
620 // (2) Divide by 2^x for integer types: replace with SR[L or A]{X}
622 const Type* resultType = instrNode->getInstruction()->getType();
624 if (resultType->isIntegral())
628 int64_t C = GetConstantValueAsSignedInt(constOp, isValidConst);
631 bool needNeg = false;
640 minstr = new MachineInstr(ADD);
641 minstr->SetMachineOperand(0,MachineOperand::MO_VirtualRegister,
642 instrNode->leftChild()->getValue());
643 minstr->SetMachineOperand(1,target.getRegInfo().getZeroRegNum());
645 else if (IsPowerOf2(C, pow))
647 MachineOpCode opCode= ((resultType->isSigned())
648 ? (resultType==Type::LongTy)? SRAX : SRA
649 : (resultType==Type::LongTy)? SRLX : SRL);
650 minstr = new MachineInstr(opCode);
651 minstr->SetMachineOperand(0, MachineOperand::MO_VirtualRegister,
652 instrNode->leftChild()->getValue());
653 minstr->SetMachineOperand(1, MachineOperand::MO_UnextendedImmed,
657 if (minstr && needNeg)
658 { // insert <reg = SUB 0, reg> after the instr to flip the sign
659 getMinstr2 = CreateIntNegInstruction(target,
660 instrNode->getValue());
666 if (resultType == Type::FloatTy ||
667 resultType == Type::DoubleTy)
670 double dval = ((ConstPoolFP*) constOp)->getValue();
672 if (isValidConst && fabs(dval) == 1)
674 bool needNeg = (dval < 0);
676 MachineOpCode opCode = needNeg
677 ? (resultType == Type::FloatTy? FNEGS : FNEGD)
678 : (resultType == Type::FloatTy? FMOVS : FMOVD);
680 minstr = new MachineInstr(opCode);
681 minstr->SetMachineOperand(0, MachineOperand::MO_VirtualRegister,
682 instrNode->leftChild()->getValue());
688 minstr->SetMachineOperand(2, MachineOperand::MO_VirtualRegister,
689 instrNode->getValue());
695 //------------------------------------------------------------------------
696 // Function SetOperandsForMemInstr
698 // Choose addressing mode for the given load or store instruction.
699 // Use [reg+reg] if it is an indexed reference, and the index offset is
700 // not a constant or if it cannot fit in the offset field.
701 // Use [reg+offset] in all other cases.
703 // This assumes that all array refs are "lowered" to one of these forms:
704 // %x = load (subarray*) ptr, constant ; single constant offset
705 // %x = load (subarray*) ptr, offsetVal ; single non-constant offset
706 // Generally, this should happen via strength reduction + LICM.
707 // Also, strength reduction should take care of using the same register for
708 // the loop index variable and an array index, when that is profitable.
709 //------------------------------------------------------------------------
712 SetOperandsForMemInstr(MachineInstr* minstr,
713 const InstructionNode* vmInstrNode,
714 const TargetMachine& target)
716 MemAccessInst* memInst = (MemAccessInst*) vmInstrNode->getInstruction();
718 // Variables to hold the index vector, ptr value, and offset value.
719 // The major work here is to extract these for all 3 instruction types
720 // and then call the common function SetMemOperands_Internal().
722 const vector<ConstPoolVal*>* idxVec = & memInst->getIndexVec();
723 vector<ConstPoolVal*>* newIdxVec = NULL;
725 Value* arrayOffsetVal = NULL;
727 // Test if a GetElemPtr instruction is being folded into this mem instrn.
728 // If so, it will be in the left child for Load and GetElemPtr,
729 // and in the right child for Store instructions.
731 InstrTreeNode* ptrChild = (vmInstrNode->getOpLabel() == Instruction::Store
732 ? vmInstrNode->rightChild()
733 : vmInstrNode->leftChild());
735 if (ptrChild->getOpLabel() == Instruction::GetElementPtr ||
736 ptrChild->getOpLabel() == GetElemPtrIdx)
738 // There is a GetElemPtr instruction and there may be a chain of
739 // more than one. Use the pointer value of the last one in the chain.
740 // Fold the index vectors from the entire chain and from the mem
741 // instruction into one single index vector.
742 // Finally, we never fold for an array instruction so make that NULL.
744 newIdxVec = new vector<ConstPoolVal*>;
745 ptrVal = FoldGetElemChain((InstructionNode*) ptrChild, *newIdxVec);
747 newIdxVec->insert(newIdxVec->end(), idxVec->begin(), idxVec->end());
750 assert(! ((PointerType*)ptrVal->getType())->getValueType()->isArrayType()
751 && "GetElemPtr cannot be folded into array refs in selection");
755 // There is no GetElemPtr instruction.
756 // Use the pointer value and the index vector from the Mem instruction.
757 // If it is an array reference, get the array offset value.
759 ptrVal = memInst->getPtrOperand();
762 ((const PointerType*) ptrVal->getType())->getValueType();
763 if (opType->isArrayType())
765 assert((memInst->getNumOperands()
766 == (unsigned) 1 + memInst->getFirstOffsetIdx())
767 && "Array refs must be lowered before Instruction Selection");
769 arrayOffsetVal = memInst->getOperand(memInst->getFirstOffsetIdx());
773 SetMemOperands_Internal(minstr, vmInstrNode, ptrVal, arrayOffsetVal,
776 if (newIdxVec != NULL)
782 SetMemOperands_Internal(MachineInstr* minstr,
783 const InstructionNode* vmInstrNode,
785 Value* arrayOffsetVal,
786 const vector<ConstPoolVal*>& idxVec,
787 const TargetMachine& target)
789 MemAccessInst* memInst = (MemAccessInst*) vmInstrNode->getInstruction();
791 // Initialize so we default to storing the offset in a register.
792 int64_t smallConstOffset;
793 Value* valueForRegOffset = NULL;
794 MachineOperand::MachineOperandType offsetOpType =MachineOperand::MO_VirtualRegister;
796 // Check if there is an index vector and if so, if it translates to
797 // a small enough constant to fit in the immediate-offset field.
799 if (idxVec.size() > 0)
801 bool isConstantOffset = false;
804 const PointerType* ptrType = (PointerType*) ptrVal->getType();
806 if (ptrType->getValueType()->isStructType())
808 // the offset is always constant for structs
809 isConstantOffset = true;
811 // Compute the offset value using the index vector
812 offset = target.DataLayout.getIndexedOffset(ptrType, idxVec);
816 // It must be an array ref. Check if the offset is a constant,
817 // and that the indexing has been lowered to a single offset.
819 assert(ptrType->getValueType()->isArrayType());
820 assert(arrayOffsetVal != NULL
821 && "Expect to be given Value* for array offsets");
823 if (ConstPoolVal *CPV = dyn_cast<ConstPoolVal>(arrayOffsetVal))
825 isConstantOffset = true; // always constant for structs
826 assert(arrayOffsetVal->getType()->isIntegral());
827 offset = (CPV->getType()->isSigned()
828 ? ((ConstPoolSInt*)CPV)->getValue()
829 : (int64_t) ((ConstPoolUInt*)CPV)->getValue());
833 valueForRegOffset = arrayOffsetVal;
837 if (isConstantOffset)
839 // create a virtual register for the constant
840 valueForRegOffset = ConstPoolSInt::get(Type::IntTy, offset);
845 offsetOpType = MachineOperand::MO_SignExtendedImmed;
846 smallConstOffset = 0;
849 // Operand 0 is value for STORE, ptr for LOAD or GET_ELEMENT_PTR
850 // It is the left child in the instruction tree in all cases.
851 Value* leftVal = vmInstrNode->leftChild()->getValue();
852 minstr->SetMachineOperand(0, MachineOperand::MO_VirtualRegister, leftVal);
854 // Operand 1 is ptr for STORE, offset for LOAD or GET_ELEMENT_PTR
855 // Operand 2 is offset for STORE, result reg for LOAD or GET_ELEMENT_PTR
857 unsigned offsetOpNum = (memInst->getOpcode() == Instruction::Store)? 2 : 1;
858 if (offsetOpType == MachineOperand::MO_VirtualRegister)
860 assert(valueForRegOffset != NULL);
861 minstr->SetMachineOperand(offsetOpNum, offsetOpType, valueForRegOffset);
864 minstr->SetMachineOperand(offsetOpNum, offsetOpType, smallConstOffset);
866 if (memInst->getOpcode() == Instruction::Store)
867 minstr->SetMachineOperand(1, MachineOperand::MO_VirtualRegister, ptrVal);
869 minstr->SetMachineOperand(2, MachineOperand::MO_VirtualRegister,
870 vmInstrNode->getValue());
875 // Substitute operand `operandNum' of the instruction in node `treeNode'
876 // in place of the use(s) of that instruction in node `parent'.
877 // Check both explicit and implicit operands!
880 ForwardOperand(InstructionNode* treeNode,
881 InstrTreeNode* parent,
884 assert(treeNode && parent && "Invalid invocation of ForwardOperand");
886 Instruction* unusedOp = treeNode->getInstruction();
887 Value* fwdOp = unusedOp->getOperand(operandNum);
889 // The parent itself may be a list node, so find the real parent instruction
890 while (parent->getNodeType() != InstrTreeNode::NTInstructionNode)
892 parent = parent->parent();
893 assert(parent && "ERROR: Non-instruction node has no parent in tree.");
895 InstructionNode* parentInstrNode = (InstructionNode*) parent;
897 Instruction* userInstr = parentInstrNode->getInstruction();
898 MachineCodeForVMInstr& mvec = userInstr->getMachineInstrVec();
899 for (unsigned i=0, N=mvec.size(); i < N; i++)
901 MachineInstr* minstr = mvec[i];
903 for (unsigned i=0, numOps=minstr->getNumOperands(); i < numOps; ++i)
905 const MachineOperand& mop = minstr->getOperand(i);
906 if (mop.getOperandType() == MachineOperand::MO_VirtualRegister &&
907 mop.getVRegValue() == unusedOp)
909 minstr->SetMachineOperand(i, MachineOperand::MO_VirtualRegister,
914 for (unsigned i=0, numOps=minstr->getNumImplicitRefs(); i < numOps; ++i)
915 if (minstr->getImplicitRef(i) == unusedOp)
916 minstr->setImplicitRef(i, fwdOp, minstr->implicitRefIsDefined(i));
922 CreateCopyInstructionsByType(const TargetMachine& target,
925 vector<MachineInstr*>& minstrVec)
927 bool loadConstantToReg = false;
929 const Type* resultType = dest->getType();
931 MachineOpCode opCode = ChooseAddInstructionByType(resultType);
932 if (opCode == INVALID_OPCODE)
934 assert(0 && "Unsupported result type in CreateCopyInstructionsByType()");
938 // if `src' is a constant that doesn't fit in the immed field or if it is
939 // a global variable (i.e., a constant address), generate a load
940 // instruction instead of an add
942 if (isa<ConstPoolVal>(src))
944 unsigned int machineRegNum;
946 MachineOperand::MachineOperandType opType =
947 ChooseRegOrImmed(src, opCode, target, /*canUseImmed*/ true,
948 machineRegNum, immedValue);
950 if (opType == MachineOperand::MO_VirtualRegister)
951 loadConstantToReg = true;
953 else if (isa<GlobalValue>(src))
954 loadConstantToReg = true;
956 if (loadConstantToReg)
957 { // `src' is constant and cannot fit in immed field for the ADD
958 // Insert instructions to "load" the constant into a register
959 vector<TmpInstruction*> tempVec;
960 target.getInstrInfo().CreateCodeToLoadConst(src,dest,minstrVec,tempVec);
961 for (unsigned i=0; i < tempVec.size(); i++)
962 dest->getMachineInstrVec().addTempValue(tempVec[i]);
965 { // Create the appropriate add instruction.
966 // Make `src' the second operand, in case it is a constant
967 // Use (unsigned long) 0 for a NULL pointer value.
969 const Type* nullValueType =
970 (resultType->getPrimitiveID() == Type::PointerTyID)? Type::ULongTy
972 MachineInstr* minstr = new MachineInstr(opCode);
973 minstr->SetMachineOperand(0, MachineOperand::MO_VirtualRegister,
974 ConstPoolVal::getNullConstant(nullValueType));
975 minstr->SetMachineOperand(1, MachineOperand::MO_VirtualRegister, src);
976 minstr->SetMachineOperand(2, MachineOperand::MO_VirtualRegister, dest);
977 minstrVec.push_back(minstr);
982 //******************* Externally Visible Functions *************************/
985 //------------------------------------------------------------------------
986 // External Function: GetInstructionsForProlog
987 // External Function: GetInstructionsForEpilog
990 // Create prolog and epilog code for procedure entry and exit
991 //------------------------------------------------------------------------
994 GetInstructionsForProlog(BasicBlock* entryBB,
995 TargetMachine &target,
998 int64_t s0=0; // used to avoid overloading ambiguity below
1000 // The second operand is the stack size. If it does not fit in the
1001 // immediate field, we either have to find an unused register in the
1002 // caller's window or move some elements to the dynamically allocated
1003 // area of the stack frame (just above save area and method args).
1004 Method* method = entryBB->getParent();
1005 MachineCodeForMethod& mcodeInfo = method->getMachineCode();
1006 unsigned int staticStackSize = mcodeInfo.getStaticStackSize();
1008 assert(target.getInstrInfo().constantFitsInImmedField(SAVE, staticStackSize)
1009 && "Stack size too large for immediate field of SAVE instruction. Need additional work as described in the comment above");
1011 mvec[0] = new MachineInstr(SAVE);
1012 mvec[0]->SetMachineOperand(0, target.getRegInfo().getStackPointer());
1013 mvec[0]->SetMachineOperand(1, MachineOperand::MO_SignExtendedImmed,
1015 mvec[0]->SetMachineOperand(2, target.getRegInfo().getStackPointer());
1022 GetInstructionsForEpilog(BasicBlock* anExitBB,
1023 TargetMachine &target,
1024 MachineInstr** mvec)
1026 int64_t s0=0; // used to avoid overloading ambiguity below
1028 mvec[0] = new MachineInstr(RESTORE);
1029 mvec[0]->SetMachineOperand(0, target.getRegInfo().getZeroRegNum());
1030 mvec[0]->SetMachineOperand(1, MachineOperand::MO_SignExtendedImmed, s0);
1031 mvec[0]->SetMachineOperand(2, target.getRegInfo().getZeroRegNum());
1037 //------------------------------------------------------------------------
1038 // External Function: ThisIsAChainRule
1041 // Check if a given BURG rule is a chain rule.
1042 //------------------------------------------------------------------------
1045 ThisIsAChainRule(int eruleno)
1049 case 111: // stmt: reg
1050 case 113: // stmt: bool
1072 return false; break;
1077 //------------------------------------------------------------------------
1078 // External Function: GetInstructionsByRule
1081 // Choose machine instructions for the SPARC according to the
1082 // patterns chosen by the BURG-generated parser.
1083 //------------------------------------------------------------------------
1086 GetInstructionsByRule(InstructionNode* subtreeRoot,
1090 MachineInstr** mvec)
1092 int numInstr = 1; // initialize for common case
1093 bool checkCast = false; // initialize here to use fall-through
1094 Value *leftVal, *rightVal;
1097 int forwardOperandNum = -1;
1098 int64_t s0=0, s8=8; // variables holding constants to avoid
1099 uint64_t u0=0; // overloading ambiguities below
1101 UltraSparc& target = (UltraSparc&) tgt;
1103 for (unsigned i=0; i < MAX_INSTR_PER_VMINSTR; i++)
1107 // Let's check for chain rules outside the switch so that we don't have
1108 // to duplicate the list of chain rule production numbers here again
1110 if (ThisIsAChainRule(ruleForNode))
1112 // Chain rules have a single nonterminal on the RHS.
1113 // Get the rule that matches the RHS non-terminal and use that instead.
1115 assert(nts[0] && ! nts[1]
1116 && "A chain rule should have only one RHS non-terminal!");
1117 nextRule = burm_rule(subtreeRoot->state, nts[0]);
1118 nts = burm_nts[nextRule];
1119 numInstr = GetInstructionsByRule(subtreeRoot, nextRule, nts,target,mvec);
1123 switch(ruleForNode) {
1124 case 1: // stmt: Ret
1125 case 2: // stmt: RetValue(reg)
1126 // NOTE: Prepass of register allocation is responsible
1127 // for moving return value to appropriate register.
1128 // Mark the return-address register as a hidden virtual reg.
1129 // Mark the return value register as an implicit ref of
1130 // the machine instruction.
1131 { // Finally put a NOP in the delay slot.
1132 ReturnInst* returnInstr = (ReturnInst*) subtreeRoot->getInstruction();
1133 assert(returnInstr->getOpcode() == Instruction::Ret);
1134 Method* method = returnInstr->getParent()->getParent();
1136 Instruction* returnReg = new TmpInstruction(TMP_INSTRUCTION_OPCODE,
1138 returnInstr->getMachineInstrVec().addTempValue(returnReg);
1140 mvec[0] = new MachineInstr(JMPLRET);
1141 mvec[0]->SetMachineOperand(0, MachineOperand::MO_VirtualRegister,
1143 mvec[0]->SetMachineOperand(1, MachineOperand::MO_SignExtendedImmed,s8);
1144 mvec[0]->SetMachineOperand(2, target.getRegInfo().getZeroRegNum());
1146 if (returnInstr->getReturnValue() != NULL)
1147 mvec[0]->addImplicitRef(returnInstr->getReturnValue());
1149 unsigned n = numInstr++; // delay slot
1150 mvec[n] = new MachineInstr(NOP);
1155 case 3: // stmt: Store(reg,reg)
1156 case 4: // stmt: Store(reg,ptrreg)
1157 mvec[0] = new MachineInstr(
1158 ChooseStoreInstruction(
1159 subtreeRoot->leftChild()->getValue()->getType()));
1160 SetOperandsForMemInstr(mvec[0], subtreeRoot, target);
1163 case 5: // stmt: BrUncond
1164 mvec[0] = new MachineInstr(BA);
1165 mvec[0]->SetMachineOperand(0, MachineOperand::MO_CCRegister,
1167 mvec[0]->SetMachineOperand(1, MachineOperand::MO_PCRelativeDisp,
1168 ((BranchInst*) subtreeRoot->getInstruction())->getSuccessor(0));
1171 mvec[numInstr++] = new MachineInstr(NOP);
1174 case 206: // stmt: BrCond(setCCconst)
1175 // setCCconst => boolean was computed with `%b = setCC type reg1 const'
1176 // If the constant is ZERO, we can use the branch-on-integer-register
1177 // instructions and avoid the SUBcc instruction entirely.
1178 // Otherwise this is just the same as case 5, so just fall through.
1180 InstrTreeNode* constNode = subtreeRoot->leftChild()->rightChild();
1182 constNode->getNodeType() ==InstrTreeNode::NTConstNode);
1183 ConstPoolVal* constVal = (ConstPoolVal*) constNode->getValue();
1186 if ((constVal->getType()->isIntegral()
1187 || constVal->getType()->isPointerType())
1188 && GetConstantValueAsSignedInt(constVal, isValidConst) == 0
1191 // That constant is a zero after all...
1192 // Use the left child of setCC as the first argument!
1193 mvec[0] = new MachineInstr(ChooseBprInstruction(subtreeRoot));
1194 mvec[0]->SetMachineOperand(0, MachineOperand::MO_VirtualRegister,
1195 subtreeRoot->leftChild()->leftChild()->getValue());
1196 mvec[0]->SetMachineOperand(1, MachineOperand::MO_PCRelativeDisp,
1197 ((BranchInst*) subtreeRoot->getInstruction())->getSuccessor(0));
1200 mvec[numInstr++] = new MachineInstr(NOP);
1204 mvec[n] = new MachineInstr(BA);
1205 mvec[n]->SetMachineOperand(0, MachineOperand::MO_CCRegister,
1207 mvec[n]->SetMachineOperand(1, MachineOperand::MO_PCRelativeDisp,
1208 ((BranchInst*) subtreeRoot->getInstruction())->getSuccessor(1));
1211 mvec[numInstr++] = new MachineInstr(NOP);
1215 // ELSE FALL THROUGH
1218 case 6: // stmt: BrCond(bool)
1219 // bool => boolean was computed with some boolean operator
1220 // (SetCC, Not, ...). We need to check whether the type was a FP,
1221 // signed int or unsigned int, and check the branching condition in
1222 // order to choose the branch to use.
1226 mvec[0] = new MachineInstr(ChooseBccInstruction(subtreeRoot,
1228 mvec[0]->SetMachineOperand(0, MachineOperand::MO_CCRegister,
1229 subtreeRoot->leftChild()->getValue());
1230 mvec[0]->SetMachineOperand(1, MachineOperand::MO_PCRelativeDisp,
1231 ((BranchInst*) subtreeRoot->getInstruction())->getSuccessor(0));
1234 mvec[numInstr++] = new MachineInstr(NOP);
1238 mvec[n] = new MachineInstr(BA);
1239 mvec[n]->SetMachineOperand(0, MachineOperand::MO_CCRegister,
1241 mvec[n]->SetMachineOperand(1, MachineOperand::MO_PCRelativeDisp,
1242 ((BranchInst*) subtreeRoot->getInstruction())->getSuccessor(1));
1245 mvec[numInstr++] = new MachineInstr(NOP);
1249 case 208: // stmt: BrCond(boolconst)
1251 // boolconst => boolean is a constant; use BA to first or second label
1252 ConstPoolVal* constVal =
1253 cast<ConstPoolVal>(subtreeRoot->leftChild()->getValue());
1254 unsigned dest = ((ConstPoolBool*) constVal)->getValue()? 0 : 1;
1256 mvec[0] = new MachineInstr(BA);
1257 mvec[0]->SetMachineOperand(0, MachineOperand::MO_CCRegister,
1259 mvec[0]->SetMachineOperand(1, MachineOperand::MO_PCRelativeDisp,
1260 ((BranchInst*) subtreeRoot->getInstruction())->getSuccessor(dest));
1263 mvec[numInstr++] = new MachineInstr(NOP);
1267 case 8: // stmt: BrCond(boolreg)
1268 // boolreg => boolean is stored in an existing register.
1269 // Just use the branch-on-integer-register instruction!
1272 mvec[0] = new MachineInstr(BRNZ);
1273 mvec[0]->SetMachineOperand(0, MachineOperand::MO_VirtualRegister,
1274 subtreeRoot->leftChild()->getValue());
1275 mvec[0]->SetMachineOperand(1, MachineOperand::MO_PCRelativeDisp,
1276 ((BranchInst*) subtreeRoot->getInstruction())->getSuccessor(0));
1279 mvec[numInstr++] = new MachineInstr(NOP); // delay slot
1283 mvec[n] = new MachineInstr(BA);
1284 mvec[n]->SetMachineOperand(0, MachineOperand::MO_CCRegister,
1286 mvec[n]->SetMachineOperand(1, MachineOperand::MO_PCRelativeDisp,
1287 ((BranchInst*) subtreeRoot->getInstruction())->getSuccessor(1));
1290 mvec[numInstr++] = new MachineInstr(NOP);
1294 case 9: // stmt: Switch(reg)
1295 assert(0 && "*** SWITCH instruction is not implemented yet.");
1299 case 10: // reg: VRegList(reg, reg)
1300 assert(0 && "VRegList should never be the topmost non-chain rule");
1303 case 21: // reg: Not(reg): Implemented as reg = reg XOR-NOT 0
1304 mvec[0] = new MachineInstr(XNOR);
1305 mvec[0]->SetMachineOperand(0, MachineOperand::MO_VirtualRegister,
1306 subtreeRoot->leftChild()->getValue());
1307 mvec[0]->SetMachineOperand(1, target.getRegInfo().getZeroRegNum());
1308 mvec[0]->SetMachineOperand(2, MachineOperand::MO_VirtualRegister,
1309 subtreeRoot->getValue());
1312 case 322: // reg: ToBoolTy(bool):
1313 case 22: // reg: ToBoolTy(reg):
1314 opType = subtreeRoot->leftChild()->getValue()->getType();
1315 assert(opType->isIntegral() || opType == Type::BoolTy);
1317 forwardOperandNum = 0;
1320 case 23: // reg: ToUByteTy(reg)
1321 case 25: // reg: ToUShortTy(reg)
1322 case 27: // reg: ToUIntTy(reg)
1323 case 29: // reg: ToULongTy(reg)
1324 opType = subtreeRoot->leftChild()->getValue()->getType();
1325 assert(opType->isIntegral() ||
1326 opType->isPointerType() ||
1327 opType == Type::BoolTy && "Cast is illegal for other types");
1329 forwardOperandNum = 0;
1332 case 24: // reg: ToSByteTy(reg)
1333 case 26: // reg: ToShortTy(reg)
1334 case 28: // reg: ToIntTy(reg)
1335 case 30: // reg: ToLongTy(reg)
1336 opType = subtreeRoot->leftChild()->getValue()->getType();
1337 if (opType->isIntegral() || opType == Type::BoolTy)
1340 forwardOperandNum = 0;
1344 mvec[0] = new MachineInstr(ChooseConvertToIntInstr(subtreeRoot,
1346 Set2OperandsFromInstr(mvec[0], subtreeRoot, target);
1350 case 31: // reg: ToFloatTy(reg):
1351 case 32: // reg: ToDoubleTy(reg):
1352 case 232: // reg: ToDoubleTy(Constant):
1354 // If this instruction has a parent (a user) in the tree
1355 // and the user is translated as an FsMULd instruction,
1356 // then the cast is unnecessary. So check that first.
1357 // In the future, we'll want to do the same for the FdMULq instruction,
1358 // so do the check here instead of only for ToFloatTy(reg).
1360 if (subtreeRoot->parent() != NULL &&
1361 ((InstructionNode*) subtreeRoot->parent())->getInstruction()->getMachineInstrVec()[0]->getOpCode() == FSMULD)
1364 forwardOperandNum = 0;
1368 opType = subtreeRoot->leftChild()->getValue()->getType();
1369 MachineOpCode opCode=ChooseConvertToFloatInstr(subtreeRoot,opType);
1370 if (opCode == INVALID_OPCODE) // no conversion needed
1373 forwardOperandNum = 0;
1377 mvec[0] = new MachineInstr(opCode);
1378 Set2OperandsFromInstr(mvec[0], subtreeRoot, target);
1383 case 19: // reg: ToArrayTy(reg):
1384 case 20: // reg: ToPointerTy(reg):
1386 forwardOperandNum = 0;
1389 case 233: // reg: Add(reg, Constant)
1390 mvec[0] = CreateAddConstInstruction(subtreeRoot);
1391 if (mvec[0] != NULL)
1393 // ELSE FALL THROUGH
1395 case 33: // reg: Add(reg, reg)
1396 mvec[0] = new MachineInstr(ChooseAddInstruction(subtreeRoot));
1397 Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
1400 case 234: // reg: Sub(reg, Constant)
1401 mvec[0] = CreateSubConstInstruction(subtreeRoot);
1402 if (mvec[0] != NULL)
1404 // ELSE FALL THROUGH
1406 case 34: // reg: Sub(reg, reg)
1407 mvec[0] = new MachineInstr(ChooseSubInstruction(subtreeRoot));
1408 Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
1411 case 135: // reg: Mul(todouble, todouble)
1415 case 35: // reg: Mul(reg, reg)
1416 mvec[0] =new MachineInstr(ChooseMulInstruction(subtreeRoot,checkCast));
1417 Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
1420 case 335: // reg: Mul(todouble, todoubleConst)
1424 case 235: // reg: Mul(reg, Constant)
1425 mvec[0] = CreateMulConstInstruction(target, subtreeRoot, mvec[1]);
1426 if (mvec[0] == NULL)
1428 mvec[0] = new MachineInstr(ChooseMulInstruction(subtreeRoot,
1430 Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
1433 if (mvec[1] != NULL)
1437 case 236: // reg: Div(reg, Constant)
1438 mvec[0] = CreateDivConstInstruction(target, subtreeRoot, mvec[1]);
1439 if (mvec[0] != NULL)
1441 if (mvec[1] != NULL)
1445 // ELSE FALL THROUGH
1447 case 36: // reg: Div(reg, reg)
1448 mvec[0] = new MachineInstr(ChooseDivInstruction(target, subtreeRoot));
1449 Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
1452 case 37: // reg: Rem(reg, reg)
1453 case 237: // reg: Rem(reg, Constant)
1454 assert(0 && "REM instruction unimplemented for the SPARC.");
1457 case 38: // reg: And(reg, reg)
1458 case 238: // reg: And(reg, Constant)
1459 mvec[0] = new MachineInstr(AND);
1460 Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
1463 case 138: // reg: And(reg, not)
1464 mvec[0] = new MachineInstr(ANDN);
1465 Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
1468 case 39: // reg: Or(reg, reg)
1469 case 239: // reg: Or(reg, Constant)
1470 mvec[0] = new MachineInstr(ORN);
1471 Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
1474 case 139: // reg: Or(reg, not)
1475 mvec[0] = new MachineInstr(ORN);
1476 Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
1479 case 40: // reg: Xor(reg, reg)
1480 case 240: // reg: Xor(reg, Constant)
1481 mvec[0] = new MachineInstr(XOR);
1482 Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
1485 case 140: // reg: Xor(reg, not)
1486 mvec[0] = new MachineInstr(XNOR);
1487 Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
1490 case 41: // boolconst: SetCC(reg, Constant)
1491 // Check if this is an integer comparison, and
1492 // there is a parent, and the parent decided to use
1493 // a branch-on-integer-register instead of branch-on-condition-code.
1494 // If so, the SUBcc instruction is not required.
1495 // (However, we must still check for constants to be loaded from
1496 // the constant pool so that such a load can be associated with
1497 // this instruction.)
1499 // Otherwise this is just the same as case 42, so just fall through.
1501 if (subtreeRoot->leftChild()->getValue()->getType()->isIntegral() &&
1502 subtreeRoot->parent() != NULL)
1504 InstructionNode* parent = (InstructionNode*) subtreeRoot->parent();
1505 assert(parent->getNodeType() == InstrTreeNode::NTInstructionNode);
1506 const vector<MachineInstr*>&
1507 minstrVec = parent->getInstruction()->getMachineInstrVec();
1508 MachineOpCode parentOpCode;
1509 if (parent->getInstruction()->getOpcode() == Instruction::Br &&
1510 (parentOpCode = minstrVec[0]->getOpCode()) >= BRZ &&
1511 parentOpCode <= BRGEZ)
1513 numInstr = 0; // don't forward the operand!
1517 // ELSE FALL THROUGH
1519 case 42: // bool: SetCC(reg, reg):
1521 // If result of the SetCC is only used for a single branch, we can
1522 // discard the result. Otherwise, the boolean value must go into
1523 // an integer register.
1525 bool keepBoolVal = (subtreeRoot->parent() == NULL ||
1526 ((InstructionNode*) subtreeRoot->parent())
1527 ->getInstruction()->getOpcode() !=Instruction::Br);
1528 bool subValIsBoolVal =
1529 subtreeRoot->getInstruction()->getOpcode() == Instruction::SetNE;
1530 bool keepSubVal = keepBoolVal && subValIsBoolVal;
1531 bool computeBoolVal = keepBoolVal && ! subValIsBoolVal;
1535 MachineOpCode movOpCode;
1537 if (subtreeRoot->leftChild()->getValue()->getType()->isIntegral() ||
1538 subtreeRoot->leftChild()->getValue()->getType()->isPointerType())
1540 // Integer condition: dest. should be %g0 or an integer register.
1541 // If result must be saved but condition is not SetEQ then we need
1542 // a separate instruction to compute the bool result, so discard
1543 // result of SUBcc instruction anyway.
1545 mvec[0] = new MachineInstr(SUBcc);
1546 Set3OperandsFromInstr(mvec[0], subtreeRoot, target, ! keepSubVal);
1548 // mark the 4th operand as being a CC register, and a "result"
1549 mvec[0]->SetMachineOperand(3, MachineOperand::MO_CCRegister,
1550 subtreeRoot->getValue(),/*def*/true);
1553 { // recompute bool using the integer condition codes
1555 ChooseMovpccAfterSub(subtreeRoot,mustClearReg,valueToMove);
1560 // FP condition: dest of FCMP should be some FCCn register
1561 mvec[0] = new MachineInstr(ChooseFcmpInstruction(subtreeRoot));
1562 mvec[0]->SetMachineOperand(0,MachineOperand::MO_CCRegister,
1563 subtreeRoot->getValue());
1564 mvec[0]->SetMachineOperand(1,MachineOperand::MO_VirtualRegister,
1565 subtreeRoot->leftChild()->getValue());
1566 mvec[0]->SetMachineOperand(2,MachineOperand::MO_VirtualRegister,
1567 subtreeRoot->rightChild()->getValue());
1570 {// recompute bool using the FP condition codes
1571 mustClearReg = true;
1573 movOpCode = ChooseMovFpccInstruction(subtreeRoot);
1580 {// Unconditionally set register to 0
1582 mvec[n] = new MachineInstr(SETHI);
1583 mvec[n]->SetMachineOperand(0,MachineOperand::MO_UnextendedImmed,
1585 mvec[n]->SetMachineOperand(1,MachineOperand::MO_VirtualRegister,
1586 subtreeRoot->getValue());
1589 // Now conditionally move `valueToMove' (0 or 1) into the register
1591 mvec[n] = new MachineInstr(movOpCode);
1592 mvec[n]->SetMachineOperand(0, MachineOperand::MO_CCRegister,
1593 subtreeRoot->getValue());
1594 mvec[n]->SetMachineOperand(1, MachineOperand::MO_UnextendedImmed,
1596 mvec[n]->SetMachineOperand(2, MachineOperand::MO_VirtualRegister,
1597 subtreeRoot->getValue());
1602 case 43: // boolreg: VReg
1603 case 44: // boolreg: Constant
1607 case 51: // reg: Load(reg)
1608 case 52: // reg: Load(ptrreg)
1609 case 53: // reg: LoadIdx(reg,reg)
1610 case 54: // reg: LoadIdx(ptrreg,reg)
1611 mvec[0] = new MachineInstr(ChooseLoadInstruction(
1612 subtreeRoot->getValue()->getType()));
1613 SetOperandsForMemInstr(mvec[0], subtreeRoot, target);
1616 case 55: // reg: GetElemPtr(reg)
1617 case 56: // reg: GetElemPtrIdx(reg,reg)
1618 if (subtreeRoot->parent() != NULL)
1620 // Check if the parent was an array access.
1621 // If so, we still need to generate this instruction.
1622 MemAccessInst* memInst = (MemAccessInst*)
1623 subtreeRoot->getInstruction();
1624 const PointerType* ptrType =
1625 (const PointerType*) memInst->getPtrOperand()->getType();
1626 if (! ptrType->getValueType()->isArrayType())
1627 {// we don't need a separate instr
1628 numInstr = 0; // don't forward operand!
1632 // else in all other cases we need to a separate ADD instruction
1633 mvec[0] = new MachineInstr(ADD);
1634 SetOperandsForMemInstr(mvec[0], subtreeRoot, target);
1637 case 57: // reg: Alloca: Implement as 1 instruction:
1638 { // add %fp, offsetFromFP -> result
1639 Instruction* instr = subtreeRoot->getInstruction();
1640 const PointerType* instrType = (const PointerType*) instr->getType();
1641 assert(instrType->isPointerType());
1643 target.findOptimalStorageSize(instrType->getValueType());
1644 assert(tsize != 0 && "Just to check when this can happen");
1646 Method* method = instr->getParent()->getParent();
1647 MachineCodeForMethod& mcode = method->getMachineCode();
1649 target.getFrameInfo().getFirstAutomaticVarOffsetFromFP(method)
1650 - (tsize + mcode.getAutomaticVarsSize());
1652 mcode.putLocalVarAtOffsetFromFP(instr, offsetFromFP, tsize);
1654 // Create a temporary Value to hold the constant offset.
1655 // This is needed because it may not fit in the immediate field.
1656 ConstPoolSInt* offsetVal=ConstPoolSInt::get(Type::IntTy, offsetFromFP);
1658 // Instruction 1: add %fp, offsetFromFP -> result
1659 mvec[0] = new MachineInstr(ADD);
1660 mvec[0]->SetMachineOperand(0, target.getRegInfo().getFramePointer());
1661 mvec[0]->SetMachineOperand(1, MachineOperand::MO_VirtualRegister,
1663 mvec[0]->SetMachineOperand(2, MachineOperand::MO_VirtualRegister,
1668 case 58: // reg: Alloca(reg): Implement as 3 instructions:
1669 // mul num, typeSz -> tmp
1670 // sub %sp, tmp -> %sp
1671 { // add %sp, frameSizeBelowDynamicArea -> result
1672 Instruction* instr = subtreeRoot->getInstruction();
1673 const PointerType* instrType = (const PointerType*) instr->getType();
1674 assert(instrType->isPointerType() &&
1675 instrType->getValueType()->isArrayType());
1676 const Type* eltType =
1677 ((ArrayType*) instrType->getValueType())->getElementType();
1678 int tsize = (int) target.findOptimalStorageSize(eltType);
1680 assert(tsize != 0 && "Just to check when this can happen");
1682 // Create a temporary Value to hold the constant type-size
1683 ConstPoolSInt* tsizeVal = ConstPoolSInt::get(Type::IntTy, tsize);
1685 // Create a temporary Value to hold the constant offset from SP
1686 Method* method = instr->getParent()->getParent();
1687 MachineCodeForMethod& mcode = method->getMachineCode();
1688 int frameSizeBelowDynamicArea =
1689 target.getFrameInfo().getFrameSizeBelowDynamicArea(method);
1690 ConstPoolSInt* lowerAreaSizeVal = ConstPoolSInt::get(Type::IntTy,
1691 frameSizeBelowDynamicArea);
1692 cerr << "***" << endl
1693 << "*** Variable-size ALLOCA operation needs more work:" << endl
1694 << "*** We have to precompute the size of "
1695 << " optional arguments in the stack frame" << endl
1697 assert(0 && "SEE MESSAGE ABOVE");
1699 // Create a temporary value to hold `tmp'
1700 Instruction* tmpInstr = new TmpInstruction(TMP_INSTRUCTION_OPCODE,
1701 subtreeRoot->leftChild()->getValue(),
1702 NULL /*could insert tsize here*/);
1703 subtreeRoot->getInstruction()->getMachineInstrVec().addTempValue(tmpInstr);
1705 // Instruction 1: mul numElements, typeSize -> tmp
1706 mvec[0] = new MachineInstr(MULX);
1707 mvec[0]->SetMachineOperand(0, MachineOperand::MO_VirtualRegister,
1708 subtreeRoot->leftChild()->getValue());
1709 mvec[0]->SetMachineOperand(1, MachineOperand::MO_VirtualRegister,
1711 mvec[0]->SetMachineOperand(2, MachineOperand::MO_VirtualRegister,
1714 // Instruction 2: sub %sp, tmp -> %sp
1716 mvec[1] = new MachineInstr(SUB);
1717 mvec[1]->SetMachineOperand(0, target.getRegInfo().getStackPointer());
1718 mvec[1]->SetMachineOperand(1, MachineOperand::MO_VirtualRegister,
1720 mvec[1]->SetMachineOperand(2, target.getRegInfo().getStackPointer());
1722 // Instruction 3: add %sp, frameSizeBelowDynamicArea -> result
1724 mvec[2] = new MachineInstr(ADD);
1725 mvec[2]->SetMachineOperand(0, target.getRegInfo().getStackPointer());
1726 mvec[2]->SetMachineOperand(1, MachineOperand::MO_VirtualRegister,
1728 mvec[2]->SetMachineOperand(2,MachineOperand::MO_VirtualRegister,instr);
1732 case 61: // reg: Call
1733 // Generate a call-indirect (i.e., jmpl) for now to expose
1734 // the potential need for registers. If an absolute address
1735 // is available, replace this with a CALL instruction.
1736 // Mark both the indirection register and the return-address
1737 // register as hidden virtual registers.
1738 // Also, mark the operands of the Call and return value (if
1739 // any) as implicit operands of the CALL machine instruction.
1741 CallInst *callInstr = cast<CallInst>(subtreeRoot->getInstruction());
1742 Value *callee = callInstr->getCalledValue();
1744 Instruction* retAddrReg = new TmpInstruction(TMP_INSTRUCTION_OPCODE,
1747 // Note temporary values in the machineInstrVec for the VM instr.
1749 // WARNING: Operands 0..N-1 must go in slots 0..N-1 of implicitUses.
1750 // The result value must go in slot N. This is assumed
1751 // in register allocation.
1753 callInstr->getMachineInstrVec().addTempValue(retAddrReg);
1756 // Generate the machine instruction and its operands.
1757 // Use CALL for direct function calls; this optimistically assumes
1758 // the PC-relative address fits in the CALL address field (22 bits).
1759 // Use JMPL for indirect calls.
1761 if (callee->getValueType() == Value::MethodVal)
1762 { // direct function call
1763 mvec[0] = new MachineInstr(CALL);
1764 mvec[0]->SetMachineOperand(0, MachineOperand::MO_PCRelativeDisp,
1768 { // indirect function call
1769 mvec[0] = new MachineInstr(JMPLCALL);
1770 mvec[0]->SetMachineOperand(0, MachineOperand::MO_VirtualRegister,
1772 mvec[0]->SetMachineOperand(1, MachineOperand::MO_SignExtendedImmed,
1774 mvec[0]->SetMachineOperand(2, MachineOperand::MO_VirtualRegister,
1778 // Add the call operands and return value as implicit refs
1779 for (unsigned i=0, N=callInstr->getNumOperands(); i < N; ++i)
1780 if (callInstr->getOperand(i) != callee)
1781 mvec[0]->addImplicitRef(callInstr->getOperand(i));
1783 if (callInstr->getType() != Type::VoidTy)
1784 mvec[0]->addImplicitRef(callInstr, /*isDef*/ true);
1786 // For the CALL instruction, the ret. addr. reg. is also implicit
1787 if (callee->getValueType() == Value::MethodVal)
1788 mvec[0]->addImplicitRef(retAddrReg, /*isDef*/ true);
1790 mvec[numInstr++] = new MachineInstr(NOP); // delay slot
1794 case 62: // reg: Shl(reg, reg)
1795 opType = subtreeRoot->leftChild()->getValue()->getType();
1796 assert(opType->isIntegral()
1797 || opType == Type::BoolTy
1798 || opType->isPointerType()&& "Shl unsupported for other types");
1799 mvec[0] = new MachineInstr((opType == Type::LongTy)? SLLX : SLL);
1800 Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
1803 case 63: // reg: Shr(reg, reg)
1804 opType = subtreeRoot->leftChild()->getValue()->getType();
1805 assert(opType->isIntegral()
1806 || opType == Type::BoolTy
1807 || opType->isPointerType() &&"Shr unsupported for other types");
1808 mvec[0] = new MachineInstr((opType->isSigned()
1809 ? ((opType == Type::LongTy)? SRAX : SRA)
1810 : ((opType == Type::LongTy)? SRLX : SRL)));
1811 Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
1814 case 64: // reg: Phi(reg,reg)
1815 { // This instruction has variable #operands, so resultPos is 0.
1816 Instruction* phi = subtreeRoot->getInstruction();
1817 mvec[0] = new MachineInstr(PHI, 1 + phi->getNumOperands());
1818 mvec[0]->SetMachineOperand(0, MachineOperand::MO_VirtualRegister,
1819 subtreeRoot->getValue());
1820 for (unsigned i=0, N=phi->getNumOperands(); i < N; i++)
1821 mvec[0]->SetMachineOperand(i+1, MachineOperand::MO_VirtualRegister,
1822 phi->getOperand(i));
1825 case 71: // reg: VReg
1826 case 72: // reg: Constant
1827 numInstr = 0; // don't forward the value
1831 assert(0 && "Unrecognized BURG rule");
1837 if (forwardOperandNum >= 0)
1838 { // We did not generate a machine instruction but need to use operand.
1839 // If user is in the same tree, replace Value in its machine operand.
1840 // If not, insert a copy instruction which should get coalesced away
1841 // by register allocation.
1842 if (subtreeRoot->parent() != NULL)
1843 ForwardOperand(subtreeRoot, subtreeRoot->parent(), forwardOperandNum);
1846 vector<MachineInstr*> minstrVec;
1847 CreateCopyInstructionsByType(target,
1848 subtreeRoot->getInstruction()->getOperand(forwardOperandNum),
1849 subtreeRoot->getInstruction(), minstrVec);
1850 assert(minstrVec.size() > 0);
1851 for (unsigned i=0; i < minstrVec.size(); ++i)
1852 mvec[numInstr++] = minstrVec[i];