1 //===-- MSchedGraphSB.cpp - Scheduling Graph ----------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // A graph class for dependencies. This graph only contains true, anti, and
11 // output data dependencies for a given MachineBasicBlock. Dependencies
12 // across iterations are also computed. Unless data dependence analysis
13 // is provided, a conservative approach of adding dependencies between all
14 // loads and stores is taken.
15 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "ModuloSchedSB"
18 #include "MSchedGraphSB.h"
19 #include "../SparcV9RegisterInfo.h"
20 #include "../MachineCodeForInstruction.h"
21 #include "llvm/BasicBlock.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Instructions.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/MachineBasicBlock.h"
26 #include "llvm/Target/TargetInstrInfo.h"
27 #include "llvm/Support/Debug.h"
31 #include "llvm/Target/TargetSchedInfo.h"
32 #include "../SparcV9Internals.h"
36 //MSchedGraphSBNode constructor
37 MSchedGraphSBNode::MSchedGraphSBNode(const MachineInstr* inst,
38 MSchedGraphSB *graph, unsigned idx,
39 unsigned late, bool isBranch)
40 : Inst(inst), Parent(graph), index(idx), latency(late),
41 isBranchInstr(isBranch) {
44 graph->addNode(inst, this);
47 //MSchedGraphSBNode constructor
48 MSchedGraphSBNode::MSchedGraphSBNode(const MachineInstr* inst,
49 std::vector<const MachineInstr*> &other,
50 MSchedGraphSB *graph, unsigned idx,
51 unsigned late, bool isPNode)
52 : Inst(inst), otherInstrs(other), Parent(graph), index(idx), latency(late), isPredicateNode(isPNode) {
55 isBranchInstr = false;
58 graph->addNode(inst, this);
61 //MSchedGraphSBNode copy constructor
62 MSchedGraphSBNode::MSchedGraphSBNode(const MSchedGraphSBNode &N)
63 : Predecessors(N.Predecessors), Successors(N.Successors) {
69 isBranchInstr = N.isBranchInstr;
70 otherInstrs = N.otherInstrs;
73 //Print the node (instruction and latency)
74 void MSchedGraphSBNode::print(std::ostream &os) const {
76 os << "MSchedGraphSBNode: Inst=" << *Inst << ", latency= " << latency << "\n";
82 //Get the edge from a predecessor to this node
83 MSchedGraphSBEdge MSchedGraphSBNode::getInEdge(MSchedGraphSBNode *pred) {
84 //Loop over all the successors of our predecessor
85 //return the edge the corresponds to this in edge
86 for (MSchedGraphSBNode::succ_iterator I = pred->succ_begin(),
87 E = pred->succ_end(); I != E; ++I) {
91 assert(0 && "Should have found edge between this node and its predecessor!");
95 //Get the iteration difference for the edge from this node to its successor
96 unsigned MSchedGraphSBNode::getIteDiff(MSchedGraphSBNode *succ) {
97 for(std::vector<MSchedGraphSBEdge>::iterator I = Successors.begin(),
100 if(I->getDest() == succ)
101 return I->getIteDiff();
106 //Get the index into the vector of edges for the edge from pred to this node
107 unsigned MSchedGraphSBNode::getInEdgeNum(MSchedGraphSBNode *pred) {
108 //Loop over all the successors of our predecessor
109 //return the edge the corresponds to this in edge
111 for(MSchedGraphSBNode::succ_iterator I = pred->succ_begin(),
112 E = pred->succ_end();
118 assert(0 && "Should have found edge between this node and its predecessor!");
122 //Determine if succ is a successor of this node
123 bool MSchedGraphSBNode::isSuccessor(MSchedGraphSBNode *succ) {
124 for(succ_iterator I = succ_begin(), E = succ_end(); I != E; ++I)
130 //Dtermine if pred is a predecessor of this node
131 bool MSchedGraphSBNode::isPredecessor(MSchedGraphSBNode *pred) {
132 if(std::find( Predecessors.begin(), Predecessors.end(),
133 pred) != Predecessors.end())
139 //Add a node to the graph
140 void MSchedGraphSB::addNode(const MachineInstr* MI,
141 MSchedGraphSBNode *node) {
143 //Make sure node does not already exist
144 assert(GraphMap.find(MI) == GraphMap.end()
145 && "New MSchedGraphSBNode already exists for this instruction");
150 //Delete a node to the graph
151 void MSchedGraphSB::deleteNode(MSchedGraphSBNode *node) {
153 //Delete the edge to this node from all predecessors
154 while(node->pred_size() > 0) {
155 //DEBUG(std::cerr << "Delete edge from: " << **P << " to " << *node << "\n");
156 MSchedGraphSBNode *pred = *(node->pred_begin());
157 pred->deleteSuccessor(node);
160 //Remove this node from the graph
161 GraphMap.erase(node->getInst());
166 //Create a graph for a machine block. The ignoreInstrs map is so that
167 //we ignore instructions associated to the index variable since this
168 //is a special case in Modulo Scheduling. We only want to deal with
169 //the body of the loop.
170 MSchedGraphSB::MSchedGraphSB(std::vector<const MachineBasicBlock*> &bbs,
171 const TargetMachine &targ,
172 std::map<const MachineInstr*, unsigned> &ignoreInstrs,
173 DependenceAnalyzer &DA,
174 std::map<MachineInstr*, Instruction*> &machineTollvm)
175 : BBs(bbs), Target(targ) {
177 //Make sure there is at least one BB and it is not null,
178 assert(((bbs.size() >= 1) && bbs[1] != NULL) && "Basic Block is null");
180 std::map<MSchedGraphSBNode*, std::set<MachineInstr*> > liveOutsideTrace;
181 std::set<const BasicBlock*> llvmBBs;
183 for(std::vector<const MachineBasicBlock*>::iterator MBB = bbs.begin(), ME = bbs.end()-1;
185 llvmBBs.insert((*MBB)->getBasicBlock());
187 //create predicate nodes
188 DEBUG(std::cerr << "Create predicate nodes\n");
189 for(std::vector<const MachineBasicBlock*>::iterator MBB = bbs.begin(), ME = bbs.end()-1;
191 //Get LLVM basic block
192 BasicBlock *BB = (BasicBlock*) (*MBB)->getBasicBlock();
195 BranchInst *b = dyn_cast<BranchInst>(BB->getTerminator());
197 std::vector<const MachineInstr*> otherInstrs;
198 MachineInstr *instr = 0;
200 //Get the condition for the branch (we already checked if it was conditional)
201 if(b->isConditional()) {
203 Value *cond = b->getCondition();
205 DEBUG(std::cerr << "Condition: " << *cond << "\n");
207 assert(cond && "Condition must not be null!");
209 if(Instruction *I = dyn_cast<Instruction>(cond)) {
210 MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(I);
211 if(tempMvec.size() > 0) {
212 DEBUG(std::cerr << *(tempMvec[tempMvec.size()-1]) << "\n");;
213 instr = (MachineInstr*) tempMvec[tempMvec.size()-1];
218 //Get Machine target information for calculating latency
219 const TargetInstrInfo *MTI = Target.getInstrInfo();
221 MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(b);
222 int offset = tempMvec.size();
223 for (unsigned j = 0; j < tempMvec.size(); j++) {
224 MachineInstr *mi = tempMvec[j];
225 if(MTI->isNop(mi->getOpcode()))
230 DEBUG(std::cerr << "No Cond MI: " << *mi << "\n");
233 DEBUG(std::cerr << *mi << "\n");;
234 otherInstrs.push_back(mi);
238 //Node is created and added to the graph automatically
239 MSchedGraphSBNode *node = new MSchedGraphSBNode(instr, otherInstrs, this, (*MBB)->size()-offset-1, 3, true);
241 DEBUG(std::cerr << "Created Node: " << *node << "\n");
243 //Now loop over all instructions and see if their def is live outside the trace
244 MachineBasicBlock *mb = (MachineBasicBlock*) *MBB;
245 for(MachineBasicBlock::iterator I = mb->begin(), E = mb->end(); I != E; ++I) {
246 MachineInstr *instr = I;
247 if(MTI->isNop(instr->getOpcode()) || MTI->isBranch(instr->getOpcode()))
249 if(node->getInst() == instr)
252 for(unsigned i=0; i < instr->getNumOperands(); ++i) {
253 MachineOperand &mOp = instr->getOperand(i);
254 if(mOp.isDef() && mOp.getType() == MachineOperand::MO_VirtualRegister) {
255 Value *val = mOp.getVRegValue();
256 //Check if there is a use not in the trace
257 for(Value::use_iterator V = val->use_begin(), VE = val->use_end(); V != VE; ++V) {
258 if (Instruction *Inst = dyn_cast<Instruction>(*V)) {
259 if(llvmBBs.count(Inst->getParent()))
260 liveOutsideTrace[node].insert(instr);
270 //Create nodes and edges for this BB
271 buildNodesAndEdges(ignoreInstrs, DA, machineTollvm, liveOutsideTrace);
276 //Copies the graph and keeps a map from old to new nodes
277 MSchedGraphSB::MSchedGraphSB(const MSchedGraphSB &G,
278 std::map<MSchedGraphSBNode*, MSchedGraphSBNode*> &newNodes)
283 std::map<MSchedGraphSBNode*, MSchedGraphSBNode*> oldToNew;
285 for(MSchedGraphSB::const_iterator N = G.GraphMap.begin(),
286 NE = G.GraphMap.end(); N != NE; ++N) {
288 MSchedGraphSBNode *newNode = new MSchedGraphSBNode(*(N->second));
289 oldToNew[&*(N->second)] = newNode;
290 newNodes[newNode] = &*(N->second);
291 GraphMap[&*(N->first)] = newNode;
294 //Loop over nodes and update edges to point to new nodes
295 for(MSchedGraphSB::iterator N = GraphMap.begin(), NE = GraphMap.end();
298 //Get the node we are dealing with
299 MSchedGraphSBNode *node = &*(N->second);
301 node->setParent(this);
303 //Loop over nodes successors and predecessors and update to the new nodes
304 for(unsigned i = 0; i < node->pred_size(); ++i) {
305 node->setPredecessor(i, oldToNew[node->getPredecessor(i)]);
308 for(unsigned i = 0; i < node->succ_size(); ++i) {
309 MSchedGraphSBEdge *edge = node->getSuccessor(i);
310 MSchedGraphSBNode *oldDest = edge->getDest();
311 edge->setDest(oldToNew[oldDest]);
316 //Deconstructor, deletes all nodes in the graph
317 MSchedGraphSB::~MSchedGraphSB () {
318 for(MSchedGraphSB::iterator I = GraphMap.begin(), E = GraphMap.end();
324 void MSchedGraphSB::print(std::ostream &os) const {
325 for(MSchedGraphSB::const_iterator N = GraphMap.begin(), NE = GraphMap.end();
328 //Get the node we are dealing with
329 MSchedGraphSBNode *node = &*(N->second);
331 os << "Node Start\n";
333 os << "Successors:\n";
335 for(unsigned i = 0; i < node->succ_size(); ++i) {
336 MSchedGraphSBEdge *edge = node->getSuccessor(i);
337 MSchedGraphSBNode *oldDest = edge->getDest();
344 //Calculate total delay
345 int MSchedGraphSB::totalDelay() {
348 for(MSchedGraphSB::const_iterator N = GraphMap.begin(), NE = GraphMap.end();
351 //Get the node we are dealing with
352 MSchedGraphSBNode *node = &*(N->second);
353 sum += node->getLatency();
358 bool MSchedGraphSB::instrCauseException(MachineOpCode opCode) {
359 //Check for integer divide
360 if(opCode == V9::SDIVXr || opCode == V9::SDIVXi
361 || opCode == V9::UDIVXr || opCode == V9::UDIVXi)
364 //Check for loads or stores
365 const TargetInstrInfo *MTI = Target.getInstrInfo();
366 //if( MTI->isLoad(opCode) ||
367 if(MTI->isStore(opCode))
370 //Check for any floating point operation
371 const TargetSchedInfo *msi = Target.getSchedInfo();
372 InstrSchedClass sc = msi->getSchedClass(opCode);
374 //FIXME: Should check for floating point instructions!
375 //if(sc == SPARC_FGA || sc == SPARC_FGM)
382 //Add edges between the nodes
383 void MSchedGraphSB::buildNodesAndEdges(std::map<const MachineInstr*, unsigned> &ignoreInstrs,
384 DependenceAnalyzer &DA,
385 std::map<MachineInstr*, Instruction*> &machineTollvm,
386 std::map<MSchedGraphSBNode*, std::set<MachineInstr*> > &liveOutsideTrace) {
389 //Get Machine target information for calculating latency
390 const TargetInstrInfo *MTI = Target.getInstrInfo();
392 std::vector<MSchedGraphSBNode*> memInstructions;
393 std::map<int, std::vector<OpIndexNodePair> > regNumtoNodeMap;
394 std::map<const Value*, std::vector<OpIndexNodePair> > valuetoNodeMap;
396 //Save PHI instructions to deal with later
397 std::vector<const MachineInstr*> phiInstrs;
400 MSchedGraphSBNode *lastPred = 0;
403 for(std::vector<const MachineBasicBlock*>::iterator B = BBs.begin(),
404 BE = BBs.end(); B != BE; ++B) {
406 const MachineBasicBlock *BB = *B;
409 //Loop over instructions in MBB and add nodes and edges
410 for (MachineBasicBlock::const_iterator MI = BB->begin(), e = BB->end();
413 //Ignore indvar instructions
414 if(ignoreInstrs.count(MI)) {
419 //Get each instruction of machine basic block, get the delay
420 //using the op code, create a new node for it, and add to the
423 MachineOpCode opCode = MI->getOpcode();
427 delay = MTI->maxLatency(opCode);
429 //Create new node for this machine instruction and add to the graph.
430 //Create only if not a nop
431 if(MTI->isNop(opCode))
434 //Sparc BE does not use PHI opcode, so assert on this case
435 assert(opCode != TargetInstrInfo::PHI && "Did not expect PHI opcode");
437 bool isBranch = false;
440 if(MTI->isBranch(opCode))
443 //Node is created and added to the graph automatically
444 MSchedGraphSBNode *node = 0;
445 if(!GraphMap.count(MI)){
446 node = new MSchedGraphSBNode(MI, this, index, delay);
447 DEBUG(std::cerr << "Created Node: " << *node << "\n");
451 if(node->isPredicate()) {
452 //Create edge between this node and last pred, then switch to new pred
454 lastPred->addOutEdge(node, MSchedGraphSBEdge::PredDep,
455 MSchedGraphSBEdge::NonDataDep, 0);
457 if(liveOutsideTrace.count(lastPred)) {
458 for(std::set<MachineInstr*>::iterator L = liveOutsideTrace[lastPred].begin(), LE = liveOutsideTrace[lastPred].end(); L != LE; ++L)
459 lastPred->addOutEdge(GraphMap[*L], MSchedGraphSBEdge::PredDep,
460 MSchedGraphSBEdge::NonDataDep, 1);
469 //Add dependencies to instructions that cause exceptions
471 lastPred->print(std::cerr);
473 if(!node->isPredicate() && instrCauseException(opCode)) {
475 lastPred->addOutEdge(node, MSchedGraphSBEdge::PredDep,
476 MSchedGraphSBEdge::NonDataDep, 0);
481 //Check OpCode to keep track of memory operations to add memory
482 //dependencies later.
483 if(MTI->isLoad(opCode) || MTI->isStore(opCode))
484 memInstructions.push_back(node);
486 //Loop over all operands, and put them into the register number to
487 //graph node map for determining dependencies
488 //If an operands is a use/def, we have an anti dependence to itself
489 for(unsigned i=0; i < MI->getNumOperands(); ++i) {
491 const MachineOperand &mOp = MI->getOperand(i);
493 //Check if it has an allocated register
494 if(mOp.hasAllocatedReg()) {
495 int regNum = mOp.getReg();
497 if(regNum != SparcV9::g0) {
499 regNumtoNodeMap[regNum].push_back(std::make_pair(i, node));
505 //Add virtual registers dependencies
506 //Check if any exist in the value map already and create dependencies
508 if(mOp.getType() == MachineOperand::MO_VirtualRegister
509 || mOp.getType() == MachineOperand::MO_CCRegister) {
511 //Make sure virtual register value is not null
512 assert((mOp.getVRegValue() != NULL) && "Null value is defined");
514 //Check if this is a read operation in a phi node, if so DO NOT PROCESS
515 if(mOp.isUse() && (opCode == TargetInstrInfo::PHI)) {
516 DEBUG(std::cerr << "Read Operation in a PHI node\n");
520 if (const Value* srcI = mOp.getVRegValue()) {
522 //Find value in the map
523 std::map<const Value*, std::vector<OpIndexNodePair> >::iterator V
524 = valuetoNodeMap.find(srcI);
526 //If there is something in the map already, add edges from
528 //to this one we are processing
529 if(V != valuetoNodeMap.end()) {
530 addValueEdges(V->second, node, mOp.isUse(), mOp.isDef(), phiInstrs);
533 V->second.push_back(std::make_pair(i,node));
535 //Otherwise put it in the map
538 valuetoNodeMap[mOp.getVRegValue()].push_back(std::make_pair(i, node));
545 //Loop over LLVM BB, examine phi instructions, and add them to our
546 //phiInstr list to process
547 const BasicBlock *llvm_bb = BB->getBasicBlock();
548 for(BasicBlock::const_iterator I = llvm_bb->begin(), E = llvm_bb->end();
550 if(const PHINode *PN = dyn_cast<PHINode>(I)) {
551 MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(PN);
552 for (unsigned j = 0; j < tempMvec.size(); j++) {
553 if(!ignoreInstrs.count(tempMvec[j])) {
554 DEBUG(std::cerr << "Inserting phi instr into map: " << *tempMvec[j] << "\n");
555 phiInstrs.push_back((MachineInstr*) tempMvec[j]);
562 addMemEdges(memInstructions, DA, machineTollvm);
563 addMachRegEdges(regNumtoNodeMap);
565 //Finally deal with PHI Nodes and Value*
566 for(std::vector<const MachineInstr*>::iterator I = phiInstrs.begin(),
567 E = phiInstrs.end(); I != E; ++I) {
569 //Get Node for this instruction
570 std::map<const MachineInstr*, MSchedGraphSBNode*>::iterator X;
573 if(X == GraphMap.end())
576 MSchedGraphSBNode *node = X->second;
578 DEBUG(std::cerr << "Adding ite diff edges for node: " << *node << "\n");
580 //Loop over operands for this instruction and add value edges
581 for(unsigned i=0; i < (*I)->getNumOperands(); ++i) {
583 const MachineOperand &mOp = (*I)->getOperand(i);
584 if((mOp.getType() == MachineOperand::MO_VirtualRegister
585 || mOp.getType() == MachineOperand::MO_CCRegister) && mOp.isUse()) {
587 //find the value in the map
588 if (const Value* srcI = mOp.getVRegValue()) {
590 //Find value in the map
591 std::map<const Value*, std::vector<OpIndexNodePair> >::iterator V
592 = valuetoNodeMap.find(srcI);
594 //If there is something in the map already, add edges from
596 //to this one we are processing
597 if(V != valuetoNodeMap.end()) {
598 addValueEdges(V->second, node, mOp.isUse(), mOp.isDef(),
607 //Add dependencies for Value*s
608 void MSchedGraphSB::addValueEdges(std::vector<OpIndexNodePair> &NodesInMap,
609 MSchedGraphSBNode *destNode, bool nodeIsUse,
610 bool nodeIsDef, std::vector<const MachineInstr*> &phiInstrs, int diff) {
612 for(std::vector<OpIndexNodePair>::iterator I = NodesInMap.begin(),
613 E = NodesInMap.end(); I != E; ++I) {
615 //Get node in vectors machine operand that is the same value as node
616 MSchedGraphSBNode *srcNode = I->second;
617 MachineOperand mOp = srcNode->getInst()->getOperand(I->first);
620 if(std::find(phiInstrs.begin(), phiInstrs.end(), srcNode->getInst()) == phiInstrs.end())
623 //Node is a Def, so add output dep.
626 DEBUG(std::cerr << "Edge from " << *srcNode << " to " << *destNode << " (itediff=" << diff << ", type=anti)\n");
627 srcNode->addOutEdge(destNode, MSchedGraphSBEdge::ValueDep,
628 MSchedGraphSBEdge::AntiDep, diff);
631 DEBUG(std::cerr << "Edge from " << *srcNode << " to " << *destNode << " (itediff=" << diff << ", type=output)\n");
632 srcNode->addOutEdge(destNode, MSchedGraphSBEdge::ValueDep,
633 MSchedGraphSBEdge::OutputDep, diff);
638 DEBUG(std::cerr << "Edge from " << *srcNode << " to " << *destNode << " (itediff=" << diff << ", type=true)\n");
639 srcNode->addOutEdge(destNode, MSchedGraphSBEdge::ValueDep,
640 MSchedGraphSBEdge::TrueDep, diff);
646 //Add dependencies for machine registers across iterations
647 void MSchedGraphSB::addMachRegEdges(std::map<int, std::vector<OpIndexNodePair> >& regNumtoNodeMap) {
648 //Loop over all machine registers in the map, and add dependencies
649 //between the instructions that use it
650 typedef std::map<int, std::vector<OpIndexNodePair> > regNodeMap;
651 for(regNodeMap::iterator I = regNumtoNodeMap.begin();
652 I != regNumtoNodeMap.end(); ++I) {
653 //Get the register number
654 int regNum = (*I).first;
656 //Get Vector of nodes that use this register
657 std::vector<OpIndexNodePair> Nodes = (*I).second;
659 //Loop over nodes and determine the dependence between the other
660 //nodes in the vector
661 for(unsigned i =0; i < Nodes.size(); ++i) {
663 //Get src node operator index that uses this machine register
664 int srcOpIndex = Nodes[i].first;
666 //Get the actual src Node
667 MSchedGraphSBNode *srcNode = Nodes[i].second;
670 const MachineOperand &srcMOp = srcNode->getInst()->getOperand(srcOpIndex);
672 bool srcIsUseandDef = srcMOp.isDef() && srcMOp.isUse();
673 bool srcIsUse = srcMOp.isUse() && !srcMOp.isDef();
676 //Look at all instructions after this in execution order
677 for(unsigned j=i+1; j < Nodes.size(); ++j) {
679 //Sink node is a write
680 if(Nodes[j].second->getInst()->getOperand(Nodes[j].first).isDef()) {
681 //Src only uses the register (read)
683 srcNode->addOutEdge(Nodes[j].second,
684 MSchedGraphSBEdge::MachineRegister,
685 MSchedGraphSBEdge::AntiDep);
687 else if(srcIsUseandDef) {
688 srcNode->addOutEdge(Nodes[j].second,
689 MSchedGraphSBEdge::MachineRegister,
690 MSchedGraphSBEdge::AntiDep);
692 srcNode->addOutEdge(Nodes[j].second,
693 MSchedGraphSBEdge::MachineRegister,
694 MSchedGraphSBEdge::OutputDep);
697 srcNode->addOutEdge(Nodes[j].second,
698 MSchedGraphSBEdge::MachineRegister,
699 MSchedGraphSBEdge::OutputDep);
701 //Dest node is a read
703 if(!srcIsUse || srcIsUseandDef)
704 srcNode->addOutEdge(Nodes[j].second,
705 MSchedGraphSBEdge::MachineRegister,
706 MSchedGraphSBEdge::TrueDep);
711 //Look at all the instructions before this one since machine registers
712 //could live across iterations.
713 for(unsigned j = 0; j < i; ++j) {
714 //Sink node is a write
715 if(Nodes[j].second->getInst()->getOperand(Nodes[j].first).isDef()) {
716 //Src only uses the register (read)
718 srcNode->addOutEdge(Nodes[j].second,
719 MSchedGraphSBEdge::MachineRegister,
720 MSchedGraphSBEdge::AntiDep, 1);
721 else if(srcIsUseandDef) {
722 srcNode->addOutEdge(Nodes[j].second,
723 MSchedGraphSBEdge::MachineRegister,
724 MSchedGraphSBEdge::AntiDep, 1);
726 srcNode->addOutEdge(Nodes[j].second,
727 MSchedGraphSBEdge::MachineRegister,
728 MSchedGraphSBEdge::OutputDep, 1);
731 srcNode->addOutEdge(Nodes[j].second,
732 MSchedGraphSBEdge::MachineRegister,
733 MSchedGraphSBEdge::OutputDep, 1);
735 //Dest node is a read
737 if(!srcIsUse || srcIsUseandDef)
738 srcNode->addOutEdge(Nodes[j].second,
739 MSchedGraphSBEdge::MachineRegister,
740 MSchedGraphSBEdge::TrueDep,1 );
752 //Add edges between all loads and stores
753 //Can be less strict with alias analysis and data dependence analysis.
754 void MSchedGraphSB::addMemEdges(const std::vector<MSchedGraphSBNode*>& memInst,
755 DependenceAnalyzer &DA,
756 std::map<MachineInstr*, Instruction*> &machineTollvm) {
758 //Get Target machine instruction info
759 const TargetInstrInfo *TMI = Target.getInstrInfo();
761 //Loop over all memory instructions in the vector
762 //Knowing that they are in execution, add true, anti, and output dependencies
763 for (unsigned srcIndex = 0; srcIndex < memInst.size(); ++srcIndex) {
765 MachineInstr *srcInst = (MachineInstr*) memInst[srcIndex]->getInst();
767 //Get the machine opCode to determine type of memory instruction
768 MachineOpCode srcNodeOpCode = srcInst->getOpcode();
770 //All instructions after this one in execution order have an
771 //iteration delay of 0
772 for(unsigned destIndex = 0; destIndex < memInst.size(); ++destIndex) {
775 if(destIndex == srcIndex)
778 MachineInstr *destInst = (MachineInstr*) memInst[destIndex]->getInst();
780 DEBUG(std::cerr << "MInst1: " << *srcInst << "\n");
781 DEBUG(std::cerr << "MInst2: " << *destInst << "\n");
783 //Assuming instructions without corresponding llvm instructions
784 //are from constant pools.
785 if (!machineTollvm.count(srcInst) || !machineTollvm.count(destInst))
788 bool useDepAnalyzer = true;
790 //Some machine loads and stores are generated by casts, so be
791 //conservative and always add deps
792 Instruction *srcLLVM = machineTollvm[srcInst];
793 Instruction *destLLVM = machineTollvm[destInst];
794 if(!isa<LoadInst>(srcLLVM)
795 && !isa<StoreInst>(srcLLVM)) {
796 if(isa<BinaryOperator>(srcLLVM)) {
797 if(isa<ConstantFP>(srcLLVM->getOperand(0)) || isa<ConstantFP>(srcLLVM->getOperand(1)))
800 useDepAnalyzer = false;
802 if(!isa<LoadInst>(destLLVM)
803 && !isa<StoreInst>(destLLVM)) {
804 if(isa<BinaryOperator>(destLLVM)) {
805 if(isa<ConstantFP>(destLLVM->getOperand(0)) || isa<ConstantFP>(destLLVM->getOperand(1)))
808 useDepAnalyzer = false;
811 //Use dep analysis when we have corresponding llvm loads/stores
813 bool srcBeforeDest = true;
814 if(destIndex < srcIndex)
815 srcBeforeDest = false;
817 DependenceResult dr = DA.getDependenceInfo(machineTollvm[srcInst],
818 machineTollvm[destInst],
821 for(std::vector<Dependence>::iterator d = dr.dependences.begin(),
822 de = dr.dependences.end(); d != de; ++d) {
823 //Add edge from load to store
824 memInst[srcIndex]->addOutEdge(memInst[destIndex],
825 MSchedGraphSBEdge::MemoryDep,
826 d->getDepType(), d->getIteDiff());
830 //Otherwise, we can not do any further analysis and must make a dependence
833 //Get the machine opCode to determine type of memory instruction
834 MachineOpCode destNodeOpCode = destInst->getOpcode();
836 //Get the Value* that we are reading from the load, always the first op
837 const MachineOperand &mOp = srcInst->getOperand(0);
838 const MachineOperand &mOp2 = destInst->getOperand(0);
840 if(mOp.hasAllocatedReg())
841 if(mOp.getReg() == SparcV9::g0)
843 if(mOp2.hasAllocatedReg())
844 if(mOp2.getReg() == SparcV9::g0)
847 DEBUG(std::cerr << "Adding dependence for machine instructions\n");
849 if(TMI->isLoad(srcNodeOpCode)) {
851 if(TMI->isStore(destNodeOpCode))
852 memInst[srcIndex]->addOutEdge(memInst[destIndex],
853 MSchedGraphSBEdge::MemoryDep,
854 MSchedGraphSBEdge::AntiDep, 0);
856 else if(TMI->isStore(srcNodeOpCode)) {
857 if(TMI->isStore(destNodeOpCode))
858 memInst[srcIndex]->addOutEdge(memInst[destIndex],
859 MSchedGraphSBEdge::MemoryDep,
860 MSchedGraphSBEdge::OutputDep, 0);
863 memInst[srcIndex]->addOutEdge(memInst[destIndex],
864 MSchedGraphSBEdge::MemoryDep,
865 MSchedGraphSBEdge::TrueDep, 0);