1 //===- SchedGraph.cpp - Scheduling Graph Implementation -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Scheduling graph based on SSA graph plus extra dependence edges capturing
11 // dependences due to machine resources (machine registers, CC registers, and
14 //===----------------------------------------------------------------------===//
16 #include "SchedGraph.h"
17 #include "llvm/Function.h"
18 #include "llvm/iOther.h"
19 #include "llvm/CodeGen/MachineCodeForInstruction.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/Target/TargetInstrInfo.h"
22 #include "llvm/Target/TargetMachine.h"
23 #include "llvm/Target/TargetRegInfo.h"
24 #include "Support/STLExtras.h"
28 //*********************** Internal Data Structures *************************/
30 // The following two types need to be classes, not typedefs, so we can use
31 // opaque declarations in SchedGraph.h
33 struct RefVec: public std::vector<std::pair<SchedGraphNode*, int> > {
34 typedef std::vector<std::pair<SchedGraphNode*,int> >::iterator iterator;
36 std::vector<std::pair<SchedGraphNode*,int> >::const_iterator const_iterator;
39 struct RegToRefVecMap: public hash_map<int, RefVec> {
40 typedef hash_map<int, RefVec>:: iterator iterator;
41 typedef hash_map<int, RefVec>::const_iterator const_iterator;
44 struct ValueToDefVecMap: public hash_map<const Value*, RefVec> {
45 typedef hash_map<const Value*, RefVec>:: iterator iterator;
46 typedef hash_map<const Value*, RefVec>::const_iterator const_iterator;
51 // class SchedGraphNode
54 SchedGraphNode::SchedGraphNode(unsigned NID, MachineBasicBlock *mbb,
55 int indexInBB, const TargetMachine& Target)
56 : SchedGraphNodeCommon(NID,indexInBB), MBB(mbb), MI(mbb ? (*mbb)[indexInBB] : 0) {
58 MachineOpCode mopCode = MI->getOpCode();
59 latency = Target.getInstrInfo().hasResultInterlock(mopCode)
60 ? Target.getInstrInfo().minLatency(mopCode)
61 : Target.getInstrInfo().maxLatency(mopCode);
66 // Method: SchedGraphNode Destructor
69 // Free memory allocated by the SchedGraphNode object.
72 // Do not delete the edges here. The base class will take care of that.
73 // Only handle subclass specific stuff here (where currently there is
76 SchedGraphNode::~SchedGraphNode() {
82 SchedGraph::SchedGraph(MachineBasicBlock &mbb, const TargetMachine& target)
88 // Method: SchedGraph Destructor
91 // This method deletes memory allocated by the SchedGraph object.
94 // Do not delete the graphRoot or graphLeaf here. The base class handles
97 SchedGraph::~SchedGraph() {
98 for (const_iterator I = begin(); I != end(); ++I)
102 void SchedGraph::dump() const {
103 std::cerr << " Sched Graph for Basic Block: ";
104 std::cerr << MBB.getBasicBlock()->getName()
105 << " (" << MBB.getBasicBlock() << ")";
107 std::cerr << "\n\n Actual Root nodes : ";
108 for (unsigned i=0, N=graphRoot->outEdges.size(); i < N; i++)
109 std::cerr << graphRoot->outEdges[i]->getSink()->getNodeId()
110 << ((i == N-1)? "" : ", ");
112 std::cerr << "\n Graph Nodes:\n";
113 for (const_iterator I=begin(); I != end(); ++I)
114 std::cerr << "\n" << *I->second;
121 void SchedGraph::addDummyEdges() {
122 assert(graphRoot->outEdges.size() == 0);
124 for (const_iterator I=begin(); I != end(); ++I) {
125 SchedGraphNode* node = (*I).second;
126 assert(node != graphRoot && node != graphLeaf);
127 if (node->beginInEdges() == node->endInEdges())
128 (void) new SchedGraphEdge(graphRoot, node, SchedGraphEdge::CtrlDep,
129 SchedGraphEdge::NonDataDep, 0);
130 if (node->beginOutEdges() == node->endOutEdges())
131 (void) new SchedGraphEdge(node, graphLeaf, SchedGraphEdge::CtrlDep,
132 SchedGraphEdge::NonDataDep, 0);
137 void SchedGraph::addCDEdges(const TerminatorInst* term,
138 const TargetMachine& target) {
139 const TargetInstrInfo& mii = target.getInstrInfo();
140 MachineCodeForInstruction &termMvec = MachineCodeForInstruction::get(term);
142 // Find the first branch instr in the sequence of machine instrs for term
145 while (! mii.isBranch(termMvec[first]->getOpCode()) &&
146 ! mii.isReturn(termMvec[first]->getOpCode()))
148 assert(first < termMvec.size() &&
149 "No branch instructions for terminator? Ok, but weird!");
150 if (first == termMvec.size())
153 SchedGraphNode* firstBrNode = getGraphNodeForInstr(termMvec[first]);
155 // Add CD edges from each instruction in the sequence to the
156 // *last preceding* branch instr. in the sequence
157 // Use a latency of 0 because we only need to prevent out-of-order issue.
159 for (unsigned i = termMvec.size(); i > first+1; --i) {
160 SchedGraphNode* toNode = getGraphNodeForInstr(termMvec[i-1]);
161 assert(toNode && "No node for instr generated for branch/ret?");
163 for (unsigned j = i-1; j != 0; --j)
164 if (mii.isBranch(termMvec[j-1]->getOpCode()) ||
165 mii.isReturn(termMvec[j-1]->getOpCode())) {
166 SchedGraphNode* brNode = getGraphNodeForInstr(termMvec[j-1]);
167 assert(brNode && "No node for instr generated for branch/ret?");
168 (void) new SchedGraphEdge(brNode, toNode, SchedGraphEdge::CtrlDep,
169 SchedGraphEdge::NonDataDep, 0);
170 break; // only one incoming edge is enough
174 // Add CD edges from each instruction preceding the first branch
175 // to the first branch. Use a latency of 0 as above.
177 for (unsigned i = first; i != 0; --i) {
178 SchedGraphNode* fromNode = getGraphNodeForInstr(termMvec[i-1]);
179 assert(fromNode && "No node for instr generated for branch?");
180 (void) new SchedGraphEdge(fromNode, firstBrNode, SchedGraphEdge::CtrlDep,
181 SchedGraphEdge::NonDataDep, 0);
184 // Now add CD edges to the first branch instruction in the sequence from
185 // all preceding instructions in the basic block. Use 0 latency again.
187 for (unsigned i=0, N=MBB.size(); i < N; i++) {
188 if (MBB[i] == termMvec[first]) // reached the first branch
191 SchedGraphNode* fromNode = this->getGraphNodeForInstr(MBB[i]);
192 if (fromNode == NULL)
193 continue; // dummy instruction, e.g., PHI
195 (void) new SchedGraphEdge(fromNode, firstBrNode,
196 SchedGraphEdge::CtrlDep,
197 SchedGraphEdge::NonDataDep, 0);
199 // If we find any other machine instructions (other than due to
200 // the terminator) that also have delay slots, add an outgoing edge
201 // from the instruction to the instructions in the delay slots.
203 unsigned d = mii.getNumDelaySlots(MBB[i]->getOpCode());
204 assert(i+d < N && "Insufficient delay slots for instruction?");
206 for (unsigned j=1; j <= d; j++) {
207 SchedGraphNode* toNode = this->getGraphNodeForInstr(MBB[i+j]);
208 assert(toNode && "No node for machine instr in delay slot?");
209 (void) new SchedGraphEdge(fromNode, toNode,
210 SchedGraphEdge::CtrlDep,
211 SchedGraphEdge::NonDataDep, 0);
216 static const int SG_LOAD_REF = 0;
217 static const int SG_STORE_REF = 1;
218 static const int SG_CALL_REF = 2;
220 static const unsigned int SG_DepOrderArray[][3] = {
221 { SchedGraphEdge::NonDataDep,
222 SchedGraphEdge::AntiDep,
223 SchedGraphEdge::AntiDep },
224 { SchedGraphEdge::TrueDep,
225 SchedGraphEdge::OutputDep,
226 SchedGraphEdge::TrueDep | SchedGraphEdge::OutputDep },
227 { SchedGraphEdge::TrueDep,
228 SchedGraphEdge::AntiDep | SchedGraphEdge::OutputDep,
229 SchedGraphEdge::TrueDep | SchedGraphEdge::AntiDep
230 | SchedGraphEdge::OutputDep }
234 // Add a dependence edge between every pair of machine load/store/call
235 // instructions, where at least one is a store or a call.
236 // Use latency 1 just to ensure that memory operations are ordered;
237 // latency does not otherwise matter (true dependences enforce that).
239 void SchedGraph::addMemEdges(const std::vector<SchedGraphNode*>& memNodeVec,
240 const TargetMachine& target) {
241 const TargetInstrInfo& mii = target.getInstrInfo();
243 // Instructions in memNodeVec are in execution order within the basic block,
244 // so simply look at all pairs <memNodeVec[i], memNodeVec[j: j > i]>.
246 for (unsigned im=0, NM=memNodeVec.size(); im < NM; im++) {
247 MachineOpCode fromOpCode = memNodeVec[im]->getOpCode();
248 int fromType = (mii.isCall(fromOpCode)? SG_CALL_REF
249 : (mii.isLoad(fromOpCode)? SG_LOAD_REF
251 for (unsigned jm=im+1; jm < NM; jm++) {
252 MachineOpCode toOpCode = memNodeVec[jm]->getOpCode();
253 int toType = (mii.isCall(toOpCode)? SG_CALL_REF
254 : (mii.isLoad(toOpCode)? SG_LOAD_REF
257 if (fromType != SG_LOAD_REF || toType != SG_LOAD_REF)
258 (void) new SchedGraphEdge(memNodeVec[im], memNodeVec[jm],
259 SchedGraphEdge::MemoryDep,
260 SG_DepOrderArray[fromType][toType], 1);
265 // Add edges from/to CC reg instrs to/from call instrs.
266 // Essentially this prevents anything that sets or uses a CC reg from being
267 // reordered w.r.t. a call.
268 // Use a latency of 0 because we only need to prevent out-of-order issue,
269 // like with control dependences.
271 void SchedGraph::addCallDepEdges(const std::vector<SchedGraphNode*>& callDepNodeVec,
272 const TargetMachine& target) {
273 const TargetInstrInfo& mii = target.getInstrInfo();
275 // Instructions in memNodeVec are in execution order within the basic block,
276 // so simply look at all pairs <memNodeVec[i], memNodeVec[j: j > i]>.
278 for (unsigned ic=0, NC=callDepNodeVec.size(); ic < NC; ic++)
279 if (mii.isCall(callDepNodeVec[ic]->getOpCode())) {
280 // Add SG_CALL_REF edges from all preds to this instruction.
281 for (unsigned jc=0; jc < ic; jc++)
282 (void) new SchedGraphEdge(callDepNodeVec[jc], callDepNodeVec[ic],
283 SchedGraphEdge::MachineRegister,
284 MachineIntRegsRID, 0);
286 // And do the same from this instruction to all successors.
287 for (unsigned jc=ic+1; jc < NC; jc++)
288 (void) new SchedGraphEdge(callDepNodeVec[ic], callDepNodeVec[jc],
289 SchedGraphEdge::MachineRegister,
290 MachineIntRegsRID, 0);
293 #ifdef CALL_DEP_NODE_VEC_CANNOT_WORK
294 // Find the call instruction nodes and put them in a vector.
295 std::vector<SchedGraphNode*> callNodeVec;
296 for (unsigned im=0, NM=memNodeVec.size(); im < NM; im++)
297 if (mii.isCall(memNodeVec[im]->getOpCode()))
298 callNodeVec.push_back(memNodeVec[im]);
300 // Now walk the entire basic block, looking for CC instructions *and*
301 // call instructions, and keep track of the order of the instructions.
302 // Use the call node vec to quickly find earlier and later call nodes
303 // relative to the current CC instruction.
305 int lastCallNodeIdx = -1;
306 for (unsigned i=0, N=bbMvec.size(); i < N; i++)
307 if (mii.isCall(bbMvec[i]->getOpCode())) {
309 for ( ; lastCallNodeIdx < (int)callNodeVec.size(); ++lastCallNodeIdx)
310 if (callNodeVec[lastCallNodeIdx]->getMachineInstr() == bbMvec[i])
312 assert(lastCallNodeIdx < (int)callNodeVec.size() && "Missed Call?");
314 else if (mii.isCCInstr(bbMvec[i]->getOpCode())) {
315 // Add incoming/outgoing edges from/to preceding/later calls
316 SchedGraphNode* ccNode = this->getGraphNodeForInstr(bbMvec[i]);
318 for ( ; j <= lastCallNodeIdx; j++)
319 (void) new SchedGraphEdge(callNodeVec[j], ccNode,
320 MachineCCRegsRID, 0);
321 for ( ; j < (int) callNodeVec.size(); j++)
322 (void) new SchedGraphEdge(ccNode, callNodeVec[j],
323 MachineCCRegsRID, 0);
329 void SchedGraph::addMachineRegEdges(RegToRefVecMap& regToRefVecMap,
330 const TargetMachine& target) {
331 // This code assumes that two registers with different numbers are
334 for (RegToRefVecMap::iterator I = regToRefVecMap.begin();
335 I != regToRefVecMap.end(); ++I) {
336 int regNum = (*I).first;
337 RefVec& regRefVec = (*I).second;
339 // regRefVec is ordered by control flow order in the basic block
340 for (unsigned i=0; i < regRefVec.size(); ++i) {
341 SchedGraphNode* node = regRefVec[i].first;
342 unsigned int opNum = regRefVec[i].second;
343 const MachineOperand& mop =
344 node->getMachineInstr()->getExplOrImplOperand(opNum);
345 bool isDef = mop.opIsDefOnly();
346 bool isDefAndUse = mop.opIsDefAndUse();
348 for (unsigned p=0; p < i; ++p) {
349 SchedGraphNode* prevNode = regRefVec[p].first;
350 if (prevNode != node) {
351 unsigned int prevOpNum = regRefVec[p].second;
352 const MachineOperand& prevMop =
353 prevNode->getMachineInstr()->getExplOrImplOperand(prevOpNum);
354 bool prevIsDef = prevMop.opIsDefOnly();
355 bool prevIsDefAndUse = prevMop.opIsDefAndUse();
358 new SchedGraphEdge(prevNode, node, regNum,
359 SchedGraphEdge::OutputDep);
360 if (!prevIsDef || prevIsDefAndUse)
361 new SchedGraphEdge(prevNode, node, regNum,
362 SchedGraphEdge::AntiDep);
366 if (!isDef || isDefAndUse)
367 new SchedGraphEdge(prevNode, node, regNum,
368 SchedGraphEdge::TrueDep);
376 // Adds dependences to/from refNode from/to all other defs
377 // in the basic block. refNode may be a use, a def, or both.
378 // We do not consider other uses because we are not building use-use deps.
380 void SchedGraph::addEdgesForValue(SchedGraphNode* refNode,
381 const RefVec& defVec,
382 const Value* defValue,
384 bool refNodeIsDefAndUse,
385 const TargetMachine& target) {
386 bool refNodeIsUse = !refNodeIsDef || refNodeIsDefAndUse;
388 // Add true or output dep edges from all def nodes before refNode in BB.
389 // Add anti or output dep edges to all def nodes after refNode.
390 for (RefVec::const_iterator I=defVec.begin(), E=defVec.end(); I != E; ++I) {
391 if ((*I).first == refNode)
392 continue; // Dont add any self-loops
394 if ((*I).first->getOrigIndexInBB() < refNode->getOrigIndexInBB()) {
395 // (*).first is before refNode
397 (void) new SchedGraphEdge((*I).first, refNode, defValue,
398 SchedGraphEdge::OutputDep);
400 (void) new SchedGraphEdge((*I).first, refNode, defValue,
401 SchedGraphEdge::TrueDep);
403 // (*).first is after refNode
405 (void) new SchedGraphEdge(refNode, (*I).first, defValue,
406 SchedGraphEdge::OutputDep);
408 (void) new SchedGraphEdge(refNode, (*I).first, defValue,
409 SchedGraphEdge::AntiDep);
415 void SchedGraph::addEdgesForInstruction(const MachineInstr& MI,
416 const ValueToDefVecMap& valueToDefVecMap,
417 const TargetMachine& target) {
418 SchedGraphNode* node = getGraphNodeForInstr(&MI);
422 // Add edges for all operands of the machine instruction.
424 for (unsigned i = 0, numOps = MI.getNumOperands(); i != numOps; ++i) {
425 switch (MI.getOperand(i).getType()) {
426 case MachineOperand::MO_VirtualRegister:
427 case MachineOperand::MO_CCRegister:
428 if (const Value* srcI = MI.getOperand(i).getVRegValue()) {
429 ValueToDefVecMap::const_iterator I = valueToDefVecMap.find(srcI);
430 if (I != valueToDefVecMap.end())
431 addEdgesForValue(node, I->second, srcI,
432 MI.getOperand(i).opIsDefOnly(),
433 MI.getOperand(i).opIsDefAndUse(), target);
437 case MachineOperand::MO_MachineRegister:
440 case MachineOperand::MO_SignExtendedImmed:
441 case MachineOperand::MO_UnextendedImmed:
442 case MachineOperand::MO_PCRelativeDisp:
443 case MachineOperand::MO_ConstantPoolIndex:
444 break; // nothing to do for immediate fields
447 assert(0 && "Unknown machine operand type in SchedGraph builder");
452 // Add edges for values implicitly used by the machine instruction.
453 // Examples include function arguments to a Call instructions or the return
454 // value of a Ret instruction.
456 for (unsigned i=0, N=MI.getNumImplicitRefs(); i < N; ++i)
457 if (MI.getImplicitOp(i).opIsUse() || MI.getImplicitOp(i).opIsDefAndUse())
458 if (const Value* srcI = MI.getImplicitRef(i)) {
459 ValueToDefVecMap::const_iterator I = valueToDefVecMap.find(srcI);
460 if (I != valueToDefVecMap.end())
461 addEdgesForValue(node, I->second, srcI,
462 MI.getImplicitOp(i).opIsDefOnly(),
463 MI.getImplicitOp(i).opIsDefAndUse(), target);
468 void SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target,
469 SchedGraphNode* node,
470 std::vector<SchedGraphNode*>& memNodeVec,
471 std::vector<SchedGraphNode*>& callDepNodeVec,
472 RegToRefVecMap& regToRefVecMap,
473 ValueToDefVecMap& valueToDefVecMap) {
474 const TargetInstrInfo& mii = target.getInstrInfo();
476 MachineOpCode opCode = node->getOpCode();
478 if (mii.isCall(opCode) || mii.isCCInstr(opCode))
479 callDepNodeVec.push_back(node);
481 if (mii.isLoad(opCode) || mii.isStore(opCode) || mii.isCall(opCode))
482 memNodeVec.push_back(node);
484 // Collect the register references and value defs. for explicit operands
486 const MachineInstr& MI = *node->getMachineInstr();
487 for (int i=0, numOps = (int) MI.getNumOperands(); i < numOps; i++) {
488 const MachineOperand& mop = MI.getOperand(i);
490 // if this references a register other than the hardwired
491 // "zero" register, record the reference.
492 if (mop.hasAllocatedReg()) {
493 int regNum = mop.getAllocatedRegNum();
495 // If this is not a dummy zero register, record the reference in order
496 if (regNum != target.getRegInfo().getZeroRegNum())
497 regToRefVecMap[mop.getAllocatedRegNum()]
498 .push_back(std::make_pair(node, i));
500 // If this is a volatile register, add the instruction to callDepVec
501 // (only if the node is not already on the callDepVec!)
502 if (callDepNodeVec.size() == 0 || callDepNodeVec.back() != node)
505 int regInClass = target.getRegInfo().getClassRegNum(regNum, rcid);
506 if (target.getRegInfo().getMachineRegClass(rcid)
507 ->isRegVolatile(regInClass))
508 callDepNodeVec.push_back(node);
511 continue; // nothing more to do
514 // ignore all other non-def operands
515 if (!MI.getOperand(i).opIsDefOnly() &&
516 !MI.getOperand(i).opIsDefAndUse())
519 // We must be defining a value.
520 assert((mop.getType() == MachineOperand::MO_VirtualRegister ||
521 mop.getType() == MachineOperand::MO_CCRegister)
522 && "Do not expect any other kind of operand to be defined!");
523 assert(mop.getVRegValue() != NULL && "Null value being defined?");
525 valueToDefVecMap[mop.getVRegValue()].push_back(std::make_pair(node, i));
529 // Collect value defs. for implicit operands. They may have allocated
530 // physical registers also.
532 for (unsigned i=0, N = MI.getNumImplicitRefs(); i != N; ++i) {
533 const MachineOperand& mop = MI.getImplicitOp(i);
534 if (mop.hasAllocatedReg()) {
535 int regNum = mop.getAllocatedRegNum();
536 if (regNum != target.getRegInfo().getZeroRegNum())
537 regToRefVecMap[mop.getAllocatedRegNum()]
538 .push_back(std::make_pair(node, i + MI.getNumOperands()));
539 continue; // nothing more to do
542 if (mop.opIsDefOnly() || mop.opIsDefAndUse()) {
543 assert(MI.getImplicitRef(i) != NULL && "Null value being defined?");
544 valueToDefVecMap[MI.getImplicitRef(i)].push_back(std::make_pair(node,
551 void SchedGraph::buildNodesForBB(const TargetMachine& target,
552 MachineBasicBlock& MBB,
553 std::vector<SchedGraphNode*>& memNodeVec,
554 std::vector<SchedGraphNode*>& callDepNodeVec,
555 RegToRefVecMap& regToRefVecMap,
556 ValueToDefVecMap& valueToDefVecMap) {
557 const TargetInstrInfo& mii = target.getInstrInfo();
559 // Build graph nodes for each VM instruction and gather def/use info.
560 // Do both those together in a single pass over all machine instructions.
561 for (unsigned i=0; i < MBB.size(); i++)
562 if (!mii.isDummyPhiInstr(MBB[i]->getOpCode())) {
563 SchedGraphNode* node = new SchedGraphNode(getNumNodes(), &MBB, i, target);
564 noteGraphNodeForInstr(MBB[i], node);
566 // Remember all register references and value defs
567 findDefUseInfoAtInstr(target, node, memNodeVec, callDepNodeVec,
568 regToRefVecMap, valueToDefVecMap);
573 void SchedGraph::buildGraph(const TargetMachine& target) {
574 // Use this data structure to note all machine operands that compute
575 // ordinary LLVM values. These must be computed defs (i.e., instructions).
576 // Note that there may be multiple machine instructions that define
578 ValueToDefVecMap valueToDefVecMap;
580 // Use this data structure to note all memory instructions.
581 // We use this to add memory dependence edges without a second full walk.
582 std::vector<SchedGraphNode*> memNodeVec;
584 // Use this data structure to note all instructions that access physical
585 // registers that can be modified by a call (including call instructions)
586 std::vector<SchedGraphNode*> callDepNodeVec;
588 // Use this data structure to note any uses or definitions of
589 // machine registers so we can add edges for those later without
590 // extra passes over the nodes.
591 // The vector holds an ordered list of references to the machine reg,
592 // ordered according to control-flow order. This only works for a
593 // single basic block, hence the assertion. Each reference is identified
594 // by the pair: <node, operand-number>.
596 RegToRefVecMap regToRefVecMap;
598 // Make a dummy root node. We'll add edges to the real roots later.
599 graphRoot = new SchedGraphNode(0, NULL, -1, target);
600 graphLeaf = new SchedGraphNode(1, NULL, -1, target);
602 //----------------------------------------------------------------
603 // First add nodes for all the machine instructions in the basic block
604 // because this greatly simplifies identifying which edges to add.
605 // Do this one VM instruction at a time since the SchedGraphNode needs that.
606 // Also, remember the load/store instructions to add memory deps later.
607 //----------------------------------------------------------------
609 buildNodesForBB(target, MBB, memNodeVec, callDepNodeVec,
610 regToRefVecMap, valueToDefVecMap);
612 //----------------------------------------------------------------
613 // Now add edges for the following (all are incoming edges except (4)):
614 // (1) operands of the machine instruction, including hidden operands
615 // (2) machine register dependences
616 // (3) memory load/store dependences
617 // (3) other resource dependences for the machine instruction, if any
618 // (4) output dependences when multiple machine instructions define the
619 // same value; all must have been generated from a single VM instrn
620 // (5) control dependences to branch instructions generated for the
621 // terminator instruction of the BB. Because of delay slots and
622 // 2-way conditional branches, multiple CD edges are needed
623 // (see addCDEdges for details).
624 // Also, note any uses or defs of machine registers.
626 //----------------------------------------------------------------
628 // First, add edges to the terminator instruction of the basic block.
629 this->addCDEdges(MBB.getBasicBlock()->getTerminator(), target);
631 // Then add memory dep edges: store->load, load->store, and store->store.
632 // Call instructions are treated as both load and store.
633 this->addMemEdges(memNodeVec, target);
635 // Then add edges between call instructions and CC set/use instructions
636 this->addCallDepEdges(callDepNodeVec, target);
638 // Then add incoming def-use (SSA) edges for each machine instruction.
639 for (unsigned i=0, N=MBB.size(); i < N; i++)
640 addEdgesForInstruction(*MBB[i], valueToDefVecMap, target);
642 #ifdef NEED_SEPARATE_NONSSA_EDGES_CODE
643 // Then add non-SSA edges for all VM instructions in the block.
644 // We assume that all machine instructions that define a value are
645 // generated from the VM instruction corresponding to that value.
646 // TODO: This could probably be done much more efficiently.
647 for (BasicBlock::const_iterator II = bb->begin(); II != bb->end(); ++II)
648 this->addNonSSAEdgesForValue(*II, target);
649 #endif //NEED_SEPARATE_NONSSA_EDGES_CODE
651 // Then add edges for dependences on machine registers
652 this->addMachineRegEdges(regToRefVecMap, target);
654 // Finally, add edges from the dummy root and to dummy leaf
655 this->addDummyEdges();
660 // class SchedGraphSet
662 SchedGraphSet::SchedGraphSet(const Function* _function,
663 const TargetMachine& target) :
664 function(_function) {
665 buildGraphsForMethod(function, target);
668 SchedGraphSet::~SchedGraphSet() {
669 // delete all the graphs
670 for(iterator I = begin(), E = end(); I != E; ++I)
671 delete *I; // destructor is a friend
675 void SchedGraphSet::dump() const {
676 std::cerr << "======== Sched graphs for function `" << function->getName()
679 for (const_iterator I=begin(); I != end(); ++I)
682 std::cerr << "\n====== End graphs for function `" << function->getName()
687 void SchedGraphSet::buildGraphsForMethod(const Function *F,
688 const TargetMachine& target) {
689 MachineFunction &MF = MachineFunction::get(F);
690 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
691 addGraph(new SchedGraph(*I, target));
695 void SchedGraphEdge::print(std::ostream &os) const {
696 os << "edge [" << src->getNodeId() << "] -> ["
697 << sink->getNodeId() << "] : ";
700 case SchedGraphEdge::CtrlDep:
703 case SchedGraphEdge::ValueDep:
704 os<< "Reg Value " << val;
706 case SchedGraphEdge::MemoryDep:
709 case SchedGraphEdge::MachineRegister:
710 os<< "Reg " << machineRegNum;
712 case SchedGraphEdge::MachineResource:
713 os<<"Resource "<< resourceId;
720 os << " : delay = " << minDelay << "\n";
723 void SchedGraphNode::print(std::ostream &os) const {
724 os << std::string(8, ' ')
725 << "Node " << ID << " : "
726 << "latency = " << latency << "\n" << std::string(12, ' ');
728 if (getMachineInstr() == NULL)
729 os << "(Dummy node)\n";
731 os << *getMachineInstr() << "\n" << std::string(12, ' ');
732 os << inEdges.size() << " Incoming Edges:\n";
733 for (unsigned i=0, N = inEdges.size(); i < N; i++)
734 os << std::string(16, ' ') << *inEdges[i];
736 os << std::string(12, ' ') << outEdges.size()
737 << " Outgoing Edges:\n";
738 for (unsigned i=0, N= outEdges.size(); i < N; i++)
739 os << std::string(16, ' ') << *outEdges[i];
743 } // End llvm namespace