1 //===- SparcV8RegisterInfo.cpp - SparcV8 Register Information ---*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the SparcV8 implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "SparcV8RegisterInfo.h"
16 #include "SparcV8Subtarget.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/Type.h"
21 #include "llvm/ADT/STLExtras.h"
25 SparcV8RegisterInfo::SparcV8RegisterInfo(SparcV8Subtarget &st)
26 : SparcV8GenRegisterInfo(V8::ADJCALLSTACKDOWN,
27 V8::ADJCALLSTACKUP), Subtarget(st) {
30 void SparcV8RegisterInfo::
31 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
32 unsigned SrcReg, int FI,
33 const TargetRegisterClass *RC) const {
34 // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
35 if (RC == V8::IntRegsRegisterClass)
36 BuildMI(MBB, I, V8::STri, 3).addFrameIndex(FI).addImm(0).addReg(SrcReg);
37 else if (RC == V8::FPRegsRegisterClass)
38 BuildMI(MBB, I, V8::STFri, 3).addFrameIndex(FI).addImm(0).addReg(SrcReg);
39 else if (RC == V8::DFPRegsRegisterClass)
40 BuildMI(MBB, I, V8::STDFri, 3).addFrameIndex(FI).addImm(0).addReg(SrcReg);
42 assert(0 && "Can't store this register to stack slot");
45 void SparcV8RegisterInfo::
46 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
47 unsigned DestReg, int FI,
48 const TargetRegisterClass *RC) const {
49 if (RC == V8::IntRegsRegisterClass)
50 BuildMI(MBB, I, V8::LDri, 2, DestReg).addFrameIndex(FI).addImm(0);
51 else if (RC == V8::FPRegsRegisterClass)
52 BuildMI(MBB, I, V8::LDFri, 2, DestReg).addFrameIndex(FI).addImm (0);
53 else if (RC == V8::DFPRegsRegisterClass)
54 BuildMI(MBB, I, V8::LDDFri, 2, DestReg).addFrameIndex(FI).addImm(0);
56 assert(0 && "Can't load this register from stack slot");
59 void SparcV8RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
60 MachineBasicBlock::iterator I,
61 unsigned DestReg, unsigned SrcReg,
62 const TargetRegisterClass *RC) const {
63 if (RC == V8::IntRegsRegisterClass)
64 BuildMI(MBB, I, V8::ORrr, 2, DestReg).addReg(V8::G0).addReg(SrcReg);
65 else if (RC == V8::FPRegsRegisterClass)
66 BuildMI(MBB, I, V8::FMOVS, 1, DestReg).addReg(SrcReg);
67 else if (RC == V8::DFPRegsRegisterClass)
68 BuildMI(MBB, I, Subtarget.isV9() ? V8::FMOVD : V8::FpMOVD,
69 1, DestReg).addReg(SrcReg);
71 assert (0 && "Can't copy this register");
74 MachineInstr *SparcV8RegisterInfo::foldMemoryOperand(MachineInstr* MI,
78 switch (MI->getOpcode()) {
80 if (MI->getOperand(1).isRegister() && MI->getOperand(1).getReg() == V8::G0&&
81 MI->getOperand(0).isRegister() && MI->getOperand(2).isRegister()) {
82 if (OpNum == 0) // COPY -> STORE
83 return BuildMI(V8::STri, 3).addFrameIndex(FI).addImm(0)
84 .addReg(MI->getOperand(2).getReg());
86 return BuildMI(V8::LDri, 2, MI->getOperand(0).getReg())
87 .addFrameIndex(FI).addImm(0);
94 if (OpNum == 0) // COPY -> STORE
95 return BuildMI(isFloat ? V8::STFri : V8::STDFri, 3)
96 .addFrameIndex(FI).addImm(0).addReg(MI->getOperand(1).getReg());
98 return BuildMI(isFloat ? V8::LDFri : V8::LDDFri, 2,
99 MI->getOperand(0).getReg()).addFrameIndex(FI).addImm(0);
105 void SparcV8RegisterInfo::
106 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
107 MachineBasicBlock::iterator I) const {
108 MachineInstr &MI = *I;
109 int Size = MI.getOperand(0).getImmedValue();
110 if (MI.getOpcode() == V8::ADJCALLSTACKDOWN)
113 BuildMI(MBB, I, V8::ADDri, 2, V8::O6).addReg(V8::O6).addSImm(Size);
118 SparcV8RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
120 MachineInstr &MI = *II;
121 while (!MI.getOperand(i).isFrameIndex()) {
123 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
126 int FrameIndex = MI.getOperand(i).getFrameIndex();
128 // Addressable stack objects are accessed using neg. offsets from %fp
129 MachineFunction &MF = *MI.getParent()->getParent();
130 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
131 MI.getOperand(i+1).getImmedValue();
133 // Replace frame index with a frame pointer reference.
134 if (Offset >= -4096 && Offset <= 4095) {
135 // If the offset is small enough to fit in the immediate field, directly
137 MI.SetMachineOperandReg(i, V8::I6);
138 MI.SetMachineOperandConst(i+1, MachineOperand::MO_SignExtendedImmed,Offset);
140 // Otherwise, emit a G1 = SETHI %hi(offset). FIXME: it would be better to
141 // scavenge a register here instead of reserving G1 all of the time.
142 unsigned OffHi = (unsigned)Offset >> 10U;
143 BuildMI(*MI.getParent(), II, V8::SETHIi, 1, V8::G1).addImm(OffHi);
145 BuildMI(*MI.getParent(), II, V8::ADDrr, 2,
146 V8::G1).addReg(V8::G1).addReg(V8::I6);
147 // Insert: G1+%lo(offset) into the user.
148 MI.SetMachineOperandReg(i, V8::G1);
149 MI.SetMachineOperandConst(i+1, MachineOperand::MO_SignExtendedImmed,
150 Offset & ((1 << 10)-1));
154 void SparcV8RegisterInfo::
155 processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
157 void SparcV8RegisterInfo::emitPrologue(MachineFunction &MF) const {
158 MachineBasicBlock &MBB = MF.front();
159 MachineFrameInfo *MFI = MF.getFrameInfo();
161 // Get the number of bytes to allocate from the FrameInfo
162 int NumBytes = (int) MFI->getStackSize();
164 // Emit the correct save instruction based on the number of bytes in
165 // the frame. Minimum stack frame size according to V8 ABI is:
166 // 16 words for register window spill
167 // 1 word for address of returned aggregate-value
168 // + 6 words for passing parameters on the stack
170 // 23 words * 4 bytes per word = 92 bytes
172 // Round up to next doubleword boundary -- a double-word boundary
173 // is required by the ABI.
174 NumBytes = (NumBytes + 7) & ~7;
175 NumBytes = -NumBytes;
177 if (NumBytes >= -4096) {
178 BuildMI(MBB, MBB.begin(), V8::SAVEri, 2,
179 V8::O6).addImm(NumBytes).addReg(V8::O6);
181 MachineBasicBlock::iterator InsertPt = MBB.begin();
182 // Emit this the hard way. This clobbers G1 which we always know is
184 unsigned OffHi = (unsigned)NumBytes >> 10U;
185 BuildMI(MBB, InsertPt, V8::SETHIi, 1, V8::G1).addImm(OffHi);
187 BuildMI(MBB, InsertPt, V8::ORri, 2, V8::G1)
188 .addReg(V8::G1).addImm(NumBytes & ((1 << 10)-1));
189 BuildMI(MBB, InsertPt, V8::SAVErr, 2,
190 V8::O6).addReg(V8::O6).addReg(V8::G1);
194 void SparcV8RegisterInfo::emitEpilogue(MachineFunction &MF,
195 MachineBasicBlock &MBB) const {
196 MachineBasicBlock::iterator MBBI = prior(MBB.end());
197 assert(MBBI->getOpcode() == V8::RETL &&
198 "Can only put epilog before 'retl' instruction!");
199 BuildMI(MBB, MBBI, V8::RESTORErr, 2, V8::G0).addReg(V8::G0).addReg(V8::G0);
202 #include "SparcV8GenRegisterInfo.inc"