1 //===- SparcRegisterInfo.cpp - SPARC Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the SPARC implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "SparcRegisterInfo.h"
16 #include "SparcSubtarget.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineLocation.h"
21 #include "llvm/Target/TargetInstrInfo.h"
22 #include "llvm/Type.h"
23 #include "llvm/ADT/BitVector.h"
24 #include "llvm/ADT/STLExtras.h"
27 SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st,
28 const TargetInstrInfo &tii)
29 : SparcGenRegisterInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
30 Subtarget(st), TII(tii) {
33 void SparcRegisterInfo::
34 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
35 unsigned SrcReg, int FI,
36 const TargetRegisterClass *RC) const {
37 // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
38 if (RC == SP::IntRegsRegisterClass)
39 BuildMI(MBB, I, TII.get(SP::STri)).addFrameIndex(FI).addImm(0)
40 .addReg(SrcReg, false, false, true);
41 else if (RC == SP::FPRegsRegisterClass)
42 BuildMI(MBB, I, TII.get(SP::STFri)).addFrameIndex(FI).addImm(0)
43 .addReg(SrcReg, false, false, true);
44 else if (RC == SP::DFPRegsRegisterClass)
45 BuildMI(MBB, I, TII.get(SP::STDFri)).addFrameIndex(FI).addImm(0)
46 .addReg(SrcReg, false, false, true);
48 assert(0 && "Can't store this register to stack slot");
51 void SparcRegisterInfo::
52 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
53 unsigned DestReg, int FI,
54 const TargetRegisterClass *RC) const {
55 if (RC == SP::IntRegsRegisterClass)
56 BuildMI(MBB, I, TII.get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0);
57 else if (RC == SP::FPRegsRegisterClass)
58 BuildMI(MBB, I, TII.get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0);
59 else if (RC == SP::DFPRegsRegisterClass)
60 BuildMI(MBB, I, TII.get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0);
62 assert(0 && "Can't load this register from stack slot");
65 void SparcRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
66 MachineBasicBlock::iterator I,
67 unsigned DestReg, unsigned SrcReg,
68 const TargetRegisterClass *DestRC,
69 const TargetRegisterClass *SrcRC) const {
70 if (DestRC != SrcRC) {
71 cerr << "Not yet supported!";
75 if (DestRC == SP::IntRegsRegisterClass)
76 BuildMI(MBB, I, TII.get(SP::ORrr), DestReg).addReg(SP::G0).addReg(SrcReg);
77 else if (DestRC == SP::FPRegsRegisterClass)
78 BuildMI(MBB, I, TII.get(SP::FMOVS), DestReg).addReg(SrcReg);
79 else if (DestRC == SP::DFPRegsRegisterClass)
80 BuildMI(MBB, I, TII.get(Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD),DestReg)
83 assert (0 && "Can't copy this register");
86 void SparcRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
87 MachineBasicBlock::iterator I,
89 const MachineInstr *Orig) const {
90 MachineInstr *MI = Orig->clone();
91 MI->getOperand(0).setReg(DestReg);
95 MachineInstr *SparcRegisterInfo::foldMemoryOperand(MachineInstr* MI,
99 MachineInstr *NewMI = NULL;
100 switch (MI->getOpcode()) {
102 if (MI->getOperand(1).isRegister() && MI->getOperand(1).getReg() == SP::G0&&
103 MI->getOperand(0).isRegister() && MI->getOperand(2).isRegister()) {
104 if (OpNum == 0) // COPY -> STORE
105 NewMI = BuildMI(TII.get(SP::STri)).addFrameIndex(FI).addImm(0)
106 .addReg(MI->getOperand(2).getReg());
108 NewMI = BuildMI(TII.get(SP::LDri), MI->getOperand(0).getReg())
109 .addFrameIndex(FI).addImm(0);
116 if (OpNum == 0) // COPY -> STORE
117 NewMI = BuildMI(TII.get(isFloat ? SP::STFri : SP::STDFri))
118 .addFrameIndex(FI).addImm(0).addReg(MI->getOperand(1).getReg());
120 NewMI = BuildMI(TII.get(isFloat ? SP::LDFri : SP::LDDFri),
121 MI->getOperand(0).getReg()).addFrameIndex(FI).addImm(0);
126 NewMI->copyKillDeadInfo(MI);
130 const unsigned* SparcRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
132 static const unsigned CalleeSavedRegs[] = { 0 };
133 return CalleeSavedRegs;
136 BitVector SparcRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
137 BitVector Reserved(getNumRegs());
138 Reserved.set(SP::G2);
139 Reserved.set(SP::G3);
140 Reserved.set(SP::G4);
141 Reserved.set(SP::O6);
142 Reserved.set(SP::I6);
143 Reserved.set(SP::I7);
144 Reserved.set(SP::G0);
145 Reserved.set(SP::G5);
146 Reserved.set(SP::G6);
147 Reserved.set(SP::G7);
152 const TargetRegisterClass* const*
153 SparcRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
154 static const TargetRegisterClass * const CalleeSavedRegClasses[] = { 0 };
155 return CalleeSavedRegClasses;
158 bool SparcRegisterInfo::hasFP(const MachineFunction &MF) const {
162 void SparcRegisterInfo::
163 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
164 MachineBasicBlock::iterator I) const {
165 MachineInstr &MI = *I;
166 int Size = MI.getOperand(0).getImmedValue();
167 if (MI.getOpcode() == SP::ADJCALLSTACKDOWN)
170 BuildMI(MBB, I, TII.get(SP::ADDri), SP::O6).addReg(SP::O6).addImm(Size);
174 void SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
175 int SPAdj, RegScavenger *RS) const {
176 assert(SPAdj == 0 && "Unexpected");
179 MachineInstr &MI = *II;
180 while (!MI.getOperand(i).isFrameIndex()) {
182 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
185 int FrameIndex = MI.getOperand(i).getFrameIndex();
187 // Addressable stack objects are accessed using neg. offsets from %fp
188 MachineFunction &MF = *MI.getParent()->getParent();
189 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
190 MI.getOperand(i+1).getImmedValue();
192 // Replace frame index with a frame pointer reference.
193 if (Offset >= -4096 && Offset <= 4095) {
194 // If the offset is small enough to fit in the immediate field, directly
196 MI.getOperand(i).ChangeToRegister(SP::I6, false);
197 MI.getOperand(i+1).ChangeToImmediate(Offset);
199 // Otherwise, emit a G1 = SETHI %hi(offset). FIXME: it would be better to
200 // scavenge a register here instead of reserving G1 all of the time.
201 unsigned OffHi = (unsigned)Offset >> 10U;
202 BuildMI(*MI.getParent(), II, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
204 BuildMI(*MI.getParent(), II, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
206 // Insert: G1+%lo(offset) into the user.
207 MI.getOperand(i).ChangeToRegister(SP::G1, false);
208 MI.getOperand(i+1).ChangeToImmediate(Offset & ((1 << 10)-1));
212 void SparcRegisterInfo::
213 processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
215 void SparcRegisterInfo::emitPrologue(MachineFunction &MF) const {
216 MachineBasicBlock &MBB = MF.front();
217 MachineFrameInfo *MFI = MF.getFrameInfo();
219 // Get the number of bytes to allocate from the FrameInfo
220 int NumBytes = (int) MFI->getStackSize();
222 // Emit the correct save instruction based on the number of bytes in
223 // the frame. Minimum stack frame size according to V8 ABI is:
224 // 16 words for register window spill
225 // 1 word for address of returned aggregate-value
226 // + 6 words for passing parameters on the stack
228 // 23 words * 4 bytes per word = 92 bytes
230 // Round up to next doubleword boundary -- a double-word boundary
231 // is required by the ABI.
232 NumBytes = (NumBytes + 7) & ~7;
233 NumBytes = -NumBytes;
235 if (NumBytes >= -4096) {
236 BuildMI(MBB, MBB.begin(), TII.get(SP::SAVEri),
237 SP::O6).addImm(NumBytes).addReg(SP::O6);
239 MachineBasicBlock::iterator InsertPt = MBB.begin();
240 // Emit this the hard way. This clobbers G1 which we always know is
242 unsigned OffHi = (unsigned)NumBytes >> 10U;
243 BuildMI(MBB, InsertPt, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
245 BuildMI(MBB, InsertPt, TII.get(SP::ORri), SP::G1)
246 .addReg(SP::G1).addImm(NumBytes & ((1 << 10)-1));
247 BuildMI(MBB, InsertPt, TII.get(SP::SAVErr), SP::O6)
248 .addReg(SP::O6).addReg(SP::G1);
252 void SparcRegisterInfo::emitEpilogue(MachineFunction &MF,
253 MachineBasicBlock &MBB) const {
254 MachineBasicBlock::iterator MBBI = prior(MBB.end());
255 assert(MBBI->getOpcode() == SP::RETL &&
256 "Can only put epilog before 'retl' instruction!");
257 BuildMI(MBB, MBBI, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0)
261 unsigned SparcRegisterInfo::getRARegister() const {
262 assert(0 && "What is the return address register");
266 unsigned SparcRegisterInfo::getFrameRegister(MachineFunction &MF) const {
267 assert(0 && "What is the frame register");
271 unsigned SparcRegisterInfo::getEHExceptionRegister() const {
272 assert(0 && "What is the exception register");
276 unsigned SparcRegisterInfo::getEHHandlerRegister() const {
277 assert(0 && "What is the exception handler register");
281 #include "SparcGenRegisterInfo.inc"