1 //===-- SparcInstrInfo.td - Target Description for Sparc Target -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Sparc instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Instruction format superclass
16 //===----------------------------------------------------------------------===//
18 include "SparcInstrFormats.td"
20 //===----------------------------------------------------------------------===//
21 // Feature predicates.
22 //===----------------------------------------------------------------------===//
24 // True when generating 32-bit code.
25 def Is32Bit : Predicate<"!Subtarget.is64Bit()">;
27 // True when generating 64-bit code. This also implies HasV9.
28 def Is64Bit : Predicate<"Subtarget.is64Bit()">;
30 // HasV9 - This predicate is true when the target processor supports V9
31 // instructions. Note that the machine may be running in 32-bit mode.
32 def HasV9 : Predicate<"Subtarget.isV9()">;
34 // HasNoV9 - This predicate is true when the target doesn't have V9
35 // instructions. Use of this is just a hack for the isel not having proper
36 // costs for V8 instructions that are more expensive than their V9 ones.
37 def HasNoV9 : Predicate<"!Subtarget.isV9()">;
39 // HasVIS - This is true when the target processor has VIS extensions.
40 def HasVIS : Predicate<"Subtarget.isVIS()">;
42 // UseDeprecatedInsts - This predicate is true when the target processor is a
43 // V8, or when it is V9 but the V8 deprecated instructions are efficient enough
44 // to use when appropriate. In either of these cases, the instruction selector
45 // will pick deprecated instructions.
46 def UseDeprecatedInsts : Predicate<"Subtarget.useDeprecatedV8Instructions()">;
48 //===----------------------------------------------------------------------===//
49 // Instruction Pattern Stuff
50 //===----------------------------------------------------------------------===//
52 def simm11 : PatLeaf<(imm), [{ return isInt<11>(N->getSExtValue()); }]>;
54 def simm13 : PatLeaf<(imm), [{ return isInt<13>(N->getSExtValue()); }]>;
56 def LO10 : SDNodeXForm<imm, [{
57 return CurDAG->getTargetConstant((unsigned)N->getZExtValue() & 1023,
61 def HI22 : SDNodeXForm<imm, [{
62 // Transformation function: shift the immediate value down into the low bits.
63 return CurDAG->getTargetConstant((unsigned)N->getZExtValue() >> 10, MVT::i32);
66 def SETHIimm : PatLeaf<(imm), [{
67 return isShiftedUInt<22, 10>(N->getZExtValue());
71 def ADDRrr : ComplexPattern<iPTR, 2, "SelectADDRrr", [], []>;
72 def ADDRri : ComplexPattern<iPTR, 2, "SelectADDRri", [frameindex], []>;
75 def MEMrr : Operand<iPTR> {
76 let PrintMethod = "printMemOperand";
77 let MIOperandInfo = (ops ptr_rc, ptr_rc);
79 def MEMri : Operand<iPTR> {
80 let PrintMethod = "printMemOperand";
81 let MIOperandInfo = (ops ptr_rc, i32imm);
84 // Branch targets have OtherVT type.
85 def brtarget : Operand<OtherVT>;
86 def calltarget : Operand<i32>;
88 // Operand for printing out a condition code.
89 let PrintMethod = "printCCOperand" in
90 def CCOp : Operand<i32>;
93 SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisSameAs<0, 1>]>;
95 SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
97 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>]>;
99 SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
101 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
103 def SPcmpicc : SDNode<"SPISD::CMPICC", SDTIntBinOp, [SDNPOutGlue]>;
104 def SPcmpfcc : SDNode<"SPISD::CMPFCC", SDTSPcmpfcc, [SDNPOutGlue]>;
105 def SPbricc : SDNode<"SPISD::BRICC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
106 def SPbrxcc : SDNode<"SPISD::BRXCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
107 def SPbrfcc : SDNode<"SPISD::BRFCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
109 def SPhi : SDNode<"SPISD::Hi", SDTIntUnaryOp>;
110 def SPlo : SDNode<"SPISD::Lo", SDTIntUnaryOp>;
112 def SPftoi : SDNode<"SPISD::FTOI", SDTSPFTOI>;
113 def SPitof : SDNode<"SPISD::ITOF", SDTSPITOF>;
115 def SPselecticc : SDNode<"SPISD::SELECT_ICC", SDTSPselectcc, [SDNPInGlue]>;
116 def SPselectxcc : SDNode<"SPISD::SELECT_XCC", SDTSPselectcc, [SDNPInGlue]>;
117 def SPselectfcc : SDNode<"SPISD::SELECT_FCC", SDTSPselectcc, [SDNPInGlue]>;
119 // These are target-independent nodes, but have target-specific formats.
120 def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
121 def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
124 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart,
125 [SDNPHasChain, SDNPOutGlue]>;
126 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd,
127 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
129 def SDT_SPCall : SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>;
130 def call : SDNode<"SPISD::CALL", SDT_SPCall,
131 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
134 def SDT_SPRet : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
135 def retflag : SDNode<"SPISD::RET_FLAG", SDT_SPRet,
136 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
138 def flushw : SDNode<"SPISD::FLUSHW", SDTNone,
139 [SDNPHasChain, SDNPSideEffect, SDNPMayStore]>;
141 def getPCX : Operand<i32> {
142 let PrintMethod = "printGetPCX";
145 //===----------------------------------------------------------------------===//
146 // SPARC Flag Conditions
147 //===----------------------------------------------------------------------===//
149 // Note that these values must be kept in sync with the CCOp::CondCode enum
151 class ICC_VAL<int N> : PatLeaf<(i32 N)>;
152 def ICC_NE : ICC_VAL< 9>; // Not Equal
153 def ICC_E : ICC_VAL< 1>; // Equal
154 def ICC_G : ICC_VAL<10>; // Greater
155 def ICC_LE : ICC_VAL< 2>; // Less or Equal
156 def ICC_GE : ICC_VAL<11>; // Greater or Equal
157 def ICC_L : ICC_VAL< 3>; // Less
158 def ICC_GU : ICC_VAL<12>; // Greater Unsigned
159 def ICC_LEU : ICC_VAL< 4>; // Less or Equal Unsigned
160 def ICC_CC : ICC_VAL<13>; // Carry Clear/Great or Equal Unsigned
161 def ICC_CS : ICC_VAL< 5>; // Carry Set/Less Unsigned
162 def ICC_POS : ICC_VAL<14>; // Positive
163 def ICC_NEG : ICC_VAL< 6>; // Negative
164 def ICC_VC : ICC_VAL<15>; // Overflow Clear
165 def ICC_VS : ICC_VAL< 7>; // Overflow Set
167 class FCC_VAL<int N> : PatLeaf<(i32 N)>;
168 def FCC_U : FCC_VAL<23>; // Unordered
169 def FCC_G : FCC_VAL<22>; // Greater
170 def FCC_UG : FCC_VAL<21>; // Unordered or Greater
171 def FCC_L : FCC_VAL<20>; // Less
172 def FCC_UL : FCC_VAL<19>; // Unordered or Less
173 def FCC_LG : FCC_VAL<18>; // Less or Greater
174 def FCC_NE : FCC_VAL<17>; // Not Equal
175 def FCC_E : FCC_VAL<25>; // Equal
176 def FCC_UE : FCC_VAL<24>; // Unordered or Equal
177 def FCC_GE : FCC_VAL<25>; // Greater or Equal
178 def FCC_UGE : FCC_VAL<26>; // Unordered or Greater or Equal
179 def FCC_LE : FCC_VAL<27>; // Less or Equal
180 def FCC_ULE : FCC_VAL<28>; // Unordered or Less or Equal
181 def FCC_O : FCC_VAL<29>; // Ordered
183 //===----------------------------------------------------------------------===//
184 // Instruction Class Templates
185 //===----------------------------------------------------------------------===//
187 /// F3_12 multiclass - Define a normal F3_1/F3_2 pattern in one shot.
188 multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode> {
189 def rr : F3_1<2, Op3Val,
190 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
191 !strconcat(OpcStr, " $b, $c, $dst"),
192 [(set i32:$dst, (OpNode i32:$b, i32:$c))]>;
193 def ri : F3_2<2, Op3Val,
194 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
195 !strconcat(OpcStr, " $b, $c, $dst"),
196 [(set i32:$dst, (OpNode i32:$b, (i32 simm13:$c)))]>;
199 /// F3_12np multiclass - Define a normal F3_1/F3_2 pattern in one shot, with no
201 multiclass F3_12np<string OpcStr, bits<6> Op3Val> {
202 def rr : F3_1<2, Op3Val,
203 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
204 !strconcat(OpcStr, " $b, $c, $dst"), []>;
205 def ri : F3_2<2, Op3Val,
206 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
207 !strconcat(OpcStr, " $b, $c, $dst"), []>;
210 //===----------------------------------------------------------------------===//
212 //===----------------------------------------------------------------------===//
214 // Pseudo instructions.
215 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
216 : InstSP<outs, ins, asmstr, pattern>;
220 def GETPCX : Pseudo<(outs getPCX:$getpcseq), (ins), "$getpcseq", [] >;
223 let Defs = [O6], Uses = [O6] in {
224 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
225 "!ADJCALLSTACKDOWN $amt",
226 [(callseq_start timm:$amt)]>;
227 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
228 "!ADJCALLSTACKUP $amt1",
229 [(callseq_end timm:$amt1, timm:$amt2)]>;
232 let hasSideEffects = 1, mayStore = 1 in {
233 let rd = 0, rs1 = 0, rs2 = 0 in
234 def FLUSHW : F3_1<0b10, 0b101011, (outs), (ins),
236 [(flushw)]>, Requires<[HasV9]>;
237 let rd = 0, rs1 = 1, simm13 = 3 in
238 def TA3 : F3_2<0b10, 0b111010, (outs), (ins),
243 def UNIMP : F2_1<0b000, (outs), (ins i32imm:$val),
246 // FpMOVD/FpNEGD/FpABSD - These are lowered to single-precision ops by the
248 let Predicates = [HasNoV9] in { // Only emit these in V8 mode.
249 def FpMOVD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src),
250 "!FpMOVD $src, $dst", []>;
251 def FpNEGD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src),
252 "!FpNEGD $src, $dst",
253 [(set f64:$dst, (fneg f64:$src))]>;
254 def FpABSD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src),
255 "!FpABSD $src, $dst",
256 [(set f64:$dst, (fabs f64:$src))]>;
259 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
260 // instruction selection into a branch sequence. This has to handle all
261 // permutations of selection between i32/f32/f64 on ICC and FCC.
262 // Expanded after instruction selection.
263 let Uses = [ICC], usesCustomInserter = 1 in {
264 def SELECT_CC_Int_ICC
265 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
266 "; SELECT_CC_Int_ICC PSEUDO!",
267 [(set i32:$dst, (SPselecticc i32:$T, i32:$F, imm:$Cond))]>;
269 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
270 "; SELECT_CC_FP_ICC PSEUDO!",
271 [(set f32:$dst, (SPselecticc f32:$T, f32:$F, imm:$Cond))]>;
273 def SELECT_CC_DFP_ICC
274 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
275 "; SELECT_CC_DFP_ICC PSEUDO!",
276 [(set f64:$dst, (SPselecticc f64:$T, f64:$F, imm:$Cond))]>;
279 let usesCustomInserter = 1, Uses = [FCC] in {
281 def SELECT_CC_Int_FCC
282 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
283 "; SELECT_CC_Int_FCC PSEUDO!",
284 [(set i32:$dst, (SPselectfcc i32:$T, i32:$F, imm:$Cond))]>;
287 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
288 "; SELECT_CC_FP_FCC PSEUDO!",
289 [(set f32:$dst, (SPselectfcc f32:$T, f32:$F, imm:$Cond))]>;
290 def SELECT_CC_DFP_FCC
291 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
292 "; SELECT_CC_DFP_FCC PSEUDO!",
293 [(set f64:$dst, (SPselectfcc f64:$T, f64:$F, imm:$Cond))]>;
297 // Section A.3 - Synthetic Instructions, p. 85
298 // special cases of JMPL:
299 let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, isBarrier = 1 in {
300 let rd = O7.Num, rs1 = G0.Num in
301 def RETL: F3_2<2, 0b111000, (outs), (ins i32imm:$val),
302 "jmp %o7+$val", [(retflag simm13:$val)]>;
304 let rd = I7.Num, rs1 = G0.Num in
305 def RET: F3_2<2, 0b111000, (outs), (ins i32imm:$val),
309 // Section B.1 - Load Integer Instructions, p. 90
310 def LDSBrr : F3_1<3, 0b001001,
311 (outs IntRegs:$dst), (ins MEMrr:$addr),
312 "ldsb [$addr], $dst",
313 [(set i32:$dst, (sextloadi8 ADDRrr:$addr))]>;
314 def LDSBri : F3_2<3, 0b001001,
315 (outs IntRegs:$dst), (ins MEMri:$addr),
316 "ldsb [$addr], $dst",
317 [(set i32:$dst, (sextloadi8 ADDRri:$addr))]>;
318 def LDSHrr : F3_1<3, 0b001010,
319 (outs IntRegs:$dst), (ins MEMrr:$addr),
320 "ldsh [$addr], $dst",
321 [(set i32:$dst, (sextloadi16 ADDRrr:$addr))]>;
322 def LDSHri : F3_2<3, 0b001010,
323 (outs IntRegs:$dst), (ins MEMri:$addr),
324 "ldsh [$addr], $dst",
325 [(set i32:$dst, (sextloadi16 ADDRri:$addr))]>;
326 def LDUBrr : F3_1<3, 0b000001,
327 (outs IntRegs:$dst), (ins MEMrr:$addr),
328 "ldub [$addr], $dst",
329 [(set i32:$dst, (zextloadi8 ADDRrr:$addr))]>;
330 def LDUBri : F3_2<3, 0b000001,
331 (outs IntRegs:$dst), (ins MEMri:$addr),
332 "ldub [$addr], $dst",
333 [(set i32:$dst, (zextloadi8 ADDRri:$addr))]>;
334 def LDUHrr : F3_1<3, 0b000010,
335 (outs IntRegs:$dst), (ins MEMrr:$addr),
336 "lduh [$addr], $dst",
337 [(set i32:$dst, (zextloadi16 ADDRrr:$addr))]>;
338 def LDUHri : F3_2<3, 0b000010,
339 (outs IntRegs:$dst), (ins MEMri:$addr),
340 "lduh [$addr], $dst",
341 [(set i32:$dst, (zextloadi16 ADDRri:$addr))]>;
342 def LDrr : F3_1<3, 0b000000,
343 (outs IntRegs:$dst), (ins MEMrr:$addr),
345 [(set i32:$dst, (load ADDRrr:$addr))]>;
346 def LDri : F3_2<3, 0b000000,
347 (outs IntRegs:$dst), (ins MEMri:$addr),
349 [(set i32:$dst, (load ADDRri:$addr))]>;
351 // Section B.2 - Load Floating-point Instructions, p. 92
352 def LDFrr : F3_1<3, 0b100000,
353 (outs FPRegs:$dst), (ins MEMrr:$addr),
355 [(set f32:$dst, (load ADDRrr:$addr))]>;
356 def LDFri : F3_2<3, 0b100000,
357 (outs FPRegs:$dst), (ins MEMri:$addr),
359 [(set f32:$dst, (load ADDRri:$addr))]>;
360 def LDDFrr : F3_1<3, 0b100011,
361 (outs DFPRegs:$dst), (ins MEMrr:$addr),
363 [(set f64:$dst, (load ADDRrr:$addr))]>;
364 def LDDFri : F3_2<3, 0b100011,
365 (outs DFPRegs:$dst), (ins MEMri:$addr),
367 [(set f64:$dst, (load ADDRri:$addr))]>;
369 // Section B.4 - Store Integer Instructions, p. 95
370 def STBrr : F3_1<3, 0b000101,
371 (outs), (ins MEMrr:$addr, IntRegs:$src),
373 [(truncstorei8 i32:$src, ADDRrr:$addr)]>;
374 def STBri : F3_2<3, 0b000101,
375 (outs), (ins MEMri:$addr, IntRegs:$src),
377 [(truncstorei8 i32:$src, ADDRri:$addr)]>;
378 def STHrr : F3_1<3, 0b000110,
379 (outs), (ins MEMrr:$addr, IntRegs:$src),
381 [(truncstorei16 i32:$src, ADDRrr:$addr)]>;
382 def STHri : F3_2<3, 0b000110,
383 (outs), (ins MEMri:$addr, IntRegs:$src),
385 [(truncstorei16 i32:$src, ADDRri:$addr)]>;
386 def STrr : F3_1<3, 0b000100,
387 (outs), (ins MEMrr:$addr, IntRegs:$src),
389 [(store i32:$src, ADDRrr:$addr)]>;
390 def STri : F3_2<3, 0b000100,
391 (outs), (ins MEMri:$addr, IntRegs:$src),
393 [(store i32:$src, ADDRri:$addr)]>;
395 // Section B.5 - Store Floating-point Instructions, p. 97
396 def STFrr : F3_1<3, 0b100100,
397 (outs), (ins MEMrr:$addr, FPRegs:$src),
399 [(store f32:$src, ADDRrr:$addr)]>;
400 def STFri : F3_2<3, 0b100100,
401 (outs), (ins MEMri:$addr, FPRegs:$src),
403 [(store f32:$src, ADDRri:$addr)]>;
404 def STDFrr : F3_1<3, 0b100111,
405 (outs), (ins MEMrr:$addr, DFPRegs:$src),
407 [(store f64:$src, ADDRrr:$addr)]>;
408 def STDFri : F3_2<3, 0b100111,
409 (outs), (ins MEMri:$addr, DFPRegs:$src),
411 [(store f64:$src, ADDRri:$addr)]>;
413 // Section B.9 - SETHI Instruction, p. 104
414 def SETHIi: F2_1<0b100,
415 (outs IntRegs:$dst), (ins i32imm:$src),
417 [(set i32:$dst, SETHIimm:$src)]>;
419 // Section B.10 - NOP Instruction, p. 105
420 // (It's a special case of SETHI)
421 let rd = 0, imm22 = 0 in
422 def NOP : F2_1<0b100, (outs), (ins), "nop", []>;
424 // Section B.11 - Logical Instructions, p. 106
425 defm AND : F3_12<"and", 0b000001, and>;
427 def ANDNrr : F3_1<2, 0b000101,
428 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
430 [(set i32:$dst, (and i32:$b, (not i32:$c)))]>;
431 def ANDNri : F3_2<2, 0b000101,
432 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
433 "andn $b, $c, $dst", []>;
435 defm OR : F3_12<"or", 0b000010, or>;
437 def ORNrr : F3_1<2, 0b000110,
438 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
440 [(set i32:$dst, (or i32:$b, (not i32:$c)))]>;
441 def ORNri : F3_2<2, 0b000110,
442 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
443 "orn $b, $c, $dst", []>;
444 defm XOR : F3_12<"xor", 0b000011, xor>;
446 def XNORrr : F3_1<2, 0b000111,
447 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
449 [(set i32:$dst, (not (xor i32:$b, i32:$c)))]>;
450 def XNORri : F3_2<2, 0b000111,
451 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
452 "xnor $b, $c, $dst", []>;
454 // Section B.12 - Shift Instructions, p. 107
455 defm SLL : F3_12<"sll", 0b100101, shl>;
456 defm SRL : F3_12<"srl", 0b100110, srl>;
457 defm SRA : F3_12<"sra", 0b100111, sra>;
459 // Section B.13 - Add Instructions, p. 108
460 defm ADD : F3_12<"add", 0b000000, add>;
462 // "LEA" forms of add (patterns to make tblgen happy)
463 def LEA_ADDri : F3_2<2, 0b000000,
464 (outs IntRegs:$dst), (ins MEMri:$addr),
465 "add ${addr:arith}, $dst",
466 [(set iPTR:$dst, ADDRri:$addr)]>;
469 defm ADDCC : F3_12<"addcc", 0b010000, addc>;
472 defm ADDX : F3_12<"addx", 0b001000, adde>;
474 // Section B.15 - Subtract Instructions, p. 110
475 defm SUB : F3_12 <"sub" , 0b000100, sub>;
477 defm SUBX : F3_12 <"subx" , 0b001100, sube>;
480 defm SUBCC : F3_12 <"subcc", 0b010100, SPcmpicc>;
482 let Uses = [ICC], Defs = [ICC] in
483 def SUBXCCrr: F3_1<2, 0b011100,
484 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
485 "subxcc $b, $c, $dst", []>;
488 // Section B.18 - Multiply Instructions, p. 113
490 defm UMUL : F3_12np<"umul", 0b001010>;
491 defm SMUL : F3_12 <"smul", 0b001011, mul>;
494 // Section B.19 - Divide Instructions, p. 115
496 defm UDIV : F3_12np<"udiv", 0b001110>;
497 defm SDIV : F3_12np<"sdiv", 0b001111>;
500 // Section B.20 - SAVE and RESTORE, p. 117
501 defm SAVE : F3_12np<"save" , 0b111100>;
502 defm RESTORE : F3_12np<"restore", 0b111101>;
504 // Section B.21 - Branch on Integer Condition Codes Instructions, p. 119
506 // conditional branch class:
507 class BranchSP<bits<4> cc, dag ins, string asmstr, list<dag> pattern>
508 : F2_2<cc, 0b010, (outs), ins, asmstr, pattern> {
510 let isTerminator = 1;
511 let hasDelaySlot = 1;
515 def BA : BranchSP<0b1000, (ins brtarget:$dst),
519 // Indirect branch instructions.
520 let isTerminator = 1, isBarrier = 1,
521 hasDelaySlot = 1, isBranch =1,
522 isIndirectBranch = 1 in {
523 def BINDrr : F3_1<2, 0b111000,
524 (outs), (ins MEMrr:$ptr),
526 [(brind ADDRrr:$ptr)]>;
527 def BINDri : F3_2<2, 0b111000,
528 (outs), (ins MEMri:$ptr),
530 [(brind ADDRri:$ptr)]>;
533 // FIXME: the encoding for the JIT should look at the condition field.
535 def BCOND : BranchSP<0, (ins brtarget:$dst, CCOp:$cc),
537 [(SPbricc bb:$dst, imm:$cc)]>;
540 // Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121
542 // floating-point conditional branch class:
543 class FPBranchSP<bits<4> cc, dag ins, string asmstr, list<dag> pattern>
544 : F2_2<cc, 0b110, (outs), ins, asmstr, pattern> {
546 let isTerminator = 1;
547 let hasDelaySlot = 1;
550 // FIXME: the encoding for the JIT should look at the condition field.
552 def FBCOND : FPBranchSP<0, (ins brtarget:$dst, CCOp:$cc),
554 [(SPbrfcc bb:$dst, imm:$cc)]>;
557 // Section B.24 - Call and Link Instruction, p. 125
558 // This is the only Format 1 instruction
560 hasDelaySlot = 1, isCall = 1,
561 Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7,
562 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
564 def CALL : InstSP<(outs), (ins calltarget:$dst, variable_ops),
568 let Inst{29-0} = disp;
572 def JMPLrr : F3_1<2, 0b111000,
573 (outs), (ins MEMrr:$ptr, variable_ops),
575 [(call ADDRrr:$ptr)]>;
576 def JMPLri : F3_2<2, 0b111000,
577 (outs), (ins MEMri:$ptr, variable_ops),
579 [(call ADDRri:$ptr)]>;
582 // Section B.28 - Read State Register Instructions
584 def RDY : F3_1<2, 0b101000,
585 (outs IntRegs:$dst), (ins),
588 // Section B.29 - Write State Register Instructions
590 def WRYrr : F3_1<2, 0b110000,
591 (outs), (ins IntRegs:$b, IntRegs:$c),
592 "wr $b, $c, %y", []>;
593 def WRYri : F3_2<2, 0b110000,
594 (outs), (ins IntRegs:$b, i32imm:$c),
595 "wr $b, $c, %y", []>;
597 // Convert Integer to Floating-point Instructions, p. 141
598 def FITOS : F3_3<2, 0b110100, 0b011000100,
599 (outs FPRegs:$dst), (ins FPRegs:$src),
601 [(set FPRegs:$dst, (SPitof FPRegs:$src))]>;
602 def FITOD : F3_3<2, 0b110100, 0b011001000,
603 (outs DFPRegs:$dst), (ins FPRegs:$src),
605 [(set DFPRegs:$dst, (SPitof FPRegs:$src))]>;
607 // Convert Floating-point to Integer Instructions, p. 142
608 def FSTOI : F3_3<2, 0b110100, 0b011010001,
609 (outs FPRegs:$dst), (ins FPRegs:$src),
611 [(set FPRegs:$dst, (SPftoi FPRegs:$src))]>;
612 def FDTOI : F3_3<2, 0b110100, 0b011010010,
613 (outs FPRegs:$dst), (ins DFPRegs:$src),
615 [(set FPRegs:$dst, (SPftoi DFPRegs:$src))]>;
617 // Convert between Floating-point Formats Instructions, p. 143
618 def FSTOD : F3_3<2, 0b110100, 0b011001001,
619 (outs DFPRegs:$dst), (ins FPRegs:$src),
621 [(set f64:$dst, (fextend f32:$src))]>;
622 def FDTOS : F3_3<2, 0b110100, 0b011000110,
623 (outs FPRegs:$dst), (ins DFPRegs:$src),
625 [(set f32:$dst, (fround f64:$src))]>;
627 // Floating-point Move Instructions, p. 144
628 def FMOVS : F3_3<2, 0b110100, 0b000000001,
629 (outs FPRegs:$dst), (ins FPRegs:$src),
630 "fmovs $src, $dst", []>;
631 def FNEGS : F3_3<2, 0b110100, 0b000000101,
632 (outs FPRegs:$dst), (ins FPRegs:$src),
634 [(set f32:$dst, (fneg f32:$src))]>;
635 def FABSS : F3_3<2, 0b110100, 0b000001001,
636 (outs FPRegs:$dst), (ins FPRegs:$src),
638 [(set f32:$dst, (fabs f32:$src))]>;
641 // Floating-point Square Root Instructions, p.145
642 def FSQRTS : F3_3<2, 0b110100, 0b000101001,
643 (outs FPRegs:$dst), (ins FPRegs:$src),
645 [(set f32:$dst, (fsqrt f32:$src))]>;
646 def FSQRTD : F3_3<2, 0b110100, 0b000101010,
647 (outs DFPRegs:$dst), (ins DFPRegs:$src),
649 [(set f64:$dst, (fsqrt f64:$src))]>;
653 // Floating-point Add and Subtract Instructions, p. 146
654 def FADDS : F3_3<2, 0b110100, 0b001000001,
655 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
656 "fadds $src1, $src2, $dst",
657 [(set f32:$dst, (fadd f32:$src1, f32:$src2))]>;
658 def FADDD : F3_3<2, 0b110100, 0b001000010,
659 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
660 "faddd $src1, $src2, $dst",
661 [(set f64:$dst, (fadd f64:$src1, f64:$src2))]>;
662 def FSUBS : F3_3<2, 0b110100, 0b001000101,
663 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
664 "fsubs $src1, $src2, $dst",
665 [(set f32:$dst, (fsub f32:$src1, f32:$src2))]>;
666 def FSUBD : F3_3<2, 0b110100, 0b001000110,
667 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
668 "fsubd $src1, $src2, $dst",
669 [(set f64:$dst, (fsub f64:$src1, f64:$src2))]>;
671 // Floating-point Multiply and Divide Instructions, p. 147
672 def FMULS : F3_3<2, 0b110100, 0b001001001,
673 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
674 "fmuls $src1, $src2, $dst",
675 [(set f32:$dst, (fmul f32:$src1, f32:$src2))]>;
676 def FMULD : F3_3<2, 0b110100, 0b001001010,
677 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
678 "fmuld $src1, $src2, $dst",
679 [(set f64:$dst, (fmul f64:$src1, f64:$src2))]>;
680 def FSMULD : F3_3<2, 0b110100, 0b001101001,
681 (outs DFPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
682 "fsmuld $src1, $src2, $dst",
683 [(set f64:$dst, (fmul (fextend f32:$src1),
684 (fextend f32:$src2)))]>;
685 def FDIVS : F3_3<2, 0b110100, 0b001001101,
686 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
687 "fdivs $src1, $src2, $dst",
688 [(set f32:$dst, (fdiv f32:$src1, f32:$src2))]>;
689 def FDIVD : F3_3<2, 0b110100, 0b001001110,
690 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
691 "fdivd $src1, $src2, $dst",
692 [(set f64:$dst, (fdiv f64:$src1, f64:$src2))]>;
694 // Floating-point Compare Instructions, p. 148
695 // Note: the 2nd template arg is different for these guys.
696 // Note 2: the result of a FCMP is not available until the 2nd cycle
697 // after the instr is retired, but there is no interlock. This behavior
698 // is modelled with a forced noop after the instruction.
699 let Defs = [FCC] in {
700 def FCMPS : F3_3<2, 0b110101, 0b001010001,
701 (outs), (ins FPRegs:$src1, FPRegs:$src2),
702 "fcmps $src1, $src2\n\tnop",
703 [(SPcmpfcc f32:$src1, f32:$src2)]>;
704 def FCMPD : F3_3<2, 0b110101, 0b001010010,
705 (outs), (ins DFPRegs:$src1, DFPRegs:$src2),
706 "fcmpd $src1, $src2\n\tnop",
707 [(SPcmpfcc f64:$src1, f64:$src2)]>;
710 //===----------------------------------------------------------------------===//
712 //===----------------------------------------------------------------------===//
714 // V9 Conditional Moves.
715 let Predicates = [HasV9], Constraints = "$f = $rd" in {
716 // Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual.
717 // FIXME: Add instruction encodings for the JIT some day.
718 let Uses = [ICC] in {
720 : Pseudo<(outs IntRegs:$rd), (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cc),
721 "mov$cc %icc, $rs2, $rd",
722 [(set i32:$rd, (SPselecticc i32:$rs2, i32:$f, imm:$cc))]>;
724 : Pseudo<(outs IntRegs:$rd), (ins i32imm:$i, IntRegs:$f, CCOp:$cc),
725 "mov$cc %icc, $i, $rd",
726 [(set i32:$rd, (SPselecticc simm11:$i, i32:$f, imm:$cc))]>;
729 let Uses = [FCC] in {
731 : Pseudo<(outs IntRegs:$rd), (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cc),
732 "mov$cc %fcc0, $rs2, $rd",
733 [(set i32:$rd, (SPselectfcc i32:$rs2, i32:$f, imm:$cc))]>;
735 : Pseudo<(outs IntRegs:$rd), (ins i32imm:$i, IntRegs:$f, CCOp:$cc),
736 "mov$cc %fcc0, $i, $rd",
737 [(set i32:$rd, (SPselectfcc simm11:$i, i32:$f, imm:$cc))]>;
740 let Uses = [ICC] in {
742 : Pseudo<(outs FPRegs:$rd), (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cc),
743 "fmovs$cc %icc, $rs2, $rd",
744 [(set f32:$rd, (SPselecticc f32:$rs2, f32:$f, imm:$cc))]>;
746 : Pseudo<(outs DFPRegs:$rd), (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cc),
747 "fmovd$cc %icc, $rs2, $rd",
748 [(set f64:$rd, (SPselecticc f64:$rs2, f64:$f, imm:$cc))]>;
751 let Uses = [FCC] in {
753 : Pseudo<(outs FPRegs:$rd), (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cc),
754 "fmovs$cc %fcc0, $rs2, $rd",
755 [(set f32:$rd, (SPselectfcc f32:$rs2, f32:$f, imm:$cc))]>;
757 : Pseudo<(outs DFPRegs:$rd), (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cc),
758 "fmovd$cc %fcc0, $rs2, $rd",
759 [(set f64:$rd, (SPselectfcc f64:$rs2, f64:$f, imm:$cc))]>;
764 // Floating-Point Move Instructions, p. 164 of the V9 manual.
765 let Predicates = [HasV9] in {
766 def FMOVD : F3_3<2, 0b110100, 0b000000010,
767 (outs DFPRegs:$dst), (ins DFPRegs:$src),
768 "fmovd $src, $dst", []>;
769 def FNEGD : F3_3<2, 0b110100, 0b000000110,
770 (outs DFPRegs:$dst), (ins DFPRegs:$src),
772 [(set f64:$dst, (fneg f64:$src))]>;
773 def FABSD : F3_3<2, 0b110100, 0b000001010,
774 (outs DFPRegs:$dst), (ins DFPRegs:$src),
776 [(set f64:$dst, (fabs f64:$src))]>;
779 // POPCrr - This does a ctpop of a 64-bit register. As such, we have to clear
780 // the top 32-bits before using it. To do this clearing, we use a SLLri X,0.
781 def POPCrr : F3_1<2, 0b101110,
782 (outs IntRegs:$dst), (ins IntRegs:$src),
783 "popc $src, $dst", []>, Requires<[HasV9]>;
784 def : Pat<(ctpop i32:$src),
785 (POPCrr (SLLri $src, 0))>;
787 //===----------------------------------------------------------------------===//
788 // Non-Instruction Patterns
789 //===----------------------------------------------------------------------===//
792 def : Pat<(i32 simm13:$val),
793 (ORri (i32 G0), imm:$val)>;
794 // Arbitrary immediates.
795 def : Pat<(i32 imm:$val),
796 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;
799 def : Pat<(subc i32:$b, i32:$c),
801 def : Pat<(subc i32:$b, simm13:$val),
802 (SUBCCri $b, imm:$val)>;
804 // Global addresses, constant pool entries
805 def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>;
806 def : Pat<(SPlo tglobaladdr:$in), (ORri (i32 G0), tglobaladdr:$in)>;
807 def : Pat<(SPhi tconstpool:$in), (SETHIi tconstpool:$in)>;
808 def : Pat<(SPlo tconstpool:$in), (ORri (i32 G0), tconstpool:$in)>;
811 def : Pat<(SPhi tblockaddress:$in), (SETHIi tblockaddress:$in)>;
812 def : Pat<(SPlo tblockaddress:$in), (ORri (i32 G0), tblockaddress:$in)>;
814 // Add reg, lo. This is used when taking the addr of a global/constpool entry.
815 def : Pat<(add iPTR:$r, (SPlo tglobaladdr:$in)), (ADDri $r, tglobaladdr:$in)>;
816 def : Pat<(add iPTR:$r, (SPlo tconstpool:$in)), (ADDri $r, tconstpool:$in)>;
817 def : Pat<(add iPTR:$r, (SPlo tblockaddress:$in)),
818 (ADDri $r, tblockaddress:$in)>;
821 def : Pat<(call tglobaladdr:$dst),
822 (CALL tglobaladdr:$dst)>;
823 def : Pat<(call texternalsym:$dst),
824 (CALL texternalsym:$dst)>;
826 // Map integer extload's to zextloads.
827 def : Pat<(i32 (extloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
828 def : Pat<(i32 (extloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>;
829 def : Pat<(i32 (extloadi8 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
830 def : Pat<(i32 (extloadi8 ADDRri:$src)), (LDUBri ADDRri:$src)>;
831 def : Pat<(i32 (extloadi16 ADDRrr:$src)), (LDUHrr ADDRrr:$src)>;
832 def : Pat<(i32 (extloadi16 ADDRri:$src)), (LDUHri ADDRri:$src)>;
834 // zextload bool -> zextload byte
835 def : Pat<(i32 (zextloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
836 def : Pat<(i32 (zextloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>;
838 // store 0, addr -> store %g0, addr
839 def : Pat<(store (i32 0), ADDRrr:$dst), (STrr ADDRrr:$dst, (i32 G0))>;
840 def : Pat<(store (i32 0), ADDRri:$dst), (STri ADDRri:$dst, (i32 G0))>;
842 include "SparcInstr64Bit.td"