1 //===-- SparcInstrInfo.td - Target Description for Sparc Target -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Sparc instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Instruction format superclass
16 //===----------------------------------------------------------------------===//
18 include "SparcInstrFormats.td"
20 //===----------------------------------------------------------------------===//
21 // Feature predicates.
22 //===----------------------------------------------------------------------===//
24 // True when generating 32-bit code.
25 def Is32Bit : Predicate<"!Subtarget.is64Bit()">;
27 // True when generating 64-bit code. This also implies HasV9.
28 def Is64Bit : Predicate<"Subtarget.is64Bit()">;
30 // HasV9 - This predicate is true when the target processor supports V9
31 // instructions. Note that the machine may be running in 32-bit mode.
32 def HasV9 : Predicate<"Subtarget.isV9()">;
34 // HasNoV9 - This predicate is true when the target doesn't have V9
35 // instructions. Use of this is just a hack for the isel not having proper
36 // costs for V8 instructions that are more expensive than their V9 ones.
37 def HasNoV9 : Predicate<"!Subtarget.isV9()">;
39 // HasVIS - This is true when the target processor has VIS extensions.
40 def HasVIS : Predicate<"Subtarget.isVIS()">;
42 // HasHardQuad - This is true when the target processor supports quad floating
43 // point instructions.
44 def HasHardQuad : Predicate<"Subtarget.hasHardQuad()">;
46 // UseDeprecatedInsts - This predicate is true when the target processor is a
47 // V8, or when it is V9 but the V8 deprecated instructions are efficient enough
48 // to use when appropriate. In either of these cases, the instruction selector
49 // will pick deprecated instructions.
50 def UseDeprecatedInsts : Predicate<"Subtarget.useDeprecatedV8Instructions()">;
52 //===----------------------------------------------------------------------===//
53 // Instruction Pattern Stuff
54 //===----------------------------------------------------------------------===//
56 def simm11 : PatLeaf<(imm), [{ return isInt<11>(N->getSExtValue()); }]>;
58 def simm13 : PatLeaf<(imm), [{ return isInt<13>(N->getSExtValue()); }]>;
60 def LO10 : SDNodeXForm<imm, [{
61 return CurDAG->getTargetConstant((unsigned)N->getZExtValue() & 1023,
65 def HI22 : SDNodeXForm<imm, [{
66 // Transformation function: shift the immediate value down into the low bits.
67 return CurDAG->getTargetConstant((unsigned)N->getZExtValue() >> 10, MVT::i32);
70 def SETHIimm : PatLeaf<(imm), [{
71 return isShiftedUInt<22, 10>(N->getZExtValue());
75 def ADDRrr : ComplexPattern<iPTR, 2, "SelectADDRrr", [], []>;
76 def ADDRri : ComplexPattern<iPTR, 2, "SelectADDRri", [frameindex], []>;
79 def MEMrr : Operand<iPTR> {
80 let PrintMethod = "printMemOperand";
81 let MIOperandInfo = (ops ptr_rc, ptr_rc);
83 def MEMri : Operand<iPTR> {
84 let PrintMethod = "printMemOperand";
85 let MIOperandInfo = (ops ptr_rc, i32imm);
88 def TLSSym : Operand<iPTR>;
90 // Branch targets have OtherVT type.
91 def brtarget : Operand<OtherVT>;
92 def calltarget : Operand<i32>;
94 // Operand for printing out a condition code.
95 let PrintMethod = "printCCOperand" in
96 def CCOp : Operand<i32>;
99 SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
101 SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisSameAs<0, 1>]>;
103 SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
105 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>]>;
107 SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
109 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
111 SDTypeProfile<1, 1, [SDTCisVT<0, f64>, SDTCisFP<1>]>;
113 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f64>]>;
116 SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, SDTCisPtrTy<2>]>;
118 SDTypeProfile<1, 2, [SDTCisPtrTy<0>, SDTCisPtrTy<1>]>;
120 def SPcmpicc : SDNode<"SPISD::CMPICC", SDTSPcmpicc, [SDNPOutGlue]>;
121 def SPcmpfcc : SDNode<"SPISD::CMPFCC", SDTSPcmpfcc, [SDNPOutGlue]>;
122 def SPbricc : SDNode<"SPISD::BRICC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
123 def SPbrxcc : SDNode<"SPISD::BRXCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
124 def SPbrfcc : SDNode<"SPISD::BRFCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
126 def SPhi : SDNode<"SPISD::Hi", SDTIntUnaryOp>;
127 def SPlo : SDNode<"SPISD::Lo", SDTIntUnaryOp>;
129 def SPftoi : SDNode<"SPISD::FTOI", SDTSPFTOI>;
130 def SPitof : SDNode<"SPISD::ITOF", SDTSPITOF>;
131 def SPftox : SDNode<"SPISD::FTOX", SDTSPFTOX>;
132 def SPxtof : SDNode<"SPISD::XTOF", SDTSPXTOF>;
134 def SPselecticc : SDNode<"SPISD::SELECT_ICC", SDTSPselectcc, [SDNPInGlue]>;
135 def SPselectxcc : SDNode<"SPISD::SELECT_XCC", SDTSPselectcc, [SDNPInGlue]>;
136 def SPselectfcc : SDNode<"SPISD::SELECT_FCC", SDTSPselectcc, [SDNPInGlue]>;
138 // These are target-independent nodes, but have target-specific formats.
139 def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
140 def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
143 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart,
144 [SDNPHasChain, SDNPOutGlue]>;
145 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd,
146 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
148 def SDT_SPCall : SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>;
149 def call : SDNode<"SPISD::CALL", SDT_SPCall,
150 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
153 def SDT_SPRet : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
154 def retflag : SDNode<"SPISD::RET_FLAG", SDT_SPRet,
155 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
157 def flushw : SDNode<"SPISD::FLUSHW", SDTNone,
158 [SDNPHasChain, SDNPSideEffect, SDNPMayStore]>;
160 def tlsadd : SDNode<"SPISD::TLS_ADD", SDTSPtlsadd>;
161 def tlsld : SDNode<"SPISD::TLS_LD", SDTSPtlsld>;
162 def tlscall : SDNode<"SPISD::TLS_CALL", SDT_SPCall,
163 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
166 def getPCX : Operand<i32> {
167 let PrintMethod = "printGetPCX";
170 //===----------------------------------------------------------------------===//
171 // SPARC Flag Conditions
172 //===----------------------------------------------------------------------===//
174 // Note that these values must be kept in sync with the CCOp::CondCode enum
176 class ICC_VAL<int N> : PatLeaf<(i32 N)>;
177 def ICC_NE : ICC_VAL< 9>; // Not Equal
178 def ICC_E : ICC_VAL< 1>; // Equal
179 def ICC_G : ICC_VAL<10>; // Greater
180 def ICC_LE : ICC_VAL< 2>; // Less or Equal
181 def ICC_GE : ICC_VAL<11>; // Greater or Equal
182 def ICC_L : ICC_VAL< 3>; // Less
183 def ICC_GU : ICC_VAL<12>; // Greater Unsigned
184 def ICC_LEU : ICC_VAL< 4>; // Less or Equal Unsigned
185 def ICC_CC : ICC_VAL<13>; // Carry Clear/Great or Equal Unsigned
186 def ICC_CS : ICC_VAL< 5>; // Carry Set/Less Unsigned
187 def ICC_POS : ICC_VAL<14>; // Positive
188 def ICC_NEG : ICC_VAL< 6>; // Negative
189 def ICC_VC : ICC_VAL<15>; // Overflow Clear
190 def ICC_VS : ICC_VAL< 7>; // Overflow Set
192 class FCC_VAL<int N> : PatLeaf<(i32 N)>;
193 def FCC_U : FCC_VAL<23>; // Unordered
194 def FCC_G : FCC_VAL<22>; // Greater
195 def FCC_UG : FCC_VAL<21>; // Unordered or Greater
196 def FCC_L : FCC_VAL<20>; // Less
197 def FCC_UL : FCC_VAL<19>; // Unordered or Less
198 def FCC_LG : FCC_VAL<18>; // Less or Greater
199 def FCC_NE : FCC_VAL<17>; // Not Equal
200 def FCC_E : FCC_VAL<25>; // Equal
201 def FCC_UE : FCC_VAL<24>; // Unordered or Equal
202 def FCC_GE : FCC_VAL<25>; // Greater or Equal
203 def FCC_UGE : FCC_VAL<26>; // Unordered or Greater or Equal
204 def FCC_LE : FCC_VAL<27>; // Less or Equal
205 def FCC_ULE : FCC_VAL<28>; // Unordered or Less or Equal
206 def FCC_O : FCC_VAL<29>; // Ordered
208 //===----------------------------------------------------------------------===//
209 // Instruction Class Templates
210 //===----------------------------------------------------------------------===//
212 /// F3_12 multiclass - Define a normal F3_1/F3_2 pattern in one shot.
213 multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode> {
214 def rr : F3_1<2, Op3Val,
215 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
216 !strconcat(OpcStr, " $b, $c, $dst"),
217 [(set i32:$dst, (OpNode i32:$b, i32:$c))]>;
218 def ri : F3_2<2, Op3Val,
219 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
220 !strconcat(OpcStr, " $b, $c, $dst"),
221 [(set i32:$dst, (OpNode i32:$b, (i32 simm13:$c)))]>;
224 /// F3_12np multiclass - Define a normal F3_1/F3_2 pattern in one shot, with no
226 multiclass F3_12np<string OpcStr, bits<6> Op3Val> {
227 def rr : F3_1<2, Op3Val,
228 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
229 !strconcat(OpcStr, " $b, $c, $dst"), []>;
230 def ri : F3_2<2, Op3Val,
231 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
232 !strconcat(OpcStr, " $b, $c, $dst"), []>;
235 //===----------------------------------------------------------------------===//
237 //===----------------------------------------------------------------------===//
239 // Pseudo instructions.
240 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
241 : InstSP<outs, ins, asmstr, pattern>;
245 def GETPCX : Pseudo<(outs getPCX:$getpcseq), (ins), "$getpcseq", [] >;
248 let Defs = [O6], Uses = [O6] in {
249 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
250 "!ADJCALLSTACKDOWN $amt",
251 [(callseq_start timm:$amt)]>;
252 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
253 "!ADJCALLSTACKUP $amt1",
254 [(callseq_end timm:$amt1, timm:$amt2)]>;
257 let hasSideEffects = 1, mayStore = 1 in {
258 let rd = 0, rs1 = 0, rs2 = 0 in
259 def FLUSHW : F3_1<0b10, 0b101011, (outs), (ins),
261 [(flushw)]>, Requires<[HasV9]>;
262 let rd = 0, rs1 = 1, simm13 = 3 in
263 def TA3 : F3_2<0b10, 0b111010, (outs), (ins),
269 def UNIMP : F2_1<0b000, (outs), (ins i32imm:$val),
272 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
273 // instruction selection into a branch sequence. This has to handle all
274 // permutations of selection between i32/f32/f64 on ICC and FCC.
275 // Expanded after instruction selection.
276 let Uses = [ICC], usesCustomInserter = 1 in {
277 def SELECT_CC_Int_ICC
278 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
279 "; SELECT_CC_Int_ICC PSEUDO!",
280 [(set i32:$dst, (SPselecticc i32:$T, i32:$F, imm:$Cond))]>;
282 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
283 "; SELECT_CC_FP_ICC PSEUDO!",
284 [(set f32:$dst, (SPselecticc f32:$T, f32:$F, imm:$Cond))]>;
286 def SELECT_CC_DFP_ICC
287 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
288 "; SELECT_CC_DFP_ICC PSEUDO!",
289 [(set f64:$dst, (SPselecticc f64:$T, f64:$F, imm:$Cond))]>;
291 def SELECT_CC_QFP_ICC
292 : Pseudo<(outs QFPRegs:$dst), (ins QFPRegs:$T, QFPRegs:$F, i32imm:$Cond),
293 "; SELECT_CC_QFP_ICC PSEUDO!",
294 [(set f128:$dst, (SPselecticc f128:$T, f128:$F, imm:$Cond))]>;
297 let usesCustomInserter = 1, Uses = [FCC] in {
299 def SELECT_CC_Int_FCC
300 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
301 "; SELECT_CC_Int_FCC PSEUDO!",
302 [(set i32:$dst, (SPselectfcc i32:$T, i32:$F, imm:$Cond))]>;
305 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
306 "; SELECT_CC_FP_FCC PSEUDO!",
307 [(set f32:$dst, (SPselectfcc f32:$T, f32:$F, imm:$Cond))]>;
308 def SELECT_CC_DFP_FCC
309 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
310 "; SELECT_CC_DFP_FCC PSEUDO!",
311 [(set f64:$dst, (SPselectfcc f64:$T, f64:$F, imm:$Cond))]>;
312 def SELECT_CC_QFP_FCC
313 : Pseudo<(outs QFPRegs:$dst), (ins QFPRegs:$T, QFPRegs:$F, i32imm:$Cond),
314 "; SELECT_CC_QFP_FCC PSEUDO!",
315 [(set f128:$dst, (SPselectfcc f128:$T, f128:$F, imm:$Cond))]>;
319 // Section A.3 - Synthetic Instructions, p. 85
320 // special cases of JMPL:
321 let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, isBarrier = 1 in {
322 let rd = 0, rs1 = 15 in
323 def RETL: F3_2<2, 0b111000, (outs), (ins i32imm:$val),
324 "jmp %o7+$val", [(retflag simm13:$val)]>;
326 let rd = 0, rs1 = 31 in
327 def RET: F3_2<2, 0b111000, (outs), (ins i32imm:$val),
331 // Section B.1 - Load Integer Instructions, p. 90
332 def LDSBrr : F3_1<3, 0b001001,
333 (outs IntRegs:$dst), (ins MEMrr:$addr),
334 "ldsb [$addr], $dst",
335 [(set i32:$dst, (sextloadi8 ADDRrr:$addr))]>;
336 def LDSBri : F3_2<3, 0b001001,
337 (outs IntRegs:$dst), (ins MEMri:$addr),
338 "ldsb [$addr], $dst",
339 [(set i32:$dst, (sextloadi8 ADDRri:$addr))]>;
340 def LDSHrr : F3_1<3, 0b001010,
341 (outs IntRegs:$dst), (ins MEMrr:$addr),
342 "ldsh [$addr], $dst",
343 [(set i32:$dst, (sextloadi16 ADDRrr:$addr))]>;
344 def LDSHri : F3_2<3, 0b001010,
345 (outs IntRegs:$dst), (ins MEMri:$addr),
346 "ldsh [$addr], $dst",
347 [(set i32:$dst, (sextloadi16 ADDRri:$addr))]>;
348 def LDUBrr : F3_1<3, 0b000001,
349 (outs IntRegs:$dst), (ins MEMrr:$addr),
350 "ldub [$addr], $dst",
351 [(set i32:$dst, (zextloadi8 ADDRrr:$addr))]>;
352 def LDUBri : F3_2<3, 0b000001,
353 (outs IntRegs:$dst), (ins MEMri:$addr),
354 "ldub [$addr], $dst",
355 [(set i32:$dst, (zextloadi8 ADDRri:$addr))]>;
356 def LDUHrr : F3_1<3, 0b000010,
357 (outs IntRegs:$dst), (ins MEMrr:$addr),
358 "lduh [$addr], $dst",
359 [(set i32:$dst, (zextloadi16 ADDRrr:$addr))]>;
360 def LDUHri : F3_2<3, 0b000010,
361 (outs IntRegs:$dst), (ins MEMri:$addr),
362 "lduh [$addr], $dst",
363 [(set i32:$dst, (zextloadi16 ADDRri:$addr))]>;
364 def LDrr : F3_1<3, 0b000000,
365 (outs IntRegs:$dst), (ins MEMrr:$addr),
367 [(set i32:$dst, (load ADDRrr:$addr))]>;
368 def LDri : F3_2<3, 0b000000,
369 (outs IntRegs:$dst), (ins MEMri:$addr),
371 [(set i32:$dst, (load ADDRri:$addr))]>;
373 // Section B.2 - Load Floating-point Instructions, p. 92
374 def LDFrr : F3_1<3, 0b100000,
375 (outs FPRegs:$dst), (ins MEMrr:$addr),
377 [(set f32:$dst, (load ADDRrr:$addr))]>;
378 def LDFri : F3_2<3, 0b100000,
379 (outs FPRegs:$dst), (ins MEMri:$addr),
381 [(set f32:$dst, (load ADDRri:$addr))]>;
382 def LDDFrr : F3_1<3, 0b100011,
383 (outs DFPRegs:$dst), (ins MEMrr:$addr),
385 [(set f64:$dst, (load ADDRrr:$addr))]>;
386 def LDDFri : F3_2<3, 0b100011,
387 (outs DFPRegs:$dst), (ins MEMri:$addr),
389 [(set f64:$dst, (load ADDRri:$addr))]>;
390 def LDQFrr : F3_1<3, 0b100010,
391 (outs QFPRegs:$dst), (ins MEMrr:$addr),
393 [(set f128:$dst, (load ADDRrr:$addr))]>,
394 Requires<[HasV9, HasHardQuad]>;
395 def LDQFri : F3_2<3, 0b100010,
396 (outs QFPRegs:$dst), (ins MEMri:$addr),
398 [(set f128:$dst, (load ADDRri:$addr))]>,
399 Requires<[HasV9, HasHardQuad]>;
401 // Section B.4 - Store Integer Instructions, p. 95
402 def STBrr : F3_1<3, 0b000101,
403 (outs), (ins MEMrr:$addr, IntRegs:$rd),
405 [(truncstorei8 i32:$rd, ADDRrr:$addr)]>;
406 def STBri : F3_2<3, 0b000101,
407 (outs), (ins MEMri:$addr, IntRegs:$rd),
409 [(truncstorei8 i32:$rd, ADDRri:$addr)]>;
410 def STHrr : F3_1<3, 0b000110,
411 (outs), (ins MEMrr:$addr, IntRegs:$rd),
413 [(truncstorei16 i32:$rd, ADDRrr:$addr)]>;
414 def STHri : F3_2<3, 0b000110,
415 (outs), (ins MEMri:$addr, IntRegs:$rd),
417 [(truncstorei16 i32:$rd, ADDRri:$addr)]>;
418 def STrr : F3_1<3, 0b000100,
419 (outs), (ins MEMrr:$addr, IntRegs:$rd),
421 [(store i32:$rd, ADDRrr:$addr)]>;
422 def STri : F3_2<3, 0b000100,
423 (outs), (ins MEMri:$addr, IntRegs:$rd),
425 [(store i32:$rd, ADDRri:$addr)]>;
427 // Section B.5 - Store Floating-point Instructions, p. 97
428 def STFrr : F3_1<3, 0b100100,
429 (outs), (ins MEMrr:$addr, FPRegs:$rd),
431 [(store f32:$rd, ADDRrr:$addr)]>;
432 def STFri : F3_2<3, 0b100100,
433 (outs), (ins MEMri:$addr, FPRegs:$rd),
435 [(store f32:$rd, ADDRri:$addr)]>;
436 def STDFrr : F3_1<3, 0b100111,
437 (outs), (ins MEMrr:$addr, DFPRegs:$rd),
439 [(store f64:$rd, ADDRrr:$addr)]>;
440 def STDFri : F3_2<3, 0b100111,
441 (outs), (ins MEMri:$addr, DFPRegs:$rd),
443 [(store f64:$rd, ADDRri:$addr)]>;
444 def STQFrr : F3_1<3, 0b100110,
445 (outs), (ins MEMrr:$addr, QFPRegs:$rd),
447 [(store f128:$rd, ADDRrr:$addr)]>,
448 Requires<[HasV9, HasHardQuad]>;
449 def STQFri : F3_2<3, 0b100110,
450 (outs), (ins MEMri:$addr, QFPRegs:$rd),
452 [(store f128:$rd, ADDRri:$addr)]>,
453 Requires<[HasV9, HasHardQuad]>;
455 // Section B.9 - SETHI Instruction, p. 104
456 def SETHIi: F2_1<0b100,
457 (outs IntRegs:$rd), (ins i32imm:$imm22),
459 [(set i32:$rd, SETHIimm:$imm22)]>;
461 // Section B.10 - NOP Instruction, p. 105
462 // (It's a special case of SETHI)
463 let rd = 0, imm22 = 0 in
464 def NOP : F2_1<0b100, (outs), (ins), "nop", []>;
466 // Section B.11 - Logical Instructions, p. 106
467 defm AND : F3_12<"and", 0b000001, and>;
469 def ANDNrr : F3_1<2, 0b000101,
470 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
472 [(set i32:$dst, (and i32:$b, (not i32:$c)))]>;
473 def ANDNri : F3_2<2, 0b000101,
474 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
475 "andn $b, $c, $dst", []>;
477 defm OR : F3_12<"or", 0b000010, or>;
479 def ORNrr : F3_1<2, 0b000110,
480 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
482 [(set i32:$dst, (or i32:$b, (not i32:$c)))]>;
483 def ORNri : F3_2<2, 0b000110,
484 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
485 "orn $b, $c, $dst", []>;
486 defm XOR : F3_12<"xor", 0b000011, xor>;
488 def XNORrr : F3_1<2, 0b000111,
489 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
491 [(set i32:$dst, (not (xor i32:$b, i32:$c)))]>;
492 def XNORri : F3_2<2, 0b000111,
493 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
494 "xnor $b, $c, $dst", []>;
496 // Section B.12 - Shift Instructions, p. 107
497 defm SLL : F3_12<"sll", 0b100101, shl>;
498 defm SRL : F3_12<"srl", 0b100110, srl>;
499 defm SRA : F3_12<"sra", 0b100111, sra>;
501 // Section B.13 - Add Instructions, p. 108
502 defm ADD : F3_12<"add", 0b000000, add>;
504 // "LEA" forms of add (patterns to make tblgen happy)
505 def LEA_ADDri : F3_2<2, 0b000000,
506 (outs IntRegs:$dst), (ins MEMri:$addr),
507 "add ${addr:arith}, $dst",
508 [(set iPTR:$dst, ADDRri:$addr)]>;
511 defm ADDCC : F3_12<"addcc", 0b010000, addc>;
513 let Uses = [ICC], Defs = [ICC] in
514 defm ADDX : F3_12<"addxcc", 0b011000, adde>;
516 // Section B.15 - Subtract Instructions, p. 110
517 defm SUB : F3_12 <"sub" , 0b000100, sub>;
518 let Uses = [ICC], Defs = [ICC] in
519 defm SUBX : F3_12 <"subxcc" , 0b011100, sube>;
522 defm SUBCC : F3_12 <"subcc", 0b010100, subc>;
524 let Defs = [ICC], rd = 0 in {
525 def CMPrr : F3_1<2, 0b010100,
526 (outs), (ins IntRegs:$b, IntRegs:$c),
528 [(SPcmpicc i32:$b, i32:$c)]>;
529 def CMPri : F3_2<2, 0b010100,
530 (outs), (ins IntRegs:$b, i32imm:$c),
532 [(SPcmpicc i32:$b, (i32 simm13:$c))]>;
535 let Uses = [ICC], Defs = [ICC] in
536 def SUBXCCrr: F3_1<2, 0b011100,
537 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
538 "subxcc $b, $c, $dst", []>;
541 // Section B.18 - Multiply Instructions, p. 113
543 defm UMUL : F3_12np<"umul", 0b001010>;
544 defm SMUL : F3_12 <"smul", 0b001011, mul>;
547 // Section B.19 - Divide Instructions, p. 115
549 defm UDIV : F3_12np<"udiv", 0b001110>;
550 defm SDIV : F3_12np<"sdiv", 0b001111>;
553 // Section B.20 - SAVE and RESTORE, p. 117
554 defm SAVE : F3_12np<"save" , 0b111100>;
555 defm RESTORE : F3_12np<"restore", 0b111101>;
557 // Section B.21 - Branch on Integer Condition Codes Instructions, p. 119
559 // unconditional branch class.
560 class BranchAlways<dag ins, string asmstr, list<dag> pattern>
561 : F2_2<0b010, (outs), ins, asmstr, pattern> {
563 let isTerminator = 1;
564 let hasDelaySlot = 1;
569 def BA : BranchAlways<(ins brtarget:$imm22), "ba $imm22", [(br bb:$imm22)]>;
571 // conditional branch class:
572 class BranchSP<dag ins, string asmstr, list<dag> pattern>
573 : F2_2<0b010, (outs), ins, asmstr, pattern> {
575 let isTerminator = 1;
576 let hasDelaySlot = 1;
579 // Indirect branch instructions.
580 let isTerminator = 1, isBarrier = 1,
581 hasDelaySlot = 1, isBranch =1,
582 isIndirectBranch = 1, rd = 0 in {
583 def BINDrr : F3_1<2, 0b111000,
584 (outs), (ins MEMrr:$ptr),
586 [(brind ADDRrr:$ptr)]>;
587 def BINDri : F3_2<2, 0b111000,
588 (outs), (ins MEMri:$ptr),
590 [(brind ADDRri:$ptr)]>;
594 def BCOND : BranchSP<(ins brtarget:$imm22, CCOp:$cond),
596 [(SPbricc bb:$imm22, imm:$cond)]>;
598 // Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121
600 // floating-point conditional branch class:
601 class FPBranchSP<dag ins, string asmstr, list<dag> pattern>
602 : F2_2<0b110, (outs), ins, asmstr, pattern> {
604 let isTerminator = 1;
605 let hasDelaySlot = 1;
609 def FBCOND : FPBranchSP<(ins brtarget:$imm22, CCOp:$cond),
611 [(SPbrfcc bb:$imm22, imm:$cond)]>;
614 // Section B.24 - Call and Link Instruction, p. 125
615 // This is the only Format 1 instruction
617 hasDelaySlot = 1, isCall = 1 in {
618 def CALL : InstSP<(outs), (ins calltarget:$dst, variable_ops),
622 let Inst{29-0} = disp;
626 def JMPLrr : F3_1<2, 0b111000,
627 (outs), (ins MEMrr:$ptr, variable_ops),
629 [(call ADDRrr:$ptr)]> { let rd = 15; }
630 def JMPLri : F3_2<2, 0b111000,
631 (outs), (ins MEMri:$ptr, variable_ops),
633 [(call ADDRri:$ptr)]> { let rd = 15; }
636 // Section B.28 - Read State Register Instructions
637 let Uses = [Y], rs1 = 0, rs2 = 0 in
638 def RDY : F3_1<2, 0b101000,
639 (outs IntRegs:$dst), (ins),
642 // Section B.29 - Write State Register Instructions
643 let Defs = [Y], rd = 0 in {
644 def WRYrr : F3_1<2, 0b110000,
645 (outs), (ins IntRegs:$b, IntRegs:$c),
646 "wr $b, $c, %y", []>;
647 def WRYri : F3_2<2, 0b110000,
648 (outs), (ins IntRegs:$b, i32imm:$c),
649 "wr $b, $c, %y", []>;
651 // Convert Integer to Floating-point Instructions, p. 141
652 def FITOS : F3_3u<2, 0b110100, 0b011000100,
653 (outs FPRegs:$dst), (ins FPRegs:$src),
655 [(set FPRegs:$dst, (SPitof FPRegs:$src))]>;
656 def FITOD : F3_3u<2, 0b110100, 0b011001000,
657 (outs DFPRegs:$dst), (ins FPRegs:$src),
659 [(set DFPRegs:$dst, (SPitof FPRegs:$src))]>;
660 def FITOQ : F3_3u<2, 0b110100, 0b011001100,
661 (outs QFPRegs:$dst), (ins FPRegs:$src),
663 [(set QFPRegs:$dst, (SPitof FPRegs:$src))]>,
664 Requires<[HasHardQuad]>;
666 // Convert Floating-point to Integer Instructions, p. 142
667 def FSTOI : F3_3u<2, 0b110100, 0b011010001,
668 (outs FPRegs:$dst), (ins FPRegs:$src),
670 [(set FPRegs:$dst, (SPftoi FPRegs:$src))]>;
671 def FDTOI : F3_3u<2, 0b110100, 0b011010010,
672 (outs FPRegs:$dst), (ins DFPRegs:$src),
674 [(set FPRegs:$dst, (SPftoi DFPRegs:$src))]>;
675 def FQTOI : F3_3u<2, 0b110100, 0b011010011,
676 (outs FPRegs:$dst), (ins QFPRegs:$src),
678 [(set FPRegs:$dst, (SPftoi QFPRegs:$src))]>,
679 Requires<[HasHardQuad]>;
681 // Convert between Floating-point Formats Instructions, p. 143
682 def FSTOD : F3_3u<2, 0b110100, 0b011001001,
683 (outs DFPRegs:$dst), (ins FPRegs:$src),
685 [(set f64:$dst, (fextend f32:$src))]>;
686 def FSTOQ : F3_3u<2, 0b110100, 0b011001101,
687 (outs QFPRegs:$dst), (ins FPRegs:$src),
689 [(set f128:$dst, (fextend f32:$src))]>,
690 Requires<[HasHardQuad]>;
691 def FDTOS : F3_3u<2, 0b110100, 0b011000110,
692 (outs FPRegs:$dst), (ins DFPRegs:$src),
694 [(set f32:$dst, (fround f64:$src))]>;
695 def FDTOQ : F3_3u<2, 0b110100, 0b01101110,
696 (outs QFPRegs:$dst), (ins DFPRegs:$src),
698 [(set f128:$dst, (fextend f64:$src))]>,
699 Requires<[HasHardQuad]>;
700 def FQTOS : F3_3u<2, 0b110100, 0b011000111,
701 (outs FPRegs:$dst), (ins QFPRegs:$src),
703 [(set f32:$dst, (fround f128:$src))]>,
704 Requires<[HasHardQuad]>;
705 def FQTOD : F3_3u<2, 0b110100, 0b011001011,
706 (outs DFPRegs:$dst), (ins QFPRegs:$src),
708 [(set f64:$dst, (fround f128:$src))]>,
709 Requires<[HasHardQuad]>;
711 // Floating-point Move Instructions, p. 144
712 def FMOVS : F3_3u<2, 0b110100, 0b000000001,
713 (outs FPRegs:$dst), (ins FPRegs:$src),
714 "fmovs $src, $dst", []>;
715 def FNEGS : F3_3u<2, 0b110100, 0b000000101,
716 (outs FPRegs:$dst), (ins FPRegs:$src),
718 [(set f32:$dst, (fneg f32:$src))]>;
719 def FABSS : F3_3u<2, 0b110100, 0b000001001,
720 (outs FPRegs:$dst), (ins FPRegs:$src),
722 [(set f32:$dst, (fabs f32:$src))]>;
725 // Floating-point Square Root Instructions, p.145
726 def FSQRTS : F3_3u<2, 0b110100, 0b000101001,
727 (outs FPRegs:$dst), (ins FPRegs:$src),
729 [(set f32:$dst, (fsqrt f32:$src))]>;
730 def FSQRTD : F3_3u<2, 0b110100, 0b000101010,
731 (outs DFPRegs:$dst), (ins DFPRegs:$src),
733 [(set f64:$dst, (fsqrt f64:$src))]>;
734 def FSQRTQ : F3_3u<2, 0b110100, 0b000101011,
735 (outs QFPRegs:$dst), (ins QFPRegs:$src),
737 [(set f128:$dst, (fsqrt f128:$src))]>,
738 Requires<[HasHardQuad]>;
742 // Floating-point Add and Subtract Instructions, p. 146
743 def FADDS : F3_3<2, 0b110100, 0b001000001,
744 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
745 "fadds $src1, $src2, $dst",
746 [(set f32:$dst, (fadd f32:$src1, f32:$src2))]>;
747 def FADDD : F3_3<2, 0b110100, 0b001000010,
748 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
749 "faddd $src1, $src2, $dst",
750 [(set f64:$dst, (fadd f64:$src1, f64:$src2))]>;
751 def FADDQ : F3_3<2, 0b110100, 0b001000011,
752 (outs QFPRegs:$dst), (ins QFPRegs:$src1, QFPRegs:$src2),
753 "faddq $src1, $src2, $dst",
754 [(set f128:$dst, (fadd f128:$src1, f128:$src2))]>,
755 Requires<[HasHardQuad]>;
757 def FSUBS : F3_3<2, 0b110100, 0b001000101,
758 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
759 "fsubs $src1, $src2, $dst",
760 [(set f32:$dst, (fsub f32:$src1, f32:$src2))]>;
761 def FSUBD : F3_3<2, 0b110100, 0b001000110,
762 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
763 "fsubd $src1, $src2, $dst",
764 [(set f64:$dst, (fsub f64:$src1, f64:$src2))]>;
765 def FSUBQ : F3_3<2, 0b110100, 0b001000111,
766 (outs QFPRegs:$dst), (ins QFPRegs:$src1, QFPRegs:$src2),
767 "fsubq $src1, $src2, $dst",
768 [(set f128:$dst, (fsub f128:$src1, f128:$src2))]>,
769 Requires<[HasHardQuad]>;
772 // Floating-point Multiply and Divide Instructions, p. 147
773 def FMULS : F3_3<2, 0b110100, 0b001001001,
774 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
775 "fmuls $src1, $src2, $dst",
776 [(set f32:$dst, (fmul f32:$src1, f32:$src2))]>;
777 def FMULD : F3_3<2, 0b110100, 0b001001010,
778 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
779 "fmuld $src1, $src2, $dst",
780 [(set f64:$dst, (fmul f64:$src1, f64:$src2))]>;
781 def FMULQ : F3_3<2, 0b110100, 0b001001011,
782 (outs QFPRegs:$dst), (ins QFPRegs:$src1, QFPRegs:$src2),
783 "fmulq $src1, $src2, $dst",
784 [(set f128:$dst, (fmul f128:$src1, f128:$src2))]>,
785 Requires<[HasHardQuad]>;
787 def FSMULD : F3_3<2, 0b110100, 0b001101001,
788 (outs DFPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
789 "fsmuld $src1, $src2, $dst",
790 [(set f64:$dst, (fmul (fextend f32:$src1),
791 (fextend f32:$src2)))]>;
792 def FDMULQ : F3_3<2, 0b110100, 0b001101110,
793 (outs QFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
794 "fdmulq $src1, $src2, $dst",
795 [(set f128:$dst, (fmul (fextend f64:$src1),
796 (fextend f64:$src2)))]>,
797 Requires<[HasHardQuad]>;
799 def FDIVS : F3_3<2, 0b110100, 0b001001101,
800 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
801 "fdivs $src1, $src2, $dst",
802 [(set f32:$dst, (fdiv f32:$src1, f32:$src2))]>;
803 def FDIVD : F3_3<2, 0b110100, 0b001001110,
804 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
805 "fdivd $src1, $src2, $dst",
806 [(set f64:$dst, (fdiv f64:$src1, f64:$src2))]>;
807 def FDIVQ : F3_3<2, 0b110100, 0b001001111,
808 (outs QFPRegs:$dst), (ins QFPRegs:$src1, QFPRegs:$src2),
809 "fdivq $src1, $src2, $dst",
810 [(set f128:$dst, (fdiv f128:$src1, f128:$src2))]>,
811 Requires<[HasHardQuad]>;
813 // Floating-point Compare Instructions, p. 148
814 // Note: the 2nd template arg is different for these guys.
815 // Note 2: the result of a FCMP is not available until the 2nd cycle
816 // after the instr is retired, but there is no interlock in Sparc V8.
817 // This behavior is modeled with a forced noop after the instruction in
820 let Defs = [FCC] in {
821 def FCMPS : F3_3c<2, 0b110101, 0b001010001,
822 (outs), (ins FPRegs:$src1, FPRegs:$src2),
823 "fcmps $src1, $src2",
824 [(SPcmpfcc f32:$src1, f32:$src2)]>;
825 def FCMPD : F3_3c<2, 0b110101, 0b001010010,
826 (outs), (ins DFPRegs:$src1, DFPRegs:$src2),
827 "fcmpd $src1, $src2",
828 [(SPcmpfcc f64:$src1, f64:$src2)]>;
829 def FCMPQ : F3_3c<2, 0b110101, 0b001010011,
830 (outs), (ins QFPRegs:$src1, QFPRegs:$src2),
831 "fcmpq $src1, $src2",
832 [(SPcmpfcc f128:$src1, f128:$src2)]>,
833 Requires<[HasHardQuad]>;
836 //===----------------------------------------------------------------------===//
837 // Instructions for Thread Local Storage(TLS).
838 //===----------------------------------------------------------------------===//
840 def TLS_ADDrr : F3_1<2, 0b000000,
842 (ins IntRegs:$rs1, IntRegs:$rs2, TLSSym:$sym),
843 "add $rs1, $rs2, $rd, $sym",
845 (tlsadd i32:$rs1, i32:$rs2, tglobaltlsaddr:$sym))]>;
848 def TLS_LDrr : F3_1<3, 0b000000,
849 (outs IntRegs:$dst), (ins MEMrr:$addr, TLSSym:$sym),
850 "ld [$addr], $dst, $sym",
852 (tlsld ADDRrr:$addr, tglobaltlsaddr:$sym))]>;
854 let Uses = [O6], isCall = 1, hasDelaySlot = 1 in
855 def TLS_CALL : InstSP<(outs),
856 (ins calltarget:$disp, TLSSym:$sym, variable_ops),
858 [(tlscall texternalsym:$disp, tglobaltlsaddr:$sym)]> {
861 let Inst{29-0} = disp;
864 //===----------------------------------------------------------------------===//
866 //===----------------------------------------------------------------------===//
868 // V9 Conditional Moves.
869 let Predicates = [HasV9], Constraints = "$f = $rd" in {
870 // Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual.
871 let Uses = [ICC], cc = 0b100 in {
873 : F4_1<0b101100, (outs IntRegs:$rd),
874 (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
875 "mov$cond %icc, $rs2, $rd",
876 [(set i32:$rd, (SPselecticc i32:$rs2, i32:$f, imm:$cond))]>;
879 : F4_2<0b101100, (outs IntRegs:$rd),
880 (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond),
881 "mov$cond %icc, $simm11, $rd",
883 (SPselecticc simm11:$simm11, i32:$f, imm:$cond))]>;
886 let Uses = [FCC], cc = 0b000 in {
888 : F4_1<0b101100, (outs IntRegs:$rd),
889 (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
890 "mov$cond %fcc0, $rs2, $rd",
891 [(set i32:$rd, (SPselectfcc i32:$rs2, i32:$f, imm:$cond))]>;
893 : F4_2<0b101100, (outs IntRegs:$rd),
894 (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond),
895 "mov$cond %fcc0, $simm11, $rd",
897 (SPselectfcc simm11:$simm11, i32:$f, imm:$cond))]>;
900 let Uses = [ICC], opf_cc = 0b100 in {
902 : F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
903 (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
904 "fmovs$cond %icc, $rs2, $rd",
905 [(set f32:$rd, (SPselecticc f32:$rs2, f32:$f, imm:$cond))]>;
907 : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd),
908 (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
909 "fmovd$cond %icc, $rs2, $rd",
910 [(set f64:$rd, (SPselecticc f64:$rs2, f64:$f, imm:$cond))]>;
912 : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
913 (ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
914 "fmovd$cond %icc, $rs2, $rd",
915 [(set f128:$rd, (SPselecticc f128:$rs2, f128:$f, imm:$cond))]>;
918 let Uses = [FCC], opf_cc = 0b000 in {
920 : F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
921 (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
922 "fmovs$cond %fcc0, $rs2, $rd",
923 [(set f32:$rd, (SPselectfcc f32:$rs2, f32:$f, imm:$cond))]>;
925 : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd),
926 (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
927 "fmovd$cond %fcc0, $rs2, $rd",
928 [(set f64:$rd, (SPselectfcc f64:$rs2, f64:$f, imm:$cond))]>;
930 : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
931 (ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
932 "fmovd$cond %fcc0, $rs2, $rd",
933 [(set f128:$rd, (SPselectfcc f128:$rs2, f128:$f, imm:$cond))]>;
938 // Floating-Point Move Instructions, p. 164 of the V9 manual.
939 let Predicates = [HasV9] in {
940 def FMOVD : F3_3u<2, 0b110100, 0b000000010,
941 (outs DFPRegs:$dst), (ins DFPRegs:$src),
942 "fmovd $src, $dst", []>;
943 def FMOVQ : F3_3u<2, 0b110100, 0b000000011,
944 (outs QFPRegs:$dst), (ins QFPRegs:$src),
945 "fmovq $src, $dst", []>,
946 Requires<[HasHardQuad]>;
947 def FNEGD : F3_3u<2, 0b110100, 0b000000110,
948 (outs DFPRegs:$dst), (ins DFPRegs:$src),
950 [(set f64:$dst, (fneg f64:$src))]>;
951 def FNEGQ : F3_3u<2, 0b110100, 0b000000111,
952 (outs QFPRegs:$dst), (ins QFPRegs:$src),
954 [(set f128:$dst, (fneg f128:$src))]>,
955 Requires<[HasHardQuad]>;
956 def FABSD : F3_3u<2, 0b110100, 0b000001010,
957 (outs DFPRegs:$dst), (ins DFPRegs:$src),
959 [(set f64:$dst, (fabs f64:$src))]>;
960 def FABSQ : F3_3u<2, 0b110100, 0b000001011,
961 (outs QFPRegs:$dst), (ins QFPRegs:$src),
963 [(set f128:$dst, (fabs f128:$src))]>,
964 Requires<[HasHardQuad]>;
967 // POPCrr - This does a ctpop of a 64-bit register. As such, we have to clear
968 // the top 32-bits before using it. To do this clearing, we use a SLLri X,0.
970 def POPCrr : F3_1<2, 0b101110,
971 (outs IntRegs:$dst), (ins IntRegs:$src),
972 "popc $src, $dst", []>, Requires<[HasV9]>;
973 def : Pat<(ctpop i32:$src),
974 (POPCrr (SLLri $src, 0))>;
976 //===----------------------------------------------------------------------===//
977 // Non-Instruction Patterns
978 //===----------------------------------------------------------------------===//
981 def : Pat<(i32 simm13:$val),
982 (ORri (i32 G0), imm:$val)>;
983 // Arbitrary immediates.
984 def : Pat<(i32 imm:$val),
985 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;
988 // Global addresses, constant pool entries
989 def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>;
990 def : Pat<(SPlo tglobaladdr:$in), (ORri (i32 G0), tglobaladdr:$in)>;
991 def : Pat<(SPhi tconstpool:$in), (SETHIi tconstpool:$in)>;
992 def : Pat<(SPlo tconstpool:$in), (ORri (i32 G0), tconstpool:$in)>;
994 // GlobalTLS addresses
995 def : Pat<(SPhi tglobaltlsaddr:$in), (SETHIi tglobaltlsaddr:$in)>;
996 def : Pat<(SPlo tglobaltlsaddr:$in), (ORri (i32 G0), tglobaltlsaddr:$in)>;
997 def : Pat<(add (SPhi tglobaltlsaddr:$in1), (SPlo tglobaltlsaddr:$in2)),
998 (ADDri (SETHIi tglobaltlsaddr:$in1), (tglobaltlsaddr:$in2))>;
999 def : Pat<(xor (SPhi tglobaltlsaddr:$in1), (SPlo tglobaltlsaddr:$in2)),
1000 (XORri (SETHIi tglobaltlsaddr:$in1), (tglobaltlsaddr:$in2))>;
1003 def : Pat<(SPhi tblockaddress:$in), (SETHIi tblockaddress:$in)>;
1004 def : Pat<(SPlo tblockaddress:$in), (ORri (i32 G0), tblockaddress:$in)>;
1006 // Add reg, lo. This is used when taking the addr of a global/constpool entry.
1007 def : Pat<(add iPTR:$r, (SPlo tglobaladdr:$in)), (ADDri $r, tglobaladdr:$in)>;
1008 def : Pat<(add iPTR:$r, (SPlo tconstpool:$in)), (ADDri $r, tconstpool:$in)>;
1009 def : Pat<(add iPTR:$r, (SPlo tblockaddress:$in)),
1010 (ADDri $r, tblockaddress:$in)>;
1013 def : Pat<(call tglobaladdr:$dst),
1014 (CALL tglobaladdr:$dst)>;
1015 def : Pat<(call texternalsym:$dst),
1016 (CALL texternalsym:$dst)>;
1018 // Map integer extload's to zextloads.
1019 def : Pat<(i32 (extloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
1020 def : Pat<(i32 (extloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>;
1021 def : Pat<(i32 (extloadi8 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
1022 def : Pat<(i32 (extloadi8 ADDRri:$src)), (LDUBri ADDRri:$src)>;
1023 def : Pat<(i32 (extloadi16 ADDRrr:$src)), (LDUHrr ADDRrr:$src)>;
1024 def : Pat<(i32 (extloadi16 ADDRri:$src)), (LDUHri ADDRri:$src)>;
1026 // zextload bool -> zextload byte
1027 def : Pat<(i32 (zextloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
1028 def : Pat<(i32 (zextloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>;
1030 // store 0, addr -> store %g0, addr
1031 def : Pat<(store (i32 0), ADDRrr:$dst), (STrr ADDRrr:$dst, (i32 G0))>;
1032 def : Pat<(store (i32 0), ADDRri:$dst), (STri ADDRri:$dst, (i32 G0))>;
1034 include "SparcInstr64Bit.td"