1 //===-- SparcInstrInfo.cpp - Sparc Instruction Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Sparc implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "SparcInstrInfo.h"
16 #include "SparcMachineFunctionInfo.h"
17 #include "SparcSubtarget.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineMemOperand.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Support/TargetRegistry.h"
27 #define GET_INSTRINFO_CTOR_DTOR
28 #include "SparcGenInstrInfo.inc"
33 // Pin the vtable to this file.
34 void SparcInstrInfo::anchor() {}
36 SparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST)
37 : SparcGenInstrInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
38 RI(ST), Subtarget(ST) {
41 /// isLoadFromStackSlot - If the specified machine instruction is a direct
42 /// load from a stack slot, return the virtual or physical register number of
43 /// the destination along with the FrameIndex of the loaded stack slot. If
44 /// not, return 0. This predicate must return 0 if the instruction has
45 /// any side effects other than loading from the stack slot.
46 unsigned SparcInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
47 int &FrameIndex) const {
48 if (MI->getOpcode() == SP::LDri ||
49 MI->getOpcode() == SP::LDXri ||
50 MI->getOpcode() == SP::LDFri ||
51 MI->getOpcode() == SP::LDDFri ||
52 MI->getOpcode() == SP::LDQFri) {
53 if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() &&
54 MI->getOperand(2).getImm() == 0) {
55 FrameIndex = MI->getOperand(1).getIndex();
56 return MI->getOperand(0).getReg();
62 /// isStoreToStackSlot - If the specified machine instruction is a direct
63 /// store to a stack slot, return the virtual or physical register number of
64 /// the source reg along with the FrameIndex of the loaded stack slot. If
65 /// not, return 0. This predicate must return 0 if the instruction has
66 /// any side effects other than storing to the stack slot.
67 unsigned SparcInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
68 int &FrameIndex) const {
69 if (MI->getOpcode() == SP::STri ||
70 MI->getOpcode() == SP::STXri ||
71 MI->getOpcode() == SP::STFri ||
72 MI->getOpcode() == SP::STDFri ||
73 MI->getOpcode() == SP::STQFri) {
74 if (MI->getOperand(0).isFI() && MI->getOperand(1).isImm() &&
75 MI->getOperand(1).getImm() == 0) {
76 FrameIndex = MI->getOperand(0).getIndex();
77 return MI->getOperand(2).getReg();
83 static bool IsIntegerCC(unsigned CC)
85 return (CC <= SPCC::ICC_VC);
89 static SPCC::CondCodes GetOppositeBranchCondition(SPCC::CondCodes CC)
92 case SPCC::ICC_NE: return SPCC::ICC_E;
93 case SPCC::ICC_E: return SPCC::ICC_NE;
94 case SPCC::ICC_G: return SPCC::ICC_LE;
95 case SPCC::ICC_LE: return SPCC::ICC_G;
96 case SPCC::ICC_GE: return SPCC::ICC_L;
97 case SPCC::ICC_L: return SPCC::ICC_GE;
98 case SPCC::ICC_GU: return SPCC::ICC_LEU;
99 case SPCC::ICC_LEU: return SPCC::ICC_GU;
100 case SPCC::ICC_CC: return SPCC::ICC_CS;
101 case SPCC::ICC_CS: return SPCC::ICC_CC;
102 case SPCC::ICC_POS: return SPCC::ICC_NEG;
103 case SPCC::ICC_NEG: return SPCC::ICC_POS;
104 case SPCC::ICC_VC: return SPCC::ICC_VS;
105 case SPCC::ICC_VS: return SPCC::ICC_VC;
107 case SPCC::FCC_U: return SPCC::FCC_O;
108 case SPCC::FCC_O: return SPCC::FCC_U;
109 case SPCC::FCC_G: return SPCC::FCC_ULE;
110 case SPCC::FCC_LE: return SPCC::FCC_UG;
111 case SPCC::FCC_UG: return SPCC::FCC_LE;
112 case SPCC::FCC_ULE: return SPCC::FCC_G;
113 case SPCC::FCC_L: return SPCC::FCC_UGE;
114 case SPCC::FCC_GE: return SPCC::FCC_UL;
115 case SPCC::FCC_UL: return SPCC::FCC_GE;
116 case SPCC::FCC_UGE: return SPCC::FCC_L;
117 case SPCC::FCC_LG: return SPCC::FCC_UE;
118 case SPCC::FCC_UE: return SPCC::FCC_LG;
119 case SPCC::FCC_NE: return SPCC::FCC_E;
120 case SPCC::FCC_E: return SPCC::FCC_NE;
122 llvm_unreachable("Invalid cond code");
125 bool SparcInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
126 MachineBasicBlock *&TBB,
127 MachineBasicBlock *&FBB,
128 SmallVectorImpl<MachineOperand> &Cond,
129 bool AllowModify) const
132 MachineBasicBlock::iterator I = MBB.end();
133 MachineBasicBlock::iterator UnCondBrIter = MBB.end();
134 while (I != MBB.begin()) {
137 if (I->isDebugValue())
140 // When we see a non-terminator, we are done.
141 if (!isUnpredicatedTerminator(I))
144 // Terminator is not a branch.
148 // Handle Unconditional branches.
149 if (I->getOpcode() == SP::BA) {
153 TBB = I->getOperand(0).getMBB();
157 while (llvm::next(I) != MBB.end())
158 llvm::next(I)->eraseFromParent();
163 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
165 I->eraseFromParent();
167 UnCondBrIter = MBB.end();
171 TBB = I->getOperand(0).getMBB();
175 unsigned Opcode = I->getOpcode();
176 if (Opcode != SP::BCOND && Opcode != SP::FBCOND)
177 return true; // Unknown Opcode.
179 SPCC::CondCodes BranchCode = (SPCC::CondCodes)I->getOperand(1).getImm();
182 MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
183 if (AllowModify && UnCondBrIter != MBB.end() &&
184 MBB.isLayoutSuccessor(TargetBB)) {
186 // Transform the code
201 BranchCode = GetOppositeBranchCondition(BranchCode);
202 MachineBasicBlock::iterator OldInst = I;
203 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(Opcode))
204 .addMBB(UnCondBrIter->getOperand(0).getMBB()).addImm(BranchCode);
205 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(SP::BA))
208 OldInst->eraseFromParent();
209 UnCondBrIter->eraseFromParent();
211 UnCondBrIter = MBB.end();
216 TBB = I->getOperand(0).getMBB();
217 Cond.push_back(MachineOperand::CreateImm(BranchCode));
220 // FIXME: Handle subsequent conditional branches.
221 // For now, we can't handle multiple conditional branches.
228 SparcInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
229 MachineBasicBlock *FBB,
230 const SmallVectorImpl<MachineOperand> &Cond,
232 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
233 assert((Cond.size() == 1 || Cond.size() == 0) &&
234 "Sparc branch conditions should have one component!");
237 assert(!FBB && "Unconditional branch with multiple successors!");
238 BuildMI(&MBB, DL, get(SP::BA)).addMBB(TBB);
242 // Conditional branch
243 unsigned CC = Cond[0].getImm();
246 BuildMI(&MBB, DL, get(SP::BCOND)).addMBB(TBB).addImm(CC);
248 BuildMI(&MBB, DL, get(SP::FBCOND)).addMBB(TBB).addImm(CC);
252 BuildMI(&MBB, DL, get(SP::BA)).addMBB(FBB);
256 unsigned SparcInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const
258 MachineBasicBlock::iterator I = MBB.end();
260 while (I != MBB.begin()) {
263 if (I->isDebugValue())
266 if (I->getOpcode() != SP::BA
267 && I->getOpcode() != SP::BCOND
268 && I->getOpcode() != SP::FBCOND)
269 break; // Not a branch
271 I->eraseFromParent();
278 void SparcInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
279 MachineBasicBlock::iterator I, DebugLoc DL,
280 unsigned DestReg, unsigned SrcReg,
281 bool KillSrc) const {
282 unsigned numSubRegs = 0;
284 const unsigned *subRegIdx = 0;
286 const unsigned DFP_FP_SubRegsIdx[] = { SP::sub_even, SP::sub_odd };
287 const unsigned QFP_DFP_SubRegsIdx[] = { SP::sub_even64, SP::sub_odd64 };
288 const unsigned QFP_FP_SubRegsIdx[] = { SP::sub_even, SP::sub_odd,
289 SP::sub_odd64_then_sub_even,
290 SP::sub_odd64_then_sub_odd };
292 if (SP::IntRegsRegClass.contains(DestReg, SrcReg))
293 BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0)
294 .addReg(SrcReg, getKillRegState(KillSrc));
295 else if (SP::FPRegsRegClass.contains(DestReg, SrcReg))
296 BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg)
297 .addReg(SrcReg, getKillRegState(KillSrc));
298 else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg)) {
299 if (Subtarget.isV9()) {
300 BuildMI(MBB, I, DL, get(SP::FMOVD), DestReg)
301 .addReg(SrcReg, getKillRegState(KillSrc));
303 // Use two FMOVS instructions.
304 subRegIdx = DFP_FP_SubRegsIdx;
308 } else if (SP::QFPRegsRegClass.contains(DestReg, SrcReg)) {
309 if (Subtarget.isV9()) {
310 if (Subtarget.hasHardQuad()) {
311 BuildMI(MBB, I, DL, get(SP::FMOVQ), DestReg)
312 .addReg(SrcReg, getKillRegState(KillSrc));
314 // Use two FMOVD instructions.
315 subRegIdx = QFP_DFP_SubRegsIdx;
320 // Use four FMOVS instructions.
321 subRegIdx = QFP_FP_SubRegsIdx;
326 llvm_unreachable("Impossible reg-to-reg copy");
328 if (numSubRegs == 0 || subRegIdx == 0 || movOpc == 0)
331 const TargetRegisterInfo *TRI = &getRegisterInfo();
332 MachineInstr *MovMI = 0;
334 for (unsigned i = 0; i != numSubRegs; ++i) {
335 unsigned Dst = TRI->getSubReg(DestReg, subRegIdx[i]);
336 unsigned Src = TRI->getSubReg(SrcReg, subRegIdx[i]);
337 assert(Dst && Src && "Bad sub-register");
339 MovMI = BuildMI(MBB, I, DL, get(movOpc), Dst).addReg(Src);
341 // Add implicit super-register defs and kills to the last MovMI.
342 MovMI->addRegisterDefined(DestReg, TRI);
344 MovMI->addRegisterKilled(SrcReg, TRI);
347 void SparcInstrInfo::
348 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
349 unsigned SrcReg, bool isKill, int FI,
350 const TargetRegisterClass *RC,
351 const TargetRegisterInfo *TRI) const {
353 if (I != MBB.end()) DL = I->getDebugLoc();
355 MachineFunction *MF = MBB.getParent();
356 const MachineFrameInfo &MFI = *MF->getFrameInfo();
357 MachineMemOperand *MMO =
358 MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
359 MachineMemOperand::MOStore,
360 MFI.getObjectSize(FI),
361 MFI.getObjectAlignment(FI));
363 // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
364 if (RC == &SP::I64RegsRegClass)
365 BuildMI(MBB, I, DL, get(SP::STXri)).addFrameIndex(FI).addImm(0)
366 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
367 else if (RC == &SP::IntRegsRegClass)
368 BuildMI(MBB, I, DL, get(SP::STri)).addFrameIndex(FI).addImm(0)
369 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
370 else if (RC == &SP::FPRegsRegClass)
371 BuildMI(MBB, I, DL, get(SP::STFri)).addFrameIndex(FI).addImm(0)
372 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
373 else if (SP::DFPRegsRegClass.hasSubClassEq(RC))
374 BuildMI(MBB, I, DL, get(SP::STDFri)).addFrameIndex(FI).addImm(0)
375 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
376 else if (SP::QFPRegsRegClass.hasSubClassEq(RC))
377 // Use STQFri irrespective of its legality. If STQ is not legal, it will be
378 // lowered into two STDs in eliminateFrameIndex.
379 BuildMI(MBB, I, DL, get(SP::STQFri)).addFrameIndex(FI).addImm(0)
380 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
382 llvm_unreachable("Can't store this register to stack slot");
385 void SparcInstrInfo::
386 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
387 unsigned DestReg, int FI,
388 const TargetRegisterClass *RC,
389 const TargetRegisterInfo *TRI) const {
391 if (I != MBB.end()) DL = I->getDebugLoc();
393 MachineFunction *MF = MBB.getParent();
394 const MachineFrameInfo &MFI = *MF->getFrameInfo();
395 MachineMemOperand *MMO =
396 MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
397 MachineMemOperand::MOLoad,
398 MFI.getObjectSize(FI),
399 MFI.getObjectAlignment(FI));
401 if (RC == &SP::I64RegsRegClass)
402 BuildMI(MBB, I, DL, get(SP::LDXri), DestReg).addFrameIndex(FI).addImm(0)
404 else if (RC == &SP::IntRegsRegClass)
405 BuildMI(MBB, I, DL, get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0)
407 else if (RC == &SP::FPRegsRegClass)
408 BuildMI(MBB, I, DL, get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0)
410 else if (SP::DFPRegsRegClass.hasSubClassEq(RC))
411 BuildMI(MBB, I, DL, get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0)
413 else if (SP::QFPRegsRegClass.hasSubClassEq(RC))
414 // Use LDQFri irrespective of its legality. If LDQ is not legal, it will be
415 // lowered into two LDDs in eliminateFrameIndex.
416 BuildMI(MBB, I, DL, get(SP::LDQFri), DestReg).addFrameIndex(FI).addImm(0)
419 llvm_unreachable("Can't load this register from stack slot");
422 unsigned SparcInstrInfo::getGlobalBaseReg(MachineFunction *MF) const
424 SparcMachineFunctionInfo *SparcFI = MF->getInfo<SparcMachineFunctionInfo>();
425 unsigned GlobalBaseReg = SparcFI->getGlobalBaseReg();
426 if (GlobalBaseReg != 0)
427 return GlobalBaseReg;
429 // Insert the set of GlobalBaseReg into the first MBB of the function
430 MachineBasicBlock &FirstMBB = MF->front();
431 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
432 MachineRegisterInfo &RegInfo = MF->getRegInfo();
434 GlobalBaseReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
439 BuildMI(FirstMBB, MBBI, dl, get(SP::GETPCX), GlobalBaseReg);
440 SparcFI->setGlobalBaseReg(GlobalBaseReg);
441 return GlobalBaseReg;