1 //===-- SparcInstrFormats.td - Sparc Instruction Formats ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 class InstSP<dag outs, dag ins, string asmstr, list<dag> pattern>
18 let Inst{31-30} = op; // Top two bits are the 'op' field
20 dag OutOperandList = outs;
21 dag InOperandList = ins;
22 let AsmString = asmstr;
23 let Pattern = pattern;
25 let DecoderNamespace = "Sparc";
26 field bits<32> SoftFail = 0;
29 //===----------------------------------------------------------------------===//
30 // Format #2 instruction classes in the Sparc
31 //===----------------------------------------------------------------------===//
33 // Format 2 instructions
34 class F2<dag outs, dag ins, string asmstr, list<dag> pattern>
35 : InstSP<outs, ins, asmstr, pattern> {
39 let Inst{24-22} = op2;
40 let Inst{21-0} = imm22;
43 // Specific F2 classes: SparcV8 manual, page 44
45 class F2_1<bits<3> op2Val, dag outs, dag ins, string asmstr, list<dag> pattern>
46 : F2<outs, ins, asmstr, pattern> {
54 class F2_2<bits<3> op2Val, bit annul, dag outs, dag ins, string asmstr,
55 list<dag> pattern> : F2<outs, ins, asmstr, pattern> {
60 let Inst{28-25} = cond;
63 class F2_3<bits<3> op2Val, bit annul, bit pred,
64 dag outs, dag ins, string asmstr, list<dag> pattern>
65 : InstSP<outs, ins, asmstr, pattern> {
73 let Inst{28-25} = cond;
74 let Inst{24-22} = op2Val;
77 let Inst{18-0} = imm19;
80 //===----------------------------------------------------------------------===//
81 // Format #3 instruction classes in the Sparc
82 //===----------------------------------------------------------------------===//
84 class F3<dag outs, dag ins, string asmstr, list<dag> pattern>
85 : InstSP<outs, ins, asmstr, pattern> {
89 let op{1} = 1; // Op = 2 or 3
91 let Inst{24-19} = op3;
92 let Inst{18-14} = rs1;
95 // Specific F3 classes: SparcV8 manual, page 44
97 class F3_1_asi<bits<2> opVal, bits<6> op3val, bits<8> asi, dag outs, dag ins,
98 string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
104 let Inst{13} = 0; // i field = 0
105 let Inst{12-5} = asi; // address space identifier
109 class F3_1<bits<2> opVal, bits<6> op3val, dag outs, dag ins, string asmstr,
110 list<dag> pattern> : F3_1_asi<opVal, op3val, 0, outs, ins,
113 class F3_2<bits<2> opVal, bits<6> op3val, dag outs, dag ins,
114 string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
120 let Inst{13} = 1; // i field = 1
121 let Inst{12-0} = simm13;
125 class F3_3<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins,
126 string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
132 let Inst{13-5} = opfval; // fp opcode
136 // floating-point unary operations.
137 class F3_3u<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins,
138 string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
145 let Inst{13-5} = opfval; // fp opcode
149 // floating-point compares.
150 class F3_3c<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins,
151 string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
158 let Inst{13-5} = opfval; // fp opcode
162 // Shift by register rs2.
163 class F3_Sr<bits<2> opVal, bits<6> op3val, bit xVal, dag outs, dag ins,
164 string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
165 bit x = xVal; // 1 for 64-bit shifts.
171 let Inst{13} = 0; // i field = 0
172 let Inst{12} = x; // extended registers.
176 // Shift by immediate.
177 class F3_Si<bits<2> opVal, bits<6> op3val, bit xVal, dag outs, dag ins,
178 string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
179 bit x = xVal; // 1 for 64-bit shifts.
180 bits<6> shcnt; // shcnt32 / shcnt64.
185 let Inst{13} = 1; // i field = 1
186 let Inst{12} = x; // extended registers.
187 let Inst{5-0} = shcnt;
190 // Define rr and ri shift instructions with patterns.
191 multiclass F3_S<string OpcStr, bits<6> Op3Val, bit XVal, SDNode OpNode,
192 ValueType VT, RegisterClass RC> {
193 def rr : F3_Sr<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs1, IntRegs:$rs2),
194 !strconcat(OpcStr, " $rs1, $rs2, $rd"),
195 [(set VT:$rd, (OpNode VT:$rs1, i32:$rs2))]>;
196 def ri : F3_Si<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs1, i32imm:$shcnt),
197 !strconcat(OpcStr, " $rs1, $shcnt, $rd"),
198 [(set VT:$rd, (OpNode VT:$rs1, (i32 imm:$shcnt)))]>;
201 class F4<bits<6> op3, dag outs, dag ins, string asmstr, list<dag> pattern>
202 : InstSP<outs, ins, asmstr, pattern> {
206 let Inst{29-25} = rd;
207 let Inst{24-19} = op3;
211 class F4_1<bits<6> op3, dag outs, dag ins,
212 string asmstr, list<dag> pattern>
213 : F4<op3, outs, ins, asmstr, pattern> {
220 let Inst{11} = cc{0};
221 let Inst{12} = cc{1};
223 let Inst{17-14} = cond;
224 let Inst{18} = cc{2};
228 class F4_2<bits<6> op3, dag outs, dag ins,
229 string asmstr, list<dag> pattern>
230 : F4<op3, outs, ins, asmstr, pattern> {
235 let Inst{10-0} = simm11;
236 let Inst{11} = cc{0};
237 let Inst{12} = cc{1};
239 let Inst{17-14} = cond;
240 let Inst{18} = cc{2};
243 class F4_3<bits<6> op3, bits<6> opf_low, dag outs, dag ins,
244 string asmstr, list<dag> pattern>
245 : F4<op3, outs, ins, asmstr, pattern> {
251 let Inst{17-14} = cond;
252 let Inst{13-11} = opf_cc;
253 let Inst{10-5} = opf_low;