1 //===-- SparcInstr64Bit.td - 64-bit instructions for Sparc Target ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains instruction definitions and patterns needed for 64-bit
11 // code generation on SPARC v9.
13 // Some SPARC v9 instructions are defined in SparcInstrInfo.td because they can
14 // also be used in 32-bit code running on a SPARC v9 CPU.
16 //===----------------------------------------------------------------------===//
18 let Predicates = [Is64Bit] in {
19 // The same integer registers are used for i32 and i64 values.
20 // When registers hold i32 values, the high bits are don't care.
21 // This give us free trunc and anyext.
22 def : Pat<(i64 (anyext i32:$val)), (COPY $val)>;
23 def : Pat<(i32 (trunc i64:$val)), (COPY $val)>;
25 } // Predicates = [Is64Bit]
28 //===----------------------------------------------------------------------===//
29 // 64-bit Shift Instructions.
30 //===----------------------------------------------------------------------===//
32 // The 32-bit shift instructions are still available. The left shift srl
33 // instructions shift all 64 bits, but it only accepts a 5-bit shift amount.
35 // The srl instructions only shift the low 32 bits and clear the high 32 bits.
36 // Finally, sra shifts the low 32 bits and sign-extends to 64 bits.
38 let Predicates = [Is64Bit] in {
40 def : Pat<(i64 (zext i32:$val)), (SRLri $val, 0)>;
41 def : Pat<(i64 (sext i32:$val)), (SRAri $val, 0)>;
43 defm SLLX : F3_S<"sllx", 0b100101, 1, shl, i64, I64Regs>;
44 defm SRLX : F3_S<"srlx", 0b100110, 1, srl, i64, I64Regs>;
45 defm SRAX : F3_S<"srax", 0b100111, 1, sra, i64, I64Regs>;
47 } // Predicates = [Is64Bit]
50 //===----------------------------------------------------------------------===//
52 //===----------------------------------------------------------------------===//
54 // All 32-bit immediates can be materialized with sethi+or, but 64-bit
55 // immediates may require more code. There may be a point where it is
56 // preferable to use a constant pool load instead, depending on the
59 // The %g0 register is constant 0.
60 // This is useful for stx %g0, [...], for example.
61 def : Pat<(i64 0), (i64 G0)>, Requires<[Is64Bit]>;
63 // Single-instruction patterns.
65 // The ALU instructions want their simm13 operands as i32 immediates.
66 def as_i32imm : SDNodeXForm<imm, [{
67 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i32);
69 def : Pat<(i64 simm13:$val), (ORri (i64 G0), (as_i32imm $val))>;
70 def : Pat<(i64 SETHIimm:$val), (SETHIi (HI22 $val))>;
72 // Double-instruction patterns.
74 // All unsigned i32 immediates can be handled by sethi+or.
75 def uimm32 : PatLeaf<(imm), [{ return isUInt<32>(N->getZExtValue()); }]>;
76 def : Pat<(i64 uimm32:$val), (ORri (SETHIi (HI22 $val)), (LO10 $val))>,
79 // All negative i33 immediates can be handled by sethi+xor.
80 def nimm33 : PatLeaf<(imm), [{
81 int64_t Imm = N->getSExtValue();
82 return Imm < 0 && isInt<33>(Imm);
84 // Bits 10-31 inverted. Same as assembler's %hix.
85 def HIX22 : SDNodeXForm<imm, [{
86 uint64_t Val = (~N->getZExtValue() >> 10) & ((1u << 22) - 1);
87 return CurDAG->getTargetConstant(Val, MVT::i32);
89 // Bits 0-9 with ones in bits 10-31. Same as assembler's %lox.
90 def LOX10 : SDNodeXForm<imm, [{
91 return CurDAG->getTargetConstant(~(~N->getZExtValue() & 0x3ff), MVT::i32);
93 def : Pat<(i64 nimm33:$val), (XORri (SETHIi (HIX22 $val)), (LOX10 $val))>,
96 // More possible patterns:
103 // (xor (sllx sethi), simm13)
104 // (sllx (xor sethi, simm13))
108 // (or sethi, (sllx sethi))
109 // (xnor sethi, (sllx sethi))
113 // (or (sllx sethi), (or sethi, simm13))
114 // (xnor (sllx sethi), (or sethi, simm13))
115 // (or (sllx sethi), (sllx sethi))
116 // (xnor (sllx sethi), (sllx sethi))
118 // Worst case is 6 instrs:
120 // (or (sllx (or sethi, simmm13)), (or sethi, simm13))
122 // Bits 42-63, same as assembler's %hh.
123 def HH22 : SDNodeXForm<imm, [{
124 uint64_t Val = (N->getZExtValue() >> 42) & ((1u << 22) - 1);
125 return CurDAG->getTargetConstant(Val, MVT::i32);
127 // Bits 32-41, same as assembler's %hm.
128 def HM10 : SDNodeXForm<imm, [{
129 uint64_t Val = (N->getZExtValue() >> 32) & ((1u << 10) - 1);
130 return CurDAG->getTargetConstant(Val, MVT::i32);
132 def : Pat<(i64 imm:$val),
133 (ORrr (SLLXri (ORri (SETHIi (HH22 $val)), (HM10 $val)), (i64 32)),
134 (ORri (SETHIi (HI22 $val)), (LO10 $val)))>,
138 //===----------------------------------------------------------------------===//
139 // 64-bit Integer Arithmetic and Logic.
140 //===----------------------------------------------------------------------===//
142 let Predicates = [Is64Bit] in {
144 // Register-register instructions.
146 def : Pat<(and i64:$a, i64:$b), (ANDrr $a, $b)>;
147 def : Pat<(or i64:$a, i64:$b), (ORrr $a, $b)>;
148 def : Pat<(xor i64:$a, i64:$b), (XORrr $a, $b)>;
150 def : Pat<(and i64:$a, (not i64:$b)), (ANDNrr $a, $b)>;
151 def : Pat<(or i64:$a, (not i64:$b)), (ORNrr $a, $b)>;
152 def : Pat<(xor i64:$a, (not i64:$b)), (XNORrr $a, $b)>;
154 def : Pat<(add i64:$a, i64:$b), (ADDrr $a, $b)>;
155 def : Pat<(sub i64:$a, i64:$b), (SUBrr $a, $b)>;
157 // Add/sub with carry were renamed to addc/subc in SPARC v9.
158 def : Pat<(adde i64:$a, i64:$b), (ADDXrr $a, $b)>;
159 def : Pat<(sube i64:$a, i64:$b), (SUBXrr $a, $b)>;
161 def : Pat<(addc i64:$a, i64:$b), (ADDCCrr $a, $b)>;
162 def : Pat<(subc i64:$a, i64:$b), (SUBCCrr $a, $b)>;
164 def : Pat<(SPcmpicc i64:$a, i64:$b), (SUBCCrr $a, $b)>;
166 // Register-immediate instructions.
168 def : Pat<(and i64:$a, (i64 simm13:$b)), (ANDri $a, (as_i32imm $b))>;
169 def : Pat<(or i64:$a, (i64 simm13:$b)), (ORri $a, (as_i32imm $b))>;
170 def : Pat<(xor i64:$a, (i64 simm13:$b)), (XORri $a, (as_i32imm $b))>;
172 def : Pat<(add i64:$a, (i64 simm13:$b)), (ADDri $a, (as_i32imm $b))>;
173 def : Pat<(sub i64:$a, (i64 simm13:$b)), (SUBri $a, (as_i32imm $b))>;
175 def : Pat<(SPcmpicc i64:$a, (i64 simm13:$b)), (SUBCCri $a, (as_i32imm $b))>;
177 } // Predicates = [Is64Bit]
180 //===----------------------------------------------------------------------===//
181 // 64-bit Loads and Stores.
182 //===----------------------------------------------------------------------===//
184 // All the 32-bit loads and stores are available. The extending loads are sign
185 // or zero-extending to 64 bits. The LDrr and LDri instructions load 32 bits
186 // zero-extended to i64. Their mnemonic is lduw in SPARC v9 (Load Unsigned
189 // SPARC v9 adds 64-bit loads as well as a sign-extending ldsw i32 loads.
191 let Predicates = [Is64Bit] in {
194 def LDXrr : F3_1<3, 0b001011,
195 (outs I64Regs:$dst), (ins MEMrr:$addr),
197 [(set i64:$dst, (load ADDRrr:$addr))]>;
198 def LDXri : F3_2<3, 0b001011,
199 (outs I64Regs:$dst), (ins MEMri:$addr),
201 [(set i64:$dst, (load ADDRri:$addr))]>;
203 // Extending loads to i64.
204 def : Pat<(i64 (zextloadi8 ADDRrr:$addr)), (LDUBrr ADDRrr:$addr)>;
205 def : Pat<(i64 (zextloadi8 ADDRri:$addr)), (LDUBri ADDRri:$addr)>;
206 def : Pat<(i64 (sextloadi8 ADDRrr:$addr)), (LDSBrr ADDRrr:$addr)>;
207 def : Pat<(i64 (sextloadi8 ADDRri:$addr)), (LDSBri ADDRri:$addr)>;
209 def : Pat<(i64 (zextloadi16 ADDRrr:$addr)), (LDUHrr ADDRrr:$addr)>;
210 def : Pat<(i64 (zextloadi16 ADDRri:$addr)), (LDUHri ADDRri:$addr)>;
211 def : Pat<(i64 (sextloadi16 ADDRrr:$addr)), (LDSHrr ADDRrr:$addr)>;
212 def : Pat<(i64 (sextloadi16 ADDRri:$addr)), (LDSHri ADDRri:$addr)>;
214 def : Pat<(i64 (zextloadi32 ADDRrr:$addr)), (LDrr ADDRrr:$addr)>;
215 def : Pat<(i64 (zextloadi32 ADDRri:$addr)), (LDri ADDRri:$addr)>;
217 // Sign-extending load of i32 into i64 is a new SPARC v9 instruction.
218 def LDSWrr : F3_1<3, 0b001011,
219 (outs I64Regs:$dst), (ins MEMrr:$addr),
220 "ldsw [$addr], $dst",
221 [(set i64:$dst, (sextloadi32 ADDRrr:$addr))]>;
222 def LDSWri : F3_2<3, 0b001011,
223 (outs I64Regs:$dst), (ins MEMri:$addr),
224 "ldsw [$addr], $dst",
225 [(set i64:$dst, (sextloadi32 ADDRri:$addr))]>;
228 def STXrr : F3_1<3, 0b001110,
229 (outs), (ins MEMrr:$addr, I64Regs:$src),
231 [(store i64:$src, ADDRrr:$addr)]>;
232 def STXri : F3_2<3, 0b001110,
233 (outs), (ins MEMri:$addr, I64Regs:$src),
235 [(store i64:$src, ADDRri:$addr)]>;
237 // Truncating stores from i64 are identical to the i32 stores.
238 def : Pat<(truncstorei8 i64:$src, ADDRrr:$addr), (STBrr ADDRrr:$addr, $src)>;
239 def : Pat<(truncstorei8 i64:$src, ADDRri:$addr), (STBri ADDRri:$addr, $src)>;
240 def : Pat<(truncstorei16 i64:$src, ADDRrr:$addr), (STHrr ADDRrr:$addr, $src)>;
241 def : Pat<(truncstorei16 i64:$src, ADDRri:$addr), (STHri ADDRri:$addr, $src)>;
242 def : Pat<(truncstorei32 i64:$src, ADDRrr:$addr), (STrr ADDRrr:$addr, $src)>;
243 def : Pat<(truncstorei32 i64:$src, ADDRri:$addr), (STri ADDRri:$addr, $src)>;
245 } // Predicates = [Is64Bit]
248 //===----------------------------------------------------------------------===//
249 // 64-bit Conditionals.
250 //===----------------------------------------------------------------------===//
252 // Flag-setting instructions like subcc and addcc set both icc and xcc flags.
253 // The icc flags correspond to the 32-bit result, and the xcc are for the
254 // full 64-bit result.
256 // We reuse CMPICC SDNodes for compares, but use new BRXCC branch nodes for
257 // 64-bit compares. See LowerBR_CC.
260 def BPXCC : BranchSP<0, (ins brtarget:$dst, CCOp:$cc),
262 [(SPbrxcc bb:$dst, imm:$cc)]>;