lib/Target/Sparc/SparcISelLowering.h

   1 //===-- SparcISelLowering.h - Sparc DAG Lowering Interface ------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the interfaces that Sparc uses to lower LLVM code into a
  11 // selection DAG.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #ifndef SPARC_ISELLOWERING_H
  16 #define SPARC_ISELLOWERING_H
  17
  18 #include "Sparc.h"
  19 #include "llvm/Target/TargetLowering.h"
  20
  21 namespace llvm {
  22   class SparcSubtarget;
  23
  24   namespace SPISD {
  25     enum {
  26       FIRST_NUMBER = ISD::BUILTIN_OP_END,
  27       CMPICC,      // Compare two GPR operands, set icc+xcc.
  28       CMPFCC,      // Compare two FP operands, set fcc.
  29       BRICC,       // Branch to dest on icc condition
  30       BRXCC,       // Branch to dest on xcc condition (64-bit only).
  31       BRFCC,       // Branch to dest on fcc condition
  32       SELECT_ICC,  // Select between two values using the current ICC flags.
  33       SELECT_XCC,  // Select between two values using the current XCC flags.
  34       SELECT_FCC,  // Select between two values using the current FCC flags.
  35
  36       Hi, Lo,      // Hi/Lo operations, typically on a global address.
  37
  38       FTOI,        // FP to Int within a FP register.
  39       ITOF,        // Int to FP within a FP register.
  40
  41       CALL,        // A call instruction.
  42       RET_FLAG,    // Return with a flag operand.
  43       GLOBAL_BASE_REG, // Global base reg for PIC.
  44       FLUSHW,      // FLUSH register windows to stack.
  45
  46       TLS_ADD,     // For Thread Local Storage (TLS).
  47       TLS_LD,
  48       TLS_CALL
  49     };
  50   }
  51
  52   class SparcTargetLowering : public TargetLowering {
  53     const SparcSubtarget *Subtarget;
  54   public:
  55     SparcTargetLowering(TargetMachine &TM);
  56     virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
  57
  58     /// computeMaskedBitsForTargetNode - Determine which of the bits specified
  59     /// in Mask are known to be either zero or one and return them in the
  60     /// KnownZero/KnownOne bitsets.
  61     virtual void computeMaskedBitsForTargetNode(const SDValue Op,
  62                                                 APInt &KnownZero,
  63                                                 APInt &KnownOne,
  64                                                 const SelectionDAG &DAG,
  65                                                 unsigned Depth = 0) const;
  66
  67     virtual MachineBasicBlock *
  68       EmitInstrWithCustomInserter(MachineInstr *MI,
  69                                   MachineBasicBlock *MBB) const;
  70
  71     virtual const char *getTargetNodeName(unsigned Opcode) const;
  72
  73     ConstraintType getConstraintType(const std::string &Constraint) const;
  74     std::pair<unsigned, const TargetRegisterClass*>
  75     getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const;
  76
  77     virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
  78     virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
  79
  80     virtual SDValue
  81       LowerFormalArguments(SDValue Chain,
  82                            CallingConv::ID CallConv,
  83                            bool isVarArg,
  84                            const SmallVectorImpl<ISD::InputArg> &Ins,
  85                            SDLoc dl, SelectionDAG &DAG,
  86                            SmallVectorImpl<SDValue> &InVals) const;
  87     SDValue LowerFormalArguments_32(SDValue Chain,
  88                                     CallingConv::ID CallConv,
  89                                     bool isVarArg,
  90                                     const SmallVectorImpl<ISD::InputArg> &Ins,
  91                                     SDLoc dl, SelectionDAG &DAG,
  92                                     SmallVectorImpl<SDValue> &InVals) const;
  93     SDValue LowerFormalArguments_64(SDValue Chain,
  94                                     CallingConv::ID CallConv,
  95                                     bool isVarArg,
  96                                     const SmallVectorImpl<ISD::InputArg> &Ins,
  97                                     SDLoc dl, SelectionDAG &DAG,
  98                                     SmallVectorImpl<SDValue> &InVals) const;
  99
 100     virtual SDValue
 101       LowerCall(TargetLowering::CallLoweringInfo &CLI,
 102                 SmallVectorImpl<SDValue> &InVals) const;
 103     SDValue LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
 104                          SmallVectorImpl<SDValue> &InVals) const;
 105     SDValue LowerCall_64(TargetLowering::CallLoweringInfo &CLI,
 106                          SmallVectorImpl<SDValue> &InVals) const;
 107
 108     virtual SDValue
 109       LowerReturn(SDValue Chain,
 110                   CallingConv::ID CallConv, bool isVarArg,
 111                   const SmallVectorImpl<ISD::OutputArg> &Outs,
 112                   const SmallVectorImpl<SDValue> &OutVals,
 113                   SDLoc dl, SelectionDAG &DAG) const;
 114     SDValue LowerReturn_32(SDValue Chain,
 115                            CallingConv::ID CallConv, bool IsVarArg,
 116                            const SmallVectorImpl<ISD::OutputArg> &Outs,
 117                            const SmallVectorImpl<SDValue> &OutVals,
 118                            SDLoc DL, SelectionDAG &DAG) const;
 119     SDValue LowerReturn_64(SDValue Chain,
 120                            CallingConv::ID CallConv, bool IsVarArg,
 121                            const SmallVectorImpl<ISD::OutputArg> &Outs,
 122                            const SmallVectorImpl<SDValue> &OutVals,
 123                            SDLoc DL, SelectionDAG &DAG) const;
 124
 125     SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
 126     SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
 127     SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
 128     SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
 129
 130     unsigned getSRetArgSize(SelectionDAG &DAG, SDValue Callee) const;
 131     SDValue withTargetFlags(SDValue Op, unsigned TF, SelectionDAG &DAG) const;
 132     SDValue makeHiLoPair(SDValue Op, unsigned HiTF, unsigned LoTF,
 133                          SelectionDAG &DAG) const;
 134     SDValue makeAddress(SDValue Op, SelectionDAG &DAG) const;
 135
 136     SDValue LowerF128_LibCallArg(SDValue Chain, ArgListTy &Args,
 137                                  SDValue Arg, SDLoc DL,
 138                                  SelectionDAG &DAG) const;
 139     SDValue LowerF128Op(SDValue Op, SelectionDAG &DAG,
 140                         const char *LibFuncName,
 141                         unsigned numArgs) const;
 142     SDValue LowerF128Compare(SDValue LHS, SDValue RHS,
 143                              unsigned &SPCC,
 144                              SDLoc DL,
 145                              SelectionDAG &DAG) const;
 146
 147     bool ShouldShrinkFPConstant(EVT VT) const {
 148       // Do not shrink FP constpool if VT == MVT::f128.
 149       // (ldd, call _Q_fdtoq) is more expensive than two ldds.
 150       return VT != MVT::f128;
 151     }
 152   };
 153 } // end namespace llvm
 154
 155 #endif    // SPARC_ISELLOWERING_H