1 //===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the interfaces that Sparc uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "SparcISelLowering.h"
16 #include "SparcTargetMachine.h"
17 #include "llvm/Function.h"
18 #include "llvm/CodeGen/CallingConvLower.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/SelectionDAG.h"
24 #include "llvm/ADT/VectorExtras.h"
25 #include "llvm/Support/ErrorHandling.h"
29 //===----------------------------------------------------------------------===//
30 // Calling Convention Implementation
31 //===----------------------------------------------------------------------===//
33 #include "SparcGenCallingConv.inc"
35 static SDValue LowerRET(SDValue Op, SelectionDAG &DAG) {
36 // CCValAssign - represent the assignment of the return value to locations.
37 SmallVector<CCValAssign, 16> RVLocs;
38 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
39 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
40 DebugLoc dl = Op.getDebugLoc();
42 // CCState - Info about the registers and stack slot.
43 CCState CCInfo(CC, isVarArg, DAG.getTarget(), RVLocs, DAG.getContext());
45 // Analize return values of ISD::RET
46 CCInfo.AnalyzeReturn(Op.getNode(), RetCC_Sparc32);
48 // If this is the first return lowered for this function, add the regs to the
49 // liveout set for the function.
50 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
51 for (unsigned i = 0; i != RVLocs.size(); ++i)
52 if (RVLocs[i].isRegLoc())
53 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
56 SDValue Chain = Op.getOperand(0);
59 // Copy the result values into the output registers.
60 for (unsigned i = 0; i != RVLocs.size(); ++i) {
61 CCValAssign &VA = RVLocs[i];
62 assert(VA.isRegLoc() && "Can only return in registers!");
64 // ISD::RET => ret chain, (regnum1,val1), ...
65 // So i*2+1 index only the regnums.
66 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
67 Op.getOperand(i*2+1), Flag);
69 // Guarantee that all emitted copies are stuck together with flags.
70 Flag = Chain.getValue(1);
74 return DAG.getNode(SPISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
75 return DAG.getNode(SPISD::RET_FLAG, dl, MVT::Other, Chain);
78 /// LowerArguments - V8 uses a very simple ABI, where all values are passed in
79 /// either one or two GPRs, including FP values. TODO: we should pass FP values
80 /// in FP registers for fastcc functions.
82 SparcTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op,
84 MachineFunction &MF = DAG.getMachineFunction();
85 MachineRegisterInfo &RegInfo = MF.getRegInfo();
86 SDValue Root = Op.getOperand(0);
87 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
88 unsigned CC = MF.getFunction()->getCallingConv();
89 DebugLoc dl = Op.getDebugLoc();
91 // Assign locations to all of the incoming arguments.
92 SmallVector<CCValAssign, 16> ArgLocs;
93 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs, DAG.getContext());
94 CCInfo.AnalyzeFormalArguments(Op.getNode(), CC_Sparc32);
96 static const unsigned ArgRegs[] = {
97 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
99 const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6;
100 unsigned ArgOffset = 68;
102 SmallVector<SDValue, 16> ArgValues;
103 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
105 CCValAssign &VA = ArgLocs[i];
106 // FIXME: We ignore the register assignments of AnalyzeFormalArguments
107 // because it doesn't know how to split a double into two i32 registers.
108 MVT ObjectVT = VA.getValVT();
109 switch (ObjectVT.getSimpleVT()) {
110 default: llvm_unreachable("Unhandled argument type!");
115 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
116 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
117 MF.getRegInfo().addLiveIn(*CurArgReg++, VReg);
118 SDValue Arg = DAG.getCopyFromReg(Root, dl, VReg, MVT::i32);
119 if (ObjectVT != MVT::i32) {
120 unsigned AssertOp = ISD::AssertSext;
121 Arg = DAG.getNode(AssertOp, dl, MVT::i32, Arg,
122 DAG.getValueType(ObjectVT));
123 Arg = DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, Arg);
125 ArgValues.push_back(Arg);
127 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
128 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
130 if (ObjectVT == MVT::i32) {
131 Load = DAG.getLoad(MVT::i32, dl, Root, FIPtr, NULL, 0);
133 ISD::LoadExtType LoadOp = ISD::SEXTLOAD;
135 // Sparc is big endian, so add an offset based on the ObjectVT.
136 unsigned Offset = 4-std::max(1U, ObjectVT.getSizeInBits()/8);
137 FIPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIPtr,
138 DAG.getConstant(Offset, MVT::i32));
139 Load = DAG.getExtLoad(LoadOp, dl, MVT::i32, Root, FIPtr,
141 Load = DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, Load);
143 ArgValues.push_back(Load);
149 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
150 // FP value is passed in an integer register.
151 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
152 MF.getRegInfo().addLiveIn(*CurArgReg++, VReg);
153 SDValue Arg = DAG.getCopyFromReg(Root, dl, VReg, MVT::i32);
155 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Arg);
156 ArgValues.push_back(Arg);
158 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
159 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
160 SDValue Load = DAG.getLoad(MVT::f32, dl, Root, FIPtr, NULL, 0);
161 ArgValues.push_back(Load);
170 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
171 unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
172 MF.getRegInfo().addLiveIn(*CurArgReg++, VRegHi);
173 HiVal = DAG.getCopyFromReg(Root, dl, VRegHi, MVT::i32);
175 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
176 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
177 HiVal = DAG.getLoad(MVT::i32, dl, Root, FIPtr, NULL, 0);
181 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
182 unsigned VRegLo = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
183 MF.getRegInfo().addLiveIn(*CurArgReg++, VRegLo);
184 LoVal = DAG.getCopyFromReg(Root, dl, VRegLo, MVT::i32);
186 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4);
187 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
188 LoVal = DAG.getLoad(MVT::i32, dl, Root, FIPtr, NULL, 0);
191 // Compose the two halves together into an i64 unit.
193 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal);
195 // If we want a double, do a bit convert.
196 if (ObjectVT == MVT::f64)
197 WholeValue = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, WholeValue);
199 ArgValues.push_back(WholeValue);
206 // Store remaining ArgRegs to the stack if this is a varargs function.
208 // Remember the vararg offset for the va_start implementation.
209 VarArgsFrameOffset = ArgOffset;
211 std::vector<SDValue> OutChains;
213 for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
214 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
215 MF.getRegInfo().addLiveIn(*CurArgReg, VReg);
216 SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), dl, VReg, MVT::i32);
218 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
219 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
221 OutChains.push_back(DAG.getStore(DAG.getRoot(), dl, Arg, FIPtr, NULL, 0));
225 if (!OutChains.empty()) {
226 OutChains.push_back(Root);
227 Root = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
228 &OutChains[0], OutChains.size());
232 ArgValues.push_back(Root);
234 // Return the new list of results.
235 return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
236 &ArgValues[0], ArgValues.size()).getValue(Op.getResNo());
239 static SDValue LowerCALL(SDValue Op, SelectionDAG &DAG) {
240 CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
241 unsigned CallingConv = TheCall->getCallingConv();
242 SDValue Chain = TheCall->getChain();
243 SDValue Callee = TheCall->getCallee();
244 bool isVarArg = TheCall->isVarArg();
245 DebugLoc dl = TheCall->getDebugLoc();
248 // Analyze operands of the call, assigning locations to each operand.
249 SmallVector<CCValAssign, 16> ArgLocs;
250 CCState CCInfo(CallingConv, isVarArg, DAG.getTarget(), ArgLocs);
251 CCInfo.AnalyzeCallOperands(Op.getNode(), CC_Sparc32);
253 // Get the size of the outgoing arguments stack space requirement.
254 unsigned ArgsSize = CCInfo.getNextStackOffset();
255 // FIXME: We can't use this until f64 is known to take two GPRs.
259 // Count the size of the outgoing arguments.
260 unsigned ArgsSize = 0;
261 for (unsigned i = 0, e = TheCall->getNumArgs(); i != e; ++i) {
262 switch (TheCall->getArg(i).getValueType().getSimpleVT()) {
263 default: llvm_unreachable("Unknown value type!");
278 ArgsSize -= 4*6; // Space for first 6 arguments is prereserved.
283 // Keep stack frames 8-byte aligned.
284 ArgsSize = (ArgsSize+7) & ~7;
286 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, true));
288 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
289 SmallVector<SDValue, 8> MemOpChains;
292 // Walk the register/memloc assignments, inserting copies/loads.
293 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
294 CCValAssign &VA = ArgLocs[i];
296 // Arguments start after the 5 first operands of ISD::CALL
297 SDValue Arg = TheCall->getArg(i);
299 // Promote the value if needed.
300 switch (VA.getLocInfo()) {
301 default: llvm_unreachable("Unknown loc info!");
302 case CCValAssign::Full: break;
303 case CCValAssign::SExt:
304 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
306 case CCValAssign::ZExt:
307 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
309 case CCValAssign::AExt:
310 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
314 // Arguments that can be passed on register must be kept at
317 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
321 assert(VA.isMemLoc());
323 // Create a store off the stack pointer for this argument.
324 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
325 // FIXME: VERIFY THAT 68 IS RIGHT.
326 SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset()+68);
327 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
328 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
332 static const unsigned ArgRegs[] = {
333 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
335 unsigned ArgOffset = 68;
337 for (unsigned i = 0, e = TheCall->getNumArgs(); i != e; ++i) {
338 SDValue Val = TheCall->getArg(i);
339 MVT ObjectVT = Val.getValueType();
340 SDValue ValToStore(0, 0);
342 switch (ObjectVT.getSimpleVT()) {
343 default: llvm_unreachable("Unhandled argument type!");
347 if (RegsToPass.size() >= 6) {
350 RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Val));
355 if (RegsToPass.size() >= 6) {
358 // Convert this to a FP value in an int reg.
359 Val = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Val);
360 RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Val));
365 if (RegsToPass.size() >= 6) {
366 ValToStore = Val; // Whole thing is passed in memory.
370 // Break into top and bottom parts by storing to the stack and loading
371 // out the parts as integers. Top part goes in a reg.
372 SDValue StackPtr = DAG.CreateStackTemporary(MVT::f64, MVT::i32);
373 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
374 Val, StackPtr, NULL, 0);
375 // Sparc is big-endian, so the high part comes first.
376 SDValue Hi = DAG.getLoad(MVT::i32, dl, Store, StackPtr, NULL, 0, 0);
377 // Increment the pointer to the other half.
378 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
379 DAG.getIntPtrConstant(4));
380 // Load the low part.
381 SDValue Lo = DAG.getLoad(MVT::i32, dl, Store, StackPtr, NULL, 0, 0);
383 RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Hi));
385 if (RegsToPass.size() >= 6) {
390 RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Lo));
396 if (RegsToPass.size() >= 6) {
397 ValToStore = Val; // Whole thing is passed in memory.
401 // Split the value into top and bottom part. Top part goes in a reg.
402 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Val,
403 DAG.getConstant(1, MVT::i32));
404 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Val,
405 DAG.getConstant(0, MVT::i32));
406 RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Hi));
408 if (RegsToPass.size() >= 6) {
413 RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Lo));
419 if (ValToStore.getNode()) {
420 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
421 SDValue PtrOff = DAG.getConstant(ArgOffset, MVT::i32);
422 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
423 MemOpChains.push_back(DAG.getStore(Chain, dl, ValToStore,
426 ArgOffset += ObjSize;
430 // Emit all stores, make sure the occur before any copies into physregs.
431 if (!MemOpChains.empty())
432 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
433 &MemOpChains[0], MemOpChains.size());
435 // Build a sequence of copy-to-reg nodes chained together with token
436 // chain and flag operands which copy the outgoing args into registers.
437 // The InFlag in necessary since all emited instructions must be
440 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
441 unsigned Reg = RegsToPass[i].first;
442 // Remap I0->I7 -> O0->O7.
443 if (Reg >= SP::I0 && Reg <= SP::I7)
444 Reg = Reg-SP::I0+SP::O0;
446 Chain = DAG.getCopyToReg(Chain, dl, Reg, RegsToPass[i].second, InFlag);
447 InFlag = Chain.getValue(1);
450 // If the callee is a GlobalAddress node (quite common, every direct call is)
451 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
452 // Likewise ExternalSymbol -> TargetExternalSymbol.
453 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
454 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32);
455 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
456 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
458 std::vector<MVT> NodeTys;
459 NodeTys.push_back(MVT::Other); // Returns a chain
460 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
461 SDValue Ops[] = { Chain, Callee, InFlag };
462 Chain = DAG.getNode(SPISD::CALL, dl, NodeTys, Ops, InFlag.getNode() ? 3 : 2);
463 InFlag = Chain.getValue(1);
465 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true),
466 DAG.getIntPtrConstant(0, true), InFlag);
467 InFlag = Chain.getValue(1);
469 // Assign locations to each value returned by this call.
470 SmallVector<CCValAssign, 16> RVLocs;
471 CCState RVInfo(CallingConv, isVarArg, DAG.getTarget(),
472 RVLocs, DAG.getContext());
474 RVInfo.AnalyzeCallResult(TheCall, RetCC_Sparc32);
475 SmallVector<SDValue, 8> ResultVals;
477 // Copy all of the result registers out of their specified physreg.
478 for (unsigned i = 0; i != RVLocs.size(); ++i) {
479 unsigned Reg = RVLocs[i].getLocReg();
481 // Remap I0->I7 -> O0->O7.
482 if (Reg >= SP::I0 && Reg <= SP::I7)
483 Reg = Reg-SP::I0+SP::O0;
485 Chain = DAG.getCopyFromReg(Chain, dl, Reg,
486 RVLocs[i].getValVT(), InFlag).getValue(1);
487 InFlag = Chain.getValue(2);
488 ResultVals.push_back(Chain.getValue(0));
491 ResultVals.push_back(Chain);
493 // Merge everything together with a MERGE_VALUES node.
494 return DAG.getNode(ISD::MERGE_VALUES, dl,
495 TheCall->getVTList(), &ResultVals[0],
501 //===----------------------------------------------------------------------===//
502 // TargetLowering Implementation
503 //===----------------------------------------------------------------------===//
505 /// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC
507 static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) {
509 default: llvm_unreachable("Unknown integer condition code!");
510 case ISD::SETEQ: return SPCC::ICC_E;
511 case ISD::SETNE: return SPCC::ICC_NE;
512 case ISD::SETLT: return SPCC::ICC_L;
513 case ISD::SETGT: return SPCC::ICC_G;
514 case ISD::SETLE: return SPCC::ICC_LE;
515 case ISD::SETGE: return SPCC::ICC_GE;
516 case ISD::SETULT: return SPCC::ICC_CS;
517 case ISD::SETULE: return SPCC::ICC_LEU;
518 case ISD::SETUGT: return SPCC::ICC_GU;
519 case ISD::SETUGE: return SPCC::ICC_CC;
523 /// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC
525 static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
527 default: llvm_unreachable("Unknown fp condition code!");
529 case ISD::SETOEQ: return SPCC::FCC_E;
531 case ISD::SETUNE: return SPCC::FCC_NE;
533 case ISD::SETOLT: return SPCC::FCC_L;
535 case ISD::SETOGT: return SPCC::FCC_G;
537 case ISD::SETOLE: return SPCC::FCC_LE;
539 case ISD::SETOGE: return SPCC::FCC_GE;
540 case ISD::SETULT: return SPCC::FCC_UL;
541 case ISD::SETULE: return SPCC::FCC_ULE;
542 case ISD::SETUGT: return SPCC::FCC_UG;
543 case ISD::SETUGE: return SPCC::FCC_UGE;
544 case ISD::SETUO: return SPCC::FCC_U;
545 case ISD::SETO: return SPCC::FCC_O;
546 case ISD::SETONE: return SPCC::FCC_LG;
547 case ISD::SETUEQ: return SPCC::FCC_UE;
552 SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
553 : TargetLowering(TM) {
555 // Set up the register classes.
556 addRegisterClass(MVT::i32, SP::IntRegsRegisterClass);
557 addRegisterClass(MVT::f32, SP::FPRegsRegisterClass);
558 addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass);
560 // Turn FP extload into load/fextend
561 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
562 // Sparc doesn't have i1 sign extending load
563 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
564 // Turn FP truncstore into trunc + store.
565 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
567 // Custom legalize GlobalAddress nodes into LO/HI parts.
568 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
569 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
570 setOperationAction(ISD::ConstantPool , MVT::i32, Custom);
572 // Sparc doesn't have sext_inreg, replace them with shl/sra
573 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
574 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
575 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
577 // Sparc has no REM or DIVREM operations.
578 setOperationAction(ISD::UREM, MVT::i32, Expand);
579 setOperationAction(ISD::SREM, MVT::i32, Expand);
580 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
581 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
583 // Custom expand fp<->sint
584 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
585 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
588 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
589 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
591 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
592 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
594 // Sparc has no select or setcc: expand to SELECT_CC.
595 setOperationAction(ISD::SELECT, MVT::i32, Expand);
596 setOperationAction(ISD::SELECT, MVT::f32, Expand);
597 setOperationAction(ISD::SELECT, MVT::f64, Expand);
598 setOperationAction(ISD::SETCC, MVT::i32, Expand);
599 setOperationAction(ISD::SETCC, MVT::f32, Expand);
600 setOperationAction(ISD::SETCC, MVT::f64, Expand);
602 // Sparc doesn't have BRCOND either, it has BR_CC.
603 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
604 setOperationAction(ISD::BRIND, MVT::Other, Expand);
605 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
606 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
607 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
608 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
610 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
611 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
612 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
614 // SPARC has no intrinsics for these particular operations.
615 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
617 setOperationAction(ISD::FSIN , MVT::f64, Expand);
618 setOperationAction(ISD::FCOS , MVT::f64, Expand);
619 setOperationAction(ISD::FREM , MVT::f64, Expand);
620 setOperationAction(ISD::FSIN , MVT::f32, Expand);
621 setOperationAction(ISD::FCOS , MVT::f32, Expand);
622 setOperationAction(ISD::FREM , MVT::f32, Expand);
623 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
624 setOperationAction(ISD::CTTZ , MVT::i32, Expand);
625 setOperationAction(ISD::CTLZ , MVT::i32, Expand);
626 setOperationAction(ISD::ROTL , MVT::i32, Expand);
627 setOperationAction(ISD::ROTR , MVT::i32, Expand);
628 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
629 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
630 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
631 setOperationAction(ISD::FPOW , MVT::f64, Expand);
632 setOperationAction(ISD::FPOW , MVT::f32, Expand);
634 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
635 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
636 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
638 // FIXME: Sparc provides these multiplies, but we don't have them yet.
639 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
640 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
642 // We don't have line number support yet.
643 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
644 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
645 setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
646 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
648 // RET must be custom lowered, to meet ABI requirements
649 setOperationAction(ISD::RET , MVT::Other, Custom);
651 // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
652 setOperationAction(ISD::VASTART , MVT::Other, Custom);
653 // VAARG needs to be lowered to not do unaligned accesses for doubles.
654 setOperationAction(ISD::VAARG , MVT::Other, Custom);
656 // Use the default implementation.
657 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
658 setOperationAction(ISD::VAEND , MVT::Other, Expand);
659 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
660 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand);
661 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
663 // No debug info support yet.
664 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
665 setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
666 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
667 setOperationAction(ISD::DECLARE, MVT::Other, Expand);
669 setStackPointerRegisterToSaveRestore(SP::O6);
671 if (TM.getSubtarget<SparcSubtarget>().isV9())
672 setOperationAction(ISD::CTPOP, MVT::i32, Legal);
674 computeRegisterProperties();
677 const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const {
680 case SPISD::CMPICC: return "SPISD::CMPICC";
681 case SPISD::CMPFCC: return "SPISD::CMPFCC";
682 case SPISD::BRICC: return "SPISD::BRICC";
683 case SPISD::BRFCC: return "SPISD::BRFCC";
684 case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC";
685 case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC";
686 case SPISD::Hi: return "SPISD::Hi";
687 case SPISD::Lo: return "SPISD::Lo";
688 case SPISD::FTOI: return "SPISD::FTOI";
689 case SPISD::ITOF: return "SPISD::ITOF";
690 case SPISD::CALL: return "SPISD::CALL";
691 case SPISD::RET_FLAG: return "SPISD::RET_FLAG";
695 /// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
696 /// be zero. Op is expected to be a target specific node. Used by DAG
698 void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
702 const SelectionDAG &DAG,
703 unsigned Depth) const {
704 APInt KnownZero2, KnownOne2;
705 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
707 switch (Op.getOpcode()) {
709 case SPISD::SELECT_ICC:
710 case SPISD::SELECT_FCC:
711 DAG.ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne,
713 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2,
715 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
716 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
718 // Only known if known in both the LHS and RHS.
719 KnownOne &= KnownOne2;
720 KnownZero &= KnownZero2;
725 // Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so
726 // set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition.
727 static void LookThroughSetCC(SDValue &LHS, SDValue &RHS,
728 ISD::CondCode CC, unsigned &SPCC) {
729 if (isa<ConstantSDNode>(RHS) &&
730 cast<ConstantSDNode>(RHS)->getZExtValue() == 0 &&
732 ((LHS.getOpcode() == SPISD::SELECT_ICC &&
733 LHS.getOperand(3).getOpcode() == SPISD::CMPICC) ||
734 (LHS.getOpcode() == SPISD::SELECT_FCC &&
735 LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) &&
736 isa<ConstantSDNode>(LHS.getOperand(0)) &&
737 isa<ConstantSDNode>(LHS.getOperand(1)) &&
738 cast<ConstantSDNode>(LHS.getOperand(0))->getZExtValue() == 1 &&
739 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() == 0) {
740 SDValue CMPCC = LHS.getOperand(3);
741 SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getZExtValue();
742 LHS = CMPCC.getOperand(0);
743 RHS = CMPCC.getOperand(1);
747 static SDValue LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) {
748 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
749 // FIXME there isn't really any debug info here
750 DebugLoc dl = Op.getDebugLoc();
751 SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
752 SDValue Hi = DAG.getNode(SPISD::Hi, dl, MVT::i32, GA);
753 SDValue Lo = DAG.getNode(SPISD::Lo, dl, MVT::i32, GA);
754 return DAG.getNode(ISD::ADD, dl, MVT::i32, Lo, Hi);
757 static SDValue LowerCONSTANTPOOL(SDValue Op, SelectionDAG &DAG) {
758 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
759 // FIXME there isn't really any debug info here
760 DebugLoc dl = Op.getDebugLoc();
761 Constant *C = N->getConstVal();
762 SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment());
763 SDValue Hi = DAG.getNode(SPISD::Hi, dl, MVT::i32, CP);
764 SDValue Lo = DAG.getNode(SPISD::Lo, dl, MVT::i32, CP);
765 return DAG.getNode(ISD::ADD, dl, MVT::i32, Lo, Hi);
768 static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
769 DebugLoc dl = Op.getDebugLoc();
770 // Convert the fp value to integer in an FP register.
771 assert(Op.getValueType() == MVT::i32);
772 Op = DAG.getNode(SPISD::FTOI, dl, MVT::f32, Op.getOperand(0));
773 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
776 static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
777 DebugLoc dl = Op.getDebugLoc();
778 assert(Op.getOperand(0).getValueType() == MVT::i32);
779 SDValue Tmp = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Op.getOperand(0));
780 // Convert the int value to FP in an FP register.
781 return DAG.getNode(SPISD::ITOF, dl, Op.getValueType(), Tmp);
784 static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) {
785 SDValue Chain = Op.getOperand(0);
786 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
787 SDValue LHS = Op.getOperand(2);
788 SDValue RHS = Op.getOperand(3);
789 SDValue Dest = Op.getOperand(4);
790 DebugLoc dl = Op.getDebugLoc();
791 unsigned Opc, SPCC = ~0U;
793 // If this is a br_cc of a "setcc", and if the setcc got lowered into
794 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
795 LookThroughSetCC(LHS, RHS, CC, SPCC);
797 // Get the condition flag.
799 if (LHS.getValueType() == MVT::i32) {
800 std::vector<MVT> VTs;
801 VTs.push_back(MVT::i32);
802 VTs.push_back(MVT::Flag);
803 SDValue Ops[2] = { LHS, RHS };
804 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, VTs, Ops, 2).getValue(1);
805 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
808 CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Flag, LHS, RHS);
809 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
812 return DAG.getNode(Opc, dl, MVT::Other, Chain, Dest,
813 DAG.getConstant(SPCC, MVT::i32), CompareFlag);
816 static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
817 SDValue LHS = Op.getOperand(0);
818 SDValue RHS = Op.getOperand(1);
819 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
820 SDValue TrueVal = Op.getOperand(2);
821 SDValue FalseVal = Op.getOperand(3);
822 DebugLoc dl = Op.getDebugLoc();
823 unsigned Opc, SPCC = ~0U;
825 // If this is a select_cc of a "setcc", and if the setcc got lowered into
826 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
827 LookThroughSetCC(LHS, RHS, CC, SPCC);
830 if (LHS.getValueType() == MVT::i32) {
831 std::vector<MVT> VTs;
832 VTs.push_back(LHS.getValueType()); // subcc returns a value
833 VTs.push_back(MVT::Flag);
834 SDValue Ops[2] = { LHS, RHS };
835 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, VTs, Ops, 2).getValue(1);
836 Opc = SPISD::SELECT_ICC;
837 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
839 CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Flag, LHS, RHS);
840 Opc = SPISD::SELECT_FCC;
841 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
843 return DAG.getNode(Opc, dl, TrueVal.getValueType(), TrueVal, FalseVal,
844 DAG.getConstant(SPCC, MVT::i32), CompareFlag);
847 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
848 SparcTargetLowering &TLI) {
849 // vastart just stores the address of the VarArgsFrameIndex slot into the
850 // memory location argument.
851 DebugLoc dl = Op.getDebugLoc();
852 SDValue Offset = DAG.getNode(ISD::ADD, dl, MVT::i32,
853 DAG.getRegister(SP::I6, MVT::i32),
854 DAG.getConstant(TLI.getVarArgsFrameOffset(),
856 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
857 return DAG.getStore(Op.getOperand(0), dl, Offset, Op.getOperand(1), SV, 0);
860 static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) {
861 SDNode *Node = Op.getNode();
862 MVT VT = Node->getValueType(0);
863 SDValue InChain = Node->getOperand(0);
864 SDValue VAListPtr = Node->getOperand(1);
865 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
866 DebugLoc dl = Node->getDebugLoc();
867 SDValue VAList = DAG.getLoad(MVT::i32, dl, InChain, VAListPtr, SV, 0);
868 // Increment the pointer, VAList, to the next vaarg
869 SDValue NextPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, VAList,
870 DAG.getConstant(VT.getSizeInBits()/8,
872 // Store the incremented VAList to the legalized pointer
873 InChain = DAG.getStore(VAList.getValue(1), dl, NextPtr,
875 // Load the actual argument out of the pointer VAList, unless this is an
878 return DAG.getLoad(VT, dl, InChain, VAList, NULL, 0);
880 // Otherwise, load it as i64, then do a bitconvert.
881 SDValue V = DAG.getLoad(MVT::i64, dl, InChain, VAList, NULL, 0);
883 // Bit-Convert the value to f64.
885 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, V),
888 return DAG.getMergeValues(Ops, 2, dl);
891 static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) {
892 SDValue Chain = Op.getOperand(0); // Legalize the chain.
893 SDValue Size = Op.getOperand(1); // Legalize the size.
894 DebugLoc dl = Op.getDebugLoc();
896 unsigned SPReg = SP::O6;
897 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, MVT::i32);
898 SDValue NewSP = DAG.getNode(ISD::SUB, dl, MVT::i32, SP, Size); // Value
899 Chain = DAG.getCopyToReg(SP.getValue(1), dl, SPReg, NewSP); // Output chain
901 // The resultant pointer is actually 16 words from the bottom of the stack,
902 // to provide a register spill area.
903 SDValue NewVal = DAG.getNode(ISD::ADD, dl, MVT::i32, NewSP,
904 DAG.getConstant(96, MVT::i32));
905 SDValue Ops[2] = { NewVal, Chain };
906 return DAG.getMergeValues(Ops, 2, dl);
910 SDValue SparcTargetLowering::
911 LowerOperation(SDValue Op, SelectionDAG &DAG) {
912 switch (Op.getOpcode()) {
913 default: llvm_unreachable("Should not custom lower this!");
914 // Frame & Return address. Currently unimplemented
915 case ISD::RETURNADDR: return SDValue();
916 case ISD::FRAMEADDR: return SDValue();
917 case ISD::GlobalTLSAddress:
918 llvm_unreachable("TLS not implemented for Sparc.");
919 case ISD::GlobalAddress: return LowerGLOBALADDRESS(Op, DAG);
920 case ISD::ConstantPool: return LowerCONSTANTPOOL(Op, DAG);
921 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
922 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
923 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
924 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
925 case ISD::VASTART: return LowerVASTART(Op, DAG, *this);
926 case ISD::VAARG: return LowerVAARG(Op, DAG);
927 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
928 case ISD::CALL: return LowerCALL(Op, DAG);
929 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
930 case ISD::RET: return LowerRET(Op, DAG);
935 SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
936 MachineBasicBlock *BB) const {
937 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
940 DebugLoc dl = MI->getDebugLoc();
941 // Figure out the conditional branch opcode to use for this select_cc.
942 switch (MI->getOpcode()) {
943 default: llvm_unreachable("Unknown SELECT_CC!");
944 case SP::SELECT_CC_Int_ICC:
945 case SP::SELECT_CC_FP_ICC:
946 case SP::SELECT_CC_DFP_ICC:
947 BROpcode = SP::BCOND;
949 case SP::SELECT_CC_Int_FCC:
950 case SP::SELECT_CC_FP_FCC:
951 case SP::SELECT_CC_DFP_FCC:
952 BROpcode = SP::FBCOND;
956 CC = (SPCC::CondCodes)MI->getOperand(3).getImm();
958 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
959 // control-flow pattern. The incoming instruction knows the destination vreg
960 // to set, the condition code register to branch on, the true/false values to
961 // select between, and a branch opcode to use.
962 const BasicBlock *LLVM_BB = BB->getBasicBlock();
963 MachineFunction::iterator It = BB;
970 // fallthrough --> copy0MBB
971 MachineBasicBlock *thisMBB = BB;
972 MachineFunction *F = BB->getParent();
973 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
974 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
975 BuildMI(BB, dl, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC);
976 F->insert(It, copy0MBB);
977 F->insert(It, sinkMBB);
978 // Update machine-CFG edges by transferring all successors of the current
979 // block to the new block which will contain the Phi node for the select.
980 sinkMBB->transferSuccessors(BB);
981 // Next, add the true and fallthrough blocks as its successors.
982 BB->addSuccessor(copy0MBB);
983 BB->addSuccessor(sinkMBB);
987 // # fallthrough to sinkMBB
990 // Update machine-CFG edges
991 BB->addSuccessor(sinkMBB);
994 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
997 BuildMI(BB, dl, TII.get(SP::PHI), MI->getOperand(0).getReg())
998 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
999 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
1001 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
1005 //===----------------------------------------------------------------------===//
1006 // Sparc Inline Assembly Support
1007 //===----------------------------------------------------------------------===//
1009 /// getConstraintType - Given a constraint letter, return the type of
1010 /// constraint it is for this target.
1011 SparcTargetLowering::ConstraintType
1012 SparcTargetLowering::getConstraintType(const std::string &Constraint) const {
1013 if (Constraint.size() == 1) {
1014 switch (Constraint[0]) {
1016 case 'r': return C_RegisterClass;
1020 return TargetLowering::getConstraintType(Constraint);
1023 std::pair<unsigned, const TargetRegisterClass*>
1024 SparcTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
1026 if (Constraint.size() == 1) {
1027 switch (Constraint[0]) {
1029 return std::make_pair(0U, SP::IntRegsRegisterClass);
1033 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
1036 std::vector<unsigned> SparcTargetLowering::
1037 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1039 if (Constraint.size() != 1)
1040 return std::vector<unsigned>();
1042 switch (Constraint[0]) {
1045 return make_vector<unsigned>(SP::L0, SP::L1, SP::L2, SP::L3,
1046 SP::L4, SP::L5, SP::L6, SP::L7,
1047 SP::I0, SP::I1, SP::I2, SP::I3,
1049 SP::O0, SP::O1, SP::O2, SP::O3,
1050 SP::O4, SP::O5, SP::O7, 0);
1053 return std::vector<unsigned>();
1057 SparcTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
1058 // The Sparc target isn't yet aware of offsets.
1062 /// getFunctionAlignment - Return the Log2 alignment of this function.
1063 unsigned SparcTargetLowering::getFunctionAlignment(const Function *) const {