1 //===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the interfaces that Sparc uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "SparcISelLowering.h"
16 #include "SparcTargetMachine.h"
17 #include "llvm/Function.h"
18 #include "llvm/CodeGen/CallingConvLower.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/SelectionDAG.h"
24 #include "llvm/ADT/VectorExtras.h"
28 //===----------------------------------------------------------------------===//
29 // Calling Convention Implementation
30 //===----------------------------------------------------------------------===//
32 #include "SparcGenCallingConv.inc"
34 static SDValue LowerRET(SDValue Op, SelectionDAG &DAG) {
35 // CCValAssign - represent the assignment of the return value to locations.
36 SmallVector<CCValAssign, 16> RVLocs;
37 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
38 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
39 DebugLoc dl = Op.getDebugLoc();
41 // CCState - Info about the registers and stack slot.
42 CCState CCInfo(CC, isVarArg, DAG.getTarget(), RVLocs);
44 // Analize return values of ISD::RET
45 CCInfo.AnalyzeReturn(Op.getNode(), RetCC_Sparc32);
47 // If this is the first return lowered for this function, add the regs to the
48 // liveout set for the function.
49 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
50 for (unsigned i = 0; i != RVLocs.size(); ++i)
51 if (RVLocs[i].isRegLoc())
52 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
55 SDValue Chain = Op.getOperand(0);
58 // Copy the result values into the output registers.
59 for (unsigned i = 0; i != RVLocs.size(); ++i) {
60 CCValAssign &VA = RVLocs[i];
61 assert(VA.isRegLoc() && "Can only return in registers!");
63 // ISD::RET => ret chain, (regnum1,val1), ...
64 // So i*2+1 index only the regnums.
65 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
66 Op.getOperand(i*2+1), Flag);
68 // Guarantee that all emitted copies are stuck together with flags.
69 Flag = Chain.getValue(1);
73 return DAG.getNode(SPISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
74 return DAG.getNode(SPISD::RET_FLAG, dl, MVT::Other, Chain);
77 /// LowerArguments - V8 uses a very simple ABI, where all values are passed in
78 /// either one or two GPRs, including FP values. TODO: we should pass FP values
79 /// in FP registers for fastcc functions.
81 SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
82 SmallVectorImpl<SDValue> &ArgValues,
84 MachineFunction &MF = DAG.getMachineFunction();
85 MachineRegisterInfo &RegInfo = MF.getRegInfo();
87 static const unsigned ArgRegs[] = {
88 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
91 const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6;
92 unsigned ArgOffset = 68;
94 SDValue Root = DAG.getRoot();
95 std::vector<SDValue> OutChains;
97 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
98 MVT ObjectVT = getValueType(I->getType());
100 switch (ObjectVT.getSimpleVT()) {
101 default: assert(0 && "Unhandled argument type!");
106 if (I->use_empty()) { // Argument is dead.
107 if (CurArgReg < ArgRegEnd) ++CurArgReg;
108 ArgValues.push_back(DAG.getUNDEF(ObjectVT));
109 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
110 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
111 MF.getRegInfo().addLiveIn(*CurArgReg++, VReg);
112 SDValue Arg = DAG.getCopyFromReg(Root, dl, VReg, MVT::i32);
113 if (ObjectVT != MVT::i32) {
114 unsigned AssertOp = ISD::AssertSext;
115 Arg = DAG.getNode(AssertOp, dl, MVT::i32, Arg,
116 DAG.getValueType(ObjectVT));
117 Arg = DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, Arg);
119 ArgValues.push_back(Arg);
121 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
122 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
124 if (ObjectVT == MVT::i32) {
125 Load = DAG.getLoad(MVT::i32, dl, Root, FIPtr, NULL, 0);
127 ISD::LoadExtType LoadOp = ISD::SEXTLOAD;
129 // Sparc is big endian, so add an offset based on the ObjectVT.
130 unsigned Offset = 4-std::max(1U, ObjectVT.getSizeInBits()/8);
131 FIPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIPtr,
132 DAG.getConstant(Offset, MVT::i32));
133 Load = DAG.getExtLoad(LoadOp, dl, MVT::i32, Root, FIPtr,
135 Load = DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, Load);
137 ArgValues.push_back(Load);
143 if (I->use_empty()) { // Argument is dead.
144 if (CurArgReg < ArgRegEnd) ++CurArgReg;
145 ArgValues.push_back(DAG.getUNDEF(ObjectVT));
146 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
147 // FP value is passed in an integer register.
148 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
149 MF.getRegInfo().addLiveIn(*CurArgReg++, VReg);
150 SDValue Arg = DAG.getCopyFromReg(Root, dl, VReg, MVT::i32);
152 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Arg);
153 ArgValues.push_back(Arg);
155 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
156 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
157 SDValue Load = DAG.getLoad(MVT::f32, dl, Root, FIPtr, NULL, 0);
158 ArgValues.push_back(Load);
165 if (I->use_empty()) { // Argument is dead.
166 if (CurArgReg < ArgRegEnd) ++CurArgReg;
167 if (CurArgReg < ArgRegEnd) ++CurArgReg;
168 ArgValues.push_back(DAG.getUNDEF(ObjectVT));
171 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
172 unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
173 MF.getRegInfo().addLiveIn(*CurArgReg++, VRegHi);
174 HiVal = DAG.getCopyFromReg(Root, dl, VRegHi, MVT::i32);
176 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
177 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
178 HiVal = DAG.getLoad(MVT::i32, dl, Root, FIPtr, NULL, 0);
182 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
183 unsigned VRegLo = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
184 MF.getRegInfo().addLiveIn(*CurArgReg++, VRegLo);
185 LoVal = DAG.getCopyFromReg(Root, dl, VRegLo, MVT::i32);
187 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4);
188 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
189 LoVal = DAG.getLoad(MVT::i32, dl, Root, FIPtr, NULL, 0);
192 // Compose the two halves together into an i64 unit.
194 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal);
196 // If we want a double, do a bit convert.
197 if (ObjectVT == MVT::f64)
198 WholeValue = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, WholeValue);
200 ArgValues.push_back(WholeValue);
207 // Store remaining ArgRegs to the stack if this is a varargs function.
209 // Remember the vararg offset for the va_start implementation.
210 VarArgsFrameOffset = ArgOffset;
212 for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
213 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
214 MF.getRegInfo().addLiveIn(*CurArgReg, VReg);
215 SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), dl, VReg, MVT::i32);
217 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
218 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
220 OutChains.push_back(DAG.getStore(DAG.getRoot(), dl, Arg, FIPtr, NULL, 0));
225 if (!OutChains.empty())
226 DAG.setRoot(DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
227 &OutChains[0], OutChains.size()));
230 static SDValue LowerCALL(SDValue Op, SelectionDAG &DAG) {
231 CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
232 unsigned CallingConv = TheCall->getCallingConv();
233 SDValue Chain = TheCall->getChain();
234 SDValue Callee = TheCall->getCallee();
235 bool isVarArg = TheCall->isVarArg();
236 DebugLoc dl = TheCall->getDebugLoc();
239 // Analyze operands of the call, assigning locations to each operand.
240 SmallVector<CCValAssign, 16> ArgLocs;
241 CCState CCInfo(CallingConv, isVarArg, DAG.getTarget(), ArgLocs);
242 CCInfo.AnalyzeCallOperands(Op.getNode(), CC_Sparc32);
244 // Get the size of the outgoing arguments stack space requirement.
245 unsigned ArgsSize = CCInfo.getNextStackOffset();
246 // FIXME: We can't use this until f64 is known to take two GPRs.
250 // Count the size of the outgoing arguments.
251 unsigned ArgsSize = 0;
252 for (unsigned i = 0, e = TheCall->getNumArgs(); i != e; ++i) {
253 switch (TheCall->getArg(i).getValueType().getSimpleVT()) {
254 default: assert(0 && "Unknown value type!");
269 ArgsSize -= 4*6; // Space for first 6 arguments is prereserved.
274 // Keep stack frames 8-byte aligned.
275 ArgsSize = (ArgsSize+7) & ~7;
277 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, true));
279 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
280 SmallVector<SDValue, 8> MemOpChains;
283 // Walk the register/memloc assignments, inserting copies/loads.
284 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
285 CCValAssign &VA = ArgLocs[i];
287 // Arguments start after the 5 first operands of ISD::CALL
288 SDValue Arg = TheCall->getArg(i);
290 // Promote the value if needed.
291 switch (VA.getLocInfo()) {
292 default: assert(0 && "Unknown loc info!");
293 case CCValAssign::Full: break;
294 case CCValAssign::SExt:
295 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
297 case CCValAssign::ZExt:
298 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
300 case CCValAssign::AExt:
301 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
305 // Arguments that can be passed on register must be kept at
308 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
312 assert(VA.isMemLoc());
314 // Create a store off the stack pointer for this argument.
315 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
316 // FIXME: VERIFY THAT 68 IS RIGHT.
317 SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset()+68);
318 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
319 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
323 static const unsigned ArgRegs[] = {
324 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
326 unsigned ArgOffset = 68;
328 for (unsigned i = 0, e = TheCall->getNumArgs(); i != e; ++i) {
329 SDValue Val = TheCall->getArg(i);
330 MVT ObjectVT = Val.getValueType();
331 SDValue ValToStore(0, 0);
333 switch (ObjectVT.getSimpleVT()) {
334 default: assert(0 && "Unhandled argument type!");
338 if (RegsToPass.size() >= 6) {
341 RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Val));
346 if (RegsToPass.size() >= 6) {
349 // Convert this to a FP value in an int reg.
350 Val = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Val);
351 RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Val));
356 if (RegsToPass.size() >= 6) {
357 ValToStore = Val; // Whole thing is passed in memory.
361 // Break into top and bottom parts by storing to the stack and loading
362 // out the parts as integers. Top part goes in a reg.
363 SDValue StackPtr = DAG.CreateStackTemporary(MVT::f64, MVT::i32);
364 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
365 Val, StackPtr, NULL, 0);
366 // Sparc is big-endian, so the high part comes first.
367 SDValue Hi = DAG.getLoad(MVT::i32, dl, Store, StackPtr, NULL, 0, 0);
368 // Increment the pointer to the other half.
369 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
370 DAG.getIntPtrConstant(4));
371 // Load the low part.
372 SDValue Lo = DAG.getLoad(MVT::i32, dl, Store, StackPtr, NULL, 0, 0);
374 RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Hi));
376 if (RegsToPass.size() >= 6) {
381 RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Lo));
387 if (RegsToPass.size() >= 6) {
388 ValToStore = Val; // Whole thing is passed in memory.
392 // Split the value into top and bottom part. Top part goes in a reg.
393 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Val,
394 DAG.getConstant(1, MVT::i32));
395 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Val,
396 DAG.getConstant(0, MVT::i32));
397 RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Hi));
399 if (RegsToPass.size() >= 6) {
404 RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Lo));
410 if (ValToStore.getNode()) {
411 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
412 SDValue PtrOff = DAG.getConstant(ArgOffset, MVT::i32);
413 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
414 MemOpChains.push_back(DAG.getStore(Chain, dl, ValToStore,
417 ArgOffset += ObjSize;
421 // Emit all stores, make sure the occur before any copies into physregs.
422 if (!MemOpChains.empty())
423 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
424 &MemOpChains[0], MemOpChains.size());
426 // Build a sequence of copy-to-reg nodes chained together with token
427 // chain and flag operands which copy the outgoing args into registers.
428 // The InFlag in necessary since all emited instructions must be
431 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
432 unsigned Reg = RegsToPass[i].first;
433 // Remap I0->I7 -> O0->O7.
434 if (Reg >= SP::I0 && Reg <= SP::I7)
435 Reg = Reg-SP::I0+SP::O0;
437 Chain = DAG.getCopyToReg(Chain, dl, Reg, RegsToPass[i].second, InFlag);
438 InFlag = Chain.getValue(1);
441 // If the callee is a GlobalAddress node (quite common, every direct call is)
442 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
443 // Likewise ExternalSymbol -> TargetExternalSymbol.
444 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
445 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32);
446 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
447 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
449 std::vector<MVT> NodeTys;
450 NodeTys.push_back(MVT::Other); // Returns a chain
451 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
452 SDValue Ops[] = { Chain, Callee, InFlag };
453 Chain = DAG.getNode(SPISD::CALL, dl, NodeTys, Ops, InFlag.getNode() ? 3 : 2);
454 InFlag = Chain.getValue(1);
456 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true),
457 DAG.getIntPtrConstant(0, true), InFlag);
458 InFlag = Chain.getValue(1);
460 // Assign locations to each value returned by this call.
461 SmallVector<CCValAssign, 16> RVLocs;
462 CCState RVInfo(CallingConv, isVarArg, DAG.getTarget(), RVLocs);
464 RVInfo.AnalyzeCallResult(TheCall, RetCC_Sparc32);
465 SmallVector<SDValue, 8> ResultVals;
467 // Copy all of the result registers out of their specified physreg.
468 for (unsigned i = 0; i != RVLocs.size(); ++i) {
469 unsigned Reg = RVLocs[i].getLocReg();
471 // Remap I0->I7 -> O0->O7.
472 if (Reg >= SP::I0 && Reg <= SP::I7)
473 Reg = Reg-SP::I0+SP::O0;
475 Chain = DAG.getCopyFromReg(Chain, dl, Reg,
476 RVLocs[i].getValVT(), InFlag).getValue(1);
477 InFlag = Chain.getValue(2);
478 ResultVals.push_back(Chain.getValue(0));
481 ResultVals.push_back(Chain);
483 // Merge everything together with a MERGE_VALUES node.
484 return DAG.getNode(ISD::MERGE_VALUES, dl,
485 TheCall->getVTList(), &ResultVals[0],
491 //===----------------------------------------------------------------------===//
492 // TargetLowering Implementation
493 //===----------------------------------------------------------------------===//
495 /// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC
497 static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) {
499 default: assert(0 && "Unknown integer condition code!");
500 case ISD::SETEQ: return SPCC::ICC_E;
501 case ISD::SETNE: return SPCC::ICC_NE;
502 case ISD::SETLT: return SPCC::ICC_L;
503 case ISD::SETGT: return SPCC::ICC_G;
504 case ISD::SETLE: return SPCC::ICC_LE;
505 case ISD::SETGE: return SPCC::ICC_GE;
506 case ISD::SETULT: return SPCC::ICC_CS;
507 case ISD::SETULE: return SPCC::ICC_LEU;
508 case ISD::SETUGT: return SPCC::ICC_GU;
509 case ISD::SETUGE: return SPCC::ICC_CC;
513 /// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC
515 static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
517 default: assert(0 && "Unknown fp condition code!");
519 case ISD::SETOEQ: return SPCC::FCC_E;
521 case ISD::SETUNE: return SPCC::FCC_NE;
523 case ISD::SETOLT: return SPCC::FCC_L;
525 case ISD::SETOGT: return SPCC::FCC_G;
527 case ISD::SETOLE: return SPCC::FCC_LE;
529 case ISD::SETOGE: return SPCC::FCC_GE;
530 case ISD::SETULT: return SPCC::FCC_UL;
531 case ISD::SETULE: return SPCC::FCC_ULE;
532 case ISD::SETUGT: return SPCC::FCC_UG;
533 case ISD::SETUGE: return SPCC::FCC_UGE;
534 case ISD::SETUO: return SPCC::FCC_U;
535 case ISD::SETO: return SPCC::FCC_O;
536 case ISD::SETONE: return SPCC::FCC_LG;
537 case ISD::SETUEQ: return SPCC::FCC_UE;
542 SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
543 : TargetLowering(TM) {
545 // Set up the register classes.
546 addRegisterClass(MVT::i32, SP::IntRegsRegisterClass);
547 addRegisterClass(MVT::f32, SP::FPRegsRegisterClass);
548 addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass);
550 // Turn FP extload into load/fextend
551 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
552 // Sparc doesn't have i1 sign extending load
553 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
554 // Turn FP truncstore into trunc + store.
555 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
557 // Custom legalize GlobalAddress nodes into LO/HI parts.
558 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
559 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
560 setOperationAction(ISD::ConstantPool , MVT::i32, Custom);
562 // Sparc doesn't have sext_inreg, replace them with shl/sra
563 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
564 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
565 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
567 // Sparc has no REM or DIVREM operations.
568 setOperationAction(ISD::UREM, MVT::i32, Expand);
569 setOperationAction(ISD::SREM, MVT::i32, Expand);
570 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
571 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
573 // Custom expand fp<->sint
574 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
575 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
578 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
579 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
581 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
582 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
584 // Sparc has no select or setcc: expand to SELECT_CC.
585 setOperationAction(ISD::SELECT, MVT::i32, Expand);
586 setOperationAction(ISD::SELECT, MVT::f32, Expand);
587 setOperationAction(ISD::SELECT, MVT::f64, Expand);
588 setOperationAction(ISD::SETCC, MVT::i32, Expand);
589 setOperationAction(ISD::SETCC, MVT::f32, Expand);
590 setOperationAction(ISD::SETCC, MVT::f64, Expand);
592 // Sparc doesn't have BRCOND either, it has BR_CC.
593 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
594 setOperationAction(ISD::BRIND, MVT::Other, Expand);
595 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
596 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
597 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
598 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
600 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
601 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
602 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
604 // SPARC has no intrinsics for these particular operations.
605 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
607 setOperationAction(ISD::FSIN , MVT::f64, Expand);
608 setOperationAction(ISD::FCOS , MVT::f64, Expand);
609 setOperationAction(ISD::FREM , MVT::f64, Expand);
610 setOperationAction(ISD::FSIN , MVT::f32, Expand);
611 setOperationAction(ISD::FCOS , MVT::f32, Expand);
612 setOperationAction(ISD::FREM , MVT::f32, Expand);
613 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
614 setOperationAction(ISD::CTTZ , MVT::i32, Expand);
615 setOperationAction(ISD::CTLZ , MVT::i32, Expand);
616 setOperationAction(ISD::ROTL , MVT::i32, Expand);
617 setOperationAction(ISD::ROTR , MVT::i32, Expand);
618 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
619 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
620 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
621 setOperationAction(ISD::FPOW , MVT::f64, Expand);
622 setOperationAction(ISD::FPOW , MVT::f32, Expand);
624 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
625 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
626 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
628 // FIXME: Sparc provides these multiplies, but we don't have them yet.
629 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
630 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
632 // We don't have line number support yet.
633 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
634 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
635 setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
636 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
638 // RET must be custom lowered, to meet ABI requirements
639 setOperationAction(ISD::RET , MVT::Other, Custom);
641 // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
642 setOperationAction(ISD::VASTART , MVT::Other, Custom);
643 // VAARG needs to be lowered to not do unaligned accesses for doubles.
644 setOperationAction(ISD::VAARG , MVT::Other, Custom);
646 // Use the default implementation.
647 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
648 setOperationAction(ISD::VAEND , MVT::Other, Expand);
649 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
650 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand);
651 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
653 // No debug info support yet.
654 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
655 setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
656 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
657 setOperationAction(ISD::DECLARE, MVT::Other, Expand);
659 setStackPointerRegisterToSaveRestore(SP::O6);
661 if (TM.getSubtarget<SparcSubtarget>().isV9())
662 setOperationAction(ISD::CTPOP, MVT::i32, Legal);
664 computeRegisterProperties();
667 const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const {
670 case SPISD::CMPICC: return "SPISD::CMPICC";
671 case SPISD::CMPFCC: return "SPISD::CMPFCC";
672 case SPISD::BRICC: return "SPISD::BRICC";
673 case SPISD::BRFCC: return "SPISD::BRFCC";
674 case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC";
675 case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC";
676 case SPISD::Hi: return "SPISD::Hi";
677 case SPISD::Lo: return "SPISD::Lo";
678 case SPISD::FTOI: return "SPISD::FTOI";
679 case SPISD::ITOF: return "SPISD::ITOF";
680 case SPISD::CALL: return "SPISD::CALL";
681 case SPISD::RET_FLAG: return "SPISD::RET_FLAG";
685 /// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
686 /// be zero. Op is expected to be a target specific node. Used by DAG
688 void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
692 const SelectionDAG &DAG,
693 unsigned Depth) const {
694 APInt KnownZero2, KnownOne2;
695 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
697 switch (Op.getOpcode()) {
699 case SPISD::SELECT_ICC:
700 case SPISD::SELECT_FCC:
701 DAG.ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne,
703 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2,
705 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
706 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
708 // Only known if known in both the LHS and RHS.
709 KnownOne &= KnownOne2;
710 KnownZero &= KnownZero2;
715 // Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so
716 // set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition.
717 static void LookThroughSetCC(SDValue &LHS, SDValue &RHS,
718 ISD::CondCode CC, unsigned &SPCC) {
719 if (isa<ConstantSDNode>(RHS) &&
720 cast<ConstantSDNode>(RHS)->getZExtValue() == 0 &&
722 ((LHS.getOpcode() == SPISD::SELECT_ICC &&
723 LHS.getOperand(3).getOpcode() == SPISD::CMPICC) ||
724 (LHS.getOpcode() == SPISD::SELECT_FCC &&
725 LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) &&
726 isa<ConstantSDNode>(LHS.getOperand(0)) &&
727 isa<ConstantSDNode>(LHS.getOperand(1)) &&
728 cast<ConstantSDNode>(LHS.getOperand(0))->getZExtValue() == 1 &&
729 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() == 0) {
730 SDValue CMPCC = LHS.getOperand(3);
731 SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getZExtValue();
732 LHS = CMPCC.getOperand(0);
733 RHS = CMPCC.getOperand(1);
737 static SDValue LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) {
738 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
739 // FIXME there isn't really any debug info here
740 DebugLoc dl = Op.getDebugLoc();
741 SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
742 SDValue Hi = DAG.getNode(SPISD::Hi, dl, MVT::i32, GA);
743 SDValue Lo = DAG.getNode(SPISD::Lo, dl, MVT::i32, GA);
744 return DAG.getNode(ISD::ADD, dl, MVT::i32, Lo, Hi);
747 static SDValue LowerCONSTANTPOOL(SDValue Op, SelectionDAG &DAG) {
748 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
749 // FIXME there isn't really any debug info here
750 DebugLoc dl = Op.getDebugLoc();
751 Constant *C = N->getConstVal();
752 SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment());
753 SDValue Hi = DAG.getNode(SPISD::Hi, dl, MVT::i32, CP);
754 SDValue Lo = DAG.getNode(SPISD::Lo, dl, MVT::i32, CP);
755 return DAG.getNode(ISD::ADD, dl, MVT::i32, Lo, Hi);
758 static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
759 // Convert the fp value to integer in an FP register.
760 assert(Op.getValueType() == MVT::i32);
761 Op = DAG.getNode(SPISD::FTOI, MVT::f32, Op.getOperand(0));
762 return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
765 static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
766 assert(Op.getOperand(0).getValueType() == MVT::i32);
767 SDValue Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0));
768 // Convert the int value to FP in an FP register.
769 return DAG.getNode(SPISD::ITOF, Op.getValueType(), Tmp);
772 static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) {
773 SDValue Chain = Op.getOperand(0);
774 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
775 SDValue LHS = Op.getOperand(2);
776 SDValue RHS = Op.getOperand(3);
777 SDValue Dest = Op.getOperand(4);
778 DebugLoc dl = Op.getDebugLoc();
779 unsigned Opc, SPCC = ~0U;
781 // If this is a br_cc of a "setcc", and if the setcc got lowered into
782 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
783 LookThroughSetCC(LHS, RHS, CC, SPCC);
785 // Get the condition flag.
787 if (LHS.getValueType() == MVT::i32) {
788 std::vector<MVT> VTs;
789 VTs.push_back(MVT::i32);
790 VTs.push_back(MVT::Flag);
791 SDValue Ops[2] = { LHS, RHS };
792 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, VTs, Ops, 2).getValue(1);
793 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
796 CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Flag, LHS, RHS);
797 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
800 return DAG.getNode(Opc, dl, MVT::Other, Chain, Dest,
801 DAG.getConstant(SPCC, MVT::i32), CompareFlag);
804 static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
805 SDValue LHS = Op.getOperand(0);
806 SDValue RHS = Op.getOperand(1);
807 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
808 SDValue TrueVal = Op.getOperand(2);
809 SDValue FalseVal = Op.getOperand(3);
810 DebugLoc dl = Op.getDebugLoc();
811 unsigned Opc, SPCC = ~0U;
813 // If this is a select_cc of a "setcc", and if the setcc got lowered into
814 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
815 LookThroughSetCC(LHS, RHS, CC, SPCC);
818 if (LHS.getValueType() == MVT::i32) {
819 std::vector<MVT> VTs;
820 VTs.push_back(LHS.getValueType()); // subcc returns a value
821 VTs.push_back(MVT::Flag);
822 SDValue Ops[2] = { LHS, RHS };
823 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, VTs, Ops, 2).getValue(1);
824 Opc = SPISD::SELECT_ICC;
825 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
827 CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Flag, LHS, RHS);
828 Opc = SPISD::SELECT_FCC;
829 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
831 return DAG.getNode(Opc, dl, TrueVal.getValueType(), TrueVal, FalseVal,
832 DAG.getConstant(SPCC, MVT::i32), CompareFlag);
835 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
836 SparcTargetLowering &TLI) {
837 // vastart just stores the address of the VarArgsFrameIndex slot into the
838 // memory location argument.
839 DebugLoc dl = Op.getNode()->getDebugLoc();
840 SDValue Offset = DAG.getNode(ISD::ADD, dl, MVT::i32,
841 DAG.getRegister(SP::I6, MVT::i32),
842 DAG.getConstant(TLI.getVarArgsFrameOffset(),
844 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
845 return DAG.getStore(Op.getOperand(0), dl, Offset, Op.getOperand(1), SV, 0);
848 static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) {
849 SDNode *Node = Op.getNode();
850 MVT VT = Node->getValueType(0);
851 SDValue InChain = Node->getOperand(0);
852 SDValue VAListPtr = Node->getOperand(1);
853 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
854 DebugLoc dl = Node->getDebugLoc();
855 SDValue VAList = DAG.getLoad(MVT::i32, dl, InChain, VAListPtr, SV, 0);
856 // Increment the pointer, VAList, to the next vaarg
857 SDValue NextPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, VAList,
858 DAG.getConstant(VT.getSizeInBits()/8,
860 // Store the incremented VAList to the legalized pointer
861 InChain = DAG.getStore(VAList.getValue(1), dl, NextPtr,
863 // Load the actual argument out of the pointer VAList, unless this is an
866 return DAG.getLoad(VT, dl, InChain, VAList, NULL, 0);
868 // Otherwise, load it as i64, then do a bitconvert.
869 SDValue V = DAG.getLoad(MVT::i64, dl, InChain, VAList, NULL, 0);
871 // Bit-Convert the value to f64.
873 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, V),
876 return DAG.getMergeValues(Ops, 2, dl);
879 static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) {
880 SDValue Chain = Op.getOperand(0); // Legalize the chain.
881 SDValue Size = Op.getOperand(1); // Legalize the size.
882 DebugLoc dl = Op.getDebugLoc();
884 unsigned SPReg = SP::O6;
885 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, MVT::i32);
886 SDValue NewSP = DAG.getNode(ISD::SUB, dl, MVT::i32, SP, Size); // Value
887 Chain = DAG.getCopyToReg(SP.getValue(1), dl, SPReg, NewSP); // Output chain
889 // The resultant pointer is actually 16 words from the bottom of the stack,
890 // to provide a register spill area.
891 SDValue NewVal = DAG.getNode(ISD::ADD, dl, MVT::i32, NewSP,
892 DAG.getConstant(96, MVT::i32));
893 SDValue Ops[2] = { NewVal, Chain };
894 return DAG.getMergeValues(Ops, 2, dl);
898 SDValue SparcTargetLowering::
899 LowerOperation(SDValue Op, SelectionDAG &DAG) {
900 switch (Op.getOpcode()) {
901 default: assert(0 && "Should not custom lower this!");
902 // Frame & Return address. Currently unimplemented
903 case ISD::RETURNADDR: return SDValue();
904 case ISD::FRAMEADDR: return SDValue();
905 case ISD::GlobalTLSAddress:
906 assert(0 && "TLS not implemented for Sparc.");
907 case ISD::GlobalAddress: return LowerGLOBALADDRESS(Op, DAG);
908 case ISD::ConstantPool: return LowerCONSTANTPOOL(Op, DAG);
909 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
910 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
911 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
912 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
913 case ISD::VASTART: return LowerVASTART(Op, DAG, *this);
914 case ISD::VAARG: return LowerVAARG(Op, DAG);
915 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
916 case ISD::CALL: return LowerCALL(Op, DAG);
917 case ISD::RET: return LowerRET(Op, DAG);
922 SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
923 MachineBasicBlock *BB) {
924 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
927 // Figure out the conditional branch opcode to use for this select_cc.
928 switch (MI->getOpcode()) {
929 default: assert(0 && "Unknown SELECT_CC!");
930 case SP::SELECT_CC_Int_ICC:
931 case SP::SELECT_CC_FP_ICC:
932 case SP::SELECT_CC_DFP_ICC:
933 BROpcode = SP::BCOND;
935 case SP::SELECT_CC_Int_FCC:
936 case SP::SELECT_CC_FP_FCC:
937 case SP::SELECT_CC_DFP_FCC:
938 BROpcode = SP::FBCOND;
942 CC = (SPCC::CondCodes)MI->getOperand(3).getImm();
944 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
945 // control-flow pattern. The incoming instruction knows the destination vreg
946 // to set, the condition code register to branch on, the true/false values to
947 // select between, and a branch opcode to use.
948 const BasicBlock *LLVM_BB = BB->getBasicBlock();
949 MachineFunction::iterator It = BB;
956 // fallthrough --> copy0MBB
957 MachineBasicBlock *thisMBB = BB;
958 MachineFunction *F = BB->getParent();
959 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
960 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
961 BuildMI(BB, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC);
962 F->insert(It, copy0MBB);
963 F->insert(It, sinkMBB);
964 // Update machine-CFG edges by transferring all successors of the current
965 // block to the new block which will contain the Phi node for the select.
966 sinkMBB->transferSuccessors(BB);
967 // Next, add the true and fallthrough blocks as its successors.
968 BB->addSuccessor(copy0MBB);
969 BB->addSuccessor(sinkMBB);
973 // # fallthrough to sinkMBB
976 // Update machine-CFG edges
977 BB->addSuccessor(sinkMBB);
980 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
983 BuildMI(BB, TII.get(SP::PHI), MI->getOperand(0).getReg())
984 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
985 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
987 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
991 //===----------------------------------------------------------------------===//
992 // Sparc Inline Assembly Support
993 //===----------------------------------------------------------------------===//
995 /// getConstraintType - Given a constraint letter, return the type of
996 /// constraint it is for this target.
997 SparcTargetLowering::ConstraintType
998 SparcTargetLowering::getConstraintType(const std::string &Constraint) const {
999 if (Constraint.size() == 1) {
1000 switch (Constraint[0]) {
1002 case 'r': return C_RegisterClass;
1006 return TargetLowering::getConstraintType(Constraint);
1009 std::pair<unsigned, const TargetRegisterClass*>
1010 SparcTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
1012 if (Constraint.size() == 1) {
1013 switch (Constraint[0]) {
1015 return std::make_pair(0U, SP::IntRegsRegisterClass);
1019 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
1022 std::vector<unsigned> SparcTargetLowering::
1023 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1025 if (Constraint.size() != 1)
1026 return std::vector<unsigned>();
1028 switch (Constraint[0]) {
1031 return make_vector<unsigned>(SP::L0, SP::L1, SP::L2, SP::L3,
1032 SP::L4, SP::L5, SP::L6, SP::L7,
1033 SP::I0, SP::I1, SP::I2, SP::I3,
1035 SP::O0, SP::O1, SP::O2, SP::O3,
1036 SP::O4, SP::O5, SP::O7, 0);
1039 return std::vector<unsigned>();
1043 SparcTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
1044 // The Sparc target isn't yet aware of offsets.