1 //===-- SparcISelDAGToDAG.cpp - A dag to dag inst selector for Sparc ------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the SPARC target.
12 //===----------------------------------------------------------------------===//
15 #include "SparcTargetMachine.h"
16 #include "llvm/DerivedTypes.h"
17 #include "llvm/Function.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/CodeGen/SelectionDAGISel.h"
23 #include "llvm/CodeGen/SSARegMap.h"
24 #include "llvm/Target/TargetLowering.h"
25 #include "llvm/Support/Debug.h"
30 //===----------------------------------------------------------------------===//
31 // TargetLowering Implementation
32 //===----------------------------------------------------------------------===//
36 FIRST_NUMBER = ISD::BUILTIN_OP_END+SP::INSTRUCTION_LIST_END,
37 CMPICC, // Compare two GPR operands, set icc.
38 CMPFCC, // Compare two FP operands, set fcc.
39 BRICC, // Branch to dest on icc condition
40 BRFCC, // Branch to dest on fcc condition
41 SELECT_ICC, // Select between two values using the current ICC flags.
42 SELECT_FCC, // Select between two values using the current FCC flags.
44 Hi, Lo, // Hi/Lo operations, typically on a global address.
46 FTOI, // FP to Int within a FP register.
47 ITOF, // Int to FP within a FP register.
49 CALL, // A call instruction.
50 RET_FLAG, // Return with a flag operand.
54 /// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC
56 static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) {
58 default: assert(0 && "Unknown integer condition code!");
59 case ISD::SETEQ: return SPCC::ICC_E;
60 case ISD::SETNE: return SPCC::ICC_NE;
61 case ISD::SETLT: return SPCC::ICC_L;
62 case ISD::SETGT: return SPCC::ICC_G;
63 case ISD::SETLE: return SPCC::ICC_LE;
64 case ISD::SETGE: return SPCC::ICC_GE;
65 case ISD::SETULT: return SPCC::ICC_CS;
66 case ISD::SETULE: return SPCC::ICC_LEU;
67 case ISD::SETUGT: return SPCC::ICC_GU;
68 case ISD::SETUGE: return SPCC::ICC_CC;
72 /// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC
74 static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
76 default: assert(0 && "Unknown fp condition code!");
77 case ISD::SETEQ: return SPCC::FCC_E;
78 case ISD::SETNE: return SPCC::FCC_NE;
79 case ISD::SETLT: return SPCC::FCC_L;
80 case ISD::SETGT: return SPCC::FCC_G;
81 case ISD::SETLE: return SPCC::FCC_LE;
82 case ISD::SETGE: return SPCC::FCC_GE;
83 case ISD::SETULT: return SPCC::FCC_UL;
84 case ISD::SETULE: return SPCC::FCC_ULE;
85 case ISD::SETUGT: return SPCC::FCC_UG;
86 case ISD::SETUGE: return SPCC::FCC_UGE;
87 case ISD::SETUO: return SPCC::FCC_U;
88 case ISD::SETO: return SPCC::FCC_O;
89 case ISD::SETONE: return SPCC::FCC_LG;
90 case ISD::SETUEQ: return SPCC::FCC_UE;
95 class SparcTargetLowering : public TargetLowering {
96 int VarArgsFrameOffset; // Frame offset to start of varargs area.
98 SparcTargetLowering(TargetMachine &TM);
99 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
101 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
102 /// in Mask are known to be either zero or one and return them in the
103 /// KnownZero/KnownOne bitsets.
104 virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
108 unsigned Depth = 0) const;
110 virtual std::vector<SDOperand>
111 LowerArguments(Function &F, SelectionDAG &DAG);
112 virtual std::pair<SDOperand, SDOperand>
113 LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
115 bool isTailCall, SDOperand Callee, ArgListTy &Args,
117 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
118 MachineBasicBlock *MBB);
120 virtual const char *getTargetNodeName(unsigned Opcode) const;
124 SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
125 : TargetLowering(TM) {
127 // Set up the register classes.
128 addRegisterClass(MVT::i32, SP::IntRegsRegisterClass);
129 addRegisterClass(MVT::f32, SP::FPRegsRegisterClass);
130 addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass);
132 // Custom legalize GlobalAddress nodes into LO/HI parts.
133 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
134 setOperationAction(ISD::ConstantPool , MVT::i32, Custom);
136 // Sparc doesn't have sext_inreg, replace them with shl/sra
137 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
138 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
139 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
141 // Sparc has no REM operation.
142 setOperationAction(ISD::UREM, MVT::i32, Expand);
143 setOperationAction(ISD::SREM, MVT::i32, Expand);
145 // Custom expand fp<->sint
146 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
147 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
150 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
151 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
153 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
154 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
156 // Turn FP extload into load/fextend
157 setOperationAction(ISD::EXTLOAD, MVT::f32, Expand);
159 // Sparc has no select or setcc: expand to SELECT_CC.
160 setOperationAction(ISD::SELECT, MVT::i32, Expand);
161 setOperationAction(ISD::SELECT, MVT::f32, Expand);
162 setOperationAction(ISD::SELECT, MVT::f64, Expand);
163 setOperationAction(ISD::SETCC, MVT::i32, Expand);
164 setOperationAction(ISD::SETCC, MVT::f32, Expand);
165 setOperationAction(ISD::SETCC, MVT::f64, Expand);
167 // Sparc doesn't have BRCOND either, it has BR_CC.
168 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
169 setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand);
170 setOperationAction(ISD::BRTWOWAY_CC, MVT::Other, Expand);
171 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
172 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
173 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
175 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
176 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
177 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
179 // SPARC has no intrinsics for these particular operations.
180 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
181 setOperationAction(ISD::MEMSET, MVT::Other, Expand);
182 setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
184 setOperationAction(ISD::FSIN , MVT::f64, Expand);
185 setOperationAction(ISD::FCOS , MVT::f64, Expand);
186 setOperationAction(ISD::FSIN , MVT::f32, Expand);
187 setOperationAction(ISD::FCOS , MVT::f32, Expand);
188 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
189 setOperationAction(ISD::CTTZ , MVT::i32, Expand);
190 setOperationAction(ISD::CTLZ , MVT::i32, Expand);
191 setOperationAction(ISD::ROTL , MVT::i32, Expand);
192 setOperationAction(ISD::ROTR , MVT::i32, Expand);
193 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
194 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
195 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
197 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
198 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
199 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
201 // We don't have line number support yet.
202 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
203 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
204 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
206 // RET must be custom lowered, to meet ABI requirements
207 setOperationAction(ISD::RET , MVT::Other, Custom);
209 // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
210 setOperationAction(ISD::VASTART , MVT::Other, Custom);
211 // VAARG needs to be lowered to not do unaligned accesses for doubles.
212 setOperationAction(ISD::VAARG , MVT::Other, Custom);
214 // Use the default implementation.
215 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
216 setOperationAction(ISD::VAEND , MVT::Other, Expand);
217 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
218 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand);
219 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
221 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
222 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
224 setStackPointerRegisterToSaveRestore(SP::O6);
226 if (TM.getSubtarget<SparcSubtarget>().isV9()) {
227 setOperationAction(ISD::CTPOP, MVT::i32, Legal);
230 computeRegisterProperties();
233 const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const {
236 case SPISD::CMPICC: return "SPISD::CMPICC";
237 case SPISD::CMPFCC: return "SPISD::CMPFCC";
238 case SPISD::BRICC: return "SPISD::BRICC";
239 case SPISD::BRFCC: return "SPISD::BRFCC";
240 case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC";
241 case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC";
242 case SPISD::Hi: return "SPISD::Hi";
243 case SPISD::Lo: return "SPISD::Lo";
244 case SPISD::FTOI: return "SPISD::FTOI";
245 case SPISD::ITOF: return "SPISD::ITOF";
246 case SPISD::CALL: return "SPISD::CALL";
247 case SPISD::RET_FLAG: return "SPISD::RET_FLAG";
251 /// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
252 /// be zero. Op is expected to be a target specific node. Used by DAG
254 void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
258 unsigned Depth) const {
259 uint64_t KnownZero2, KnownOne2;
260 KnownZero = KnownOne = 0; // Don't know anything.
262 switch (Op.getOpcode()) {
264 case SPISD::SELECT_ICC:
265 case SPISD::SELECT_FCC:
266 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1);
267 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1);
268 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
269 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
271 // Only known if known in both the LHS and RHS.
272 KnownOne &= KnownOne2;
273 KnownZero &= KnownZero2;
278 /// LowerArguments - V8 uses a very simple ABI, where all values are passed in
279 /// either one or two GPRs, including FP values. TODO: we should pass FP values
280 /// in FP registers for fastcc functions.
281 std::vector<SDOperand>
282 SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
283 MachineFunction &MF = DAG.getMachineFunction();
284 SSARegMap *RegMap = MF.getSSARegMap();
285 std::vector<SDOperand> ArgValues;
287 static const unsigned ArgRegs[] = {
288 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
291 const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6;
292 unsigned ArgOffset = 68;
294 SDOperand Root = DAG.getRoot();
295 std::vector<SDOperand> OutChains;
297 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
298 MVT::ValueType ObjectVT = getValueType(I->getType());
301 default: assert(0 && "Unhandled argument type!");
306 if (I->use_empty()) { // Argument is dead.
307 if (CurArgReg < ArgRegEnd) ++CurArgReg;
308 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
309 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
310 unsigned VReg = RegMap->createVirtualRegister(&SP::IntRegsRegClass);
311 MF.addLiveIn(*CurArgReg++, VReg);
312 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
313 if (ObjectVT != MVT::i32) {
314 unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext
316 Arg = DAG.getNode(AssertOp, MVT::i32, Arg,
317 DAG.getValueType(ObjectVT));
318 Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg);
320 ArgValues.push_back(Arg);
322 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
323 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
325 if (ObjectVT == MVT::i32) {
326 Load = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
329 I->getType()->isSigned() ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
331 // Sparc is big endian, so add an offset based on the ObjectVT.
332 unsigned Offset = 4-std::max(1U, MVT::getSizeInBits(ObjectVT)/8);
333 FIPtr = DAG.getNode(ISD::ADD, MVT::i32, FIPtr,
334 DAG.getConstant(Offset, MVT::i32));
335 Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr,
336 DAG.getSrcValue(0), ObjectVT);
337 Load = DAG.getNode(ISD::TRUNCATE, ObjectVT, Load);
339 ArgValues.push_back(Load);
345 if (I->use_empty()) { // Argument is dead.
346 if (CurArgReg < ArgRegEnd) ++CurArgReg;
347 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
348 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
349 // FP value is passed in an integer register.
350 unsigned VReg = RegMap->createVirtualRegister(&SP::IntRegsRegClass);
351 MF.addLiveIn(*CurArgReg++, VReg);
352 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
354 Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Arg);
355 ArgValues.push_back(Arg);
357 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
358 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
359 SDOperand Load = DAG.getLoad(MVT::f32, Root, FIPtr, DAG.getSrcValue(0));
360 ArgValues.push_back(Load);
367 if (I->use_empty()) { // Argument is dead.
368 if (CurArgReg < ArgRegEnd) ++CurArgReg;
369 if (CurArgReg < ArgRegEnd) ++CurArgReg;
370 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
371 } else if (/* FIXME: Apparently this isn't safe?? */
372 0 && CurArgReg == ArgRegEnd && ObjectVT == MVT::f64 &&
373 ((CurArgReg-ArgRegs) & 1) == 0) {
374 // If this is a double argument and the whole thing lives on the stack,
375 // and the argument is aligned, load the double straight from the stack.
376 // We can't do a load in cases like void foo([6ints], int,double),
377 // because the double wouldn't be aligned!
378 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset);
379 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
380 ArgValues.push_back(DAG.getLoad(MVT::f64, Root, FIPtr,
381 DAG.getSrcValue(0)));
384 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
385 unsigned VRegHi = RegMap->createVirtualRegister(&SP::IntRegsRegClass);
386 MF.addLiveIn(*CurArgReg++, VRegHi);
387 HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32);
389 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
390 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
391 HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
395 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
396 unsigned VRegLo = RegMap->createVirtualRegister(&SP::IntRegsRegClass);
397 MF.addLiveIn(*CurArgReg++, VRegLo);
398 LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32);
400 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4);
401 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
402 LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
405 // Compose the two halves together into an i64 unit.
406 SDOperand WholeValue =
407 DAG.getNode(ISD::BUILD_PAIR, MVT::i64, LoVal, HiVal);
409 // If we want a double, do a bit convert.
410 if (ObjectVT == MVT::f64)
411 WholeValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, WholeValue);
413 ArgValues.push_back(WholeValue);
420 // Store remaining ArgRegs to the stack if this is a varargs function.
421 if (F.getFunctionType()->isVarArg()) {
422 // Remember the vararg offset for the va_start implementation.
423 VarArgsFrameOffset = ArgOffset;
425 for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
426 unsigned VReg = RegMap->createVirtualRegister(&SP::IntRegsRegClass);
427 MF.addLiveIn(*CurArgReg, VReg);
428 SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
430 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
431 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
433 OutChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(),
434 Arg, FIPtr, DAG.getSrcValue(0)));
439 if (!OutChains.empty())
440 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains));
442 // Finally, inform the code generator which regs we return values in.
443 switch (getValueType(F.getReturnType())) {
444 default: assert(0 && "Unknown type!");
445 case MVT::isVoid: break;
450 MF.addLiveOut(SP::I0);
453 MF.addLiveOut(SP::I0);
454 MF.addLiveOut(SP::I1);
457 MF.addLiveOut(SP::F0);
460 MF.addLiveOut(SP::D0);
467 std::pair<SDOperand, SDOperand>
468 SparcTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
469 bool isVarArg, unsigned CC,
470 bool isTailCall, SDOperand Callee,
471 ArgListTy &Args, SelectionDAG &DAG) {
472 MachineFunction &MF = DAG.getMachineFunction();
473 // Count the size of the outgoing arguments.
474 unsigned ArgsSize = 0;
475 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
476 switch (getValueType(Args[i].second)) {
477 default: assert(0 && "Unknown value type!");
492 ArgsSize -= 4*6; // Space for first 6 arguments is prereserved.
496 // Keep stack frames 8-byte aligned.
497 ArgsSize = (ArgsSize+7) & ~7;
499 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(ArgsSize, getPointerTy()));
501 SDOperand StackPtr, NullSV;
502 std::vector<SDOperand> Stores;
503 std::vector<SDOperand> RegValuesToPass;
504 unsigned ArgOffset = 68;
505 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
506 SDOperand Val = Args[i].first;
507 MVT::ValueType ObjectVT = Val.getValueType();
508 SDOperand ValToStore(0, 0);
511 default: assert(0 && "Unhandled argument type!");
515 // Promote the integer to 32-bits. If the input type is signed, use a
516 // sign extend, otherwise use a zero extend.
517 if (Args[i].second->isSigned())
518 Val = DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Val);
520 Val = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Val);
525 if (RegValuesToPass.size() >= 6) {
528 RegValuesToPass.push_back(Val);
533 if (RegValuesToPass.size() >= 6) {
536 // Convert this to a FP value in an int reg.
537 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Val);
538 RegValuesToPass.push_back(Val);
543 // If we can store this directly into the outgoing slot, do so. We can
544 // do this when all ArgRegs are used and if the outgoing slot is aligned.
545 // FIXME: McGill/misr fails with this.
546 if (0 && RegValuesToPass.size() >= 6 && ((ArgOffset-68) & 7) == 0) {
551 // Otherwise, convert this to a FP value in int regs.
552 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Val);
556 if (RegValuesToPass.size() >= 6) {
557 ValToStore = Val; // Whole thing is passed in memory.
561 // Split the value into top and bottom part. Top part goes in a reg.
562 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val,
563 DAG.getConstant(1, MVT::i32));
564 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val,
565 DAG.getConstant(0, MVT::i32));
566 RegValuesToPass.push_back(Hi);
568 if (RegValuesToPass.size() >= 6) {
573 RegValuesToPass.push_back(Lo);
578 if (ValToStore.Val) {
580 StackPtr = DAG.getRegister(SP::O6, MVT::i32);
581 NullSV = DAG.getSrcValue(NULL);
583 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
584 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
585 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
586 ValToStore, PtrOff, NullSV));
588 ArgOffset += ObjSize;
591 // Emit all stores, make sure the occur before any copies into physregs.
593 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
595 static const unsigned ArgRegs[] = {
596 SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5
599 // Build a sequence of copy-to-reg nodes chained together with token chain
600 // and flag operands which copy the outgoing args into O[0-5].
602 for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
603 Chain = DAG.getCopyToReg(Chain, ArgRegs[i], RegValuesToPass[i], InFlag);
604 InFlag = Chain.getValue(1);
607 // If the callee is a GlobalAddress node (quite common, every direct call is)
608 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
609 // Likewise ExternalSymbol -> TargetExternalSymbol.
610 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
611 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32);
612 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
613 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
615 std::vector<MVT::ValueType> NodeTys;
616 NodeTys.push_back(MVT::Other); // Returns a chain
617 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
618 std::vector<SDOperand> Ops;
619 Ops.push_back(Chain);
620 Ops.push_back(Callee);
622 Ops.push_back(InFlag);
623 Chain = DAG.getNode(SPISD::CALL, NodeTys, Ops);
624 InFlag = Chain.getValue(1);
626 MVT::ValueType RetTyVT = getValueType(RetTy);
628 if (RetTyVT != MVT::isVoid) {
630 default: assert(0 && "Unknown value type to return!");
634 RetVal = DAG.getCopyFromReg(Chain, SP::O0, MVT::i32, InFlag);
635 Chain = RetVal.getValue(1);
637 // Add a note to keep track of whether it is sign or zero extended.
638 RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext :ISD::AssertZext,
639 MVT::i32, RetVal, DAG.getValueType(RetTyVT));
640 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
643 RetVal = DAG.getCopyFromReg(Chain, SP::O0, MVT::i32, InFlag);
644 Chain = RetVal.getValue(1);
647 RetVal = DAG.getCopyFromReg(Chain, SP::F0, MVT::f32, InFlag);
648 Chain = RetVal.getValue(1);
651 RetVal = DAG.getCopyFromReg(Chain, SP::D0, MVT::f64, InFlag);
652 Chain = RetVal.getValue(1);
655 SDOperand Lo = DAG.getCopyFromReg(Chain, SP::O1, MVT::i32, InFlag);
656 SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), SP::O0, MVT::i32,
658 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
659 Chain = Hi.getValue(1);
664 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
665 DAG.getConstant(ArgsSize, getPointerTy()));
667 return std::make_pair(RetVal, Chain);
670 // Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so
671 // set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition.
672 static void LookThroughSetCC(SDOperand &LHS, SDOperand &RHS,
673 ISD::CondCode CC, unsigned &SPCC) {
674 if (isa<ConstantSDNode>(RHS) && cast<ConstantSDNode>(RHS)->getValue() == 0 &&
676 ((LHS.getOpcode() == SPISD::SELECT_ICC &&
677 LHS.getOperand(3).getOpcode() == SPISD::CMPICC) ||
678 (LHS.getOpcode() == SPISD::SELECT_FCC &&
679 LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) &&
680 isa<ConstantSDNode>(LHS.getOperand(0)) &&
681 isa<ConstantSDNode>(LHS.getOperand(1)) &&
682 cast<ConstantSDNode>(LHS.getOperand(0))->getValue() == 1 &&
683 cast<ConstantSDNode>(LHS.getOperand(1))->getValue() == 0) {
684 SDOperand CMPCC = LHS.getOperand(3);
685 SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getValue();
686 LHS = CMPCC.getOperand(0);
687 RHS = CMPCC.getOperand(1);
692 SDOperand SparcTargetLowering::
693 LowerOperation(SDOperand Op, SelectionDAG &DAG) {
694 switch (Op.getOpcode()) {
695 default: assert(0 && "Should not custom lower this!");
696 case ISD::GlobalAddress: {
697 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
698 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
699 SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, GA);
700 SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, GA);
701 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
703 case ISD::ConstantPool: {
704 Constant *C = cast<ConstantPoolSDNode>(Op)->get();
705 SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32,
706 cast<ConstantPoolSDNode>(Op)->getAlignment());
707 SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, CP);
708 SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, CP);
709 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
711 case ISD::FP_TO_SINT:
712 // Convert the fp value to integer in an FP register.
713 assert(Op.getValueType() == MVT::i32);
714 Op = DAG.getNode(SPISD::FTOI, MVT::f32, Op.getOperand(0));
715 return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
716 case ISD::SINT_TO_FP: {
717 assert(Op.getOperand(0).getValueType() == MVT::i32);
718 SDOperand Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0));
719 // Convert the int value to FP in an FP register.
720 return DAG.getNode(SPISD::ITOF, Op.getValueType(), Tmp);
723 SDOperand Chain = Op.getOperand(0);
724 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
725 SDOperand LHS = Op.getOperand(2);
726 SDOperand RHS = Op.getOperand(3);
727 SDOperand Dest = Op.getOperand(4);
728 unsigned Opc, SPCC = ~0U;
730 // If this is a br_cc of a "setcc", and if the setcc got lowered into
731 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
732 LookThroughSetCC(LHS, RHS, CC, SPCC);
734 // Get the condition flag.
735 SDOperand CompareFlag;
736 if (LHS.getValueType() == MVT::i32) {
737 std::vector<MVT::ValueType> VTs;
738 VTs.push_back(MVT::i32);
739 VTs.push_back(MVT::Flag);
740 std::vector<SDOperand> Ops;
743 CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops).getValue(1);
744 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
747 CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS);
748 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
751 return DAG.getNode(Opc, MVT::Other, Chain, Dest,
752 DAG.getConstant(SPCC, MVT::i32), CompareFlag);
754 case ISD::SELECT_CC: {
755 SDOperand LHS = Op.getOperand(0);
756 SDOperand RHS = Op.getOperand(1);
757 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
758 SDOperand TrueVal = Op.getOperand(2);
759 SDOperand FalseVal = Op.getOperand(3);
760 unsigned Opc, SPCC = ~0U;
762 // If this is a select_cc of a "setcc", and if the setcc got lowered into
763 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
764 LookThroughSetCC(LHS, RHS, CC, SPCC);
766 SDOperand CompareFlag;
767 if (LHS.getValueType() == MVT::i32) {
768 std::vector<MVT::ValueType> VTs;
769 VTs.push_back(LHS.getValueType()); // subcc returns a value
770 VTs.push_back(MVT::Flag);
771 std::vector<SDOperand> Ops;
774 CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops).getValue(1);
775 Opc = SPISD::SELECT_ICC;
776 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
778 CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS);
779 Opc = SPISD::SELECT_FCC;
780 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
782 return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal,
783 DAG.getConstant(SPCC, MVT::i32), CompareFlag);
786 // vastart just stores the address of the VarArgsFrameIndex slot into the
787 // memory location argument.
788 SDOperand Offset = DAG.getNode(ISD::ADD, MVT::i32,
789 DAG.getRegister(SP::I6, MVT::i32),
790 DAG.getConstant(VarArgsFrameOffset, MVT::i32));
791 return DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0), Offset,
792 Op.getOperand(1), Op.getOperand(2));
795 SDNode *Node = Op.Val;
796 MVT::ValueType VT = Node->getValueType(0);
797 SDOperand InChain = Node->getOperand(0);
798 SDOperand VAListPtr = Node->getOperand(1);
799 SDOperand VAList = DAG.getLoad(getPointerTy(), InChain, VAListPtr,
800 Node->getOperand(2));
801 // Increment the pointer, VAList, to the next vaarg
802 SDOperand NextPtr = DAG.getNode(ISD::ADD, getPointerTy(), VAList,
803 DAG.getConstant(MVT::getSizeInBits(VT)/8,
805 // Store the incremented VAList to the legalized pointer
806 InChain = DAG.getNode(ISD::STORE, MVT::Other, VAList.getValue(1), NextPtr,
807 VAListPtr, Node->getOperand(2));
808 // Load the actual argument out of the pointer VAList, unless this is an
810 if (VT != MVT::f64) {
811 return DAG.getLoad(VT, InChain, VAList, DAG.getSrcValue(0));
813 // Otherwise, load it as i64, then do a bitconvert.
814 SDOperand V = DAG.getLoad(MVT::i64, InChain, VAList, DAG.getSrcValue(0));
815 std::vector<MVT::ValueType> Tys;
816 Tys.push_back(MVT::f64);
817 Tys.push_back(MVT::Other);
818 std::vector<SDOperand> Ops;
819 // Bit-Convert the value to f64.
820 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, MVT::f64, V));
821 Ops.push_back(V.getValue(1));
822 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops);
825 case ISD::DYNAMIC_STACKALLOC: {
826 SDOperand Chain = Op.getOperand(0); // Legalize the chain.
827 SDOperand Size = Op.getOperand(1); // Legalize the size.
829 unsigned SPReg = SP::O6;
830 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, MVT::i32);
831 SDOperand NewSP = DAG.getNode(ISD::SUB, MVT::i32, SP, Size); // Value
832 Chain = DAG.getCopyToReg(SP.getValue(1), SPReg, NewSP); // Output chain
834 // The resultant pointer is actually 16 words from the bottom of the stack,
835 // to provide a register spill area.
836 SDOperand NewVal = DAG.getNode(ISD::ADD, MVT::i32, NewSP,
837 DAG.getConstant(96, MVT::i32));
838 std::vector<MVT::ValueType> Tys;
839 Tys.push_back(MVT::i32);
840 Tys.push_back(MVT::Other);
841 std::vector<SDOperand> Ops;
842 Ops.push_back(NewVal);
843 Ops.push_back(Chain);
844 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops);
849 switch(Op.getNumOperands()) {
851 assert(0 && "Do not know how to return this many arguments!");
854 return SDOperand(); // ret void is legal
857 switch(Op.getOperand(1).getValueType()) {
858 default: assert(0 && "Unknown type to return!");
859 case MVT::i32: ArgReg = SP::I0; break;
860 case MVT::f32: ArgReg = SP::F0; break;
861 case MVT::f64: ArgReg = SP::D0; break;
863 Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1),
868 Copy = DAG.getCopyToReg(Op.getOperand(0), SP::I0, Op.getOperand(2),
870 Copy = DAG.getCopyToReg(Copy, SP::I1, Op.getOperand(1), Copy.getValue(1));
873 return DAG.getNode(SPISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
879 SparcTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
880 MachineBasicBlock *BB) {
883 // Figure out the conditional branch opcode to use for this select_cc.
884 switch (MI->getOpcode()) {
885 default: assert(0 && "Unknown SELECT_CC!");
886 case SP::SELECT_CC_Int_ICC:
887 case SP::SELECT_CC_FP_ICC:
888 case SP::SELECT_CC_DFP_ICC:
889 BROpcode = SP::BCOND;
891 case SP::SELECT_CC_Int_FCC:
892 case SP::SELECT_CC_FP_FCC:
893 case SP::SELECT_CC_DFP_FCC:
894 BROpcode = SP::FBCOND;
898 CC = (SPCC::CondCodes)MI->getOperand(3).getImmedValue();
900 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
901 // control-flow pattern. The incoming instruction knows the destination vreg
902 // to set, the condition code register to branch on, the true/false values to
903 // select between, and a branch opcode to use.
904 const BasicBlock *LLVM_BB = BB->getBasicBlock();
905 ilist<MachineBasicBlock>::iterator It = BB;
912 // fallthrough --> copy0MBB
913 MachineBasicBlock *thisMBB = BB;
914 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
915 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
916 BuildMI(BB, BROpcode, 2).addMBB(sinkMBB).addImm(CC);
917 MachineFunction *F = BB->getParent();
918 F->getBasicBlockList().insert(It, copy0MBB);
919 F->getBasicBlockList().insert(It, sinkMBB);
920 // Update machine-CFG edges
921 BB->addSuccessor(copy0MBB);
922 BB->addSuccessor(sinkMBB);
926 // # fallthrough to sinkMBB
929 // Update machine-CFG edges
930 BB->addSuccessor(sinkMBB);
933 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
936 BuildMI(BB, SP::PHI, 4, MI->getOperand(0).getReg())
937 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
938 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
940 delete MI; // The pseudo instruction is gone now.
944 //===----------------------------------------------------------------------===//
945 // Instruction Selector Implementation
946 //===----------------------------------------------------------------------===//
948 //===--------------------------------------------------------------------===//
949 /// SparcDAGToDAGISel - SPARC specific code to select SPARC machine
950 /// instructions for SelectionDAG operations.
953 class SparcDAGToDAGISel : public SelectionDAGISel {
954 SparcTargetLowering Lowering;
956 /// Subtarget - Keep a pointer to the Sparc Subtarget around so that we can
957 /// make the right decision when generating code for different targets.
958 const SparcSubtarget &Subtarget;
960 SparcDAGToDAGISel(TargetMachine &TM)
961 : SelectionDAGISel(Lowering), Lowering(TM),
962 Subtarget(TM.getSubtarget<SparcSubtarget>()) {
965 void Select(SDOperand &Result, SDOperand Op);
967 // Complex Pattern Selectors.
968 bool SelectADDRrr(SDOperand N, SDOperand &R1, SDOperand &R2);
969 bool SelectADDRri(SDOperand N, SDOperand &Base, SDOperand &Offset);
971 /// InstructionSelectBasicBlock - This callback is invoked by
972 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
973 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
975 virtual const char *getPassName() const {
976 return "SPARC DAG->DAG Pattern Instruction Selection";
979 // Include the pieces autogenerated from the target description.
980 #include "SparcGenDAGISel.inc"
982 } // end anonymous namespace
984 /// InstructionSelectBasicBlock - This callback is invoked by
985 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
986 void SparcDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
989 // Select target instructions for the DAG.
990 DAG.setRoot(SelectRoot(DAG.getRoot()));
992 DAG.RemoveDeadNodes();
994 // Emit machine code to BB.
995 ScheduleAndEmitDAG(DAG);
998 bool SparcDAGToDAGISel::SelectADDRri(SDOperand Addr, SDOperand &Base,
1000 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
1001 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
1002 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1005 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
1006 Addr.getOpcode() == ISD::TargetGlobalAddress)
1007 return false; // direct calls.
1009 if (Addr.getOpcode() == ISD::ADD) {
1010 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
1011 if (Predicate_simm13(CN)) {
1012 if (FrameIndexSDNode *FIN =
1013 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
1014 // Constant offset from frame ref.
1015 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
1017 Base = Addr.getOperand(0);
1019 Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32);
1023 if (Addr.getOperand(0).getOpcode() == SPISD::Lo) {
1024 Base = Addr.getOperand(1);
1025 Offset = Addr.getOperand(0).getOperand(0);
1028 if (Addr.getOperand(1).getOpcode() == SPISD::Lo) {
1029 Base = Addr.getOperand(0);
1030 Offset = Addr.getOperand(1).getOperand(0);
1035 Offset = CurDAG->getTargetConstant(0, MVT::i32);
1039 bool SparcDAGToDAGISel::SelectADDRrr(SDOperand Addr, SDOperand &R1,
1041 if (Addr.getOpcode() == ISD::FrameIndex) return false;
1042 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
1043 Addr.getOpcode() == ISD::TargetGlobalAddress)
1044 return false; // direct calls.
1046 if (Addr.getOpcode() == ISD::ADD) {
1047 if (isa<ConstantSDNode>(Addr.getOperand(1)) &&
1048 Predicate_simm13(Addr.getOperand(1).Val))
1049 return false; // Let the reg+imm pattern catch this!
1050 if (Addr.getOperand(0).getOpcode() == SPISD::Lo ||
1051 Addr.getOperand(1).getOpcode() == SPISD::Lo)
1052 return false; // Let the reg+imm pattern catch this!
1053 R1 = Addr.getOperand(0);
1054 R2 = Addr.getOperand(1);
1059 R2 = CurDAG->getRegister(SP::G0, MVT::i32);
1063 void SparcDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
1065 if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
1066 N->getOpcode() < SPISD::FIRST_NUMBER) {
1068 return; // Already selected.
1071 // If this has already been converted, use it.
1072 std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op);
1073 if (CGMI != CodeGenMap.end()) {
1074 Result = CGMI->second;
1078 switch (N->getOpcode()) {
1082 // FIXME: should use a custom expander to expose the SRA to the dag.
1083 SDOperand DivLHS, DivRHS;
1084 Select(DivLHS, N->getOperand(0));
1085 Select(DivRHS, N->getOperand(1));
1087 // Set the Y register to the high-part.
1089 if (N->getOpcode() == ISD::SDIV) {
1090 TopPart = SDOperand(CurDAG->getTargetNode(SP::SRAri, MVT::i32, DivLHS,
1091 CurDAG->getTargetConstant(31, MVT::i32)), 0);
1093 TopPart = CurDAG->getRegister(SP::G0, MVT::i32);
1095 TopPart = SDOperand(CurDAG->getTargetNode(SP::WRYrr, MVT::Flag, TopPart,
1096 CurDAG->getRegister(SP::G0, MVT::i32)), 0);
1098 // FIXME: Handle div by immediate.
1099 unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
1100 Result = CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, TopPart);
1105 // FIXME: Handle mul by immediate.
1106 SDOperand MulLHS, MulRHS;
1107 Select(MulLHS, N->getOperand(0));
1108 Select(MulRHS, N->getOperand(1));
1109 unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr;
1110 SDNode *Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag,
1112 // The high part is in the Y register.
1113 Result = CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDOperand(Mul, 1));
1118 SelectCode(Result, Op);
1122 /// createSparcISelDag - This pass converts a legalized DAG into a
1123 /// SPARC-specific DAG, ready for instruction scheduling.
1125 FunctionPass *llvm::createSparcISelDag(TargetMachine &TM) {
1126 return new SparcDAGToDAGISel(TM);