1 //===-- SparcISelDAGToDAG.cpp - A dag to dag inst selector for Sparc ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the SPARC target.
12 //===----------------------------------------------------------------------===//
14 #include "SparcISelLowering.h"
15 #include "SparcTargetMachine.h"
16 #include "llvm/Intrinsics.h"
17 #include "llvm/CodeGen/SelectionDAGISel.h"
18 #include "llvm/Support/Compiler.h"
19 #include "llvm/Support/Debug.h"
22 //===----------------------------------------------------------------------===//
23 // Instruction Selector Implementation
24 //===----------------------------------------------------------------------===//
26 //===--------------------------------------------------------------------===//
27 /// SparcDAGToDAGISel - SPARC specific code to select SPARC machine
28 /// instructions for SelectionDAG operations.
31 class SparcDAGToDAGISel : public SelectionDAGISel {
32 /// Subtarget - Keep a pointer to the Sparc Subtarget around so that we can
33 /// make the right decision when generating code for different targets.
34 const SparcSubtarget &Subtarget;
36 explicit SparcDAGToDAGISel(SparcTargetMachine &TM)
37 : SelectionDAGISel(*TM.getTargetLowering()),
38 Subtarget(TM.getSubtarget<SparcSubtarget>()) {
41 SDNode *Select(SDValue Op);
43 // Complex Pattern Selectors.
44 bool SelectADDRrr(SDValue Op, SDValue N, SDValue &R1, SDValue &R2);
45 bool SelectADDRri(SDValue Op, SDValue N, SDValue &Base,
48 /// InstructionSelect - This callback is invoked by
49 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
50 virtual void InstructionSelect();
52 virtual const char *getPassName() const {
53 return "SPARC DAG->DAG Pattern Instruction Selection";
56 // Include the pieces autogenerated from the target description.
57 #include "SparcGenDAGISel.inc"
59 } // end anonymous namespace
61 /// InstructionSelect - This callback is invoked by
62 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
63 void SparcDAGToDAGISel::InstructionSelect() {
66 // Select target instructions for the DAG.
68 CurDAG->RemoveDeadNodes();
71 bool SparcDAGToDAGISel::SelectADDRri(SDValue Op, SDValue Addr,
72 SDValue &Base, SDValue &Offset) {
73 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
74 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
75 Offset = CurDAG->getTargetConstant(0, MVT::i32);
78 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
79 Addr.getOpcode() == ISD::TargetGlobalAddress)
80 return false; // direct calls.
82 if (Addr.getOpcode() == ISD::ADD) {
83 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
84 if (Predicate_simm13(CN)) {
85 if (FrameIndexSDNode *FIN =
86 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
87 // Constant offset from frame ref.
88 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
90 Base = Addr.getOperand(0);
92 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), MVT::i32);
96 if (Addr.getOperand(0).getOpcode() == SPISD::Lo) {
97 Base = Addr.getOperand(1);
98 Offset = Addr.getOperand(0).getOperand(0);
101 if (Addr.getOperand(1).getOpcode() == SPISD::Lo) {
102 Base = Addr.getOperand(0);
103 Offset = Addr.getOperand(1).getOperand(0);
108 Offset = CurDAG->getTargetConstant(0, MVT::i32);
112 bool SparcDAGToDAGISel::SelectADDRrr(SDValue Op, SDValue Addr,
113 SDValue &R1, SDValue &R2) {
114 if (Addr.getOpcode() == ISD::FrameIndex) return false;
115 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
116 Addr.getOpcode() == ISD::TargetGlobalAddress)
117 return false; // direct calls.
119 if (Addr.getOpcode() == ISD::ADD) {
120 if (isa<ConstantSDNode>(Addr.getOperand(1)) &&
121 Predicate_simm13(Addr.getOperand(1).getNode()))
122 return false; // Let the reg+imm pattern catch this!
123 if (Addr.getOperand(0).getOpcode() == SPISD::Lo ||
124 Addr.getOperand(1).getOpcode() == SPISD::Lo)
125 return false; // Let the reg+imm pattern catch this!
126 R1 = Addr.getOperand(0);
127 R2 = Addr.getOperand(1);
132 R2 = CurDAG->getRegister(SP::G0, MVT::i32);
136 SDNode *SparcDAGToDAGISel::Select(SDValue Op) {
137 SDNode *N = Op.getNode();
138 if (N->isMachineOpcode())
139 return NULL; // Already selected.
141 switch (N->getOpcode()) {
145 // FIXME: should use a custom expander to expose the SRA to the dag.
146 SDValue DivLHS = N->getOperand(0);
147 SDValue DivRHS = N->getOperand(1);
148 AddToISelQueue(DivLHS);
149 AddToISelQueue(DivRHS);
151 // Set the Y register to the high-part.
153 if (N->getOpcode() == ISD::SDIV) {
154 TopPart = SDValue(CurDAG->getTargetNode(SP::SRAri, MVT::i32, DivLHS,
155 CurDAG->getTargetConstant(31, MVT::i32)), 0);
157 TopPart = CurDAG->getRegister(SP::G0, MVT::i32);
159 TopPart = SDValue(CurDAG->getTargetNode(SP::WRYrr, MVT::Flag, TopPart,
160 CurDAG->getRegister(SP::G0, MVT::i32)), 0);
162 // FIXME: Handle div by immediate.
163 unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
164 return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS,
169 // FIXME: Handle mul by immediate.
170 SDValue MulLHS = N->getOperand(0);
171 SDValue MulRHS = N->getOperand(1);
172 AddToISelQueue(MulLHS);
173 AddToISelQueue(MulRHS);
174 unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr;
175 SDNode *Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag,
177 // The high part is in the Y register.
178 return CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDValue(Mul, 1));
183 return SelectCode(Op);
187 /// createSparcISelDag - This pass converts a legalized DAG into a
188 /// SPARC-specific DAG, ready for instruction scheduling.
190 FunctionPass *llvm::createSparcISelDag(SparcTargetMachine &TM) {
191 return new SparcDAGToDAGISel(TM);