1 //===-- SparcInstPrinter.cpp - Convert Sparc MCInst to assembly syntax -----==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class prints an Sparc MCInst to a .s file.
12 //===----------------------------------------------------------------------===//
14 #include "SparcInstPrinter.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/MC/MCSymbol.h"
19 #include "llvm/Support/raw_ostream.h"
22 #define DEBUG_TYPE "asm-printer"
24 // The generated AsmMatcher SparcGenAsmWriter uses "Sparc" as the target
25 // namespace. But SPARC backend uses "SP" as its namespace.
32 #define GET_INSTRUCTION_NAME
33 #define PRINT_ALIAS_INSTR
34 #include "SparcGenAsmWriter.inc"
36 bool SparcInstPrinter::isV9() const {
37 return (STI.getFeatureBits() & Sparc::FeatureV9) != 0;
40 void SparcInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const
42 OS << '%' << StringRef(getRegisterName(RegNo)).lower();
45 void SparcInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
48 if (!printAliasInstr(MI, O) && !printSparcAliasInstr(MI, O))
49 printInstruction(MI, O);
50 printAnnotation(O, Annot);
53 bool SparcInstPrinter::printSparcAliasInstr(const MCInst *MI, raw_ostream &O)
55 switch (MI->getOpcode()) {
56 default: return false;
59 if (MI->getNumOperands() != 3)
61 if (!MI->getOperand(0).isReg())
63 switch (MI->getOperand(0).getReg()) {
64 default: return false;
65 case SP::G0: // jmp $addr | ret | retl
66 if (MI->getOperand(2).isImm() &&
67 MI->getOperand(2).getImm() == 8) {
68 switch(MI->getOperand(1).getReg()) {
70 case SP::I7: O << "\tret"; return true;
71 case SP::O7: O << "\tretl"; return true;
74 O << "\tjmp "; printMemOperand(MI, 1, O);
76 case SP::O7: // call $addr
77 O << "\tcall "; printMemOperand(MI, 1, O);
81 case SP::V9FCMPS: case SP::V9FCMPD: case SP::V9FCMPQ:
82 case SP::V9FCMPES: case SP::V9FCMPED: case SP::V9FCMPEQ: {
84 || (MI->getNumOperands() != 3)
85 || (!MI->getOperand(0).isReg())
86 || (MI->getOperand(0).getReg() != SP::FCC0))
88 // if V8, skip printing %fcc0.
89 switch(MI->getOpcode()) {
91 case SP::V9FCMPS: O << "\tfcmps "; break;
92 case SP::V9FCMPD: O << "\tfcmpd "; break;
93 case SP::V9FCMPQ: O << "\tfcmpq "; break;
94 case SP::V9FCMPES: O << "\tfcmpes "; break;
95 case SP::V9FCMPED: O << "\tfcmped "; break;
96 case SP::V9FCMPEQ: O << "\tfcmpeq "; break;
98 printOperand(MI, 1, O);
100 printOperand(MI, 2, O);
106 void SparcInstPrinter::printOperand(const MCInst *MI, int opNum,
109 const MCOperand &MO = MI->getOperand (opNum);
112 printRegName(O, MO.getReg());
117 O << (int)MO.getImm();
121 assert(MO.isExpr() && "Unknown operand kind in printOperand");
122 MO.getExpr()->print(O);
125 void SparcInstPrinter::printMemOperand(const MCInst *MI, int opNum,
126 raw_ostream &O, const char *Modifier)
128 printOperand(MI, opNum, O);
130 // If this is an ADD operand, emit it like normal operands.
131 if (Modifier && !strcmp(Modifier, "arith")) {
133 printOperand(MI, opNum+1, O);
136 const MCOperand &MO = MI->getOperand(opNum+1);
138 if (MO.isReg() && MO.getReg() == SP::G0)
139 return; // don't print "+%g0"
140 if (MO.isImm() && MO.getImm() == 0)
141 return; // don't print "+0"
145 printOperand(MI, opNum+1, O);
148 void SparcInstPrinter::printCCOperand(const MCInst *MI, int opNum,
151 int CC = (int)MI->getOperand(opNum).getImm();
152 switch (MI->getOpcode()) {
160 case SP::MOVFCCrr: case SP::V9MOVFCCrr:
161 case SP::MOVFCCri: case SP::V9MOVFCCri:
162 case SP::FMOVS_FCC: case SP::V9FMOVS_FCC:
163 case SP::FMOVD_FCC: case SP::V9FMOVD_FCC:
164 case SP::FMOVQ_FCC: case SP::V9FMOVQ_FCC:
165 // Make sure CC is a fp conditional flag.
166 CC = (CC < 16) ? (CC + 16) : CC;
169 O << SPARCCondCodeToString((SPCC::CondCodes)CC);
172 bool SparcInstPrinter::printGetPCX(const MCInst *MI, unsigned opNum,
175 assert(0 && "FIXME: Implement SparcInstPrinter::printGetPCX.");