1 //===-- DelaySlotFiller.cpp - SPARC delay slot filler ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This is a simple local pass that attempts to fill delay slots with useful
11 // instructions. If no instructions can be moved into the delay slot, then a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "delay-slot-filler"
17 #include "SparcSubtarget.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/CodeGen/MachineFunctionPass.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/Support/CommandLine.h"
23 #include "llvm/Target/TargetInstrInfo.h"
24 #include "llvm/Target/TargetMachine.h"
25 #include "llvm/Target/TargetRegisterInfo.h"
29 STATISTIC(FilledSlots, "Number of delay slots filled");
31 static cl::opt<bool> DisableDelaySlotFiller(
32 "disable-sparc-delay-filler",
34 cl::desc("Disable the Sparc delay slot filler."),
38 struct Filler : public MachineFunctionPass {
39 /// Target machine description which we query for reg. names, data
43 const SparcSubtarget *Subtarget;
46 Filler(TargetMachine &tm)
47 : MachineFunctionPass(ID), TM(tm),
48 Subtarget(&TM.getSubtarget<SparcSubtarget>()) {
51 virtual const char *getPassName() const {
52 return "SPARC Delay Slot Filler";
55 bool runOnMachineBasicBlock(MachineBasicBlock &MBB);
56 bool runOnMachineFunction(MachineFunction &F) {
58 for (MachineFunction::iterator FI = F.begin(), FE = F.end();
60 Changed |= runOnMachineBasicBlock(*FI);
64 bool isDelayFiller(MachineBasicBlock &MBB,
65 MachineBasicBlock::iterator candidate);
67 void insertCallDefsUses(MachineBasicBlock::iterator MI,
68 SmallSet<unsigned, 32>& RegDefs,
69 SmallSet<unsigned, 32>& RegUses);
71 void insertDefsUses(MachineBasicBlock::iterator MI,
72 SmallSet<unsigned, 32>& RegDefs,
73 SmallSet<unsigned, 32>& RegUses);
75 bool IsRegInSet(SmallSet<unsigned, 32>& RegSet,
78 bool delayHasHazard(MachineBasicBlock::iterator candidate,
79 bool &sawLoad, bool &sawStore,
80 SmallSet<unsigned, 32> &RegDefs,
81 SmallSet<unsigned, 32> &RegUses);
83 MachineBasicBlock::iterator
84 findDelayInstr(MachineBasicBlock &MBB, MachineBasicBlock::iterator slot);
86 bool needsUnimp(MachineBasicBlock::iterator I, unsigned &StructSize);
88 bool tryCombineRestoreWithPrevInst(MachineBasicBlock &MBB,
89 MachineBasicBlock::iterator MBBI);
93 } // end of anonymous namespace
95 /// createSparcDelaySlotFillerPass - Returns a pass that fills in delay
96 /// slots in Sparc MachineFunctions
98 FunctionPass *llvm::createSparcDelaySlotFillerPass(TargetMachine &tm) {
99 return new Filler(tm);
103 /// runOnMachineBasicBlock - Fill in delay slots for the given basic block.
104 /// We assume there is only one delay slot per delayed instruction.
106 bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
107 bool Changed = false;
109 const TargetInstrInfo *TII = TM.getInstrInfo();
111 for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ) {
112 MachineBasicBlock::iterator MI = I;
115 // If MI is restore, try combining it with previous inst.
116 if (!DisableDelaySlotFiller &&
117 (MI->getOpcode() == SP::RESTORErr
118 || MI->getOpcode() == SP::RESTOREri)) {
119 Changed |= tryCombineRestoreWithPrevInst(MBB, MI);
123 if (!Subtarget->isV9() &&
124 (MI->getOpcode() == SP::FCMPS || MI->getOpcode() == SP::FCMPD
125 || MI->getOpcode() == SP::FCMPQ)) {
126 BuildMI(MBB, I, MI->getDebugLoc(), TII->get(SP::NOP));
131 // If MI has no delay slot, skip.
132 if (!MI->hasDelaySlot())
135 MachineBasicBlock::iterator D = MBB.end();
137 if (!DisableDelaySlotFiller)
138 D = findDelayInstr(MBB, MI);
144 BuildMI(MBB, I, MI->getDebugLoc(), TII->get(SP::NOP));
146 MBB.splice(I, &MBB, D);
148 unsigned structSize = 0;
149 if (needsUnimp(MI, structSize)) {
150 MachineBasicBlock::iterator J = MI;
151 ++J; // skip the delay filler.
152 assert (J != MBB.end() && "MI needs a delay instruction.");
153 BuildMI(MBB, ++J, MI->getDebugLoc(),
154 TII->get(SP::UNIMP)).addImm(structSize);
160 MachineBasicBlock::iterator
161 Filler::findDelayInstr(MachineBasicBlock &MBB,
162 MachineBasicBlock::iterator slot)
164 SmallSet<unsigned, 32> RegDefs;
165 SmallSet<unsigned, 32> RegUses;
166 bool sawLoad = false;
167 bool sawStore = false;
169 if (slot == MBB.begin())
172 if (slot->getOpcode() == SP::RET || slot->getOpcode() == SP::TLS_CALL)
175 if (slot->getOpcode() == SP::RETL) {
176 MachineBasicBlock::iterator J = slot;
179 if (J->getOpcode() == SP::RESTORErr
180 || J->getOpcode() == SP::RESTOREri) {
181 // change retl to ret.
182 slot->setDesc(TM.getInstrInfo()->get(SP::RET));
187 // Call's delay filler can def some of call's uses.
189 insertCallDefsUses(slot, RegDefs, RegUses);
191 insertDefsUses(slot, RegDefs, RegUses);
195 MachineBasicBlock::iterator I = slot;
198 done = (I == MBB.begin());
204 if (I->isDebugValue())
208 if (I->hasUnmodeledSideEffects()
212 || isDelayFiller(MBB, I))
215 if (delayHasHazard(I, sawLoad, sawStore, RegDefs, RegUses)) {
216 insertDefsUses(I, RegDefs, RegUses);
225 bool Filler::delayHasHazard(MachineBasicBlock::iterator candidate,
228 SmallSet<unsigned, 32> &RegDefs,
229 SmallSet<unsigned, 32> &RegUses)
232 if (candidate->isImplicitDef() || candidate->isKill())
235 if (candidate->mayLoad()) {
241 if (candidate->mayStore()) {
249 for (unsigned i = 0, e = candidate->getNumOperands(); i!= e; ++i) {
250 const MachineOperand &MO = candidate->getOperand(i);
254 unsigned Reg = MO.getReg();
257 // check whether Reg is defined or used before delay slot.
258 if (IsRegInSet(RegDefs, Reg) || IsRegInSet(RegUses, Reg))
262 // check whether Reg is defined before delay slot.
263 if (IsRegInSet(RegDefs, Reg))
271 void Filler::insertCallDefsUses(MachineBasicBlock::iterator MI,
272 SmallSet<unsigned, 32>& RegDefs,
273 SmallSet<unsigned, 32>& RegUses)
275 // Call defines o7, which is visible to the instruction in delay slot.
276 RegDefs.insert(SP::O7);
278 switch(MI->getOpcode()) {
279 default: llvm_unreachable("Unknown opcode.");
280 case SP::CALL: break;
283 assert(MI->getNumOperands() >= 2);
284 const MachineOperand &Reg = MI->getOperand(0);
285 assert(Reg.isReg() && "JMPL first operand is not a register.");
286 assert(Reg.isUse() && "JMPL first operand is not a use.");
287 RegUses.insert(Reg.getReg());
289 const MachineOperand &RegOrImm = MI->getOperand(1);
290 if (RegOrImm.isImm())
292 assert(RegOrImm.isReg() && "JMPLrr second operand is not a register.");
293 assert(RegOrImm.isUse() && "JMPLrr second operand is not a use.");
294 RegUses.insert(RegOrImm.getReg());
299 // Insert Defs and Uses of MI into the sets RegDefs and RegUses.
300 void Filler::insertDefsUses(MachineBasicBlock::iterator MI,
301 SmallSet<unsigned, 32>& RegDefs,
302 SmallSet<unsigned, 32>& RegUses)
304 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
305 const MachineOperand &MO = MI->getOperand(i);
309 unsigned Reg = MO.getReg();
315 // Implicit register uses of retl are return values and
316 // retl does not use them.
317 if (MO.isImplicit() && MI->getOpcode() == SP::RETL)
324 // returns true if the Reg or its alias is in the RegSet.
325 bool Filler::IsRegInSet(SmallSet<unsigned, 32>& RegSet, unsigned Reg)
327 // Check Reg and all aliased Registers.
328 for (MCRegAliasIterator AI(Reg, TM.getRegisterInfo(), true);
330 if (RegSet.count(*AI))
335 // return true if the candidate is a delay filler.
336 bool Filler::isDelayFiller(MachineBasicBlock &MBB,
337 MachineBasicBlock::iterator candidate)
339 if (candidate == MBB.begin())
341 if (candidate->getOpcode() == SP::UNIMP)
344 return candidate->hasDelaySlot();
347 bool Filler::needsUnimp(MachineBasicBlock::iterator I, unsigned &StructSize)
352 unsigned structSizeOpNum = 0;
353 switch (I->getOpcode()) {
354 default: llvm_unreachable("Unknown call opcode.");
355 case SP::CALL: structSizeOpNum = 1; break;
357 case SP::JMPLri: structSizeOpNum = 2; break;
358 case SP::TLS_CALL: return false;
361 const MachineOperand &MO = I->getOperand(structSizeOpNum);
364 StructSize = MO.getImm();
368 static bool combineRestoreADD(MachineBasicBlock::iterator RestoreMI,
369 MachineBasicBlock::iterator AddMI,
370 const TargetInstrInfo *TII)
372 // Before: add <op0>, <op1>, %i[0-7]
373 // restore %g0, %g0, %i[0-7]
375 // After : restore <op0>, <op1>, %o[0-7]
377 unsigned reg = AddMI->getOperand(0).getReg();
378 if (reg < SP::I0 || reg > SP::I7)
382 RestoreMI->eraseFromParent();
384 // Change ADD to RESTORE.
385 AddMI->setDesc(TII->get((AddMI->getOpcode() == SP::ADDrr)
389 // Map the destination register.
390 AddMI->getOperand(0).setReg(reg - SP::I0 + SP::O0);
395 static bool combineRestoreOR(MachineBasicBlock::iterator RestoreMI,
396 MachineBasicBlock::iterator OrMI,
397 const TargetInstrInfo *TII)
399 // Before: or <op0>, <op1>, %i[0-7]
400 // restore %g0, %g0, %i[0-7]
401 // and <op0> or <op1> is zero,
403 // After : restore <op0>, <op1>, %o[0-7]
405 unsigned reg = OrMI->getOperand(0).getReg();
406 if (reg < SP::I0 || reg > SP::I7)
409 // check whether it is a copy.
410 if (OrMI->getOpcode() == SP::ORrr
411 && OrMI->getOperand(1).getReg() != SP::G0
412 && OrMI->getOperand(2).getReg() != SP::G0)
415 if (OrMI->getOpcode() == SP::ORri
416 && OrMI->getOperand(1).getReg() != SP::G0
417 && (!OrMI->getOperand(2).isImm() || OrMI->getOperand(2).getImm() != 0))
421 RestoreMI->eraseFromParent();
423 // Change OR to RESTORE.
424 OrMI->setDesc(TII->get((OrMI->getOpcode() == SP::ORrr)
428 // Map the destination register.
429 OrMI->getOperand(0).setReg(reg - SP::I0 + SP::O0);
434 static bool combineRestoreSETHIi(MachineBasicBlock::iterator RestoreMI,
435 MachineBasicBlock::iterator SetHiMI,
436 const TargetInstrInfo *TII)
438 // Before: sethi imm3, %i[0-7]
439 // restore %g0, %g0, %g0
441 // After : restore %g0, (imm3<<10), %o[0-7]
443 unsigned reg = SetHiMI->getOperand(0).getReg();
444 if (reg < SP::I0 || reg > SP::I7)
447 if (!SetHiMI->getOperand(1).isImm())
450 int64_t imm = SetHiMI->getOperand(1).getImm();
452 // Is it a 3 bit immediate?
456 // Make it a 13 bit immediate.
457 imm = (imm << 10) & 0x1FFF;
459 assert(RestoreMI->getOpcode() == SP::RESTORErr);
461 RestoreMI->setDesc(TII->get(SP::RESTOREri));
463 RestoreMI->getOperand(0).setReg(reg - SP::I0 + SP::O0);
464 RestoreMI->getOperand(1).setReg(SP::G0);
465 RestoreMI->getOperand(2).ChangeToImmediate(imm);
468 // Erase the original SETHI.
469 SetHiMI->eraseFromParent();
474 bool Filler::tryCombineRestoreWithPrevInst(MachineBasicBlock &MBB,
475 MachineBasicBlock::iterator MBBI)
477 // No previous instruction.
478 if (MBBI == MBB.begin())
481 // assert that MBBI is a "restore %g0, %g0, %g0".
482 assert(MBBI->getOpcode() == SP::RESTORErr
483 && MBBI->getOperand(0).getReg() == SP::G0
484 && MBBI->getOperand(1).getReg() == SP::G0
485 && MBBI->getOperand(2).getReg() == SP::G0);
487 MachineBasicBlock::iterator PrevInst = MBBI; --PrevInst;
489 // It cannot combine with a delay filler.
490 if (isDelayFiller(MBB, PrevInst))
493 const TargetInstrInfo *TII = TM.getInstrInfo();
495 switch (PrevInst->getOpcode()) {
498 case SP::ADDri: return combineRestoreADD(MBBI, PrevInst, TII); break;
500 case SP::ORri: return combineRestoreOR(MBBI, PrevInst, TII); break;
501 case SP::SETHIi: return combineRestoreSETHIi(MBBI, PrevInst, TII); break;
503 // It cannot combine with the previous instruction.