1 //===-- DelaySlotFiller.cpp - SPARC delay slot filler ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This is a simple local pass that attempts to fill delay slots with useful
11 // instructions. If no instructions can be moved into the delay slot, then a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "delay-slot-filler"
17 #include "llvm/ADT/SmallSet.h"
18 #include "llvm/ADT/Statistic.h"
19 #include "llvm/CodeGen/MachineFunctionPass.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/Support/CommandLine.h"
22 #include "llvm/Target/TargetInstrInfo.h"
23 #include "llvm/Target/TargetMachine.h"
24 #include "llvm/Target/TargetRegisterInfo.h"
28 STATISTIC(FilledSlots, "Number of delay slots filled");
30 static cl::opt<bool> DisableDelaySlotFiller(
31 "disable-sparc-delay-filler",
33 cl::desc("Disable the Sparc delay slot filler."),
37 struct Filler : public MachineFunctionPass {
38 /// Target machine description which we query for reg. names, data
42 const TargetInstrInfo *TII;
45 Filler(TargetMachine &tm)
46 : MachineFunctionPass(ID), TM(tm), TII(tm.getInstrInfo()) { }
48 virtual const char *getPassName() const {
49 return "SPARC Delay Slot Filler";
52 bool runOnMachineBasicBlock(MachineBasicBlock &MBB);
53 bool runOnMachineFunction(MachineFunction &F) {
55 for (MachineFunction::iterator FI = F.begin(), FE = F.end();
57 Changed |= runOnMachineBasicBlock(*FI);
61 bool isDelayFiller(MachineBasicBlock &MBB,
62 MachineBasicBlock::iterator candidate);
64 void insertCallDefsUses(MachineBasicBlock::iterator MI,
65 SmallSet<unsigned, 32>& RegDefs,
66 SmallSet<unsigned, 32>& RegUses);
68 void insertDefsUses(MachineBasicBlock::iterator MI,
69 SmallSet<unsigned, 32>& RegDefs,
70 SmallSet<unsigned, 32>& RegUses);
72 bool IsRegInSet(SmallSet<unsigned, 32>& RegSet,
75 bool delayHasHazard(MachineBasicBlock::iterator candidate,
76 bool &sawLoad, bool &sawStore,
77 SmallSet<unsigned, 32> &RegDefs,
78 SmallSet<unsigned, 32> &RegUses);
80 MachineBasicBlock::iterator
81 findDelayInstr(MachineBasicBlock &MBB, MachineBasicBlock::iterator slot);
83 bool needsUnimp(MachineBasicBlock::iterator I, unsigned &StructSize);
85 bool tryCombineRestoreWithPrevInst(MachineBasicBlock &MBB,
86 MachineBasicBlock::iterator MBBI);
90 } // end of anonymous namespace
92 /// createSparcDelaySlotFillerPass - Returns a pass that fills in delay
93 /// slots in Sparc MachineFunctions
95 FunctionPass *llvm::createSparcDelaySlotFillerPass(TargetMachine &tm) {
96 return new Filler(tm);
100 /// runOnMachineBasicBlock - Fill in delay slots for the given basic block.
101 /// We assume there is only one delay slot per delayed instruction.
103 bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
104 bool Changed = false;
106 for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ) {
107 MachineBasicBlock::iterator MI = I;
110 // If MI is restore, try combining it with previous inst.
111 if (!DisableDelaySlotFiller &&
112 (MI->getOpcode() == SP::RESTORErr
113 || MI->getOpcode() == SP::RESTOREri)) {
114 Changed |= tryCombineRestoreWithPrevInst(MBB, MI);
118 // If MI has no delay slot, skip.
119 if (!MI->hasDelaySlot())
122 MachineBasicBlock::iterator D = MBB.end();
124 if (!DisableDelaySlotFiller)
125 D = findDelayInstr(MBB, MI);
131 BuildMI(MBB, I, MI->getDebugLoc(), TII->get(SP::NOP));
133 MBB.splice(I, &MBB, D);
135 unsigned structSize = 0;
136 if (needsUnimp(MI, structSize)) {
137 MachineBasicBlock::iterator J = MI;
138 ++J; // skip the delay filler.
139 assert (J != MBB.end() && "MI needs a delay instruction.");
140 BuildMI(MBB, ++J, I->getDebugLoc(),
141 TII->get(SP::UNIMP)).addImm(structSize);
147 MachineBasicBlock::iterator
148 Filler::findDelayInstr(MachineBasicBlock &MBB,
149 MachineBasicBlock::iterator slot)
151 SmallSet<unsigned, 32> RegDefs;
152 SmallSet<unsigned, 32> RegUses;
153 bool sawLoad = false;
154 bool sawStore = false;
156 if (slot == MBB.begin())
159 if (slot->getOpcode() == SP::RET)
162 if (slot->getOpcode() == SP::RETL) {
163 MachineBasicBlock::iterator J = slot;
166 if (J->getOpcode() == SP::RESTORErr
167 || J->getOpcode() == SP::RESTOREri) {
168 // change retl to ret.
169 slot->setDesc(TII->get(SP::RET));
174 // Call's delay filler can def some of call's uses.
176 insertCallDefsUses(slot, RegDefs, RegUses);
178 insertDefsUses(slot, RegDefs, RegUses);
182 MachineBasicBlock::iterator I = slot;
185 done = (I == MBB.begin());
191 if (I->isDebugValue())
195 if (I->hasUnmodeledSideEffects()
199 || isDelayFiller(MBB, I))
202 if (delayHasHazard(I, sawLoad, sawStore, RegDefs, RegUses)) {
203 insertDefsUses(I, RegDefs, RegUses);
212 bool Filler::delayHasHazard(MachineBasicBlock::iterator candidate,
215 SmallSet<unsigned, 32> &RegDefs,
216 SmallSet<unsigned, 32> &RegUses)
219 if (candidate->isImplicitDef() || candidate->isKill())
222 if (candidate->mayLoad()) {
228 if (candidate->mayStore()) {
236 for (unsigned i = 0, e = candidate->getNumOperands(); i!= e; ++i) {
237 const MachineOperand &MO = candidate->getOperand(i);
241 unsigned Reg = MO.getReg();
244 // check whether Reg is defined or used before delay slot.
245 if (IsRegInSet(RegDefs, Reg) || IsRegInSet(RegUses, Reg))
249 // check whether Reg is defined before delay slot.
250 if (IsRegInSet(RegDefs, Reg))
258 void Filler::insertCallDefsUses(MachineBasicBlock::iterator MI,
259 SmallSet<unsigned, 32>& RegDefs,
260 SmallSet<unsigned, 32>& RegUses)
262 // Call defines o7, which is visible to the instruction in delay slot.
263 RegDefs.insert(SP::O7);
265 switch(MI->getOpcode()) {
266 default: llvm_unreachable("Unknown opcode.");
267 case SP::CALL: break;
270 assert(MI->getNumOperands() >= 2);
271 const MachineOperand &Reg = MI->getOperand(0);
272 assert(Reg.isReg() && "JMPL first operand is not a register.");
273 assert(Reg.isUse() && "JMPL first operand is not a use.");
274 RegUses.insert(Reg.getReg());
276 const MachineOperand &RegOrImm = MI->getOperand(1);
277 if (RegOrImm.isImm())
279 assert(RegOrImm.isReg() && "JMPLrr second operand is not a register.");
280 assert(RegOrImm.isUse() && "JMPLrr second operand is not a use.");
281 RegUses.insert(RegOrImm.getReg());
286 // Insert Defs and Uses of MI into the sets RegDefs and RegUses.
287 void Filler::insertDefsUses(MachineBasicBlock::iterator MI,
288 SmallSet<unsigned, 32>& RegDefs,
289 SmallSet<unsigned, 32>& RegUses)
291 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
292 const MachineOperand &MO = MI->getOperand(i);
296 unsigned Reg = MO.getReg();
302 // Implicit register uses of retl are return values and
303 // retl does not use them.
304 if (MO.isImplicit() && MI->getOpcode() == SP::RETL)
311 // returns true if the Reg or its alias is in the RegSet.
312 bool Filler::IsRegInSet(SmallSet<unsigned, 32>& RegSet, unsigned Reg)
314 // Check Reg and all aliased Registers.
315 for (MCRegAliasIterator AI(Reg, TM.getRegisterInfo(), true);
317 if (RegSet.count(*AI))
322 // return true if the candidate is a delay filler.
323 bool Filler::isDelayFiller(MachineBasicBlock &MBB,
324 MachineBasicBlock::iterator candidate)
326 if (candidate == MBB.begin())
328 if (candidate->getOpcode() == SP::UNIMP)
331 return candidate->hasDelaySlot();
334 bool Filler::needsUnimp(MachineBasicBlock::iterator I, unsigned &StructSize)
339 unsigned structSizeOpNum = 0;
340 switch (I->getOpcode()) {
341 default: llvm_unreachable("Unknown call opcode.");
342 case SP::CALL: structSizeOpNum = 1; break;
344 case SP::JMPLri: structSizeOpNum = 2; break;
347 const MachineOperand &MO = I->getOperand(structSizeOpNum);
350 StructSize = MO.getImm();
354 static bool combineRestoreADD(MachineBasicBlock::iterator RestoreMI,
355 MachineBasicBlock::iterator AddMI,
356 const TargetInstrInfo *TII)
358 // Before: add <op0>, <op1>, %i[0-7]
359 // restore %g0, %g0, %i[0-7]
361 // After : restore <op0>, <op1>, %o[0-7]
363 unsigned reg = AddMI->getOperand(0).getReg();
364 if (reg < SP::I0 || reg > SP::I7)
368 RestoreMI->eraseFromParent();
370 // Change ADD to RESTORE.
371 AddMI->setDesc(TII->get((AddMI->getOpcode() == SP::ADDrr)
375 // Map the destination register.
376 AddMI->getOperand(0).setReg(reg - SP::I0 + SP::O0);
381 static bool combineRestoreOR(MachineBasicBlock::iterator RestoreMI,
382 MachineBasicBlock::iterator OrMI,
383 const TargetInstrInfo *TII)
385 // Before: or <op0>, <op1>, %i[0-7]
386 // restore %g0, %g0, %i[0-7]
387 // and <op0> or <op1> is zero,
389 // After : restore <op0>, <op1>, %o[0-7]
391 unsigned reg = OrMI->getOperand(0).getReg();
392 if (reg < SP::I0 || reg > SP::I7)
395 // check whether it is a copy.
396 if (OrMI->getOpcode() == SP::ORrr
397 && OrMI->getOperand(1).getReg() != SP::G0
398 && OrMI->getOperand(2).getReg() != SP::G0)
401 if (OrMI->getOpcode() == SP::ORri
402 && OrMI->getOperand(1).getReg() != SP::G0
403 && (!OrMI->getOperand(2).isImm() || OrMI->getOperand(2).getImm() != 0))
407 RestoreMI->eraseFromParent();
409 // Change OR to RESTORE.
410 OrMI->setDesc(TII->get((OrMI->getOpcode() == SP::ORrr)
414 // Map the destination register.
415 OrMI->getOperand(0).setReg(reg - SP::I0 + SP::O0);
420 static bool combineRestoreSETHIi(MachineBasicBlock::iterator RestoreMI,
421 MachineBasicBlock::iterator SetHiMI,
422 const TargetInstrInfo *TII)
424 // Before: sethi imm3, %i[0-7]
425 // restore %g0, %g0, %g0
427 // After : restore %g0, (imm3<<10), %o[0-7]
429 unsigned reg = SetHiMI->getOperand(0).getReg();
430 if (reg < SP::I0 || reg > SP::I7)
433 if (!SetHiMI->getOperand(1).isImm())
436 int64_t imm = SetHiMI->getOperand(1).getImm();
438 // Is it a 3 bit immediate?
442 // Make it a 13 bit immediate.
443 imm = (imm << 10) & 0x1FFF;
445 assert(RestoreMI->getOpcode() == SP::RESTORErr);
447 RestoreMI->setDesc(TII->get(SP::RESTOREri));
449 RestoreMI->getOperand(0).setReg(reg - SP::I0 + SP::O0);
450 RestoreMI->getOperand(1).setReg(SP::G0);
451 RestoreMI->getOperand(2).ChangeToImmediate(imm);
454 // Erase the original SETHI.
455 SetHiMI->eraseFromParent();
460 bool Filler::tryCombineRestoreWithPrevInst(MachineBasicBlock &MBB,
461 MachineBasicBlock::iterator MBBI)
463 // No previous instruction.
464 if (MBBI == MBB.begin())
467 // assert that MBBI is a "restore %g0, %g0, %g0".
468 assert(MBBI->getOpcode() == SP::RESTORErr
469 && MBBI->getOperand(0).getReg() == SP::G0
470 && MBBI->getOperand(1).getReg() == SP::G0
471 && MBBI->getOperand(2).getReg() == SP::G0);
473 MachineBasicBlock::iterator PrevInst = MBBI; --PrevInst;
475 // It cannot combine with a delay filler.
476 if (isDelayFiller(MBB, PrevInst))
479 switch (PrevInst->getOpcode()) {
482 case SP::ADDri: return combineRestoreADD(MBBI, PrevInst, TII); break;
484 case SP::ORri: return combineRestoreOR(MBBI, PrevInst, TII); break;
485 case SP::SETHIi: return combineRestoreSETHIi(MBBI, PrevInst, TII); break;
487 // It cannot combine with the previous instruction.