1 //===-- SparcAsmParser.cpp - Parse Sparc assembly to MCInst instructions --===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/SparcMCTargetDesc.h"
11 #include "MCTargetDesc/SparcMCExpr.h"
12 #include "llvm/ADT/STLExtras.h"
13 #include "llvm/MC/MCContext.h"
14 #include "llvm/MC/MCInst.h"
15 #include "llvm/MC/MCObjectFileInfo.h"
16 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
17 #include "llvm/MC/MCStreamer.h"
18 #include "llvm/MC/MCSubtargetInfo.h"
19 #include "llvm/MC/MCSymbol.h"
20 #include "llvm/MC/MCTargetAsmParser.h"
21 #include "llvm/Support/TargetRegistry.h"
25 // The generated AsmMatcher SparcGenAsmMatcher uses "Sparc" as the target
26 // namespace. But SPARC backend uses "SP" as its namespace.
35 class SparcAsmParser : public MCTargetAsmParser {
40 /// @name Auto-generated Match Functions
43 #define GET_ASSEMBLER_HEADER
44 #include "SparcGenAsmMatcher.inc"
48 // public interface of the MCTargetAsmParser.
49 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
50 OperandVector &Operands, MCStreamer &Out,
52 bool MatchingInlineAsm) override;
53 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
54 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
55 SMLoc NameLoc, OperandVector &Operands) override;
56 bool ParseDirective(AsmToken DirectiveID) override;
58 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
59 unsigned Kind) override;
61 // Custom parse functions for Sparc specific operands.
62 OperandMatchResultTy parseMEMOperand(OperandVector &Operands);
64 OperandMatchResultTy parseOperand(OperandVector &Operands, StringRef Name);
67 parseSparcAsmOperand(std::unique_ptr<SparcOperand> &Operand,
70 OperandMatchResultTy parseBranchModifiers(OperandVector &Operands);
72 // returns true if Tok is matched to a register and returns register in RegNo.
73 bool matchRegisterName(const AsmToken &Tok, unsigned &RegNo,
76 bool matchSparcAsmModifiers(const MCExpr *&EVal, SMLoc &EndLoc);
77 bool parseDirectiveWord(unsigned Size, SMLoc L);
79 bool is64Bit() const { return STI.getTargetTriple().startswith("sparcv9"); }
81 SparcAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser,
82 const MCInstrInfo &MII,
83 const MCTargetOptions &Options)
84 : MCTargetAsmParser(), STI(sti), Parser(parser) {
85 // Initialize the set of available features.
86 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
91 static unsigned IntRegs[32] = {
92 Sparc::G0, Sparc::G1, Sparc::G2, Sparc::G3,
93 Sparc::G4, Sparc::G5, Sparc::G6, Sparc::G7,
94 Sparc::O0, Sparc::O1, Sparc::O2, Sparc::O3,
95 Sparc::O4, Sparc::O5, Sparc::O6, Sparc::O7,
96 Sparc::L0, Sparc::L1, Sparc::L2, Sparc::L3,
97 Sparc::L4, Sparc::L5, Sparc::L6, Sparc::L7,
98 Sparc::I0, Sparc::I1, Sparc::I2, Sparc::I3,
99 Sparc::I4, Sparc::I5, Sparc::I6, Sparc::I7 };
101 static unsigned FloatRegs[32] = {
102 Sparc::F0, Sparc::F1, Sparc::F2, Sparc::F3,
103 Sparc::F4, Sparc::F5, Sparc::F6, Sparc::F7,
104 Sparc::F8, Sparc::F9, Sparc::F10, Sparc::F11,
105 Sparc::F12, Sparc::F13, Sparc::F14, Sparc::F15,
106 Sparc::F16, Sparc::F17, Sparc::F18, Sparc::F19,
107 Sparc::F20, Sparc::F21, Sparc::F22, Sparc::F23,
108 Sparc::F24, Sparc::F25, Sparc::F26, Sparc::F27,
109 Sparc::F28, Sparc::F29, Sparc::F30, Sparc::F31 };
111 static unsigned DoubleRegs[32] = {
112 Sparc::D0, Sparc::D1, Sparc::D2, Sparc::D3,
113 Sparc::D4, Sparc::D5, Sparc::D6, Sparc::D7,
114 Sparc::D8, Sparc::D7, Sparc::D8, Sparc::D9,
115 Sparc::D12, Sparc::D13, Sparc::D14, Sparc::D15,
116 Sparc::D16, Sparc::D17, Sparc::D18, Sparc::D19,
117 Sparc::D20, Sparc::D21, Sparc::D22, Sparc::D23,
118 Sparc::D24, Sparc::D25, Sparc::D26, Sparc::D27,
119 Sparc::D28, Sparc::D29, Sparc::D30, Sparc::D31 };
121 static unsigned QuadFPRegs[32] = {
122 Sparc::Q0, Sparc::Q1, Sparc::Q2, Sparc::Q3,
123 Sparc::Q4, Sparc::Q5, Sparc::Q6, Sparc::Q7,
124 Sparc::Q8, Sparc::Q9, Sparc::Q10, Sparc::Q11,
125 Sparc::Q12, Sparc::Q13, Sparc::Q14, Sparc::Q15 };
127 static unsigned ASRRegs[32] = {
128 SP::Y, SP::ASR1, SP::ASR2, SP::ASR3,
129 SP::ASR4, SP::ASR5, SP::ASR6, SP::ASR7,
130 SP::ASR8, SP::ASR9, SP::ASR10, SP::ASR11,
131 SP::ASR12, SP::ASR13, SP::ASR14, SP::ASR15,
132 SP::ASR16, SP::ASR17, SP::ASR18, SP::ASR19,
133 SP::ASR20, SP::ASR21, SP::ASR22, SP::ASR23,
134 SP::ASR24, SP::ASR25, SP::ASR26, SP::ASR27,
135 SP::ASR28, SP::ASR29, SP::ASR30, SP::ASR31};
137 /// SparcOperand - Instances of this class represent a parsed Sparc machine
139 class SparcOperand : public MCParsedAsmOperand {
159 SMLoc StartLoc, EndLoc;
188 SparcOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
190 bool isToken() const override { return Kind == k_Token; }
191 bool isReg() const override { return Kind == k_Register; }
192 bool isImm() const override { return Kind == k_Immediate; }
193 bool isMem() const override { return isMEMrr() || isMEMri(); }
194 bool isMEMrr() const { return Kind == k_MemoryReg; }
195 bool isMEMri() const { return Kind == k_MemoryImm; }
197 bool isFloatReg() const {
198 return (Kind == k_Register && Reg.Kind == rk_FloatReg);
201 bool isFloatOrDoubleReg() const {
202 return (Kind == k_Register && (Reg.Kind == rk_FloatReg
203 || Reg.Kind == rk_DoubleReg));
207 StringRef getToken() const {
208 assert(Kind == k_Token && "Invalid access!");
209 return StringRef(Tok.Data, Tok.Length);
212 unsigned getReg() const override {
213 assert((Kind == k_Register) && "Invalid access!");
217 const MCExpr *getImm() const {
218 assert((Kind == k_Immediate) && "Invalid access!");
222 unsigned getMemBase() const {
223 assert((Kind == k_MemoryReg || Kind == k_MemoryImm) && "Invalid access!");
227 unsigned getMemOffsetReg() const {
228 assert((Kind == k_MemoryReg) && "Invalid access!");
229 return Mem.OffsetReg;
232 const MCExpr *getMemOff() const {
233 assert((Kind == k_MemoryImm) && "Invalid access!");
237 /// getStartLoc - Get the location of the first token of this operand.
238 SMLoc getStartLoc() const override {
241 /// getEndLoc - Get the location of the last token of this operand.
242 SMLoc getEndLoc() const override {
246 void print(raw_ostream &OS) const override {
248 case k_Token: OS << "Token: " << getToken() << "\n"; break;
249 case k_Register: OS << "Reg: #" << getReg() << "\n"; break;
250 case k_Immediate: OS << "Imm: " << getImm() << "\n"; break;
251 case k_MemoryReg: OS << "Mem: " << getMemBase() << "+"
252 << getMemOffsetReg() << "\n"; break;
253 case k_MemoryImm: assert(getMemOff() != nullptr);
254 OS << "Mem: " << getMemBase()
255 << "+" << *getMemOff()
260 void addRegOperands(MCInst &Inst, unsigned N) const {
261 assert(N == 1 && "Invalid number of operands!");
262 Inst.addOperand(MCOperand::createReg(getReg()));
265 void addImmOperands(MCInst &Inst, unsigned N) const {
266 assert(N == 1 && "Invalid number of operands!");
267 const MCExpr *Expr = getImm();
271 void addExpr(MCInst &Inst, const MCExpr *Expr) const{
272 // Add as immediate when possible. Null MCExpr = 0.
274 Inst.addOperand(MCOperand::createImm(0));
275 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
276 Inst.addOperand(MCOperand::createImm(CE->getValue()));
278 Inst.addOperand(MCOperand::createExpr(Expr));
281 void addMEMrrOperands(MCInst &Inst, unsigned N) const {
282 assert(N == 2 && "Invalid number of operands!");
284 Inst.addOperand(MCOperand::createReg(getMemBase()));
286 assert(getMemOffsetReg() != 0 && "Invalid offset");
287 Inst.addOperand(MCOperand::createReg(getMemOffsetReg()));
290 void addMEMriOperands(MCInst &Inst, unsigned N) const {
291 assert(N == 2 && "Invalid number of operands!");
293 Inst.addOperand(MCOperand::createReg(getMemBase()));
295 const MCExpr *Expr = getMemOff();
299 static std::unique_ptr<SparcOperand> CreateToken(StringRef Str, SMLoc S) {
300 auto Op = make_unique<SparcOperand>(k_Token);
301 Op->Tok.Data = Str.data();
302 Op->Tok.Length = Str.size();
308 static std::unique_ptr<SparcOperand> CreateReg(unsigned RegNum, unsigned Kind,
310 auto Op = make_unique<SparcOperand>(k_Register);
311 Op->Reg.RegNum = RegNum;
312 Op->Reg.Kind = (SparcOperand::RegisterKind)Kind;
318 static std::unique_ptr<SparcOperand> CreateImm(const MCExpr *Val, SMLoc S,
320 auto Op = make_unique<SparcOperand>(k_Immediate);
327 static bool MorphToDoubleReg(SparcOperand &Op) {
328 unsigned Reg = Op.getReg();
329 assert(Op.Reg.Kind == rk_FloatReg);
330 unsigned regIdx = Reg - Sparc::F0;
331 if (regIdx % 2 || regIdx > 31)
333 Op.Reg.RegNum = DoubleRegs[regIdx / 2];
334 Op.Reg.Kind = rk_DoubleReg;
338 static bool MorphToQuadReg(SparcOperand &Op) {
339 unsigned Reg = Op.getReg();
341 switch (Op.Reg.Kind) {
342 default: llvm_unreachable("Unexpected register kind!");
344 regIdx = Reg - Sparc::F0;
345 if (regIdx % 4 || regIdx > 31)
347 Reg = QuadFPRegs[regIdx / 4];
350 regIdx = Reg - Sparc::D0;
351 if (regIdx % 2 || regIdx > 31)
353 Reg = QuadFPRegs[regIdx / 2];
357 Op.Reg.Kind = rk_QuadReg;
361 static std::unique_ptr<SparcOperand>
362 MorphToMEMrr(unsigned Base, std::unique_ptr<SparcOperand> Op) {
363 unsigned offsetReg = Op->getReg();
364 Op->Kind = k_MemoryReg;
366 Op->Mem.OffsetReg = offsetReg;
367 Op->Mem.Off = nullptr;
371 static std::unique_ptr<SparcOperand>
372 CreateMEMr(unsigned Base, SMLoc S, SMLoc E) {
373 auto Op = make_unique<SparcOperand>(k_MemoryReg);
375 Op->Mem.OffsetReg = Sparc::G0; // always 0
376 Op->Mem.Off = nullptr;
382 static std::unique_ptr<SparcOperand>
383 MorphToMEMri(unsigned Base, std::unique_ptr<SparcOperand> Op) {
384 const MCExpr *Imm = Op->getImm();
385 Op->Kind = k_MemoryImm;
387 Op->Mem.OffsetReg = 0;
395 bool SparcAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
396 OperandVector &Operands,
399 bool MatchingInlineAsm) {
401 SmallVector<MCInst, 8> Instructions;
402 unsigned MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
404 switch (MatchResult) {
405 case Match_Success: {
407 Out.EmitInstruction(Inst, STI);
411 case Match_MissingFeature:
413 "instruction requires a CPU feature not currently enabled");
415 case Match_InvalidOperand: {
416 SMLoc ErrorLoc = IDLoc;
417 if (ErrorInfo != ~0ULL) {
418 if (ErrorInfo >= Operands.size())
419 return Error(IDLoc, "too few operands for instruction");
421 ErrorLoc = ((SparcOperand &)*Operands[ErrorInfo]).getStartLoc();
422 if (ErrorLoc == SMLoc())
426 return Error(ErrorLoc, "invalid operand for instruction");
428 case Match_MnemonicFail:
429 return Error(IDLoc, "invalid instruction mnemonic");
431 llvm_unreachable("Implement any new match types added!");
434 bool SparcAsmParser::
435 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc)
437 const AsmToken &Tok = Parser.getTok();
438 StartLoc = Tok.getLoc();
439 EndLoc = Tok.getEndLoc();
441 if (getLexer().getKind() != AsmToken::Percent)
444 unsigned regKind = SparcOperand::rk_None;
445 if (matchRegisterName(Tok, RegNo, regKind)) {
450 return Error(StartLoc, "invalid register name");
453 static void applyMnemonicAliases(StringRef &Mnemonic, uint64_t Features,
456 bool SparcAsmParser::ParseInstruction(ParseInstructionInfo &Info,
457 StringRef Name, SMLoc NameLoc,
458 OperandVector &Operands) {
460 // First operand in MCInst is instruction mnemonic.
461 Operands.push_back(SparcOperand::CreateToken(Name, NameLoc));
463 // apply mnemonic aliases, if any, so that we can parse operands correctly.
464 applyMnemonicAliases(Name, getAvailableFeatures(), 0);
466 if (getLexer().isNot(AsmToken::EndOfStatement)) {
467 // Read the first operand.
468 if (getLexer().is(AsmToken::Comma)) {
469 if (parseBranchModifiers(Operands) != MatchOperand_Success) {
470 SMLoc Loc = getLexer().getLoc();
471 Parser.eatToEndOfStatement();
472 return Error(Loc, "unexpected token");
475 if (parseOperand(Operands, Name) != MatchOperand_Success) {
476 SMLoc Loc = getLexer().getLoc();
477 Parser.eatToEndOfStatement();
478 return Error(Loc, "unexpected token");
481 while (getLexer().is(AsmToken::Comma)) {
482 Parser.Lex(); // Eat the comma.
483 // Parse and remember the operand.
484 if (parseOperand(Operands, Name) != MatchOperand_Success) {
485 SMLoc Loc = getLexer().getLoc();
486 Parser.eatToEndOfStatement();
487 return Error(Loc, "unexpected token");
491 if (getLexer().isNot(AsmToken::EndOfStatement)) {
492 SMLoc Loc = getLexer().getLoc();
493 Parser.eatToEndOfStatement();
494 return Error(Loc, "unexpected token");
496 Parser.Lex(); // Consume the EndOfStatement.
500 bool SparcAsmParser::
501 ParseDirective(AsmToken DirectiveID)
503 StringRef IDVal = DirectiveID.getString();
505 if (IDVal == ".byte")
506 return parseDirectiveWord(1, DirectiveID.getLoc());
508 if (IDVal == ".half")
509 return parseDirectiveWord(2, DirectiveID.getLoc());
511 if (IDVal == ".word")
512 return parseDirectiveWord(4, DirectiveID.getLoc());
514 if (IDVal == ".nword")
515 return parseDirectiveWord(is64Bit() ? 8 : 4, DirectiveID.getLoc());
517 if (is64Bit() && IDVal == ".xword")
518 return parseDirectiveWord(8, DirectiveID.getLoc());
520 if (IDVal == ".register") {
521 // For now, ignore .register directive.
522 Parser.eatToEndOfStatement();
526 // Let the MC layer to handle other directives.
530 bool SparcAsmParser:: parseDirectiveWord(unsigned Size, SMLoc L) {
531 if (getLexer().isNot(AsmToken::EndOfStatement)) {
534 if (getParser().parseExpression(Value))
537 getParser().getStreamer().EmitValue(Value, Size);
539 if (getLexer().is(AsmToken::EndOfStatement))
542 // FIXME: Improve diagnostic.
543 if (getLexer().isNot(AsmToken::Comma))
544 return Error(L, "unexpected token in directive");
552 SparcAsmParser::OperandMatchResultTy
553 SparcAsmParser::parseMEMOperand(OperandVector &Operands) {
556 unsigned BaseReg = 0;
558 if (ParseRegister(BaseReg, S, E)) {
559 return MatchOperand_NoMatch;
562 switch (getLexer().getKind()) {
563 default: return MatchOperand_NoMatch;
565 case AsmToken::Comma:
566 case AsmToken::RBrac:
567 case AsmToken::EndOfStatement:
568 Operands.push_back(SparcOperand::CreateMEMr(BaseReg, S, E));
569 return MatchOperand_Success;
571 case AsmToken:: Plus:
572 Parser.Lex(); // Eat the '+'
574 case AsmToken::Minus:
578 std::unique_ptr<SparcOperand> Offset;
579 OperandMatchResultTy ResTy = parseSparcAsmOperand(Offset);
580 if (ResTy != MatchOperand_Success || !Offset)
581 return MatchOperand_NoMatch;
584 Offset->isImm() ? SparcOperand::MorphToMEMri(BaseReg, std::move(Offset))
585 : SparcOperand::MorphToMEMrr(BaseReg, std::move(Offset)));
587 return MatchOperand_Success;
590 SparcAsmParser::OperandMatchResultTy
591 SparcAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {
593 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
595 // If there wasn't a custom match, try the generic matcher below. Otherwise,
596 // there was a match, but an error occurred, in which case, just return that
597 // the operand parsing failed.
598 if (ResTy == MatchOperand_Success || ResTy == MatchOperand_ParseFail)
601 if (getLexer().is(AsmToken::LBrac)) {
603 Operands.push_back(SparcOperand::CreateToken("[",
604 Parser.getTok().getLoc()));
605 Parser.Lex(); // Eat the [
607 if (Mnemonic == "cas" || Mnemonic == "casx") {
608 SMLoc S = Parser.getTok().getLoc();
609 if (getLexer().getKind() != AsmToken::Percent)
610 return MatchOperand_NoMatch;
611 Parser.Lex(); // eat %
613 unsigned RegNo, RegKind;
614 if (!matchRegisterName(Parser.getTok(), RegNo, RegKind))
615 return MatchOperand_NoMatch;
617 Parser.Lex(); // Eat the identifier token.
618 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer()-1);
619 Operands.push_back(SparcOperand::CreateReg(RegNo, RegKind, S, E));
620 ResTy = MatchOperand_Success;
622 ResTy = parseMEMOperand(Operands);
625 if (ResTy != MatchOperand_Success)
628 if (!getLexer().is(AsmToken::RBrac))
629 return MatchOperand_ParseFail;
631 Operands.push_back(SparcOperand::CreateToken("]",
632 Parser.getTok().getLoc()));
633 Parser.Lex(); // Eat the ]
635 // Parse an optional address-space identifier after the address.
636 if (getLexer().is(AsmToken::Integer)) {
637 std::unique_ptr<SparcOperand> Op;
638 ResTy = parseSparcAsmOperand(Op, false);
639 if (ResTy != MatchOperand_Success || !Op)
640 return MatchOperand_ParseFail;
641 Operands.push_back(std::move(Op));
643 return MatchOperand_Success;
646 std::unique_ptr<SparcOperand> Op;
648 ResTy = parseSparcAsmOperand(Op, (Mnemonic == "call"));
649 if (ResTy != MatchOperand_Success || !Op)
650 return MatchOperand_ParseFail;
652 // Push the parsed operand into the list of operands
653 Operands.push_back(std::move(Op));
655 return MatchOperand_Success;
658 SparcAsmParser::OperandMatchResultTy
659 SparcAsmParser::parseSparcAsmOperand(std::unique_ptr<SparcOperand> &Op,
662 SMLoc S = Parser.getTok().getLoc();
663 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
667 switch (getLexer().getKind()) {
670 case AsmToken::Percent:
671 Parser.Lex(); // Eat the '%'.
674 if (matchRegisterName(Parser.getTok(), RegNo, RegKind)) {
675 StringRef name = Parser.getTok().getString();
676 Parser.Lex(); // Eat the identifier token.
677 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
680 Op = SparcOperand::CreateReg(RegNo, RegKind, S, E);
683 Op = SparcOperand::CreateToken("%psr", S);
686 Op = SparcOperand::CreateToken("%wim", S);
689 Op = SparcOperand::CreateToken("%tbr", S);
693 Op = SparcOperand::CreateToken("%xcc", S);
695 Op = SparcOperand::CreateToken("%icc", S);
700 if (matchSparcAsmModifiers(EVal, E)) {
701 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
702 Op = SparcOperand::CreateImm(EVal, S, E);
706 case AsmToken::Minus:
707 case AsmToken::Integer:
708 case AsmToken::LParen:
709 if (!getParser().parseExpression(EVal, E))
710 Op = SparcOperand::CreateImm(EVal, S, E);
713 case AsmToken::Identifier: {
714 StringRef Identifier;
715 if (!getParser().parseIdentifier(Identifier)) {
716 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
717 MCSymbol *Sym = getContext().GetOrCreateSymbol(Identifier);
719 const MCExpr *Res = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_None,
722 getContext().getObjectFileInfo()->getRelocM() == Reloc::PIC_)
723 Res = SparcMCExpr::Create(SparcMCExpr::VK_Sparc_WPLT30, Res,
725 Op = SparcOperand::CreateImm(Res, S, E);
730 return (Op) ? MatchOperand_Success : MatchOperand_ParseFail;
733 SparcAsmParser::OperandMatchResultTy
734 SparcAsmParser::parseBranchModifiers(OperandVector &Operands) {
736 // parse (,a|,pn|,pt)+
738 while (getLexer().is(AsmToken::Comma)) {
740 Parser.Lex(); // Eat the comma
742 if (!getLexer().is(AsmToken::Identifier))
743 return MatchOperand_ParseFail;
744 StringRef modName = Parser.getTok().getString();
745 if (modName == "a" || modName == "pn" || modName == "pt") {
746 Operands.push_back(SparcOperand::CreateToken(modName,
747 Parser.getTok().getLoc()));
748 Parser.Lex(); // eat the identifier.
751 return MatchOperand_Success;
754 bool SparcAsmParser::matchRegisterName(const AsmToken &Tok,
760 RegKind = SparcOperand::rk_None;
761 if (Tok.is(AsmToken::Identifier)) {
762 StringRef name = Tok.getString();
765 if (name.equals("fp")) {
767 RegKind = SparcOperand::rk_IntReg;
771 if (name.equals("sp")) {
773 RegKind = SparcOperand::rk_IntReg;
777 if (name.equals("y")) {
779 RegKind = SparcOperand::rk_Special;
783 if (name.substr(0, 3).equals_lower("asr")
784 && !name.substr(3).getAsInteger(10, intVal)
785 && intVal > 0 && intVal < 32) {
786 RegNo = ASRRegs[intVal];
787 RegKind = SparcOperand::rk_Special;
791 if (name.equals("icc")) {
793 RegKind = SparcOperand::rk_Special;
797 if (name.equals("psr")) {
799 RegKind = SparcOperand::rk_Special;
803 if (name.equals("wim")) {
805 RegKind = SparcOperand::rk_Special;
809 if (name.equals("tbr")) {
811 RegKind = SparcOperand::rk_Special;
815 if (name.equals("xcc")) {
816 // FIXME:: check 64bit.
818 RegKind = SparcOperand::rk_Special;
823 if (name.substr(0, 3).equals_lower("fcc")
824 && !name.substr(3).getAsInteger(10, intVal)
826 // FIXME: check 64bit and handle %fcc1 - %fcc3
827 RegNo = Sparc::FCC0 + intVal;
828 RegKind = SparcOperand::rk_Special;
833 if (name.substr(0, 1).equals_lower("g")
834 && !name.substr(1).getAsInteger(10, intVal)
836 RegNo = IntRegs[intVal];
837 RegKind = SparcOperand::rk_IntReg;
841 if (name.substr(0, 1).equals_lower("o")
842 && !name.substr(1).getAsInteger(10, intVal)
844 RegNo = IntRegs[8 + intVal];
845 RegKind = SparcOperand::rk_IntReg;
848 if (name.substr(0, 1).equals_lower("l")
849 && !name.substr(1).getAsInteger(10, intVal)
851 RegNo = IntRegs[16 + intVal];
852 RegKind = SparcOperand::rk_IntReg;
855 if (name.substr(0, 1).equals_lower("i")
856 && !name.substr(1).getAsInteger(10, intVal)
858 RegNo = IntRegs[24 + intVal];
859 RegKind = SparcOperand::rk_IntReg;
863 if (name.substr(0, 1).equals_lower("f")
864 && !name.substr(1, 2).getAsInteger(10, intVal) && intVal < 32) {
865 RegNo = FloatRegs[intVal];
866 RegKind = SparcOperand::rk_FloatReg;
870 if (name.substr(0, 1).equals_lower("f")
871 && !name.substr(1, 2).getAsInteger(10, intVal)
872 && intVal >= 32 && intVal <= 62 && (intVal % 2 == 0)) {
874 RegNo = DoubleRegs[intVal/2];
875 RegKind = SparcOperand::rk_DoubleReg;
880 if (name.substr(0, 1).equals_lower("r")
881 && !name.substr(1, 2).getAsInteger(10, intVal) && intVal < 31) {
882 RegNo = IntRegs[intVal];
883 RegKind = SparcOperand::rk_IntReg;
890 static bool hasGOTReference(const MCExpr *Expr) {
891 switch (Expr->getKind()) {
893 if (const SparcMCExpr *SE = dyn_cast<SparcMCExpr>(Expr))
894 return hasGOTReference(SE->getSubExpr());
897 case MCExpr::Constant:
900 case MCExpr::Binary: {
901 const MCBinaryExpr *BE = cast<MCBinaryExpr>(Expr);
902 return hasGOTReference(BE->getLHS()) || hasGOTReference(BE->getRHS());
905 case MCExpr::SymbolRef: {
906 const MCSymbolRefExpr &SymRef = *cast<MCSymbolRefExpr>(Expr);
907 return (SymRef.getSymbol().getName() == "_GLOBAL_OFFSET_TABLE_");
911 return hasGOTReference(cast<MCUnaryExpr>(Expr)->getSubExpr());
916 bool SparcAsmParser::matchSparcAsmModifiers(const MCExpr *&EVal,
919 AsmToken Tok = Parser.getTok();
920 if (!Tok.is(AsmToken::Identifier))
923 StringRef name = Tok.getString();
925 SparcMCExpr::VariantKind VK = SparcMCExpr::parseVariantKind(name);
927 if (VK == SparcMCExpr::VK_Sparc_None)
930 Parser.Lex(); // Eat the identifier.
931 if (Parser.getTok().getKind() != AsmToken::LParen)
934 Parser.Lex(); // Eat the LParen token.
935 const MCExpr *subExpr;
936 if (Parser.parseParenExpression(subExpr, EndLoc))
939 bool isPIC = getContext().getObjectFileInfo()->getRelocM() == Reloc::PIC_;
943 case SparcMCExpr::VK_Sparc_LO:
944 VK = (hasGOTReference(subExpr)
945 ? SparcMCExpr::VK_Sparc_PC10
946 : (isPIC ? SparcMCExpr::VK_Sparc_GOT10 : VK));
948 case SparcMCExpr::VK_Sparc_HI:
949 VK = (hasGOTReference(subExpr)
950 ? SparcMCExpr::VK_Sparc_PC22
951 : (isPIC ? SparcMCExpr::VK_Sparc_GOT22 : VK));
955 EVal = SparcMCExpr::Create(VK, subExpr, getContext());
959 extern "C" void LLVMInitializeSparcAsmParser() {
960 RegisterMCAsmParser<SparcAsmParser> A(TheSparcTarget);
961 RegisterMCAsmParser<SparcAsmParser> B(TheSparcV9Target);
962 RegisterMCAsmParser<SparcAsmParser> C(TheSparcelTarget);
965 #define GET_REGISTER_MATCHER
966 #define GET_MATCHER_IMPLEMENTATION
967 #include "SparcGenAsmMatcher.inc"
969 unsigned SparcAsmParser::validateTargetOperandClass(MCParsedAsmOperand &GOp,
971 SparcOperand &Op = (SparcOperand &)GOp;
972 if (Op.isFloatOrDoubleReg()) {
976 if (!Op.isFloatReg() || SparcOperand::MorphToDoubleReg(Op))
977 return MCTargetAsmParser::Match_Success;
980 if (SparcOperand::MorphToQuadReg(Op))
981 return MCTargetAsmParser::Match_Success;
985 return Match_InvalidOperand;