1 //===-- SparcAsmParser.cpp - Parse Sparc assembly to MCInst instructions --===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/SparcMCTargetDesc.h"
11 #include "MCTargetDesc/SparcMCExpr.h"
12 #include "llvm/ADT/STLExtras.h"
13 #include "llvm/MC/MCContext.h"
14 #include "llvm/MC/MCInst.h"
15 #include "llvm/MC/MCObjectFileInfo.h"
16 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
17 #include "llvm/MC/MCStreamer.h"
18 #include "llvm/MC/MCSubtargetInfo.h"
19 #include "llvm/MC/MCSymbol.h"
20 #include "llvm/MC/MCTargetAsmParser.h"
21 #include "llvm/Support/TargetRegistry.h"
25 // The generated AsmMatcher SparcGenAsmMatcher uses "Sparc" as the target
26 // namespace. But SPARC backend uses "SP" as its namespace.
35 class SparcAsmParser : public MCTargetAsmParser {
40 /// @name Auto-generated Match Functions
43 #define GET_ASSEMBLER_HEADER
44 #include "SparcGenAsmMatcher.inc"
48 // public interface of the MCTargetAsmParser.
49 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
50 OperandVector &Operands, MCStreamer &Out,
52 FeatureBitset &ErrorMissingFeature,
53 bool MatchingInlineAsm) override;
54 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
55 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
56 SMLoc NameLoc, OperandVector &Operands) override;
57 bool ParseDirective(AsmToken DirectiveID) override;
59 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
60 unsigned Kind) override;
62 // Custom parse functions for Sparc specific operands.
63 OperandMatchResultTy parseMEMOperand(OperandVector &Operands);
65 OperandMatchResultTy parseOperand(OperandVector &Operands, StringRef Name);
68 parseSparcAsmOperand(std::unique_ptr<SparcOperand> &Operand,
71 OperandMatchResultTy parseBranchModifiers(OperandVector &Operands);
73 // returns true if Tok is matched to a register and returns register in RegNo.
74 bool matchRegisterName(const AsmToken &Tok, unsigned &RegNo,
77 bool matchSparcAsmModifiers(const MCExpr *&EVal, SMLoc &EndLoc);
78 bool parseDirectiveWord(unsigned Size, SMLoc L);
80 bool is64Bit() const {
81 return STI.getTargetTriple().getArchName().startswith("sparcv9");
84 void expandSET(MCInst &Inst, SMLoc IDLoc,
85 SmallVectorImpl<MCInst> &Instructions);
88 SparcAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser,
89 const MCInstrInfo &MII,
90 const MCTargetOptions &Options)
91 : MCTargetAsmParser(), STI(sti), Parser(parser) {
92 // Initialize the set of available features.
93 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
98 static unsigned IntRegs[32] = {
99 Sparc::G0, Sparc::G1, Sparc::G2, Sparc::G3,
100 Sparc::G4, Sparc::G5, Sparc::G6, Sparc::G7,
101 Sparc::O0, Sparc::O1, Sparc::O2, Sparc::O3,
102 Sparc::O4, Sparc::O5, Sparc::O6, Sparc::O7,
103 Sparc::L0, Sparc::L1, Sparc::L2, Sparc::L3,
104 Sparc::L4, Sparc::L5, Sparc::L6, Sparc::L7,
105 Sparc::I0, Sparc::I1, Sparc::I2, Sparc::I3,
106 Sparc::I4, Sparc::I5, Sparc::I6, Sparc::I7 };
108 static unsigned FloatRegs[32] = {
109 Sparc::F0, Sparc::F1, Sparc::F2, Sparc::F3,
110 Sparc::F4, Sparc::F5, Sparc::F6, Sparc::F7,
111 Sparc::F8, Sparc::F9, Sparc::F10, Sparc::F11,
112 Sparc::F12, Sparc::F13, Sparc::F14, Sparc::F15,
113 Sparc::F16, Sparc::F17, Sparc::F18, Sparc::F19,
114 Sparc::F20, Sparc::F21, Sparc::F22, Sparc::F23,
115 Sparc::F24, Sparc::F25, Sparc::F26, Sparc::F27,
116 Sparc::F28, Sparc::F29, Sparc::F30, Sparc::F31 };
118 static unsigned DoubleRegs[32] = {
119 Sparc::D0, Sparc::D1, Sparc::D2, Sparc::D3,
120 Sparc::D4, Sparc::D5, Sparc::D6, Sparc::D7,
121 Sparc::D8, Sparc::D7, Sparc::D8, Sparc::D9,
122 Sparc::D12, Sparc::D13, Sparc::D14, Sparc::D15,
123 Sparc::D16, Sparc::D17, Sparc::D18, Sparc::D19,
124 Sparc::D20, Sparc::D21, Sparc::D22, Sparc::D23,
125 Sparc::D24, Sparc::D25, Sparc::D26, Sparc::D27,
126 Sparc::D28, Sparc::D29, Sparc::D30, Sparc::D31 };
128 static unsigned QuadFPRegs[32] = {
129 Sparc::Q0, Sparc::Q1, Sparc::Q2, Sparc::Q3,
130 Sparc::Q4, Sparc::Q5, Sparc::Q6, Sparc::Q7,
131 Sparc::Q8, Sparc::Q9, Sparc::Q10, Sparc::Q11,
132 Sparc::Q12, Sparc::Q13, Sparc::Q14, Sparc::Q15 };
134 static unsigned ASRRegs[32] = {
135 SP::Y, SP::ASR1, SP::ASR2, SP::ASR3,
136 SP::ASR4, SP::ASR5, SP::ASR6, SP::ASR7,
137 SP::ASR8, SP::ASR9, SP::ASR10, SP::ASR11,
138 SP::ASR12, SP::ASR13, SP::ASR14, SP::ASR15,
139 SP::ASR16, SP::ASR17, SP::ASR18, SP::ASR19,
140 SP::ASR20, SP::ASR21, SP::ASR22, SP::ASR23,
141 SP::ASR24, SP::ASR25, SP::ASR26, SP::ASR27,
142 SP::ASR28, SP::ASR29, SP::ASR30, SP::ASR31};
144 /// SparcOperand - Instances of this class represent a parsed Sparc machine
146 class SparcOperand : public MCParsedAsmOperand {
166 SMLoc StartLoc, EndLoc;
195 SparcOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
197 bool isToken() const override { return Kind == k_Token; }
198 bool isReg() const override { return Kind == k_Register; }
199 bool isImm() const override { return Kind == k_Immediate; }
200 bool isMem() const override { return isMEMrr() || isMEMri(); }
201 bool isMEMrr() const { return Kind == k_MemoryReg; }
202 bool isMEMri() const { return Kind == k_MemoryImm; }
204 bool isFloatReg() const {
205 return (Kind == k_Register && Reg.Kind == rk_FloatReg);
208 bool isFloatOrDoubleReg() const {
209 return (Kind == k_Register && (Reg.Kind == rk_FloatReg
210 || Reg.Kind == rk_DoubleReg));
214 StringRef getToken() const {
215 assert(Kind == k_Token && "Invalid access!");
216 return StringRef(Tok.Data, Tok.Length);
219 unsigned getReg() const override {
220 assert((Kind == k_Register) && "Invalid access!");
224 const MCExpr *getImm() const {
225 assert((Kind == k_Immediate) && "Invalid access!");
229 unsigned getMemBase() const {
230 assert((Kind == k_MemoryReg || Kind == k_MemoryImm) && "Invalid access!");
234 unsigned getMemOffsetReg() const {
235 assert((Kind == k_MemoryReg) && "Invalid access!");
236 return Mem.OffsetReg;
239 const MCExpr *getMemOff() const {
240 assert((Kind == k_MemoryImm) && "Invalid access!");
244 /// getStartLoc - Get the location of the first token of this operand.
245 SMLoc getStartLoc() const override {
248 /// getEndLoc - Get the location of the last token of this operand.
249 SMLoc getEndLoc() const override {
253 void print(raw_ostream &OS) const override {
255 case k_Token: OS << "Token: " << getToken() << "\n"; break;
256 case k_Register: OS << "Reg: #" << getReg() << "\n"; break;
257 case k_Immediate: OS << "Imm: " << getImm() << "\n"; break;
258 case k_MemoryReg: OS << "Mem: " << getMemBase() << "+"
259 << getMemOffsetReg() << "\n"; break;
260 case k_MemoryImm: assert(getMemOff() != nullptr);
261 OS << "Mem: " << getMemBase()
262 << "+" << *getMemOff()
267 void addRegOperands(MCInst &Inst, unsigned N) const {
268 assert(N == 1 && "Invalid number of operands!");
269 Inst.addOperand(MCOperand::createReg(getReg()));
272 void addImmOperands(MCInst &Inst, unsigned N) const {
273 assert(N == 1 && "Invalid number of operands!");
274 const MCExpr *Expr = getImm();
278 void addExpr(MCInst &Inst, const MCExpr *Expr) const{
279 // Add as immediate when possible. Null MCExpr = 0.
281 Inst.addOperand(MCOperand::createImm(0));
282 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
283 Inst.addOperand(MCOperand::createImm(CE->getValue()));
285 Inst.addOperand(MCOperand::createExpr(Expr));
288 void addMEMrrOperands(MCInst &Inst, unsigned N) const {
289 assert(N == 2 && "Invalid number of operands!");
291 Inst.addOperand(MCOperand::createReg(getMemBase()));
293 assert(getMemOffsetReg() != 0 && "Invalid offset");
294 Inst.addOperand(MCOperand::createReg(getMemOffsetReg()));
297 void addMEMriOperands(MCInst &Inst, unsigned N) const {
298 assert(N == 2 && "Invalid number of operands!");
300 Inst.addOperand(MCOperand::createReg(getMemBase()));
302 const MCExpr *Expr = getMemOff();
306 static std::unique_ptr<SparcOperand> CreateToken(StringRef Str, SMLoc S) {
307 auto Op = make_unique<SparcOperand>(k_Token);
308 Op->Tok.Data = Str.data();
309 Op->Tok.Length = Str.size();
315 static std::unique_ptr<SparcOperand> CreateReg(unsigned RegNum, unsigned Kind,
317 auto Op = make_unique<SparcOperand>(k_Register);
318 Op->Reg.RegNum = RegNum;
319 Op->Reg.Kind = (SparcOperand::RegisterKind)Kind;
325 static std::unique_ptr<SparcOperand> CreateImm(const MCExpr *Val, SMLoc S,
327 auto Op = make_unique<SparcOperand>(k_Immediate);
334 static bool MorphToDoubleReg(SparcOperand &Op) {
335 unsigned Reg = Op.getReg();
336 assert(Op.Reg.Kind == rk_FloatReg);
337 unsigned regIdx = Reg - Sparc::F0;
338 if (regIdx % 2 || regIdx > 31)
340 Op.Reg.RegNum = DoubleRegs[regIdx / 2];
341 Op.Reg.Kind = rk_DoubleReg;
345 static bool MorphToQuadReg(SparcOperand &Op) {
346 unsigned Reg = Op.getReg();
348 switch (Op.Reg.Kind) {
349 default: llvm_unreachable("Unexpected register kind!");
351 regIdx = Reg - Sparc::F0;
352 if (regIdx % 4 || regIdx > 31)
354 Reg = QuadFPRegs[regIdx / 4];
357 regIdx = Reg - Sparc::D0;
358 if (regIdx % 2 || regIdx > 31)
360 Reg = QuadFPRegs[regIdx / 2];
364 Op.Reg.Kind = rk_QuadReg;
368 static std::unique_ptr<SparcOperand>
369 MorphToMEMrr(unsigned Base, std::unique_ptr<SparcOperand> Op) {
370 unsigned offsetReg = Op->getReg();
371 Op->Kind = k_MemoryReg;
373 Op->Mem.OffsetReg = offsetReg;
374 Op->Mem.Off = nullptr;
378 static std::unique_ptr<SparcOperand>
379 CreateMEMr(unsigned Base, SMLoc S, SMLoc E) {
380 auto Op = make_unique<SparcOperand>(k_MemoryReg);
382 Op->Mem.OffsetReg = Sparc::G0; // always 0
383 Op->Mem.Off = nullptr;
389 static std::unique_ptr<SparcOperand>
390 MorphToMEMri(unsigned Base, std::unique_ptr<SparcOperand> Op) {
391 const MCExpr *Imm = Op->getImm();
392 Op->Kind = k_MemoryImm;
394 Op->Mem.OffsetReg = 0;
402 void SparcAsmParser::expandSET(MCInst &Inst, SMLoc IDLoc,
403 SmallVectorImpl<MCInst> &Instructions) {
404 MCOperand MCRegOp = Inst.getOperand(0);
405 MCOperand MCValOp = Inst.getOperand(1);
406 assert(MCRegOp.isReg());
407 assert(MCValOp.isImm() || MCValOp.isExpr());
409 // the imm operand can be either an expression or an immediate.
410 bool IsImm = Inst.getOperand(1).isImm();
411 uint64_t ImmValue = IsImm ? MCValOp.getImm() : 0;
412 const MCExpr *ValExpr;
414 ValExpr = MCConstantExpr::create(ImmValue, getContext());
416 ValExpr = MCValOp.getExpr();
418 MCOperand PrevReg = MCOperand::createReg(Sparc::G0);
420 if (!IsImm || (ImmValue & ~0x1fff)) {
423 SparcMCExpr::create(SparcMCExpr::VK_Sparc_HI, ValExpr, getContext());
424 TmpInst.setLoc(IDLoc);
425 TmpInst.setOpcode(SP::SETHIi);
426 TmpInst.addOperand(MCRegOp);
427 TmpInst.addOperand(MCOperand::createExpr(Expr));
428 Instructions.push_back(TmpInst);
432 if (!IsImm || ((ImmValue & 0x1fff) != 0 || ImmValue == 0)) {
435 SparcMCExpr::create(SparcMCExpr::VK_Sparc_LO, ValExpr, getContext());
436 TmpInst.setLoc(IDLoc);
437 TmpInst.setOpcode(SP::ORri);
438 TmpInst.addOperand(MCRegOp);
439 TmpInst.addOperand(PrevReg);
440 TmpInst.addOperand(MCOperand::createExpr(Expr));
441 Instructions.push_back(TmpInst);
445 bool SparcAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
446 OperandVector &Operands,
449 FeatureBitset &ErrorMissingFeature,
450 bool MatchingInlineAsm) {
452 SmallVector<MCInst, 8> Instructions;
453 unsigned MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
456 switch (MatchResult) {
457 case Match_Success: {
458 switch (Inst.getOpcode()) {
461 Instructions.push_back(Inst);
464 expandSET(Inst, IDLoc, Instructions);
468 for (const MCInst &I : Instructions) {
469 Out.EmitInstruction(I, STI);
474 case Match_MissingFeature:
476 "instruction requires a CPU feature not currently enabled");
478 case Match_InvalidOperand: {
479 SMLoc ErrorLoc = IDLoc;
480 if (ErrorInfo != ~0ULL) {
481 if (ErrorInfo >= Operands.size())
482 return Error(IDLoc, "too few operands for instruction");
484 ErrorLoc = ((SparcOperand &)*Operands[ErrorInfo]).getStartLoc();
485 if (ErrorLoc == SMLoc())
489 return Error(ErrorLoc, "invalid operand for instruction");
491 case Match_MnemonicFail:
492 return Error(IDLoc, "invalid instruction mnemonic");
494 llvm_unreachable("Implement any new match types added!");
497 bool SparcAsmParser::
498 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc)
500 const AsmToken &Tok = Parser.getTok();
501 StartLoc = Tok.getLoc();
502 EndLoc = Tok.getEndLoc();
504 if (getLexer().getKind() != AsmToken::Percent)
507 unsigned regKind = SparcOperand::rk_None;
508 if (matchRegisterName(Tok, RegNo, regKind)) {
513 return Error(StartLoc, "invalid register name");
516 static void applyMnemonicAliases(StringRef &Mnemonic, FeatureBitset Features,
519 bool SparcAsmParser::ParseInstruction(ParseInstructionInfo &Info,
520 StringRef Name, SMLoc NameLoc,
521 OperandVector &Operands) {
523 // First operand in MCInst is instruction mnemonic.
524 Operands.push_back(SparcOperand::CreateToken(Name, NameLoc));
526 // apply mnemonic aliases, if any, so that we can parse operands correctly.
527 applyMnemonicAliases(Name, getAvailableFeatures(), 0);
529 if (getLexer().isNot(AsmToken::EndOfStatement)) {
530 // Read the first operand.
531 if (getLexer().is(AsmToken::Comma)) {
532 if (parseBranchModifiers(Operands) != MatchOperand_Success) {
533 SMLoc Loc = getLexer().getLoc();
534 Parser.eatToEndOfStatement();
535 return Error(Loc, "unexpected token");
538 if (parseOperand(Operands, Name) != MatchOperand_Success) {
539 SMLoc Loc = getLexer().getLoc();
540 Parser.eatToEndOfStatement();
541 return Error(Loc, "unexpected token");
544 while (getLexer().is(AsmToken::Comma)) {
545 Parser.Lex(); // Eat the comma.
546 // Parse and remember the operand.
547 if (parseOperand(Operands, Name) != MatchOperand_Success) {
548 SMLoc Loc = getLexer().getLoc();
549 Parser.eatToEndOfStatement();
550 return Error(Loc, "unexpected token");
554 if (getLexer().isNot(AsmToken::EndOfStatement)) {
555 SMLoc Loc = getLexer().getLoc();
556 Parser.eatToEndOfStatement();
557 return Error(Loc, "unexpected token");
559 Parser.Lex(); // Consume the EndOfStatement.
563 bool SparcAsmParser::
564 ParseDirective(AsmToken DirectiveID)
566 StringRef IDVal = DirectiveID.getString();
568 if (IDVal == ".byte")
569 return parseDirectiveWord(1, DirectiveID.getLoc());
571 if (IDVal == ".half")
572 return parseDirectiveWord(2, DirectiveID.getLoc());
574 if (IDVal == ".word")
575 return parseDirectiveWord(4, DirectiveID.getLoc());
577 if (IDVal == ".nword")
578 return parseDirectiveWord(is64Bit() ? 8 : 4, DirectiveID.getLoc());
580 if (is64Bit() && IDVal == ".xword")
581 return parseDirectiveWord(8, DirectiveID.getLoc());
583 if (IDVal == ".register") {
584 // For now, ignore .register directive.
585 Parser.eatToEndOfStatement();
589 // Let the MC layer to handle other directives.
593 bool SparcAsmParser:: parseDirectiveWord(unsigned Size, SMLoc L) {
594 if (getLexer().isNot(AsmToken::EndOfStatement)) {
597 if (getParser().parseExpression(Value))
600 getParser().getStreamer().EmitValue(Value, Size);
602 if (getLexer().is(AsmToken::EndOfStatement))
605 // FIXME: Improve diagnostic.
606 if (getLexer().isNot(AsmToken::Comma))
607 return Error(L, "unexpected token in directive");
615 SparcAsmParser::OperandMatchResultTy
616 SparcAsmParser::parseMEMOperand(OperandVector &Operands) {
619 unsigned BaseReg = 0;
621 if (ParseRegister(BaseReg, S, E)) {
622 return MatchOperand_NoMatch;
625 switch (getLexer().getKind()) {
626 default: return MatchOperand_NoMatch;
628 case AsmToken::Comma:
629 case AsmToken::RBrac:
630 case AsmToken::EndOfStatement:
631 Operands.push_back(SparcOperand::CreateMEMr(BaseReg, S, E));
632 return MatchOperand_Success;
634 case AsmToken:: Plus:
635 Parser.Lex(); // Eat the '+'
637 case AsmToken::Minus:
641 std::unique_ptr<SparcOperand> Offset;
642 OperandMatchResultTy ResTy = parseSparcAsmOperand(Offset);
643 if (ResTy != MatchOperand_Success || !Offset)
644 return MatchOperand_NoMatch;
647 Offset->isImm() ? SparcOperand::MorphToMEMri(BaseReg, std::move(Offset))
648 : SparcOperand::MorphToMEMrr(BaseReg, std::move(Offset)));
650 return MatchOperand_Success;
653 SparcAsmParser::OperandMatchResultTy
654 SparcAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {
656 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
658 // If there wasn't a custom match, try the generic matcher below. Otherwise,
659 // there was a match, but an error occurred, in which case, just return that
660 // the operand parsing failed.
661 if (ResTy == MatchOperand_Success || ResTy == MatchOperand_ParseFail)
664 if (getLexer().is(AsmToken::LBrac)) {
666 Operands.push_back(SparcOperand::CreateToken("[",
667 Parser.getTok().getLoc()));
668 Parser.Lex(); // Eat the [
670 if (Mnemonic == "cas" || Mnemonic == "casx") {
671 SMLoc S = Parser.getTok().getLoc();
672 if (getLexer().getKind() != AsmToken::Percent)
673 return MatchOperand_NoMatch;
674 Parser.Lex(); // eat %
676 unsigned RegNo, RegKind;
677 if (!matchRegisterName(Parser.getTok(), RegNo, RegKind))
678 return MatchOperand_NoMatch;
680 Parser.Lex(); // Eat the identifier token.
681 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer()-1);
682 Operands.push_back(SparcOperand::CreateReg(RegNo, RegKind, S, E));
683 ResTy = MatchOperand_Success;
685 ResTy = parseMEMOperand(Operands);
688 if (ResTy != MatchOperand_Success)
691 if (!getLexer().is(AsmToken::RBrac))
692 return MatchOperand_ParseFail;
694 Operands.push_back(SparcOperand::CreateToken("]",
695 Parser.getTok().getLoc()));
696 Parser.Lex(); // Eat the ]
698 // Parse an optional address-space identifier after the address.
699 if (getLexer().is(AsmToken::Integer)) {
700 std::unique_ptr<SparcOperand> Op;
701 ResTy = parseSparcAsmOperand(Op, false);
702 if (ResTy != MatchOperand_Success || !Op)
703 return MatchOperand_ParseFail;
704 Operands.push_back(std::move(Op));
706 return MatchOperand_Success;
709 std::unique_ptr<SparcOperand> Op;
711 ResTy = parseSparcAsmOperand(Op, (Mnemonic == "call"));
712 if (ResTy != MatchOperand_Success || !Op)
713 return MatchOperand_ParseFail;
715 // Push the parsed operand into the list of operands
716 Operands.push_back(std::move(Op));
718 return MatchOperand_Success;
721 SparcAsmParser::OperandMatchResultTy
722 SparcAsmParser::parseSparcAsmOperand(std::unique_ptr<SparcOperand> &Op,
725 SMLoc S = Parser.getTok().getLoc();
726 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
730 switch (getLexer().getKind()) {
733 case AsmToken::Percent:
734 Parser.Lex(); // Eat the '%'.
737 if (matchRegisterName(Parser.getTok(), RegNo, RegKind)) {
738 StringRef name = Parser.getTok().getString();
739 Parser.Lex(); // Eat the identifier token.
740 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
743 Op = SparcOperand::CreateReg(RegNo, RegKind, S, E);
746 Op = SparcOperand::CreateToken("%psr", S);
749 Op = SparcOperand::CreateToken("%wim", S);
752 Op = SparcOperand::CreateToken("%tbr", S);
756 Op = SparcOperand::CreateToken("%xcc", S);
758 Op = SparcOperand::CreateToken("%icc", S);
763 if (matchSparcAsmModifiers(EVal, E)) {
764 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
765 Op = SparcOperand::CreateImm(EVal, S, E);
769 case AsmToken::Minus:
770 case AsmToken::Integer:
771 case AsmToken::LParen:
772 if (!getParser().parseExpression(EVal, E))
773 Op = SparcOperand::CreateImm(EVal, S, E);
776 case AsmToken::Identifier: {
777 StringRef Identifier;
778 if (!getParser().parseIdentifier(Identifier)) {
779 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
780 MCSymbol *Sym = getContext().getOrCreateSymbol(Identifier);
782 const MCExpr *Res = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None,
785 getContext().getObjectFileInfo()->getRelocM() == Reloc::PIC_)
786 Res = SparcMCExpr::create(SparcMCExpr::VK_Sparc_WPLT30, Res,
788 Op = SparcOperand::CreateImm(Res, S, E);
793 return (Op) ? MatchOperand_Success : MatchOperand_ParseFail;
796 SparcAsmParser::OperandMatchResultTy
797 SparcAsmParser::parseBranchModifiers(OperandVector &Operands) {
799 // parse (,a|,pn|,pt)+
801 while (getLexer().is(AsmToken::Comma)) {
803 Parser.Lex(); // Eat the comma
805 if (!getLexer().is(AsmToken::Identifier))
806 return MatchOperand_ParseFail;
807 StringRef modName = Parser.getTok().getString();
808 if (modName == "a" || modName == "pn" || modName == "pt") {
809 Operands.push_back(SparcOperand::CreateToken(modName,
810 Parser.getTok().getLoc()));
811 Parser.Lex(); // eat the identifier.
814 return MatchOperand_Success;
817 bool SparcAsmParser::matchRegisterName(const AsmToken &Tok,
823 RegKind = SparcOperand::rk_None;
824 if (Tok.is(AsmToken::Identifier)) {
825 StringRef name = Tok.getString();
828 if (name.equals("fp")) {
830 RegKind = SparcOperand::rk_IntReg;
834 if (name.equals("sp")) {
836 RegKind = SparcOperand::rk_IntReg;
840 if (name.equals("y")) {
842 RegKind = SparcOperand::rk_Special;
846 if (name.substr(0, 3).equals_lower("asr")
847 && !name.substr(3).getAsInteger(10, intVal)
848 && intVal > 0 && intVal < 32) {
849 RegNo = ASRRegs[intVal];
850 RegKind = SparcOperand::rk_Special;
854 if (name.equals("icc")) {
856 RegKind = SparcOperand::rk_Special;
860 if (name.equals("psr")) {
862 RegKind = SparcOperand::rk_Special;
866 if (name.equals("wim")) {
868 RegKind = SparcOperand::rk_Special;
872 if (name.equals("tbr")) {
874 RegKind = SparcOperand::rk_Special;
878 if (name.equals("xcc")) {
879 // FIXME:: check 64bit.
881 RegKind = SparcOperand::rk_Special;
886 if (name.substr(0, 3).equals_lower("fcc")
887 && !name.substr(3).getAsInteger(10, intVal)
889 // FIXME: check 64bit and handle %fcc1 - %fcc3
890 RegNo = Sparc::FCC0 + intVal;
891 RegKind = SparcOperand::rk_Special;
896 if (name.substr(0, 1).equals_lower("g")
897 && !name.substr(1).getAsInteger(10, intVal)
899 RegNo = IntRegs[intVal];
900 RegKind = SparcOperand::rk_IntReg;
904 if (name.substr(0, 1).equals_lower("o")
905 && !name.substr(1).getAsInteger(10, intVal)
907 RegNo = IntRegs[8 + intVal];
908 RegKind = SparcOperand::rk_IntReg;
911 if (name.substr(0, 1).equals_lower("l")
912 && !name.substr(1).getAsInteger(10, intVal)
914 RegNo = IntRegs[16 + intVal];
915 RegKind = SparcOperand::rk_IntReg;
918 if (name.substr(0, 1).equals_lower("i")
919 && !name.substr(1).getAsInteger(10, intVal)
921 RegNo = IntRegs[24 + intVal];
922 RegKind = SparcOperand::rk_IntReg;
926 if (name.substr(0, 1).equals_lower("f")
927 && !name.substr(1, 2).getAsInteger(10, intVal) && intVal < 32) {
928 RegNo = FloatRegs[intVal];
929 RegKind = SparcOperand::rk_FloatReg;
933 if (name.substr(0, 1).equals_lower("f")
934 && !name.substr(1, 2).getAsInteger(10, intVal)
935 && intVal >= 32 && intVal <= 62 && (intVal % 2 == 0)) {
937 RegNo = DoubleRegs[intVal/2];
938 RegKind = SparcOperand::rk_DoubleReg;
943 if (name.substr(0, 1).equals_lower("r")
944 && !name.substr(1, 2).getAsInteger(10, intVal) && intVal < 31) {
945 RegNo = IntRegs[intVal];
946 RegKind = SparcOperand::rk_IntReg;
953 // Determine if an expression contains a reference to the symbol
954 // "_GLOBAL_OFFSET_TABLE_".
955 static bool hasGOTReference(const MCExpr *Expr) {
956 switch (Expr->getKind()) {
958 if (const SparcMCExpr *SE = dyn_cast<SparcMCExpr>(Expr))
959 return hasGOTReference(SE->getSubExpr());
962 case MCExpr::Constant:
965 case MCExpr::Binary: {
966 const MCBinaryExpr *BE = cast<MCBinaryExpr>(Expr);
967 return hasGOTReference(BE->getLHS()) || hasGOTReference(BE->getRHS());
970 case MCExpr::SymbolRef: {
971 const MCSymbolRefExpr &SymRef = *cast<MCSymbolRefExpr>(Expr);
972 return (SymRef.getSymbol().getName() == "_GLOBAL_OFFSET_TABLE_");
976 return hasGOTReference(cast<MCUnaryExpr>(Expr)->getSubExpr());
981 bool SparcAsmParser::matchSparcAsmModifiers(const MCExpr *&EVal,
984 AsmToken Tok = Parser.getTok();
985 if (!Tok.is(AsmToken::Identifier))
988 StringRef name = Tok.getString();
990 SparcMCExpr::VariantKind VK = SparcMCExpr::parseVariantKind(name);
992 if (VK == SparcMCExpr::VK_Sparc_None)
995 Parser.Lex(); // Eat the identifier.
996 if (Parser.getTok().getKind() != AsmToken::LParen)
999 Parser.Lex(); // Eat the LParen token.
1000 const MCExpr *subExpr;
1001 if (Parser.parseParenExpression(subExpr, EndLoc))
1004 bool isPIC = getContext().getObjectFileInfo()->getRelocM() == Reloc::PIC_;
1006 // Ugly: if a sparc assembly expression says "%hi(...)" but the
1007 // expression within contains _GLOBAL_OFFSET_TABLE_, it REALLY means
1008 // %pc22. Same with %lo -> %pc10. Worse, if it doesn't contain that,
1009 // the meaning depends on whether the assembler was invoked with
1010 // -KPIC or not: if so, it really means %got22/%got10; if not, it
1011 // actually means what it said! Sigh, historical mistakes...
1015 case SparcMCExpr::VK_Sparc_LO:
1016 VK = (hasGOTReference(subExpr)
1017 ? SparcMCExpr::VK_Sparc_PC10
1018 : (isPIC ? SparcMCExpr::VK_Sparc_GOT10 : VK));
1020 case SparcMCExpr::VK_Sparc_HI:
1021 VK = (hasGOTReference(subExpr)
1022 ? SparcMCExpr::VK_Sparc_PC22
1023 : (isPIC ? SparcMCExpr::VK_Sparc_GOT22 : VK));
1027 EVal = SparcMCExpr::create(VK, subExpr, getContext());
1031 extern "C" void LLVMInitializeSparcAsmParser() {
1032 RegisterMCAsmParser<SparcAsmParser> A(TheSparcTarget);
1033 RegisterMCAsmParser<SparcAsmParser> B(TheSparcV9Target);
1034 RegisterMCAsmParser<SparcAsmParser> C(TheSparcelTarget);
1037 #define GET_REGISTER_MATCHER
1038 #define GET_MATCHER_IMPLEMENTATION
1039 #include "SparcGenAsmMatcher.inc"
1041 unsigned SparcAsmParser::validateTargetOperandClass(MCParsedAsmOperand &GOp,
1043 SparcOperand &Op = (SparcOperand &)GOp;
1044 if (Op.isFloatOrDoubleReg()) {
1048 if (!Op.isFloatReg() || SparcOperand::MorphToDoubleReg(Op))
1049 return MCTargetAsmParser::Match_Success;
1052 if (SparcOperand::MorphToQuadReg(Op))
1053 return MCTargetAsmParser::Match_Success;
1057 return Match_InvalidOperand;