1 //===-- SIRegisterInfo.cpp - SI Register Information ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief SI implementation of the TargetRegisterInfo class.
13 //===----------------------------------------------------------------------===//
16 #include "SIRegisterInfo.h"
17 #include "AMDGPUSubtarget.h"
18 #include "SIInstrInfo.h"
19 #include "SIMachineFunctionInfo.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/RegisterScavenging.h"
23 #include "llvm/IR/Function.h"
24 #include "llvm/IR/LLVMContext.h"
28 SIRegisterInfo::SIRegisterInfo(const AMDGPUSubtarget &st)
29 : AMDGPURegisterInfo(st)
32 BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
33 BitVector Reserved(getNumRegs());
34 Reserved.set(AMDGPU::EXEC);
36 // EXEC_LO and EXEC_HI could be allocated and used as regular register,
37 // but this seems likely to result in bugs, so I'm marking them as reserved.
38 Reserved.set(AMDGPU::EXEC_LO);
39 Reserved.set(AMDGPU::EXEC_HI);
41 Reserved.set(AMDGPU::INDIRECT_BASE_ADDR);
42 Reserved.set(AMDGPU::FLAT_SCR);
44 // Reserve some VGPRs to use as temp registers in case we have to spill VGPRs
45 Reserved.set(AMDGPU::VGPR255);
46 Reserved.set(AMDGPU::VGPR254);
51 unsigned SIRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
52 MachineFunction &MF) const {
53 return RC->getNumRegs();
56 bool SIRegisterInfo::requiresRegisterScavenging(const MachineFunction &Fn) const {
57 return Fn.getFrameInfo()->hasStackObjects();
60 static unsigned getNumSubRegsForSpillOp(unsigned Op) {
63 case AMDGPU::SI_SPILL_S512_SAVE:
64 case AMDGPU::SI_SPILL_S512_RESTORE:
65 case AMDGPU::SI_SPILL_V512_SAVE:
66 case AMDGPU::SI_SPILL_V512_RESTORE:
68 case AMDGPU::SI_SPILL_S256_SAVE:
69 case AMDGPU::SI_SPILL_S256_RESTORE:
70 case AMDGPU::SI_SPILL_V256_SAVE:
71 case AMDGPU::SI_SPILL_V256_RESTORE:
73 case AMDGPU::SI_SPILL_S128_SAVE:
74 case AMDGPU::SI_SPILL_S128_RESTORE:
75 case AMDGPU::SI_SPILL_V128_SAVE:
76 case AMDGPU::SI_SPILL_V128_RESTORE:
78 case AMDGPU::SI_SPILL_V96_SAVE:
79 case AMDGPU::SI_SPILL_V96_RESTORE:
81 case AMDGPU::SI_SPILL_S64_SAVE:
82 case AMDGPU::SI_SPILL_S64_RESTORE:
83 case AMDGPU::SI_SPILL_V64_SAVE:
84 case AMDGPU::SI_SPILL_V64_RESTORE:
86 case AMDGPU::SI_SPILL_S32_SAVE:
87 case AMDGPU::SI_SPILL_S32_RESTORE:
88 case AMDGPU::SI_SPILL_V32_SAVE:
89 case AMDGPU::SI_SPILL_V32_RESTORE:
91 default: llvm_unreachable("Invalid spill opcode");
95 void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
96 int SPAdj, unsigned FIOperandNum,
97 RegScavenger *RS) const {
98 MachineFunction *MF = MI->getParent()->getParent();
99 MachineBasicBlock *MBB = MI->getParent();
100 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
101 MachineFrameInfo *FrameInfo = MF->getFrameInfo();
102 const SIInstrInfo *TII = static_cast<const SIInstrInfo*>(ST.getInstrInfo());
103 DebugLoc DL = MI->getDebugLoc();
105 MachineOperand &FIOp = MI->getOperand(FIOperandNum);
106 int Index = MI->getOperand(FIOperandNum).getIndex();
108 switch (MI->getOpcode()) {
109 // SGPR register spill
110 case AMDGPU::SI_SPILL_S512_SAVE:
111 case AMDGPU::SI_SPILL_S256_SAVE:
112 case AMDGPU::SI_SPILL_S128_SAVE:
113 case AMDGPU::SI_SPILL_S64_SAVE:
114 case AMDGPU::SI_SPILL_S32_SAVE: {
115 unsigned NumSubRegs = getNumSubRegsForSpillOp(MI->getOpcode());
117 for (unsigned i = 0, e = NumSubRegs; i < e; ++i) {
118 unsigned SubReg = getPhysRegSubReg(MI->getOperand(0).getReg(),
119 &AMDGPU::SGPR_32RegClass, i);
120 struct SIMachineFunctionInfo::SpilledReg Spill =
121 MFI->getSpilledReg(MF, Index, i);
123 if (Spill.VGPR == AMDGPU::NoRegister) {
124 LLVMContext &Ctx = MF->getFunction()->getContext();
125 Ctx.emitError("Ran out of VGPRs for spilling SGPR");
128 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_WRITELANE_B32), Spill.VGPR)
133 MI->eraseFromParent();
137 // SGPR register restore
138 case AMDGPU::SI_SPILL_S512_RESTORE:
139 case AMDGPU::SI_SPILL_S256_RESTORE:
140 case AMDGPU::SI_SPILL_S128_RESTORE:
141 case AMDGPU::SI_SPILL_S64_RESTORE:
142 case AMDGPU::SI_SPILL_S32_RESTORE: {
143 unsigned NumSubRegs = getNumSubRegsForSpillOp(MI->getOpcode());
145 for (unsigned i = 0, e = NumSubRegs; i < e; ++i) {
146 unsigned SubReg = getPhysRegSubReg(MI->getOperand(0).getReg(),
147 &AMDGPU::SGPR_32RegClass, i);
148 struct SIMachineFunctionInfo::SpilledReg Spill =
149 MFI->getSpilledReg(MF, Index, i);
151 if (Spill.VGPR == AMDGPU::NoRegister) {
152 LLVMContext &Ctx = MF->getFunction()->getContext();
153 Ctx.emitError("Ran out of VGPRs for spilling SGPR");
156 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_READLANE_B32), SubReg)
161 TII->insertNOPs(MI, 3);
162 MI->eraseFromParent();
166 // VGPR register spill
167 case AMDGPU::SI_SPILL_V512_SAVE:
168 case AMDGPU::SI_SPILL_V256_SAVE:
169 case AMDGPU::SI_SPILL_V128_SAVE:
170 case AMDGPU::SI_SPILL_V96_SAVE:
171 case AMDGPU::SI_SPILL_V64_SAVE:
172 case AMDGPU::SI_SPILL_V32_SAVE: {
173 unsigned NumSubRegs = getNumSubRegsForSpillOp(MI->getOpcode());
174 unsigned SrcReg = MI->getOperand(0).getReg();
175 int64_t Offset = FrameInfo->getObjectOffset(Index);
176 unsigned Size = NumSubRegs * 4;
177 unsigned TmpReg = RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, 0);
179 for (unsigned i = 0, e = NumSubRegs; i != e; ++i) {
180 unsigned SubReg = NumSubRegs > 1 ?
181 getPhysRegSubReg(SrcReg, &AMDGPU::VGPR_32RegClass, i) :
184 MFI->LDSWaveSpillSize = std::max((unsigned)Offset + 4, (unsigned)MFI->LDSWaveSpillSize);
186 unsigned AddrReg = TII->calculateLDSSpillAddress(*MBB, MI, RS, TmpReg,
189 if (AddrReg == AMDGPU::NoRegister) {
190 LLVMContext &Ctx = MF->getFunction()->getContext();
191 Ctx.emitError("Ran out of VGPRs for spilling VGPRS");
192 AddrReg = AMDGPU::VGPR0;
195 // Store the value in LDS
196 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::DS_WRITE_B32))
198 .addReg(AddrReg, RegState::Kill) // addr
199 .addReg(SubReg) // data0
200 .addImm(0); // offset
203 MI->eraseFromParent();
206 case AMDGPU::SI_SPILL_V32_RESTORE:
207 case AMDGPU::SI_SPILL_V64_RESTORE:
208 case AMDGPU::SI_SPILL_V128_RESTORE:
209 case AMDGPU::SI_SPILL_V256_RESTORE:
210 case AMDGPU::SI_SPILL_V512_RESTORE: {
211 unsigned NumSubRegs = getNumSubRegsForSpillOp(MI->getOpcode());
212 unsigned DstReg = MI->getOperand(0).getReg();
213 int64_t Offset = FrameInfo->getObjectOffset(Index);
214 unsigned Size = NumSubRegs * 4;
215 unsigned TmpReg = RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, 0);
217 // FIXME: We could use DS_READ_B64 here to optimize for larger registers.
218 for (unsigned i = 0, e = NumSubRegs; i != e; ++i) {
219 unsigned SubReg = NumSubRegs > 1 ?
220 getPhysRegSubReg(DstReg, &AMDGPU::VGPR_32RegClass, i) :
224 unsigned AddrReg = TII->calculateLDSSpillAddress(*MBB, MI, RS, TmpReg,
226 if (AddrReg == AMDGPU::NoRegister) {
227 LLVMContext &Ctx = MF->getFunction()->getContext();
228 Ctx.emitError("Ran out of VGPRs for spilling VGPRs");
229 AddrReg = AMDGPU::VGPR0;
232 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::DS_READ_B32), SubReg)
234 .addReg(AddrReg, RegState::Kill) // addr
237 MI->eraseFromParent();
242 int64_t Offset = FrameInfo->getObjectOffset(Index);
243 FIOp.ChangeToImmediate(Offset);
244 if (!TII->isImmOperandLegal(MI, FIOperandNum, FIOp)) {
245 unsigned TmpReg = RS->scavengeRegister(&AMDGPU::VReg_32RegClass, MI, SPAdj);
246 BuildMI(*MBB, MI, MI->getDebugLoc(),
247 TII->get(AMDGPU::V_MOV_B32_e32), TmpReg)
249 FIOp.ChangeToRegister(TmpReg, false);
255 const TargetRegisterClass * SIRegisterInfo::getCFGStructurizerRegClass(
257 switch(VT.SimpleTy) {
259 case MVT::i32: return &AMDGPU::VReg_32RegClass;
263 unsigned SIRegisterInfo::getHWRegIndex(unsigned Reg) const {
264 return getEncodingValue(Reg) & 0xff;
267 const TargetRegisterClass *SIRegisterInfo::getPhysRegClass(unsigned Reg) const {
268 assert(!TargetRegisterInfo::isVirtualRegister(Reg));
270 const TargetRegisterClass *BaseClasses[] = {
271 &AMDGPU::VReg_32RegClass,
272 &AMDGPU::SReg_32RegClass,
273 &AMDGPU::VReg_64RegClass,
274 &AMDGPU::SReg_64RegClass,
275 &AMDGPU::VReg_96RegClass,
276 &AMDGPU::VReg_128RegClass,
277 &AMDGPU::SReg_128RegClass,
278 &AMDGPU::VReg_256RegClass,
279 &AMDGPU::SReg_256RegClass,
280 &AMDGPU::VReg_512RegClass
283 for (const TargetRegisterClass *BaseClass : BaseClasses) {
284 if (BaseClass->contains(Reg)) {
291 bool SIRegisterInfo::isSGPRClass(const TargetRegisterClass *RC) const {
295 return !hasVGPRs(RC);
298 bool SIRegisterInfo::hasVGPRs(const TargetRegisterClass *RC) const {
299 return getCommonSubClass(&AMDGPU::VReg_32RegClass, RC) ||
300 getCommonSubClass(&AMDGPU::VReg_64RegClass, RC) ||
301 getCommonSubClass(&AMDGPU::VReg_96RegClass, RC) ||
302 getCommonSubClass(&AMDGPU::VReg_128RegClass, RC) ||
303 getCommonSubClass(&AMDGPU::VReg_256RegClass, RC) ||
304 getCommonSubClass(&AMDGPU::VReg_512RegClass, RC);
307 const TargetRegisterClass *SIRegisterInfo::getEquivalentVGPRClass(
308 const TargetRegisterClass *SRC) const {
311 } else if (SRC == &AMDGPU::SCCRegRegClass) {
312 return &AMDGPU::VCCRegRegClass;
313 } else if (getCommonSubClass(SRC, &AMDGPU::SGPR_32RegClass)) {
314 return &AMDGPU::VReg_32RegClass;
315 } else if (getCommonSubClass(SRC, &AMDGPU::SGPR_64RegClass)) {
316 return &AMDGPU::VReg_64RegClass;
317 } else if (getCommonSubClass(SRC, &AMDGPU::SReg_128RegClass)) {
318 return &AMDGPU::VReg_128RegClass;
319 } else if (getCommonSubClass(SRC, &AMDGPU::SReg_256RegClass)) {
320 return &AMDGPU::VReg_256RegClass;
321 } else if (getCommonSubClass(SRC, &AMDGPU::SReg_512RegClass)) {
322 return &AMDGPU::VReg_512RegClass;
327 const TargetRegisterClass *SIRegisterInfo::getSubRegClass(
328 const TargetRegisterClass *RC, unsigned SubIdx) const {
329 if (SubIdx == AMDGPU::NoSubRegister)
332 // If this register has a sub-register, we can safely assume it is a 32-bit
333 // register, because all of SI's sub-registers are 32-bit.
334 if (isSGPRClass(RC)) {
335 return &AMDGPU::SGPR_32RegClass;
337 return &AMDGPU::VGPR_32RegClass;
341 unsigned SIRegisterInfo::getPhysRegSubReg(unsigned Reg,
342 const TargetRegisterClass *SubRC,
343 unsigned Channel) const {
348 case 0: return AMDGPU::VCC_LO;
349 case 1: return AMDGPU::VCC_HI;
350 default: llvm_unreachable("Invalid SubIdx for VCC");
353 case AMDGPU::FLAT_SCR:
356 return AMDGPU::FLAT_SCR_LO;
358 return AMDGPU::FLAT_SCR_HI;
360 llvm_unreachable("Invalid SubIdx for FLAT_SCR");
367 return AMDGPU::EXEC_LO;
369 return AMDGPU::EXEC_HI;
371 llvm_unreachable("Invalid SubIdx for EXEC");
376 const TargetRegisterClass *RC = getPhysRegClass(Reg);
377 // 32-bit registers don't have sub-registers, so we can just return the
378 // Reg. We need to have this check here, because the calculation below
379 // using getHWRegIndex() will fail with special 32-bit registers like
380 // VCC_LO, VCC_HI, EXEC_LO, EXEC_HI and M0.
381 if (RC->getSize() == 4) {
382 assert(Channel == 0);
386 unsigned Index = getHWRegIndex(Reg);
387 return SubRC->getRegister(Index + Channel);
390 bool SIRegisterInfo::regClassCanUseLiteralConstant(int RCID) const {
392 default: return false;
393 case AMDGPU::SSrc_32RegClassID:
394 case AMDGPU::SSrc_64RegClassID:
395 case AMDGPU::VSrc_32RegClassID:
396 case AMDGPU::VSrc_64RegClassID:
401 bool SIRegisterInfo::regClassCanUseLiteralConstant(
402 const TargetRegisterClass *RC) const {
403 return regClassCanUseLiteralConstant(RC->getID());
406 bool SIRegisterInfo::regClassCanUseInlineConstant(int RCID) const {
407 if (regClassCanUseLiteralConstant(RCID))
411 default: return false;
412 case AMDGPU::VCSrc_32RegClassID:
413 case AMDGPU::VCSrc_64RegClassID:
418 bool SIRegisterInfo::regClassCanUseInlineConstant(
419 const TargetRegisterClass *RC) const {
420 return regClassCanUseInlineConstant(RC->getID());
424 unsigned SIRegisterInfo::getPreloadedValue(const MachineFunction &MF,
425 enum PreloadedValue Value) const {
427 const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
429 case SIRegisterInfo::TGID_X:
430 return AMDGPU::SReg_32RegClass.getRegister(MFI->NumUserSGPRs + 0);
431 case SIRegisterInfo::TGID_Y:
432 return AMDGPU::SReg_32RegClass.getRegister(MFI->NumUserSGPRs + 1);
433 case SIRegisterInfo::TGID_Z:
434 return AMDGPU::SReg_32RegClass.getRegister(MFI->NumUserSGPRs + 2);
435 case SIRegisterInfo::SCRATCH_WAVE_OFFSET:
436 return AMDGPU::SReg_32RegClass.getRegister(MFI->NumUserSGPRs + 4);
437 case SIRegisterInfo::SCRATCH_PTR:
438 return AMDGPU::SGPR2_SGPR3;
439 case SIRegisterInfo::INPUT_PTR:
440 return AMDGPU::SGPR0_SGPR1;
441 case SIRegisterInfo::TIDIG_X:
442 return AMDGPU::VGPR0;
443 case SIRegisterInfo::TIDIG_Y:
444 return AMDGPU::VGPR1;
445 case SIRegisterInfo::TIDIG_Z:
446 return AMDGPU::VGPR2;
448 llvm_unreachable("unexpected preloaded value type");
451 /// \brief Returns a register that is not used at any point in the function.
452 /// If all registers are used, then this function will return
453 // AMDGPU::NoRegister.
454 unsigned SIRegisterInfo::findUnusedVGPR(const MachineRegisterInfo &MRI) const {
456 const TargetRegisterClass *RC = &AMDGPU::VGPR_32RegClass;
458 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
460 if (!MRI.isPhysRegUsed(*I))
463 return AMDGPU::NoRegister;