1 //===-- SIRegisterInfo.cpp - SI Register Information ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief SI implementation of the TargetRegisterInfo class.
13 //===----------------------------------------------------------------------===//
16 #include "SIRegisterInfo.h"
17 #include "AMDGPUSubtarget.h"
18 #include "SIInstrInfo.h"
19 #include "SIMachineFunctionInfo.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/RegisterScavenging.h"
23 #include "llvm/IR/Function.h"
24 #include "llvm/IR/LLVMContext.h"
28 SIRegisterInfo::SIRegisterInfo(const AMDGPUSubtarget &st)
29 : AMDGPURegisterInfo(st)
32 BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
33 BitVector Reserved(getNumRegs());
34 Reserved.set(AMDGPU::EXEC);
36 // EXEC_LO and EXEC_HI could be allocated and used as regular register,
37 // but this seems likely to result in bugs, so I'm marking them as reserved.
38 Reserved.set(AMDGPU::EXEC_LO);
39 Reserved.set(AMDGPU::EXEC_HI);
41 Reserved.set(AMDGPU::INDIRECT_BASE_ADDR);
42 Reserved.set(AMDGPU::FLAT_SCR);
43 Reserved.set(AMDGPU::FLAT_SCR_LO);
44 Reserved.set(AMDGPU::FLAT_SCR_HI);
46 // Reserve some VGPRs to use as temp registers in case we have to spill VGPRs
47 Reserved.set(AMDGPU::VGPR255);
48 Reserved.set(AMDGPU::VGPR254);
53 unsigned SIRegisterInfo::getRegPressureSetLimit(unsigned Idx) const {
55 // FIXME: We should adjust the max number of waves based on LDS size.
56 unsigned SGPRLimit = getNumSGPRsAllowed(ST.getMaxWavesPerCU());
57 unsigned VGPRLimit = getNumVGPRsAllowed(ST.getMaxWavesPerCU());
59 for (regclass_iterator I = regclass_begin(), E = regclass_end();
62 unsigned NumSubRegs = std::max((int)(*I)->getSize() / 4, 1);
65 if (isSGPRClass(*I)) {
66 Limit = SGPRLimit / NumSubRegs;
68 Limit = VGPRLimit / NumSubRegs;
71 const int *Sets = getRegClassPressureSets(*I);
73 for (unsigned i = 0; Sets[i] != -1; ++i) {
74 if (Sets[i] == (int)Idx)
81 bool SIRegisterInfo::requiresRegisterScavenging(const MachineFunction &Fn) const {
82 return Fn.getFrameInfo()->hasStackObjects();
85 static unsigned getNumSubRegsForSpillOp(unsigned Op) {
88 case AMDGPU::SI_SPILL_S512_SAVE:
89 case AMDGPU::SI_SPILL_S512_RESTORE:
90 case AMDGPU::SI_SPILL_V512_SAVE:
91 case AMDGPU::SI_SPILL_V512_RESTORE:
93 case AMDGPU::SI_SPILL_S256_SAVE:
94 case AMDGPU::SI_SPILL_S256_RESTORE:
95 case AMDGPU::SI_SPILL_V256_SAVE:
96 case AMDGPU::SI_SPILL_V256_RESTORE:
98 case AMDGPU::SI_SPILL_S128_SAVE:
99 case AMDGPU::SI_SPILL_S128_RESTORE:
100 case AMDGPU::SI_SPILL_V128_SAVE:
101 case AMDGPU::SI_SPILL_V128_RESTORE:
103 case AMDGPU::SI_SPILL_V96_SAVE:
104 case AMDGPU::SI_SPILL_V96_RESTORE:
106 case AMDGPU::SI_SPILL_S64_SAVE:
107 case AMDGPU::SI_SPILL_S64_RESTORE:
108 case AMDGPU::SI_SPILL_V64_SAVE:
109 case AMDGPU::SI_SPILL_V64_RESTORE:
111 case AMDGPU::SI_SPILL_S32_SAVE:
112 case AMDGPU::SI_SPILL_S32_RESTORE:
113 case AMDGPU::SI_SPILL_V32_SAVE:
114 case AMDGPU::SI_SPILL_V32_RESTORE:
116 default: llvm_unreachable("Invalid spill opcode");
120 void SIRegisterInfo::buildScratchLoadStore(MachineBasicBlock::iterator MI,
121 unsigned LoadStoreOp,
123 unsigned ScratchRsrcReg,
124 unsigned ScratchOffset,
126 RegScavenger *RS) const {
128 const SIInstrInfo *TII = static_cast<const SIInstrInfo*>(ST.getInstrInfo());
129 MachineBasicBlock *MBB = MI->getParent();
130 const MachineFunction *MF = MI->getParent()->getParent();
131 LLVMContext &Ctx = MF->getFunction()->getContext();
132 DebugLoc DL = MI->getDebugLoc();
133 bool IsLoad = TII->get(LoadStoreOp).mayLoad();
135 bool RanOutOfSGPRs = false;
136 unsigned SOffset = ScratchOffset;
138 unsigned NumSubRegs = getNumSubRegsForSpillOp(MI->getOpcode());
139 unsigned Size = NumSubRegs * 4;
141 if (!isUInt<12>(Offset + Size)) {
142 SOffset = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, MI, 0);
143 if (SOffset == AMDGPU::NoRegister) {
144 RanOutOfSGPRs = true;
145 SOffset = AMDGPU::SGPR0;
147 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_ADD_U32), SOffset)
148 .addReg(ScratchOffset)
154 Ctx.emitError("Ran out of SGPRs for spilling VGPRS");
156 for (unsigned i = 0, e = NumSubRegs; i != e; ++i, Offset += 4) {
157 unsigned SubReg = NumSubRegs > 1 ?
158 getPhysRegSubReg(Value, &AMDGPU::VGPR_32RegClass, i) :
160 bool IsKill = (i == e - 1);
162 BuildMI(*MBB, MI, DL, TII->get(LoadStoreOp))
163 .addReg(SubReg, getDefRegState(IsLoad))
164 .addReg(ScratchRsrcReg, getKillRegState(IsKill))
170 .addReg(Value, RegState::Implicit | getDefRegState(IsLoad));
174 void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
175 int SPAdj, unsigned FIOperandNum,
176 RegScavenger *RS) const {
177 MachineFunction *MF = MI->getParent()->getParent();
178 MachineBasicBlock *MBB = MI->getParent();
179 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
180 MachineFrameInfo *FrameInfo = MF->getFrameInfo();
181 const SIInstrInfo *TII = static_cast<const SIInstrInfo*>(ST.getInstrInfo());
182 DebugLoc DL = MI->getDebugLoc();
184 MachineOperand &FIOp = MI->getOperand(FIOperandNum);
185 int Index = MI->getOperand(FIOperandNum).getIndex();
187 switch (MI->getOpcode()) {
188 // SGPR register spill
189 case AMDGPU::SI_SPILL_S512_SAVE:
190 case AMDGPU::SI_SPILL_S256_SAVE:
191 case AMDGPU::SI_SPILL_S128_SAVE:
192 case AMDGPU::SI_SPILL_S64_SAVE:
193 case AMDGPU::SI_SPILL_S32_SAVE: {
194 unsigned NumSubRegs = getNumSubRegsForSpillOp(MI->getOpcode());
196 for (unsigned i = 0, e = NumSubRegs; i < e; ++i) {
197 unsigned SubReg = getPhysRegSubReg(MI->getOperand(0).getReg(),
198 &AMDGPU::SGPR_32RegClass, i);
199 struct SIMachineFunctionInfo::SpilledReg Spill =
200 MFI->getSpilledReg(MF, Index, i);
202 if (Spill.VGPR == AMDGPU::NoRegister) {
203 LLVMContext &Ctx = MF->getFunction()->getContext();
204 Ctx.emitError("Ran out of VGPRs for spilling SGPR");
207 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_WRITELANE_B32), Spill.VGPR)
212 MI->eraseFromParent();
216 // SGPR register restore
217 case AMDGPU::SI_SPILL_S512_RESTORE:
218 case AMDGPU::SI_SPILL_S256_RESTORE:
219 case AMDGPU::SI_SPILL_S128_RESTORE:
220 case AMDGPU::SI_SPILL_S64_RESTORE:
221 case AMDGPU::SI_SPILL_S32_RESTORE: {
222 unsigned NumSubRegs = getNumSubRegsForSpillOp(MI->getOpcode());
224 for (unsigned i = 0, e = NumSubRegs; i < e; ++i) {
225 unsigned SubReg = getPhysRegSubReg(MI->getOperand(0).getReg(),
226 &AMDGPU::SGPR_32RegClass, i);
227 bool isM0 = SubReg == AMDGPU::M0;
228 struct SIMachineFunctionInfo::SpilledReg Spill =
229 MFI->getSpilledReg(MF, Index, i);
231 if (Spill.VGPR == AMDGPU::NoRegister) {
232 LLVMContext &Ctx = MF->getFunction()->getContext();
233 Ctx.emitError("Ran out of VGPRs for spilling SGPR");
237 SubReg = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, MI, 0);
239 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_READLANE_B32), SubReg)
242 .addReg(MI->getOperand(0).getReg(), RegState::ImplicitDefine);
244 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
248 TII->insertNOPs(MI, 3);
249 MI->eraseFromParent();
253 // VGPR register spill
254 case AMDGPU::SI_SPILL_V512_SAVE:
255 case AMDGPU::SI_SPILL_V256_SAVE:
256 case AMDGPU::SI_SPILL_V128_SAVE:
257 case AMDGPU::SI_SPILL_V96_SAVE:
258 case AMDGPU::SI_SPILL_V64_SAVE:
259 case AMDGPU::SI_SPILL_V32_SAVE:
260 buildScratchLoadStore(MI, AMDGPU::BUFFER_STORE_DWORD_OFFSET,
261 TII->getNamedOperand(*MI, AMDGPU::OpName::src)->getReg(),
262 TII->getNamedOperand(*MI, AMDGPU::OpName::scratch_rsrc)->getReg(),
263 TII->getNamedOperand(*MI, AMDGPU::OpName::scratch_offset)->getReg(),
264 FrameInfo->getObjectOffset(Index), RS);
265 MI->eraseFromParent();
267 case AMDGPU::SI_SPILL_V32_RESTORE:
268 case AMDGPU::SI_SPILL_V64_RESTORE:
269 case AMDGPU::SI_SPILL_V96_RESTORE:
270 case AMDGPU::SI_SPILL_V128_RESTORE:
271 case AMDGPU::SI_SPILL_V256_RESTORE:
272 case AMDGPU::SI_SPILL_V512_RESTORE: {
273 buildScratchLoadStore(MI, AMDGPU::BUFFER_LOAD_DWORD_OFFSET,
274 TII->getNamedOperand(*MI, AMDGPU::OpName::dst)->getReg(),
275 TII->getNamedOperand(*MI, AMDGPU::OpName::scratch_rsrc)->getReg(),
276 TII->getNamedOperand(*MI, AMDGPU::OpName::scratch_offset)->getReg(),
277 FrameInfo->getObjectOffset(Index), RS);
278 MI->eraseFromParent();
283 int64_t Offset = FrameInfo->getObjectOffset(Index);
284 FIOp.ChangeToImmediate(Offset);
285 if (!TII->isImmOperandLegal(MI, FIOperandNum, FIOp)) {
286 unsigned TmpReg = RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, SPAdj);
287 BuildMI(*MBB, MI, MI->getDebugLoc(),
288 TII->get(AMDGPU::V_MOV_B32_e32), TmpReg)
290 FIOp.ChangeToRegister(TmpReg, false, false, true);
296 const TargetRegisterClass * SIRegisterInfo::getCFGStructurizerRegClass(
298 switch(VT.SimpleTy) {
300 case MVT::i32: return &AMDGPU::VGPR_32RegClass;
304 unsigned SIRegisterInfo::getHWRegIndex(unsigned Reg) const {
305 return getEncodingValue(Reg) & 0xff;
308 const TargetRegisterClass *SIRegisterInfo::getPhysRegClass(unsigned Reg) const {
309 assert(!TargetRegisterInfo::isVirtualRegister(Reg));
311 static const TargetRegisterClass *BaseClasses[] = {
312 &AMDGPU::VGPR_32RegClass,
313 &AMDGPU::SReg_32RegClass,
314 &AMDGPU::VReg_64RegClass,
315 &AMDGPU::SReg_64RegClass,
316 &AMDGPU::VReg_96RegClass,
317 &AMDGPU::VReg_128RegClass,
318 &AMDGPU::SReg_128RegClass,
319 &AMDGPU::VReg_256RegClass,
320 &AMDGPU::SReg_256RegClass,
321 &AMDGPU::VReg_512RegClass
324 for (const TargetRegisterClass *BaseClass : BaseClasses) {
325 if (BaseClass->contains(Reg)) {
332 bool SIRegisterInfo::hasVGPRs(const TargetRegisterClass *RC) const {
333 return getCommonSubClass(&AMDGPU::VGPR_32RegClass, RC) ||
334 getCommonSubClass(&AMDGPU::VReg_64RegClass, RC) ||
335 getCommonSubClass(&AMDGPU::VReg_96RegClass, RC) ||
336 getCommonSubClass(&AMDGPU::VReg_128RegClass, RC) ||
337 getCommonSubClass(&AMDGPU::VReg_256RegClass, RC) ||
338 getCommonSubClass(&AMDGPU::VReg_512RegClass, RC);
341 const TargetRegisterClass *SIRegisterInfo::getEquivalentVGPRClass(
342 const TargetRegisterClass *SRC) const {
345 } else if (SRC == &AMDGPU::SCCRegRegClass) {
346 return &AMDGPU::VCCRegRegClass;
347 } else if (getCommonSubClass(SRC, &AMDGPU::SGPR_32RegClass)) {
348 return &AMDGPU::VGPR_32RegClass;
349 } else if (getCommonSubClass(SRC, &AMDGPU::SGPR_64RegClass)) {
350 return &AMDGPU::VReg_64RegClass;
351 } else if (getCommonSubClass(SRC, &AMDGPU::SReg_128RegClass)) {
352 return &AMDGPU::VReg_128RegClass;
353 } else if (getCommonSubClass(SRC, &AMDGPU::SReg_256RegClass)) {
354 return &AMDGPU::VReg_256RegClass;
355 } else if (getCommonSubClass(SRC, &AMDGPU::SReg_512RegClass)) {
356 return &AMDGPU::VReg_512RegClass;
361 const TargetRegisterClass *SIRegisterInfo::getSubRegClass(
362 const TargetRegisterClass *RC, unsigned SubIdx) const {
363 if (SubIdx == AMDGPU::NoSubRegister)
366 // If this register has a sub-register, we can safely assume it is a 32-bit
367 // register, because all of SI's sub-registers are 32-bit.
368 if (isSGPRClass(RC)) {
369 return &AMDGPU::SGPR_32RegClass;
371 return &AMDGPU::VGPR_32RegClass;
375 unsigned SIRegisterInfo::getPhysRegSubReg(unsigned Reg,
376 const TargetRegisterClass *SubRC,
377 unsigned Channel) const {
382 case 0: return AMDGPU::VCC_LO;
383 case 1: return AMDGPU::VCC_HI;
384 default: llvm_unreachable("Invalid SubIdx for VCC");
387 case AMDGPU::FLAT_SCR:
390 return AMDGPU::FLAT_SCR_LO;
392 return AMDGPU::FLAT_SCR_HI;
394 llvm_unreachable("Invalid SubIdx for FLAT_SCR");
401 return AMDGPU::EXEC_LO;
403 return AMDGPU::EXEC_HI;
405 llvm_unreachable("Invalid SubIdx for EXEC");
410 const TargetRegisterClass *RC = getPhysRegClass(Reg);
411 // 32-bit registers don't have sub-registers, so we can just return the
412 // Reg. We need to have this check here, because the calculation below
413 // using getHWRegIndex() will fail with special 32-bit registers like
414 // VCC_LO, VCC_HI, EXEC_LO, EXEC_HI and M0.
415 if (RC->getSize() == 4) {
416 assert(Channel == 0);
420 unsigned Index = getHWRegIndex(Reg);
421 return SubRC->getRegister(Index + Channel);
424 bool SIRegisterInfo::opCanUseLiteralConstant(unsigned OpType) const {
425 return OpType == AMDGPU::OPERAND_REG_IMM32;
428 bool SIRegisterInfo::opCanUseInlineConstant(unsigned OpType) const {
429 if (opCanUseLiteralConstant(OpType))
432 return OpType == AMDGPU::OPERAND_REG_INLINE_C;
435 unsigned SIRegisterInfo::getPreloadedValue(const MachineFunction &MF,
436 enum PreloadedValue Value) const {
438 const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
440 case SIRegisterInfo::TGID_X:
441 return AMDGPU::SReg_32RegClass.getRegister(MFI->NumUserSGPRs + 0);
442 case SIRegisterInfo::TGID_Y:
443 return AMDGPU::SReg_32RegClass.getRegister(MFI->NumUserSGPRs + 1);
444 case SIRegisterInfo::TGID_Z:
445 return AMDGPU::SReg_32RegClass.getRegister(MFI->NumUserSGPRs + 2);
446 case SIRegisterInfo::SCRATCH_WAVE_OFFSET:
447 if (MFI->getShaderType() != ShaderType::COMPUTE)
448 return MFI->ScratchOffsetReg;
449 return AMDGPU::SReg_32RegClass.getRegister(MFI->NumUserSGPRs + 4);
450 case SIRegisterInfo::SCRATCH_PTR:
451 return AMDGPU::SGPR2_SGPR3;
452 case SIRegisterInfo::INPUT_PTR:
453 return AMDGPU::SGPR0_SGPR1;
454 case SIRegisterInfo::TIDIG_X:
455 return AMDGPU::VGPR0;
456 case SIRegisterInfo::TIDIG_Y:
457 return AMDGPU::VGPR1;
458 case SIRegisterInfo::TIDIG_Z:
459 return AMDGPU::VGPR2;
461 llvm_unreachable("unexpected preloaded value type");
464 /// \brief Returns a register that is not used at any point in the function.
465 /// If all registers are used, then this function will return
466 // AMDGPU::NoRegister.
467 unsigned SIRegisterInfo::findUnusedRegister(const MachineRegisterInfo &MRI,
468 const TargetRegisterClass *RC) const {
470 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
472 if (!MRI.isPhysRegUsed(*I))
475 return AMDGPU::NoRegister;
478 unsigned SIRegisterInfo::getNumVGPRsAllowed(unsigned WaveCount) const {
493 unsigned SIRegisterInfo::getNumSGPRsAllowed(unsigned WaveCount) const {