1 //===-- SILowerControlFlow.cpp - Use predicates for control flow ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This pass lowers the pseudo control flow instructions to real
12 /// machine instructions.
14 /// All control flow is handled using predicated instructions and
15 /// a predicate stack. Each Scalar ALU controls the operations of 64 Vector
16 /// ALUs. The Scalar ALU can update the predicate for any of the Vector ALUs
17 /// by writting to the 64-bit EXEC register (each bit corresponds to a
18 /// single vector ALU). Typically, for predicates, a vector ALU will write
19 /// to its bit of the VCC register (like EXEC VCC is 64-bits, one for each
20 /// Vector ALU) and then the ScalarALU will AND the VCC register with the
21 /// EXEC to update the predicates.
24 /// %VCC = V_CMP_GT_F32 %VGPR1, %VGPR2
25 /// %SGPR0 = SI_IF %VCC
26 /// %VGPR0 = V_ADD_F32 %VGPR0, %VGPR0
27 /// %SGPR0 = SI_ELSE %SGPR0
28 /// %VGPR0 = V_SUB_F32 %VGPR0, %VGPR0
33 /// %SGPR0 = S_AND_SAVEEXEC_B64 %VCC // Save and update the exec mask
34 /// %SGPR0 = S_XOR_B64 %SGPR0, %EXEC // Clear live bits from saved exec mask
35 /// S_CBRANCH_EXECZ label0 // This instruction is an optional
36 /// // optimization which allows us to
37 /// // branch if all the bits of
39 /// %VGPR0 = V_ADD_F32 %VGPR0, %VGPR0 // Do the IF block of the branch
42 /// %SGPR0 = S_OR_SAVEEXEC_B64 %EXEC // Restore the exec mask for the Then block
43 /// %EXEC = S_XOR_B64 %SGPR0, %EXEC // Clear live bits from saved exec mask
44 /// S_BRANCH_EXECZ label1 // Use our branch optimization
45 /// // instruction again.
46 /// %VGPR0 = V_SUB_F32 %VGPR0, %VGPR // Do the THEN block
48 /// %EXEC = S_OR_B64 %EXEC, %SGPR0 // Re-enable saved exec mask bits
49 //===----------------------------------------------------------------------===//
52 #include "SIInstrInfo.h"
53 #include "SIMachineFunctionInfo.h"
54 #include "llvm/CodeGen/MachineFunction.h"
55 #include "llvm/CodeGen/MachineFunctionPass.h"
56 #include "llvm/CodeGen/MachineInstrBuilder.h"
57 #include "llvm/CodeGen/MachineRegisterInfo.h"
63 class SILowerControlFlowPass : public MachineFunctionPass {
66 static const unsigned SkipThreshold = 12;
69 const TargetRegisterInfo *TRI;
70 const TargetInstrInfo *TII;
72 bool shouldSkip(MachineBasicBlock *From, MachineBasicBlock *To);
74 void Skip(MachineInstr &From, MachineOperand &To);
75 void SkipIfDead(MachineInstr &MI);
77 void If(MachineInstr &MI);
78 void Else(MachineInstr &MI);
79 void Break(MachineInstr &MI);
80 void IfBreak(MachineInstr &MI);
81 void ElseBreak(MachineInstr &MI);
82 void Loop(MachineInstr &MI);
83 void EndCf(MachineInstr &MI);
85 void Kill(MachineInstr &MI);
86 void Branch(MachineInstr &MI);
88 void LoadM0(MachineInstr &MI, MachineInstr *MovRel);
89 void IndirectSrc(MachineInstr &MI);
90 void IndirectDst(MachineInstr &MI);
93 SILowerControlFlowPass(TargetMachine &tm) :
94 MachineFunctionPass(ID), TRI(0), TII(0) { }
96 virtual bool runOnMachineFunction(MachineFunction &MF);
98 const char *getPassName() const {
99 return "SI Lower control flow instructions";
104 } // End anonymous namespace
106 char SILowerControlFlowPass::ID = 0;
108 FunctionPass *llvm::createSILowerControlFlowPass(TargetMachine &tm) {
109 return new SILowerControlFlowPass(tm);
112 bool SILowerControlFlowPass::shouldSkip(MachineBasicBlock *From,
113 MachineBasicBlock *To) {
115 unsigned NumInstr = 0;
117 for (MachineBasicBlock *MBB = From; MBB != To && !MBB->succ_empty();
118 MBB = *MBB->succ_begin()) {
120 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
121 NumInstr < SkipThreshold && I != E; ++I) {
123 if (I->isBundle() || !I->isBundled())
124 if (++NumInstr >= SkipThreshold)
132 void SILowerControlFlowPass::Skip(MachineInstr &From, MachineOperand &To) {
134 if (!shouldSkip(*From.getParent()->succ_begin(), To.getMBB()))
137 DebugLoc DL = From.getDebugLoc();
138 BuildMI(*From.getParent(), &From, DL, TII->get(AMDGPU::S_CBRANCH_EXECZ))
140 .addReg(AMDGPU::EXEC);
143 void SILowerControlFlowPass::SkipIfDead(MachineInstr &MI) {
145 MachineBasicBlock &MBB = *MI.getParent();
146 DebugLoc DL = MI.getDebugLoc();
148 if (!shouldSkip(&MBB, &MBB.getParent()->back()))
151 MachineBasicBlock::iterator Insert = &MI;
154 // If the exec mask is non-zero, skip the next two instructions
155 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
157 .addReg(AMDGPU::EXEC);
159 // Exec mask is zero: Export to NULL target...
160 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::EXP))
162 .addImm(0x09) // V_008DFC_SQ_EXP_NULL
166 .addReg(AMDGPU::VGPR0)
167 .addReg(AMDGPU::VGPR0)
168 .addReg(AMDGPU::VGPR0)
169 .addReg(AMDGPU::VGPR0);
171 // ... and terminate wavefront
172 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::S_ENDPGM));
175 void SILowerControlFlowPass::If(MachineInstr &MI) {
176 MachineBasicBlock &MBB = *MI.getParent();
177 DebugLoc DL = MI.getDebugLoc();
178 unsigned Reg = MI.getOperand(0).getReg();
179 unsigned Vcc = MI.getOperand(1).getReg();
181 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_AND_SAVEEXEC_B64), Reg)
184 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), Reg)
185 .addReg(AMDGPU::EXEC)
188 Skip(MI, MI.getOperand(2));
190 MI.eraseFromParent();
193 void SILowerControlFlowPass::Else(MachineInstr &MI) {
194 MachineBasicBlock &MBB = *MI.getParent();
195 DebugLoc DL = MI.getDebugLoc();
196 unsigned Dst = MI.getOperand(0).getReg();
197 unsigned Src = MI.getOperand(1).getReg();
199 BuildMI(MBB, MBB.getFirstNonPHI(), DL,
200 TII->get(AMDGPU::S_OR_SAVEEXEC_B64), Dst)
201 .addReg(Src); // Saved EXEC
203 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), AMDGPU::EXEC)
204 .addReg(AMDGPU::EXEC)
207 Skip(MI, MI.getOperand(2));
209 MI.eraseFromParent();
212 void SILowerControlFlowPass::Break(MachineInstr &MI) {
213 MachineBasicBlock &MBB = *MI.getParent();
214 DebugLoc DL = MI.getDebugLoc();
216 unsigned Dst = MI.getOperand(0).getReg();
217 unsigned Src = MI.getOperand(1).getReg();
219 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst)
220 .addReg(AMDGPU::EXEC)
223 MI.eraseFromParent();
226 void SILowerControlFlowPass::IfBreak(MachineInstr &MI) {
227 MachineBasicBlock &MBB = *MI.getParent();
228 DebugLoc DL = MI.getDebugLoc();
230 unsigned Dst = MI.getOperand(0).getReg();
231 unsigned Vcc = MI.getOperand(1).getReg();
232 unsigned Src = MI.getOperand(2).getReg();
234 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst)
238 MI.eraseFromParent();
241 void SILowerControlFlowPass::ElseBreak(MachineInstr &MI) {
242 MachineBasicBlock &MBB = *MI.getParent();
243 DebugLoc DL = MI.getDebugLoc();
245 unsigned Dst = MI.getOperand(0).getReg();
246 unsigned Saved = MI.getOperand(1).getReg();
247 unsigned Src = MI.getOperand(2).getReg();
249 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst)
253 MI.eraseFromParent();
256 void SILowerControlFlowPass::Loop(MachineInstr &MI) {
257 MachineBasicBlock &MBB = *MI.getParent();
258 DebugLoc DL = MI.getDebugLoc();
259 unsigned Src = MI.getOperand(0).getReg();
261 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_ANDN2_B64), AMDGPU::EXEC)
262 .addReg(AMDGPU::EXEC)
265 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
266 .addOperand(MI.getOperand(1))
267 .addReg(AMDGPU::EXEC);
269 MI.eraseFromParent();
272 void SILowerControlFlowPass::EndCf(MachineInstr &MI) {
273 MachineBasicBlock &MBB = *MI.getParent();
274 DebugLoc DL = MI.getDebugLoc();
275 unsigned Reg = MI.getOperand(0).getReg();
277 BuildMI(MBB, MBB.getFirstNonPHI(), DL,
278 TII->get(AMDGPU::S_OR_B64), AMDGPU::EXEC)
279 .addReg(AMDGPU::EXEC)
282 MI.eraseFromParent();
285 void SILowerControlFlowPass::Branch(MachineInstr &MI) {
286 assert(MI.getOperand(0).getMBB() == MI.getParent()->getNextNode());
287 MI.eraseFromParent();
290 void SILowerControlFlowPass::Kill(MachineInstr &MI) {
291 MachineBasicBlock &MBB = *MI.getParent();
292 DebugLoc DL = MI.getDebugLoc();
294 // Kill is only allowed in pixel shaders
295 assert(MBB.getParent()->getInfo<SIMachineFunctionInfo>()->ShaderType ==
298 // Clear this pixel from the exec mask if the operand is negative
299 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_CMPX_LE_F32_e32), AMDGPU::VCC)
301 .addOperand(MI.getOperand(0));
303 MI.eraseFromParent();
306 void SILowerControlFlowPass::LoadM0(MachineInstr &MI, MachineInstr *MovRel) {
308 MachineBasicBlock &MBB = *MI.getParent();
309 DebugLoc DL = MI.getDebugLoc();
310 MachineBasicBlock::iterator I = MI;
312 unsigned Save = MI.getOperand(1).getReg();
313 unsigned Idx = MI.getOperand(3).getReg();
315 if (AMDGPU::SReg_32RegClass.contains(Idx)) {
316 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
318 MBB.insert(I, MovRel);
319 MI.eraseFromParent();
323 assert(AMDGPU::SReg_64RegClass.contains(Save));
324 assert(AMDGPU::VReg_32RegClass.contains(Idx));
326 // Save the EXEC mask
327 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B64), Save)
328 .addReg(AMDGPU::EXEC);
330 // Read the next variant into VCC (lower 32 bits) <- also loop target
331 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32_e32), AMDGPU::VCC)
334 // Move index from VCC into M0
335 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
336 .addReg(AMDGPU::VCC);
338 // Compare the just read M0 value to all possible Idx values
339 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_CMP_EQ_U32_e32), AMDGPU::VCC)
343 // Update EXEC, save the original EXEC value to VCC
344 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_AND_SAVEEXEC_B64), AMDGPU::VCC)
345 .addReg(AMDGPU::VCC);
347 // Do the actual move
348 MBB.insert(I, MovRel);
350 // Update EXEC, switch all done bits to 0 and all todo bits to 1
351 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), AMDGPU::EXEC)
352 .addReg(AMDGPU::EXEC)
353 .addReg(AMDGPU::VCC);
355 // Loop back to V_READFIRSTLANE_B32 if there are still variants to cover
356 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
358 .addReg(AMDGPU::EXEC);
361 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B64), AMDGPU::EXEC)
364 MI.eraseFromParent();
367 void SILowerControlFlowPass::IndirectSrc(MachineInstr &MI) {
369 MachineBasicBlock &MBB = *MI.getParent();
370 DebugLoc DL = MI.getDebugLoc();
372 unsigned Dst = MI.getOperand(0).getReg();
373 unsigned Vec = MI.getOperand(2).getReg();
374 unsigned Off = MI.getOperand(4).getImm();
375 unsigned SubReg = TRI->getSubReg(Vec, AMDGPU::sub0);
379 MachineInstr *MovRel =
380 BuildMI(*MBB.getParent(), DL, TII->get(AMDGPU::V_MOVRELS_B32_e32), Dst)
381 .addReg(SubReg + Off)
382 .addReg(AMDGPU::M0, RegState::Implicit)
383 .addReg(Vec, RegState::Implicit);
388 void SILowerControlFlowPass::IndirectDst(MachineInstr &MI) {
390 MachineBasicBlock &MBB = *MI.getParent();
391 DebugLoc DL = MI.getDebugLoc();
393 unsigned Dst = MI.getOperand(0).getReg();
394 unsigned Off = MI.getOperand(4).getImm();
395 unsigned Val = MI.getOperand(5).getReg();
396 unsigned SubReg = TRI->getSubReg(Dst, AMDGPU::sub0);
400 MachineInstr *MovRel =
401 BuildMI(*MBB.getParent(), DL, TII->get(AMDGPU::V_MOVRELD_B32_e32))
402 .addReg(SubReg + Off, RegState::Define)
404 .addReg(AMDGPU::M0, RegState::Implicit)
405 .addReg(Dst, RegState::Implicit);
410 bool SILowerControlFlowPass::runOnMachineFunction(MachineFunction &MF) {
411 TII = MF.getTarget().getInstrInfo();
412 TRI = MF.getTarget().getRegisterInfo();
413 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
415 bool HaveKill = false;
417 bool NeedWQM = false;
420 for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
423 MachineBasicBlock &MBB = *BI;
424 for (MachineBasicBlock::iterator I = MBB.begin(), Next = llvm::next(I);
425 I != MBB.end(); I = Next) {
427 Next = llvm::next(I);
428 MachineInstr &MI = *I;
429 switch (MI.getOpcode()) {
436 case AMDGPU::SI_ELSE:
440 case AMDGPU::SI_BREAK:
444 case AMDGPU::SI_IF_BREAK:
448 case AMDGPU::SI_ELSE_BREAK:
452 case AMDGPU::SI_LOOP:
457 case AMDGPU::SI_END_CF:
458 if (--Depth == 0 && HaveKill) {
465 case AMDGPU::SI_KILL:
473 case AMDGPU::S_BRANCH:
477 case AMDGPU::SI_INDIRECT_SRC:
481 case AMDGPU::SI_INDIRECT_DST_V1:
482 case AMDGPU::SI_INDIRECT_DST_V2:
483 case AMDGPU::SI_INDIRECT_DST_V4:
484 case AMDGPU::SI_INDIRECT_DST_V8:
485 case AMDGPU::SI_INDIRECT_DST_V16:
489 case AMDGPU::DS_READ_B32:
492 case AMDGPU::DS_WRITE_B32:
493 case AMDGPU::DS_ADD_U32_RTN:
497 case AMDGPU::V_INTERP_P1_F32:
498 case AMDGPU::V_INTERP_P2_F32:
499 case AMDGPU::V_INTERP_MOV_F32:
508 MachineBasicBlock &MBB = MF.front();
509 // Initialize M0 to a value that won't cause LDS access to be discarded
510 // due to offset clamping
511 BuildMI(MBB, MBB.getFirstNonPHI(), DebugLoc(), TII->get(AMDGPU::S_MOV_B32),
512 AMDGPU::M0).addImm(0xffffffff);
515 if (NeedWQM && MFI->ShaderType != ShaderType::COMPUTE) {
516 MachineBasicBlock &MBB = MF.front();
517 BuildMI(MBB, MBB.getFirstNonPHI(), DebugLoc(), TII->get(AMDGPU::S_WQM_B64),
518 AMDGPU::EXEC).addReg(AMDGPU::EXEC);