1 //===-- SILowerControlFlow.cpp - Use predicates for control flow ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This pass lowers the pseudo control flow instructions to real
12 /// machine instructions.
14 /// All control flow is handled using predicated instructions and
15 /// a predicate stack. Each Scalar ALU controls the operations of 64 Vector
16 /// ALUs. The Scalar ALU can update the predicate for any of the Vector ALUs
17 /// by writting to the 64-bit EXEC register (each bit corresponds to a
18 /// single vector ALU). Typically, for predicates, a vector ALU will write
19 /// to its bit of the VCC register (like EXEC VCC is 64-bits, one for each
20 /// Vector ALU) and then the ScalarALU will AND the VCC register with the
21 /// EXEC to update the predicates.
24 /// %VCC = V_CMP_GT_F32 %VGPR1, %VGPR2
25 /// %SGPR0 = SI_IF %VCC
26 /// %VGPR0 = V_ADD_F32 %VGPR0, %VGPR0
27 /// %SGPR0 = SI_ELSE %SGPR0
28 /// %VGPR0 = V_SUB_F32 %VGPR0, %VGPR0
33 /// %SGPR0 = S_AND_SAVEEXEC_B64 %VCC // Save and update the exec mask
34 /// %SGPR0 = S_XOR_B64 %SGPR0, %EXEC // Clear live bits from saved exec mask
35 /// S_CBRANCH_EXECZ label0 // This instruction is an optional
36 /// // optimization which allows us to
37 /// // branch if all the bits of
39 /// %VGPR0 = V_ADD_F32 %VGPR0, %VGPR0 // Do the IF block of the branch
42 /// %SGPR0 = S_OR_SAVEEXEC_B64 %EXEC // Restore the exec mask for the Then block
43 /// %EXEC = S_XOR_B64 %SGPR0, %EXEC // Clear live bits from saved exec mask
44 /// S_BRANCH_EXECZ label1 // Use our branch optimization
45 /// // instruction again.
46 /// %VGPR0 = V_SUB_F32 %VGPR0, %VGPR // Do the THEN block
48 /// %EXEC = S_OR_B64 %EXEC, %SGPR0 // Re-enable saved exec mask bits
49 //===----------------------------------------------------------------------===//
52 #include "SIInstrInfo.h"
53 #include "SIMachineFunctionInfo.h"
54 #include "llvm/CodeGen/MachineFunction.h"
55 #include "llvm/CodeGen/MachineFunctionPass.h"
56 #include "llvm/CodeGen/MachineInstrBuilder.h"
57 #include "llvm/CodeGen/MachineRegisterInfo.h"
63 class SILowerControlFlowPass : public MachineFunctionPass {
66 static const unsigned SkipThreshold = 12;
69 const TargetInstrInfo *TII;
71 bool shouldSkip(MachineBasicBlock *From, MachineBasicBlock *To);
73 void Skip(MachineInstr &From, MachineOperand &To);
74 void SkipIfDead(MachineInstr &MI);
76 void If(MachineInstr &MI);
77 void Else(MachineInstr &MI);
78 void Break(MachineInstr &MI);
79 void IfBreak(MachineInstr &MI);
80 void ElseBreak(MachineInstr &MI);
81 void Loop(MachineInstr &MI);
82 void EndCf(MachineInstr &MI);
84 void Kill(MachineInstr &MI);
85 void Branch(MachineInstr &MI);
88 SILowerControlFlowPass(TargetMachine &tm) :
89 MachineFunctionPass(ID), TII(tm.getInstrInfo()) { }
91 virtual bool runOnMachineFunction(MachineFunction &MF);
93 const char *getPassName() const {
94 return "SI Lower control flow instructions";
99 } // End anonymous namespace
101 char SILowerControlFlowPass::ID = 0;
103 FunctionPass *llvm::createSILowerControlFlowPass(TargetMachine &tm) {
104 return new SILowerControlFlowPass(tm);
107 bool SILowerControlFlowPass::shouldSkip(MachineBasicBlock *From,
108 MachineBasicBlock *To) {
110 unsigned NumInstr = 0;
112 for (MachineBasicBlock *MBB = From; MBB != To && !MBB->succ_empty();
113 MBB = *MBB->succ_begin()) {
115 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
116 NumInstr < SkipThreshold && I != E; ++I) {
118 if (I->isBundle() || !I->isBundled())
119 if (++NumInstr >= SkipThreshold)
127 void SILowerControlFlowPass::Skip(MachineInstr &From, MachineOperand &To) {
129 if (!shouldSkip(*From.getParent()->succ_begin(), To.getMBB()))
132 DebugLoc DL = From.getDebugLoc();
133 BuildMI(*From.getParent(), &From, DL, TII->get(AMDGPU::S_CBRANCH_EXECZ))
135 .addReg(AMDGPU::EXEC);
138 void SILowerControlFlowPass::SkipIfDead(MachineInstr &MI) {
140 MachineBasicBlock &MBB = *MI.getParent();
141 DebugLoc DL = MI.getDebugLoc();
143 if (!shouldSkip(&MBB, &MBB.getParent()->back()))
146 MachineBasicBlock::iterator Insert = &MI;
149 // If the exec mask is non-zero, skip the next two instructions
150 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
152 .addReg(AMDGPU::EXEC);
154 // Exec mask is zero: Export to NULL target...
155 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::EXP))
157 .addImm(0x09) // V_008DFC_SQ_EXP_NULL
161 .addReg(AMDGPU::SREG_LIT_0)
162 .addReg(AMDGPU::SREG_LIT_0)
163 .addReg(AMDGPU::SREG_LIT_0)
164 .addReg(AMDGPU::SREG_LIT_0);
166 // ... and terminate wavefront
167 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::S_ENDPGM));
170 void SILowerControlFlowPass::If(MachineInstr &MI) {
171 MachineBasicBlock &MBB = *MI.getParent();
172 DebugLoc DL = MI.getDebugLoc();
173 unsigned Reg = MI.getOperand(0).getReg();
174 unsigned Vcc = MI.getOperand(1).getReg();
176 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_AND_SAVEEXEC_B64), Reg)
179 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), Reg)
180 .addReg(AMDGPU::EXEC)
183 Skip(MI, MI.getOperand(2));
185 MI.eraseFromParent();
188 void SILowerControlFlowPass::Else(MachineInstr &MI) {
189 MachineBasicBlock &MBB = *MI.getParent();
190 DebugLoc DL = MI.getDebugLoc();
191 unsigned Dst = MI.getOperand(0).getReg();
192 unsigned Src = MI.getOperand(1).getReg();
194 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_SAVEEXEC_B64), Dst)
195 .addReg(Src); // Saved EXEC
197 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), AMDGPU::EXEC)
198 .addReg(AMDGPU::EXEC)
201 Skip(MI, MI.getOperand(2));
203 MI.eraseFromParent();
206 void SILowerControlFlowPass::Break(MachineInstr &MI) {
207 MachineBasicBlock &MBB = *MI.getParent();
208 DebugLoc DL = MI.getDebugLoc();
210 unsigned Dst = MI.getOperand(0).getReg();
211 unsigned Src = MI.getOperand(1).getReg();
213 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst)
214 .addReg(AMDGPU::EXEC)
217 MI.eraseFromParent();
220 void SILowerControlFlowPass::IfBreak(MachineInstr &MI) {
221 MachineBasicBlock &MBB = *MI.getParent();
222 DebugLoc DL = MI.getDebugLoc();
224 unsigned Dst = MI.getOperand(0).getReg();
225 unsigned Vcc = MI.getOperand(1).getReg();
226 unsigned Src = MI.getOperand(2).getReg();
228 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst)
232 MI.eraseFromParent();
235 void SILowerControlFlowPass::ElseBreak(MachineInstr &MI) {
236 MachineBasicBlock &MBB = *MI.getParent();
237 DebugLoc DL = MI.getDebugLoc();
239 unsigned Dst = MI.getOperand(0).getReg();
240 unsigned Saved = MI.getOperand(1).getReg();
241 unsigned Src = MI.getOperand(2).getReg();
243 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst)
247 MI.eraseFromParent();
250 void SILowerControlFlowPass::Loop(MachineInstr &MI) {
251 MachineBasicBlock &MBB = *MI.getParent();
252 DebugLoc DL = MI.getDebugLoc();
253 unsigned Src = MI.getOperand(0).getReg();
255 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_ANDN2_B64), AMDGPU::EXEC)
256 .addReg(AMDGPU::EXEC)
259 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
260 .addOperand(MI.getOperand(1))
261 .addReg(AMDGPU::EXEC);
263 MI.eraseFromParent();
266 void SILowerControlFlowPass::EndCf(MachineInstr &MI) {
267 MachineBasicBlock &MBB = *MI.getParent();
268 DebugLoc DL = MI.getDebugLoc();
269 unsigned Reg = MI.getOperand(0).getReg();
271 BuildMI(MBB, MBB.getFirstNonPHI(), DL,
272 TII->get(AMDGPU::S_OR_B64), AMDGPU::EXEC)
273 .addReg(AMDGPU::EXEC)
276 MI.eraseFromParent();
279 void SILowerControlFlowPass::Branch(MachineInstr &MI) {
280 MachineBasicBlock *Next = MI.getParent()->getNextNode();
281 MachineBasicBlock *Target = MI.getOperand(0).getMBB();
283 MI.eraseFromParent();
288 void SILowerControlFlowPass::Kill(MachineInstr &MI) {
290 MachineBasicBlock &MBB = *MI.getParent();
291 DebugLoc DL = MI.getDebugLoc();
293 // Kill is only allowed in pixel shaders
294 assert(MBB.getParent()->getInfo<SIMachineFunctionInfo>()->ShaderType ==
297 // Clear this pixel from the exec mask if the operand is negative
298 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_CMPX_LE_F32_e32), AMDGPU::VCC)
299 .addReg(AMDGPU::SREG_LIT_0)
300 .addOperand(MI.getOperand(0));
302 MI.eraseFromParent();
305 bool SILowerControlFlowPass::runOnMachineFunction(MachineFunction &MF) {
307 bool HaveKill = false;
310 for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
313 MachineBasicBlock &MBB = *BI;
314 for (MachineBasicBlock::iterator I = MBB.begin(), Next = llvm::next(I);
315 I != MBB.end(); I = Next) {
317 Next = llvm::next(I);
318 MachineInstr &MI = *I;
319 switch (MI.getOpcode()) {
326 case AMDGPU::SI_ELSE:
330 case AMDGPU::SI_BREAK:
334 case AMDGPU::SI_IF_BREAK:
338 case AMDGPU::SI_ELSE_BREAK:
342 case AMDGPU::SI_LOOP:
347 case AMDGPU::SI_END_CF:
348 if (--Depth == 0 && HaveKill) {
355 case AMDGPU::SI_KILL:
363 case AMDGPU::S_BRANCH: