1 //===-- SILoadStoreOptimizer.cpp ------------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass tries to fuse DS instructions with close by immediate offsets.
11 // This will fuse operations such as
12 // ds_read_b32 v0, v2 offset:16
13 // ds_read_b32 v1, v2 offset:32
15 // ds_read2_b32 v[0:1], v2, offset0:4 offset1:8
18 // Future improvements:
20 // - This currently relies on the scheduler to place loads and stores next to
21 // each other, and then only merges adjacent pairs of instructions. It would
22 // be good to be more flexible with interleaved instructions, and possibly run
23 // before scheduling. It currently missing stores of constants because loading
24 // the constant into the data register is placed between the stores, although
25 // this is arguably a scheduling problem.
27 // - Live interval recomputing seems inefficient. This currently only matches
28 // one pair, and recomputes live intervals and moves on to the next pair. It
29 // would be better to compute a list of all merges that need to occur
31 // - With a list of instructions to process, we can also merge more. If a
32 // cluster of loads have offsets that are too large to fit in the 8-bit
33 // offsets, but are close enough to fit in the 8 bits, we can add to the base
34 // pointer and use the new reduced offsets.
36 //===----------------------------------------------------------------------===//
39 #include "SIInstrInfo.h"
40 #include "SIRegisterInfo.h"
41 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
42 #include "llvm/CodeGen/LiveVariables.h"
43 #include "llvm/CodeGen/MachineFunction.h"
44 #include "llvm/CodeGen/MachineFunctionPass.h"
45 #include "llvm/CodeGen/MachineInstrBuilder.h"
46 #include "llvm/CodeGen/MachineRegisterInfo.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Target/TargetMachine.h"
52 #define DEBUG_TYPE "si-load-store-opt"
56 class SILoadStoreOptimizer : public MachineFunctionPass {
58 const TargetMachine *TM;
59 const SIInstrInfo *TII;
60 const SIRegisterInfo *TRI;
61 MachineRegisterInfo *MRI;
65 static bool offsetsCanBeCombined(unsigned Offset0,
69 MachineBasicBlock::iterator findMatchingDSInst(MachineBasicBlock::iterator I,
72 void updateRegDefsUses(unsigned SrcReg,
76 MachineBasicBlock::iterator mergeRead2Pair(
77 MachineBasicBlock::iterator I,
78 MachineBasicBlock::iterator Paired,
80 const MCInstrDesc &Read2InstDesc);
82 MachineBasicBlock::iterator mergeWrite2Pair(
83 MachineBasicBlock::iterator I,
84 MachineBasicBlock::iterator Paired,
86 const MCInstrDesc &Write2InstDesc);
91 SILoadStoreOptimizer() :
92 MachineFunctionPass(ID),
101 SILoadStoreOptimizer(const TargetMachine &TM_) :
102 MachineFunctionPass(ID),
104 TII(static_cast<const SIInstrInfo*>(TM->getSubtargetImpl()->getInstrInfo())) {
105 initializeSILoadStoreOptimizerPass(*PassRegistry::getPassRegistry());
108 bool optimizeBlock(MachineBasicBlock &MBB);
110 bool runOnMachineFunction(MachineFunction &MF) override;
112 const char *getPassName() const override {
113 return "SI Load / Store Optimizer";
116 void getAnalysisUsage(AnalysisUsage &AU) const override {
117 AU.setPreservesCFG();
118 AU.addPreserved<SlotIndexes>();
119 AU.addPreserved<LiveIntervals>();
120 AU.addPreserved<LiveVariables>();
121 AU.addRequired<LiveIntervals>();
123 MachineFunctionPass::getAnalysisUsage(AU);
127 } // End anonymous namespace.
129 INITIALIZE_PASS_BEGIN(SILoadStoreOptimizer, DEBUG_TYPE,
130 "SI Load / Store Optimizer", false, false)
131 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
132 INITIALIZE_PASS_DEPENDENCY(LiveVariables)
133 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
134 INITIALIZE_PASS_END(SILoadStoreOptimizer, DEBUG_TYPE,
135 "SI Load / Store Optimizer", false, false)
137 char SILoadStoreOptimizer::ID = 0;
139 char &llvm::SILoadStoreOptimizerID = SILoadStoreOptimizer::ID;
141 FunctionPass *llvm::createSILoadStoreOptimizerPass(TargetMachine &TM) {
142 return new SILoadStoreOptimizer(TM);
145 bool SILoadStoreOptimizer::offsetsCanBeCombined(unsigned Offset0,
148 // XXX - Would the same offset be OK? Is there any reason this would happen or
150 return (Offset0 != Offset1) &&
151 isUInt<8>(Offset0 / EltSize) &&
152 isUInt<8>(Offset1 / EltSize);
155 MachineBasicBlock::iterator
156 SILoadStoreOptimizer::findMatchingDSInst(MachineBasicBlock::iterator I,
158 MachineBasicBlock::iterator E = I->getParent()->end();
159 MachineBasicBlock::iterator MBBI = I;
162 if (MBBI->getOpcode() != I->getOpcode())
165 // Don't merge volatiles.
166 if (MBBI->hasOrderedMemoryRef())
169 int AddrIdx = AMDGPU::getNamedOperandIdx(I->getOpcode(), AMDGPU::OpName::addr);
170 const MachineOperand &AddrReg0 = I->getOperand(AddrIdx);
171 const MachineOperand &AddrReg1 = MBBI->getOperand(AddrIdx);
173 // Check same base pointer. Be careful of subregisters, which can occur with
174 // vectors of pointers.
175 if (AddrReg0.getReg() == AddrReg1.getReg() &&
176 AddrReg0.getSubReg() == AddrReg1.getSubReg()) {
177 int OffsetIdx = AMDGPU::getNamedOperandIdx(I->getOpcode(),
178 AMDGPU::OpName::offset);
179 unsigned Offset0 = I->getOperand(OffsetIdx).getImm();
180 unsigned Offset1 = MBBI->getOperand(OffsetIdx).getImm();
182 // Check both offsets fit in the reduced range.
183 if (offsetsCanBeCombined(Offset0, Offset1, EltSize))
190 void SILoadStoreOptimizer::updateRegDefsUses(unsigned SrcReg,
193 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(SrcReg),
194 E = MRI->reg_end(); I != E; ) {
195 MachineOperand &O = *I;
197 O.substVirtReg(DstReg, SubIdx, *TRI);
201 MachineBasicBlock::iterator SILoadStoreOptimizer::mergeRead2Pair(
202 MachineBasicBlock::iterator I,
203 MachineBasicBlock::iterator Paired,
205 const MCInstrDesc &Read2InstDesc) {
206 MachineBasicBlock *MBB = I->getParent();
208 // Be careful, since the addresses could be subregisters themselves in weird
209 // cases, like vectors of pointers.
210 const MachineOperand *AddrReg = TII->getNamedOperand(*I, AMDGPU::OpName::addr);
212 unsigned DestReg0 = TII->getNamedOperand(*I, AMDGPU::OpName::vdst)->getReg();
214 = TII->getNamedOperand(*Paired, AMDGPU::OpName::vdst)->getReg();
216 unsigned Offset0 = TII->getNamedOperand(*I, AMDGPU::OpName::offset)->getImm();
218 = TII->getNamedOperand(*Paired, AMDGPU::OpName::offset)->getImm();
220 const TargetRegisterClass *SuperRC
221 = (EltSize == 4) ? &AMDGPU::VReg_64RegClass : &AMDGPU::VReg_128RegClass;
222 unsigned DestReg = MRI->createVirtualRegister(SuperRC);
224 DebugLoc DL = I->getDebugLoc();
225 MachineInstrBuilder Read2
226 = BuildMI(*MBB, I, DL, Read2InstDesc, DestReg)
228 .addOperand(*AddrReg) // addr
229 .addImm(Offset0 / EltSize) // offset0
230 .addImm(Offset1 / EltSize) // offset1
231 .addMemOperand(*I->memoperands_begin())
232 .addMemOperand(*Paired->memoperands_begin());
234 LIS->InsertMachineInstrInMaps(Read2);
236 unsigned SubRegIdx0 = (EltSize == 4) ? AMDGPU::sub0 : AMDGPU::sub0_sub1;
237 unsigned SubRegIdx1 = (EltSize == 4) ? AMDGPU::sub1 : AMDGPU::sub2_sub3;
238 updateRegDefsUses(DestReg0, DestReg, SubRegIdx0);
239 updateRegDefsUses(DestReg1, DestReg, SubRegIdx1);
241 LIS->RemoveMachineInstrFromMaps(I);
242 LIS->RemoveMachineInstrFromMaps(Paired);
243 I->eraseFromParent();
244 Paired->eraseFromParent();
246 LiveInterval &AddrRegLI = LIS->getInterval(AddrReg->getReg());
247 LIS->shrinkToUses(&AddrRegLI);
249 LIS->getInterval(DestReg); // Create new LI
251 DEBUG(dbgs() << "Inserted read2: " << *Read2 << '\n');
255 MachineBasicBlock::iterator SILoadStoreOptimizer::mergeWrite2Pair(
256 MachineBasicBlock::iterator I,
257 MachineBasicBlock::iterator Paired,
259 const MCInstrDesc &Write2InstDesc) {
260 MachineBasicBlock *MBB = I->getParent();
262 // Be sure to use .addOperand(), and not .addReg() with these. We want to be
263 // sure we preserve the subregister index and any register flags set on them.
264 const MachineOperand *Addr = TII->getNamedOperand(*I, AMDGPU::OpName::addr);
265 const MachineOperand *Data0 = TII->getNamedOperand(*I, AMDGPU::OpName::data0);
266 const MachineOperand *Data1
267 = TII->getNamedOperand(*Paired, AMDGPU::OpName::data0);
269 unsigned Offset0 = TII->getNamedOperand(*I, AMDGPU::OpName::offset)->getImm();
271 = TII->getNamedOperand(*Paired, AMDGPU::OpName::offset)->getImm();
273 DebugLoc DL = I->getDebugLoc();
274 MachineInstrBuilder Write2
275 = BuildMI(*MBB, I, DL, Write2InstDesc)
277 .addOperand(*Addr) // addr
278 .addOperand(*Data0) // data0
279 .addOperand(*Data1) // data1
280 .addImm(Offset0 / EltSize) // offset0
281 .addImm(Offset1 / EltSize) // offset1
282 .addMemOperand(*I->memoperands_begin())
283 .addMemOperand(*Paired->memoperands_begin());
285 // XXX - How do we express subregisters here?
286 unsigned OrigRegs[] = { Data0->getReg(), Data1->getReg(), Addr->getReg() };
288 LIS->RemoveMachineInstrFromMaps(I);
289 LIS->RemoveMachineInstrFromMaps(Paired);
290 I->eraseFromParent();
291 Paired->eraseFromParent();
293 LIS->repairIntervalsInRange(MBB, Write2, Write2, OrigRegs);
295 DEBUG(dbgs() << "Inserted write2 inst: " << *Write2 << '\n');
299 // Scan through looking for adjacent LDS operations with constant offsets from
300 // the same base register. We rely on the scheduler to do the hard work of
301 // clustering nearby loads, and assume these are all adjacent.
302 bool SILoadStoreOptimizer::optimizeBlock(MachineBasicBlock &MBB) {
303 const MCInstrDesc &Read2B32Desc = TII->get(AMDGPU::DS_READ2_B32);
304 const MCInstrDesc &Read2B64Desc = TII->get(AMDGPU::DS_READ2_B64);
305 const MCInstrDesc &Write2B32Desc = TII->get(AMDGPU::DS_WRITE2_B32);
306 const MCInstrDesc &Write2B64Desc = TII->get(AMDGPU::DS_WRITE2_B64);
308 bool Modified = false;
310 for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E;) {
311 MachineInstr &MI = *I;
313 // Don't combine if volatile.
314 if (MI.hasOrderedMemoryRef()) {
319 unsigned Opc = MI.getOpcode();
320 if (Opc == AMDGPU::DS_READ_B32 || Opc == AMDGPU::DS_READ_B64) {
321 unsigned Size = (Opc == AMDGPU::DS_READ_B64) ? 8 : 4;
322 MachineBasicBlock::iterator Match = findMatchingDSInst(I, Size);
326 const MCInstrDesc &Read2Desc
327 = (Opc == AMDGPU::DS_READ_B64) ? Read2B64Desc : Read2B32Desc;
328 I = mergeRead2Pair(I, Match, Size, Read2Desc);
334 } else if (Opc == AMDGPU::DS_WRITE_B32 || Opc == AMDGPU::DS_WRITE_B64) {
335 unsigned Size = (Opc == AMDGPU::DS_WRITE_B64) ? 8 : 4;
336 MachineBasicBlock::iterator Match = findMatchingDSInst(I, Size);
340 const MCInstrDesc &Write2Desc
341 = (Opc == AMDGPU::DS_WRITE_B64) ? Write2B64Desc : Write2B32Desc;
343 I = mergeWrite2Pair(I, Match, Size, Write2Desc);
357 bool SILoadStoreOptimizer::runOnMachineFunction(MachineFunction &MF) {
358 const TargetSubtargetInfo *STM = MF.getTarget().getSubtargetImpl();
359 TRI = static_cast<const SIRegisterInfo*>(STM->getRegisterInfo());
360 TII = static_cast<const SIInstrInfo*>(STM->getInstrInfo());
361 MRI = &MF.getRegInfo();
363 LIS = &getAnalysis<LiveIntervals>();
365 DEBUG(dbgs() << "Running SILoadStoreOptimizer\n");
367 assert(!MRI->isSSA());
369 bool Modified = false;
371 for (MachineBasicBlock &MBB : MF)
372 Modified |= optimizeBlock(MBB);