1 //===-- SIInstructions.td - SI Instruction Defintions ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // This file was originally auto-generated from a GPU register header file and
10 // all the instruction definitions were originally commented out. Instructions
11 // that are not yet supported remain commented out.
12 //===----------------------------------------------------------------------===//
19 def INTERP : InterpSlots;
21 def InterpSlot : Operand<i32> {
22 let PrintMethod = "printInterpSlot";
25 def SendMsgImm : Operand<i32> {
26 let PrintMethod = "printSendMsg";
29 def isSI : Predicate<"Subtarget.getGeneration() "
30 ">= AMDGPUSubtarget::SOUTHERN_ISLANDS">;
32 def isCI : Predicate<"Subtarget.getGeneration() "
33 ">= AMDGPUSubtarget::SEA_ISLANDS">;
34 def HasFlatAddressSpace : Predicate<"Subtarget.hasFlatAddressSpace()">;
36 def SWaitMatchClass : AsmOperandClass {
37 let Name = "SWaitCnt";
38 let RenderMethod = "addImmOperands";
39 let ParserMethod = "parseSWaitCntOps";
42 def WAIT_FLAG : InstFlag<"printWaitFlag"> {
43 let ParserMatchClass = SWaitMatchClass;
46 let SubtargetPredicate = isSI in {
48 //===----------------------------------------------------------------------===//
50 //===----------------------------------------------------------------------===//
54 //===----------------------------------------------------------------------===//
56 //===----------------------------------------------------------------------===//
60 // We are using the SGPR_32 and not the SReg_32 register class for 32-bit
61 // SMRD instructions, because the SGPR_32 register class does not include M0
62 // and writing to M0 from an SMRD instruction will hang the GPU.
63 defm S_LOAD_DWORD : SMRD_Helper <0x00, "s_load_dword", SReg_64, SGPR_32>;
64 defm S_LOAD_DWORDX2 : SMRD_Helper <0x01, "s_load_dwordx2", SReg_64, SReg_64>;
65 defm S_LOAD_DWORDX4 : SMRD_Helper <0x02, "s_load_dwordx4", SReg_64, SReg_128>;
66 defm S_LOAD_DWORDX8 : SMRD_Helper <0x03, "s_load_dwordx8", SReg_64, SReg_256>;
67 defm S_LOAD_DWORDX16 : SMRD_Helper <0x04, "s_load_dwordx16", SReg_64, SReg_512>;
69 defm S_BUFFER_LOAD_DWORD : SMRD_Helper <
70 0x08, "s_buffer_load_dword", SReg_128, SGPR_32
73 defm S_BUFFER_LOAD_DWORDX2 : SMRD_Helper <
74 0x09, "s_buffer_load_dwordx2", SReg_128, SReg_64
77 defm S_BUFFER_LOAD_DWORDX4 : SMRD_Helper <
78 0x0a, "s_buffer_load_dwordx4", SReg_128, SReg_128
81 defm S_BUFFER_LOAD_DWORDX8 : SMRD_Helper <
82 0x0b, "s_buffer_load_dwordx8", SReg_128, SReg_256
85 defm S_BUFFER_LOAD_DWORDX16 : SMRD_Helper <
86 0x0c, "s_buffer_load_dwordx16", SReg_128, SReg_512
91 //def S_MEMTIME : SMRD_ <0x0000001e, "s_memtime", []>;
92 //def S_DCACHE_INV : SMRD_ <0x0000001f, "s_dcache_inv", []>;
94 //===----------------------------------------------------------------------===//
96 //===----------------------------------------------------------------------===//
98 let isMoveImm = 1 in {
99 def S_MOV_B32 : SOP1_32 <0x00000003, "s_mov_b32", []>;
100 def S_MOV_B64 : SOP1_64 <0x00000004, "s_mov_b64", []>;
101 def S_CMOV_B32 : SOP1_32 <0x00000005, "s_cmov_b32", []>;
102 def S_CMOV_B64 : SOP1_64 <0x00000006, "s_cmov_b64", []>;
103 } // End isMoveImm = 1
105 def S_NOT_B32 : SOP1_32 <0x00000007, "s_not_b32",
106 [(set i32:$dst, (not i32:$src0))]
109 def S_NOT_B64 : SOP1_64 <0x00000008, "s_not_b64",
110 [(set i64:$dst, (not i64:$src0))]
112 def S_WQM_B32 : SOP1_32 <0x00000009, "s_wqm_b32", []>;
113 def S_WQM_B64 : SOP1_64 <0x0000000a, "s_wqm_b64", []>;
114 def S_BREV_B32 : SOP1_32 <0x0000000b, "s_brev_b32",
115 [(set i32:$dst, (AMDGPUbrev i32:$src0))]
117 def S_BREV_B64 : SOP1_64 <0x0000000c, "s_brev_b64", []>;
119 ////def S_BCNT0_I32_B32 : SOP1_BCNT0 <0x0000000d, "s_bcnt0_i32_b32", []>;
120 ////def S_BCNT0_I32_B64 : SOP1_BCNT0 <0x0000000e, "s_bcnt0_i32_b64", []>;
121 def S_BCNT1_I32_B32 : SOP1_32 <0x0000000f, "s_bcnt1_i32_b32",
122 [(set i32:$dst, (ctpop i32:$src0))]
124 def S_BCNT1_I32_B64 : SOP1_32_64 <0x00000010, "s_bcnt1_i32_b64", []>;
126 ////def S_FF0_I32_B32 : SOP1_32 <0x00000011, "s_ff0_i32_b32", []>;
127 ////def S_FF0_I32_B64 : SOP1_FF0 <0x00000012, "s_ff0_i32_b64", []>;
128 def S_FF1_I32_B32 : SOP1_32 <0x00000013, "s_ff1_i32_b32",
129 [(set i32:$dst, (cttz_zero_undef i32:$src0))]
131 ////def S_FF1_I32_B64 : SOP1_FF1 <0x00000014, "s_ff1_i32_b64", []>;
133 def S_FLBIT_I32_B32 : SOP1_32 <0x00000015, "s_flbit_i32_b32",
134 [(set i32:$dst, (ctlz_zero_undef i32:$src0))]
137 //def S_FLBIT_I32_B64 : SOP1_32 <0x00000016, "s_flbit_i32_b64", []>;
138 def S_FLBIT_I32 : SOP1_32 <0x00000017, "s_flbit_i32", []>;
139 //def S_FLBIT_I32_I64 : SOP1_32 <0x00000018, "s_flbit_i32_i64", []>;
140 def S_SEXT_I32_I8 : SOP1_32 <0x00000019, "s_sext_i32_i8",
141 [(set i32:$dst, (sext_inreg i32:$src0, i8))]
143 def S_SEXT_I32_I16 : SOP1_32 <0x0000001a, "s_sext_i32_i16",
144 [(set i32:$dst, (sext_inreg i32:$src0, i16))]
147 ////def S_BITSET0_B32 : SOP1_BITSET0 <0x0000001b, "s_bitset0_b32", []>;
148 ////def S_BITSET0_B64 : SOP1_BITSET0 <0x0000001c, "s_bitset0_b64", []>;
149 ////def S_BITSET1_B32 : SOP1_BITSET1 <0x0000001d, "s_bitset1_b32", []>;
150 ////def S_BITSET1_B64 : SOP1_BITSET1 <0x0000001e, "s_bitset1_b64", []>;
151 def S_GETPC_B64 : SOP1 <
152 0x0000001f, (outs SReg_64:$dst), (ins), "s_getpc_b64 $dst", []
156 def S_SETPC_B64 : SOP1_64 <0x00000020, "s_setpc_b64", []>;
157 def S_SWAPPC_B64 : SOP1_64 <0x00000021, "s_swappc_b64", []>;
158 def S_RFE_B64 : SOP1_64 <0x00000022, "s_rfe_b64", []>;
160 let hasSideEffects = 1, Uses = [EXEC], Defs = [EXEC] in {
162 def S_AND_SAVEEXEC_B64 : SOP1_64 <0x00000024, "s_and_saveexec_b64", []>;
163 def S_OR_SAVEEXEC_B64 : SOP1_64 <0x00000025, "s_or_saveexec_b64", []>;
164 def S_XOR_SAVEEXEC_B64 : SOP1_64 <0x00000026, "s_xor_saveexec_b64", []>;
165 def S_ANDN2_SAVEEXEC_B64 : SOP1_64 <0x00000027, "s_andn2_saveexec_b64", []>;
166 def S_ORN2_SAVEEXEC_B64 : SOP1_64 <0x00000028, "s_orn2_saveexec_b64", []>;
167 def S_NAND_SAVEEXEC_B64 : SOP1_64 <0x00000029, "s_nand_saveexec_b64", []>;
168 def S_NOR_SAVEEXEC_B64 : SOP1_64 <0x0000002a, "s_nor_saveexec_b64", []>;
169 def S_XNOR_SAVEEXEC_B64 : SOP1_64 <0x0000002b, "s_xnor_saveexec_b64", []>;
171 } // End hasSideEffects = 1
173 def S_QUADMASK_B32 : SOP1_32 <0x0000002c, "s_quadmask_b32", []>;
174 def S_QUADMASK_B64 : SOP1_64 <0x0000002d, "s_quadmask_b64", []>;
175 def S_MOVRELS_B32 : SOP1_32 <0x0000002e, "s_movrels_b32", []>;
176 def S_MOVRELS_B64 : SOP1_64 <0x0000002f, "s_movrels_b64", []>;
177 def S_MOVRELD_B32 : SOP1_32 <0x00000030, "s_movreld_b32", []>;
178 def S_MOVRELD_B64 : SOP1_64 <0x00000031, "s_movreld_b64", []>;
179 //def S_CBRANCH_JOIN : SOP1_ <0x00000032, "s_cbranch_join", []>;
180 def S_MOV_REGRD_B32 : SOP1_32 <0x00000033, "s_mov_regrd_b32", []>;
181 def S_ABS_I32 : SOP1_32 <0x00000034, "s_abs_i32", []>;
182 def S_MOV_FED_B32 : SOP1_32 <0x00000035, "s_mov_fed_b32", []>;
184 //===----------------------------------------------------------------------===//
186 //===----------------------------------------------------------------------===//
188 let Defs = [SCC] in { // Carry out goes to SCC
189 let isCommutable = 1 in {
190 def S_ADD_U32 : SOP2_32 <0x00000000, "s_add_u32", []>;
191 def S_ADD_I32 : SOP2_32 <0x00000002, "s_add_i32",
192 [(set i32:$dst, (add SSrc_32:$src0, SSrc_32:$src1))]
194 } // End isCommutable = 1
196 def S_SUB_U32 : SOP2_32 <0x00000001, "s_sub_u32", []>;
197 def S_SUB_I32 : SOP2_32 <0x00000003, "s_sub_i32",
198 [(set i32:$dst, (sub SSrc_32:$src0, SSrc_32:$src1))]
201 let Uses = [SCC] in { // Carry in comes from SCC
202 let isCommutable = 1 in {
203 def S_ADDC_U32 : SOP2_32 <0x00000004, "s_addc_u32",
204 [(set i32:$dst, (adde (i32 SSrc_32:$src0), (i32 SSrc_32:$src1)))]>;
205 } // End isCommutable = 1
207 def S_SUBB_U32 : SOP2_32 <0x00000005, "s_subb_u32",
208 [(set i32:$dst, (sube (i32 SSrc_32:$src0), (i32 SSrc_32:$src1)))]>;
209 } // End Uses = [SCC]
210 } // End Defs = [SCC]
212 def S_MIN_I32 : SOP2_32 <0x00000006, "s_min_i32",
213 [(set i32:$dst, (AMDGPUsmin i32:$src0, i32:$src1))]
215 def S_MIN_U32 : SOP2_32 <0x00000007, "s_min_u32",
216 [(set i32:$dst, (AMDGPUumin i32:$src0, i32:$src1))]
218 def S_MAX_I32 : SOP2_32 <0x00000008, "s_max_i32",
219 [(set i32:$dst, (AMDGPUsmax i32:$src0, i32:$src1))]
221 def S_MAX_U32 : SOP2_32 <0x00000009, "s_max_u32",
222 [(set i32:$dst, (AMDGPUumax i32:$src0, i32:$src1))]
225 def S_CSELECT_B32 : SOP2_SELECT_32 <
226 0x0000000a, "s_cselect_b32",
230 def S_CSELECT_B64 : SOP2_64 <0x0000000b, "s_cselect_b64", []>;
232 def S_AND_B32 : SOP2_32 <0x0000000e, "s_and_b32",
233 [(set i32:$dst, (and i32:$src0, i32:$src1))]
236 def S_AND_B64 : SOP2_64 <0x0000000f, "s_and_b64",
237 [(set i64:$dst, (and i64:$src0, i64:$src1))]
240 def S_OR_B32 : SOP2_32 <0x00000010, "s_or_b32",
241 [(set i32:$dst, (or i32:$src0, i32:$src1))]
244 def S_OR_B64 : SOP2_64 <0x00000011, "s_or_b64",
245 [(set i64:$dst, (or i64:$src0, i64:$src1))]
248 def S_XOR_B32 : SOP2_32 <0x00000012, "s_xor_b32",
249 [(set i32:$dst, (xor i32:$src0, i32:$src1))]
252 def S_XOR_B64 : SOP2_64 <0x00000013, "s_xor_b64",
253 [(set i64:$dst, (xor i64:$src0, i64:$src1))]
255 def S_ANDN2_B32 : SOP2_32 <0x00000014, "s_andn2_b32", []>;
256 def S_ANDN2_B64 : SOP2_64 <0x00000015, "s_andn2_b64", []>;
257 def S_ORN2_B32 : SOP2_32 <0x00000016, "s_orn2_b32", []>;
258 def S_ORN2_B64 : SOP2_64 <0x00000017, "s_orn2_b64", []>;
259 def S_NAND_B32 : SOP2_32 <0x00000018, "s_nand_b32", []>;
260 def S_NAND_B64 : SOP2_64 <0x00000019, "s_nand_b64", []>;
261 def S_NOR_B32 : SOP2_32 <0x0000001a, "s_nor_b32", []>;
262 def S_NOR_B64 : SOP2_64 <0x0000001b, "s_nor_b64", []>;
263 def S_XNOR_B32 : SOP2_32 <0x0000001c, "s_xnor_b32", []>;
264 def S_XNOR_B64 : SOP2_64 <0x0000001d, "s_xnor_b64", []>;
266 // Use added complexity so these patterns are preferred to the VALU patterns.
267 let AddedComplexity = 1 in {
269 def S_LSHL_B32 : SOP2_32 <0x0000001e, "s_lshl_b32",
270 [(set i32:$dst, (shl i32:$src0, i32:$src1))]
272 def S_LSHL_B64 : SOP2_SHIFT_64 <0x0000001f, "s_lshl_b64",
273 [(set i64:$dst, (shl i64:$src0, i32:$src1))]
275 def S_LSHR_B32 : SOP2_32 <0x00000020, "s_lshr_b32",
276 [(set i32:$dst, (srl i32:$src0, i32:$src1))]
278 def S_LSHR_B64 : SOP2_SHIFT_64 <0x00000021, "s_lshr_b64",
279 [(set i64:$dst, (srl i64:$src0, i32:$src1))]
281 def S_ASHR_I32 : SOP2_32 <0x00000022, "s_ashr_i32",
282 [(set i32:$dst, (sra i32:$src0, i32:$src1))]
284 def S_ASHR_I64 : SOP2_SHIFT_64 <0x00000023, "s_ashr_i64",
285 [(set i64:$dst, (sra i64:$src0, i32:$src1))]
289 def S_BFM_B32 : SOP2_32 <0x00000024, "s_bfm_b32", []>;
290 def S_BFM_B64 : SOP2_64 <0x00000025, "s_bfm_b64", []>;
291 def S_MUL_I32 : SOP2_32 <0x00000026, "s_mul_i32",
292 [(set i32:$dst, (mul i32:$src0, i32:$src1))]
295 } // End AddedComplexity = 1
297 def S_BFE_U32 : SOP2_32 <0x00000027, "s_bfe_u32", []>;
298 def S_BFE_I32 : SOP2_32 <0x00000028, "s_bfe_i32", []>;
299 def S_BFE_U64 : SOP2_64 <0x00000029, "s_bfe_u64", []>;
300 def S_BFE_I64 : SOP2_64_32 <0x0000002a, "s_bfe_i64", []>;
301 //def S_CBRANCH_G_FORK : SOP2_ <0x0000002b, "s_cbranch_g_fork", []>;
302 def S_ABSDIFF_I32 : SOP2_32 <0x0000002c, "s_absdiff_i32", []>;
304 //===----------------------------------------------------------------------===//
306 //===----------------------------------------------------------------------===//
308 def S_CMP_EQ_I32 : SOPC_32 <0x00000000, "s_cmp_eq_i32">;
309 def S_CMP_LG_I32 : SOPC_32 <0x00000001, "s_cmp_lg_i32">;
310 def S_CMP_GT_I32 : SOPC_32 <0x00000002, "s_cmp_gt_i32">;
311 def S_CMP_GE_I32 : SOPC_32 <0x00000003, "s_cmp_ge_i32">;
312 def S_CMP_LT_I32 : SOPC_32 <0x00000004, "s_cmp_lt_i32">;
313 def S_CMP_LE_I32 : SOPC_32 <0x00000005, "s_cmp_le_i32">;
314 def S_CMP_EQ_U32 : SOPC_32 <0x00000006, "s_cmp_eq_u32">;
315 def S_CMP_LG_U32 : SOPC_32 <0x00000007, "s_cmp_lg_u32">;
316 def S_CMP_GT_U32 : SOPC_32 <0x00000008, "s_cmp_gt_u32">;
317 def S_CMP_GE_U32 : SOPC_32 <0x00000009, "s_cmp_ge_u32">;
318 def S_CMP_LT_U32 : SOPC_32 <0x0000000a, "s_cmp_lt_u32">;
319 def S_CMP_LE_U32 : SOPC_32 <0x0000000b, "s_cmp_le_u32">;
320 ////def S_BITCMP0_B32 : SOPC_BITCMP0 <0x0000000c, "s_bitcmp0_b32", []>;
321 ////def S_BITCMP1_B32 : SOPC_BITCMP1 <0x0000000d, "s_bitcmp1_b32", []>;
322 ////def S_BITCMP0_B64 : SOPC_BITCMP0 <0x0000000e, "s_bitcmp0_b64", []>;
323 ////def S_BITCMP1_B64 : SOPC_BITCMP1 <0x0000000f, "s_bitcmp1_b64", []>;
324 //def S_SETVSKIP : SOPC_ <0x00000010, "s_setvskip", []>;
326 //===----------------------------------------------------------------------===//
328 //===----------------------------------------------------------------------===//
330 def S_MOVK_I32 : SOPK_32 <0x00000000, "s_movk_i32", []>;
331 def S_CMOVK_I32 : SOPK_32 <0x00000002, "s_cmovk_i32", []>;
334 This instruction is disabled for now until we can figure out how to teach
335 the instruction selector to correctly use the S_CMP* vs V_CMP*
338 When this instruction is enabled the code generator sometimes produces this
341 SCC = S_CMPK_EQ_I32 SGPR0, imm
343 VGPR0 = V_CNDMASK VCC, VGPR0, VGPR1
345 def S_CMPK_EQ_I32 : SOPK <
346 0x00000003, (outs SCCReg:$dst), (ins SReg_32:$src0, i32imm:$src1),
348 [(set i1:$dst, (setcc i32:$src0, imm:$src1, SETEQ))]
352 let isCompare = 1, Defs = [SCC] in {
353 def S_CMPK_LG_I32 : SOPK_32 <0x00000004, "s_cmpk_lg_i32", []>;
354 def S_CMPK_GT_I32 : SOPK_32 <0x00000005, "s_cmpk_gt_i32", []>;
355 def S_CMPK_GE_I32 : SOPK_32 <0x00000006, "s_cmpk_ge_i32", []>;
356 def S_CMPK_LT_I32 : SOPK_32 <0x00000007, "s_cmpk_lt_i32", []>;
357 def S_CMPK_LE_I32 : SOPK_32 <0x00000008, "s_cmpk_le_i32", []>;
358 def S_CMPK_EQ_U32 : SOPK_32 <0x00000009, "s_cmpk_eq_u32", []>;
359 def S_CMPK_LG_U32 : SOPK_32 <0x0000000a, "s_cmpk_lg_u32", []>;
360 def S_CMPK_GT_U32 : SOPK_32 <0x0000000b, "s_cmpk_gt_u32", []>;
361 def S_CMPK_GE_U32 : SOPK_32 <0x0000000c, "s_cmpk_ge_u32", []>;
362 def S_CMPK_LT_U32 : SOPK_32 <0x0000000d, "s_cmpk_lt_u32", []>;
363 def S_CMPK_LE_U32 : SOPK_32 <0x0000000e, "s_cmpk_le_u32", []>;
364 } // End isCompare = 1, Defs = [SCC]
366 let Defs = [SCC], isCommutable = 1 in {
367 def S_ADDK_I32 : SOPK_32 <0x0000000f, "s_addk_i32", []>;
368 def S_MULK_I32 : SOPK_32 <0x00000010, "s_mulk_i32", []>;
371 //def S_CBRANCH_I_FORK : SOPK_ <0x00000011, "s_cbranch_i_fork", []>;
372 def S_GETREG_B32 : SOPK_32 <0x00000012, "s_getreg_b32", []>;
373 def S_SETREG_B32 : SOPK_32 <0x00000013, "s_setreg_b32", []>;
374 def S_GETREG_REGRD_B32 : SOPK_32 <0x00000014, "s_getreg_regrd_b32", []>;
375 //def S_SETREG_IMM32_B32 : SOPK_32 <0x00000015, "s_setreg_imm32_b32", []>;
376 //def EXP : EXP_ <0x00000000, "exp", []>;
378 //===----------------------------------------------------------------------===//
380 //===----------------------------------------------------------------------===//
382 def S_NOP : SOPP <0x00000000, (ins i16imm:$simm16), "s_nop $simm16">;
384 let isTerminator = 1 in {
386 def S_ENDPGM : SOPP <0x00000001, (ins), "s_endpgm",
393 let isBranch = 1 in {
394 def S_BRANCH : SOPP <
395 0x00000002, (ins sopp_brtarget:$simm16), "s_branch $simm16",
400 let DisableEncoding = "$scc" in {
401 def S_CBRANCH_SCC0 : SOPP <
402 0x00000004, (ins sopp_brtarget:$simm16, SCCReg:$scc),
403 "s_cbranch_scc0 $simm16"
405 def S_CBRANCH_SCC1 : SOPP <
406 0x00000005, (ins sopp_brtarget:$simm16, SCCReg:$scc),
407 "s_cbranch_scc1 $simm16"
409 } // End DisableEncoding = "$scc"
411 def S_CBRANCH_VCCZ : SOPP <
412 0x00000006, (ins sopp_brtarget:$simm16, VCCReg:$vcc),
413 "s_cbranch_vccz $simm16"
415 def S_CBRANCH_VCCNZ : SOPP <
416 0x00000007, (ins sopp_brtarget:$simm16, VCCReg:$vcc),
417 "s_cbranch_vccnz $simm16"
420 let DisableEncoding = "$exec" in {
421 def S_CBRANCH_EXECZ : SOPP <
422 0x00000008, (ins sopp_brtarget:$simm16, EXECReg:$exec),
423 "s_cbranch_execz $simm16"
425 def S_CBRANCH_EXECNZ : SOPP <
426 0x00000009, (ins sopp_brtarget:$simm16, EXECReg:$exec),
427 "s_cbranch_execnz $simm16"
429 } // End DisableEncoding = "$exec"
432 } // End isBranch = 1
433 } // End isTerminator = 1
435 let hasSideEffects = 1 in {
436 def S_BARRIER : SOPP <0x0000000a, (ins), "s_barrier",
437 [(int_AMDGPU_barrier_local)]
446 def S_WAITCNT : SOPP <0x0000000c, (ins WAIT_FLAG:$simm16), "s_waitcnt $simm16">;
447 def S_SETHALT : SOPP <0x0000000d, (ins i16imm:$simm16), "s_sethalt $simm16">;
448 def S_SLEEP : SOPP <0x0000000e, (ins i16imm:$simm16), "s_sleep $simm16">;
449 def S_SETPRIO : SOPP <0x0000000f, (ins i16imm:$sim16), "s_setprio $sim16">;
451 let Uses = [EXEC] in {
452 def S_SENDMSG : SOPP <0x00000010, (ins SendMsgImm:$simm16, M0Reg:$m0), "s_sendmsg $simm16",
453 [(int_SI_sendmsg imm:$simm16, M0Reg:$m0)]
455 let DisableEncoding = "$m0";
457 } // End Uses = [EXEC]
459 def S_SENDMSGHALT : SOPP <0x00000011, (ins i16imm:$simm16), "s_sendmsghalt $simm16">;
460 def S_TRAP : SOPP <0x00000012, (ins i16imm:$simm16), "s_trap $simm16">;
461 def S_ICACHE_INV : SOPP <0x00000013, (ins), "s_icache_inv"> {
464 def S_INCPERFLEVEL : SOPP <0x00000014, (ins i16imm:$simm16), "s_incperflevel $simm16">;
465 def S_DECPERFLEVEL : SOPP <0x00000015, (ins i16imm:$simm16), "s_decperflevel $simm16">;
466 def S_TTRACEDATA : SOPP <0x00000016, (ins), "s_ttracedata"> {
469 } // End hasSideEffects
471 //===----------------------------------------------------------------------===//
473 //===----------------------------------------------------------------------===//
475 let isCompare = 1 in {
477 defm V_CMP_F_F32 : VOPC_F32 <vopc<0x0>, "v_cmp_f_f32">;
478 defm V_CMP_LT_F32 : VOPC_F32 <vopc<0x1>, "v_cmp_lt_f32", COND_OLT>;
479 defm V_CMP_EQ_F32 : VOPC_F32 <vopc<0x2>, "v_cmp_eq_f32", COND_OEQ>;
480 defm V_CMP_LE_F32 : VOPC_F32 <vopc<0x3>, "v_cmp_le_f32", COND_OLE>;
481 defm V_CMP_GT_F32 : VOPC_F32 <vopc<0x4>, "v_cmp_gt_f32", COND_OGT>;
482 defm V_CMP_LG_F32 : VOPC_F32 <vopc<0x5>, "v_cmp_lg_f32">;
483 defm V_CMP_GE_F32 : VOPC_F32 <vopc<0x6>, "v_cmp_ge_f32", COND_OGE>;
484 defm V_CMP_O_F32 : VOPC_F32 <vopc<0x7>, "v_cmp_o_f32", COND_O>;
485 defm V_CMP_U_F32 : VOPC_F32 <vopc<0x8>, "v_cmp_u_f32", COND_UO>;
486 defm V_CMP_NGE_F32 : VOPC_F32 <vopc<0x9>, "v_cmp_nge_f32">;
487 defm V_CMP_NLG_F32 : VOPC_F32 <vopc<0xa>, "v_cmp_nlg_f32">;
488 defm V_CMP_NGT_F32 : VOPC_F32 <vopc<0xb>, "v_cmp_ngt_f32">;
489 defm V_CMP_NLE_F32 : VOPC_F32 <vopc<0xc>, "v_cmp_nle_f32">;
490 defm V_CMP_NEQ_F32 : VOPC_F32 <vopc<0xd>, "v_cmp_neq_f32", COND_UNE>;
491 defm V_CMP_NLT_F32 : VOPC_F32 <vopc<0xe>, "v_cmp_nlt_f32">;
492 defm V_CMP_TRU_F32 : VOPC_F32 <vopc<0xf>, "v_cmp_tru_f32">;
494 let hasSideEffects = 1 in {
496 defm V_CMPX_F_F32 : VOPCX_F32 <vopc<0x10>, "v_cmpx_f_f32">;
497 defm V_CMPX_LT_F32 : VOPCX_F32 <vopc<0x11>, "v_cmpx_lt_f32">;
498 defm V_CMPX_EQ_F32 : VOPCX_F32 <vopc<0x12>, "v_cmpx_eq_f32">;
499 defm V_CMPX_LE_F32 : VOPCX_F32 <vopc<0x13>, "v_cmpx_le_f32">;
500 defm V_CMPX_GT_F32 : VOPCX_F32 <vopc<0x14>, "v_cmpx_gt_f32">;
501 defm V_CMPX_LG_F32 : VOPCX_F32 <vopc<0x15>, "v_cmpx_lg_f32">;
502 defm V_CMPX_GE_F32 : VOPCX_F32 <vopc<0x16>, "v_cmpx_ge_f32">;
503 defm V_CMPX_O_F32 : VOPCX_F32 <vopc<0x17>, "v_cmpx_o_f32">;
504 defm V_CMPX_U_F32 : VOPCX_F32 <vopc<0x18>, "v_cmpx_u_f32">;
505 defm V_CMPX_NGE_F32 : VOPCX_F32 <vopc<0x19>, "v_cmpx_nge_f32">;
506 defm V_CMPX_NLG_F32 : VOPCX_F32 <vopc<0x1a>, "v_cmpx_nlg_f32">;
507 defm V_CMPX_NGT_F32 : VOPCX_F32 <vopc<0x1b>, "v_cmpx_ngt_f32">;
508 defm V_CMPX_NLE_F32 : VOPCX_F32 <vopc<0x1c>, "v_cmpx_nle_f32">;
509 defm V_CMPX_NEQ_F32 : VOPCX_F32 <vopc<0x1d>, "v_cmpx_neq_f32">;
510 defm V_CMPX_NLT_F32 : VOPCX_F32 <vopc<0x1e>, "v_cmpx_nlt_f32">;
511 defm V_CMPX_TRU_F32 : VOPCX_F32 <vopc<0x1f>, "v_cmpx_tru_f32">;
513 } // End hasSideEffects = 1
515 defm V_CMP_F_F64 : VOPC_F64 <vopc<0x20>, "v_cmp_f_f64">;
516 defm V_CMP_LT_F64 : VOPC_F64 <vopc<0x21>, "v_cmp_lt_f64", COND_OLT>;
517 defm V_CMP_EQ_F64 : VOPC_F64 <vopc<0x22>, "v_cmp_eq_f64", COND_OEQ>;
518 defm V_CMP_LE_F64 : VOPC_F64 <vopc<0x23>, "v_cmp_le_f64", COND_OLE>;
519 defm V_CMP_GT_F64 : VOPC_F64 <vopc<0x24>, "v_cmp_gt_f64", COND_OGT>;
520 defm V_CMP_LG_F64 : VOPC_F64 <vopc<0x25>, "v_cmp_lg_f64">;
521 defm V_CMP_GE_F64 : VOPC_F64 <vopc<0x26>, "v_cmp_ge_f64", COND_OGE>;
522 defm V_CMP_O_F64 : VOPC_F64 <vopc<0x27>, "v_cmp_o_f64", COND_O>;
523 defm V_CMP_U_F64 : VOPC_F64 <vopc<0x28>, "v_cmp_u_f64", COND_UO>;
524 defm V_CMP_NGE_F64 : VOPC_F64 <vopc<0x29>, "v_cmp_nge_f64">;
525 defm V_CMP_NLG_F64 : VOPC_F64 <vopc<0x2a>, "v_cmp_nlg_f64">;
526 defm V_CMP_NGT_F64 : VOPC_F64 <vopc<0x2b>, "v_cmp_ngt_f64">;
527 defm V_CMP_NLE_F64 : VOPC_F64 <vopc<0x2c>, "v_cmp_nle_f64">;
528 defm V_CMP_NEQ_F64 : VOPC_F64 <vopc<0x2d>, "v_cmp_neq_f64", COND_UNE>;
529 defm V_CMP_NLT_F64 : VOPC_F64 <vopc<0x2e>, "v_cmp_nlt_f64">;
530 defm V_CMP_TRU_F64 : VOPC_F64 <vopc<0x2f>, "v_cmp_tru_f64">;
532 let hasSideEffects = 1 in {
534 defm V_CMPX_F_F64 : VOPCX_F64 <vopc<0x30>, "v_cmpx_f_f64">;
535 defm V_CMPX_LT_F64 : VOPCX_F64 <vopc<0x31>, "v_cmpx_lt_f64">;
536 defm V_CMPX_EQ_F64 : VOPCX_F64 <vopc<0x32>, "v_cmpx_eq_f64">;
537 defm V_CMPX_LE_F64 : VOPCX_F64 <vopc<0x33>, "v_cmpx_le_f64">;
538 defm V_CMPX_GT_F64 : VOPCX_F64 <vopc<0x34>, "v_cmpx_gt_f64">;
539 defm V_CMPX_LG_F64 : VOPCX_F64 <vopc<0x35>, "v_cmpx_lg_f64">;
540 defm V_CMPX_GE_F64 : VOPCX_F64 <vopc<0x36>, "v_cmpx_ge_f64">;
541 defm V_CMPX_O_F64 : VOPCX_F64 <vopc<0x37>, "v_cmpx_o_f64">;
542 defm V_CMPX_U_F64 : VOPCX_F64 <vopc<0x38>, "v_cmpx_u_f64">;
543 defm V_CMPX_NGE_F64 : VOPCX_F64 <vopc<0x39>, "v_cmpx_nge_f64">;
544 defm V_CMPX_NLG_F64 : VOPCX_F64 <vopc<0x3a>, "v_cmpx_nlg_f64">;
545 defm V_CMPX_NGT_F64 : VOPCX_F64 <vopc<0x3b>, "v_cmpx_ngt_f64">;
546 defm V_CMPX_NLE_F64 : VOPCX_F64 <vopc<0x3c>, "v_cmpx_nle_f64">;
547 defm V_CMPX_NEQ_F64 : VOPCX_F64 <vopc<0x3d>, "v_cmpx_neq_f64">;
548 defm V_CMPX_NLT_F64 : VOPCX_F64 <vopc<0x3e>, "v_cmpx_nlt_f64">;
549 defm V_CMPX_TRU_F64 : VOPCX_F64 <vopc<0x3f>, "v_cmpx_tru_f64">;
551 } // End hasSideEffects = 1
553 defm V_CMPS_F_F32 : VOPC_F32 <vopc<0x40>, "v_cmps_f_f32">;
554 defm V_CMPS_LT_F32 : VOPC_F32 <vopc<0x41>, "v_cmps_lt_f32">;
555 defm V_CMPS_EQ_F32 : VOPC_F32 <vopc<0x42>, "v_cmps_eq_f32">;
556 defm V_CMPS_LE_F32 : VOPC_F32 <vopc<0x43>, "v_cmps_le_f32">;
557 defm V_CMPS_GT_F32 : VOPC_F32 <vopc<0x44>, "v_cmps_gt_f32">;
558 defm V_CMPS_LG_F32 : VOPC_F32 <vopc<0x45>, "v_cmps_lg_f32">;
559 defm V_CMPS_GE_F32 : VOPC_F32 <vopc<0x46>, "v_cmps_ge_f32">;
560 defm V_CMPS_O_F32 : VOPC_F32 <vopc<0x47>, "v_cmps_o_f32">;
561 defm V_CMPS_U_F32 : VOPC_F32 <vopc<0x48>, "v_cmps_u_f32">;
562 defm V_CMPS_NGE_F32 : VOPC_F32 <vopc<0x49>, "v_cmps_nge_f32">;
563 defm V_CMPS_NLG_F32 : VOPC_F32 <vopc<0x4a>, "v_cmps_nlg_f32">;
564 defm V_CMPS_NGT_F32 : VOPC_F32 <vopc<0x4b>, "v_cmps_ngt_f32">;
565 defm V_CMPS_NLE_F32 : VOPC_F32 <vopc<0x4c>, "v_cmps_nle_f32">;
566 defm V_CMPS_NEQ_F32 : VOPC_F32 <vopc<0x4d>, "v_cmps_neq_f32">;
567 defm V_CMPS_NLT_F32 : VOPC_F32 <vopc<0x4e>, "v_cmps_nlt_f32">;
568 defm V_CMPS_TRU_F32 : VOPC_F32 <vopc<0x4f>, "v_cmps_tru_f32">;
570 let hasSideEffects = 1 in {
572 defm V_CMPSX_F_F32 : VOPCX_F32 <vopc<0x50>, "v_cmpsx_f_f32">;
573 defm V_CMPSX_LT_F32 : VOPCX_F32 <vopc<0x51>, "v_cmpsx_lt_f32">;
574 defm V_CMPSX_EQ_F32 : VOPCX_F32 <vopc<0x52>, "v_cmpsx_eq_f32">;
575 defm V_CMPSX_LE_F32 : VOPCX_F32 <vopc<0x53>, "v_cmpsx_le_f32">;
576 defm V_CMPSX_GT_F32 : VOPCX_F32 <vopc<0x54>, "v_cmpsx_gt_f32">;
577 defm V_CMPSX_LG_F32 : VOPCX_F32 <vopc<0x55>, "v_cmpsx_lg_f32">;
578 defm V_CMPSX_GE_F32 : VOPCX_F32 <vopc<0x56>, "v_cmpsx_ge_f32">;
579 defm V_CMPSX_O_F32 : VOPCX_F32 <vopc<0x57>, "v_cmpsx_o_f32">;
580 defm V_CMPSX_U_F32 : VOPCX_F32 <vopc<0x58>, "v_cmpsx_u_f32">;
581 defm V_CMPSX_NGE_F32 : VOPCX_F32 <vopc<0x59>, "v_cmpsx_nge_f32">;
582 defm V_CMPSX_NLG_F32 : VOPCX_F32 <vopc<0x5a>, "v_cmpsx_nlg_f32">;
583 defm V_CMPSX_NGT_F32 : VOPCX_F32 <vopc<0x5b>, "v_cmpsx_ngt_f32">;
584 defm V_CMPSX_NLE_F32 : VOPCX_F32 <vopc<0x5c>, "v_cmpsx_nle_f32">;
585 defm V_CMPSX_NEQ_F32 : VOPCX_F32 <vopc<0x5d>, "v_cmpsx_neq_f32">;
586 defm V_CMPSX_NLT_F32 : VOPCX_F32 <vopc<0x5e>, "v_cmpsx_nlt_f32">;
587 defm V_CMPSX_TRU_F32 : VOPCX_F32 <vopc<0x5f>, "v_cmpsx_tru_f32">;
589 } // End hasSideEffects = 1
591 defm V_CMPS_F_F64 : VOPC_F64 <vopc<0x60>, "v_cmps_f_f64">;
592 defm V_CMPS_LT_F64 : VOPC_F64 <vopc<0x61>, "v_cmps_lt_f64">;
593 defm V_CMPS_EQ_F64 : VOPC_F64 <vopc<0x62>, "v_cmps_eq_f64">;
594 defm V_CMPS_LE_F64 : VOPC_F64 <vopc<0x63>, "v_cmps_le_f64">;
595 defm V_CMPS_GT_F64 : VOPC_F64 <vopc<0x64>, "v_cmps_gt_f64">;
596 defm V_CMPS_LG_F64 : VOPC_F64 <vopc<0x65>, "v_cmps_lg_f64">;
597 defm V_CMPS_GE_F64 : VOPC_F64 <vopc<0x66>, "v_cmps_ge_f64">;
598 defm V_CMPS_O_F64 : VOPC_F64 <vopc<0x67>, "v_cmps_o_f64">;
599 defm V_CMPS_U_F64 : VOPC_F64 <vopc<0x68>, "v_cmps_u_f64">;
600 defm V_CMPS_NGE_F64 : VOPC_F64 <vopc<0x69>, "v_cmps_nge_f64">;
601 defm V_CMPS_NLG_F64 : VOPC_F64 <vopc<0x6a>, "v_cmps_nlg_f64">;
602 defm V_CMPS_NGT_F64 : VOPC_F64 <vopc<0x6b>, "v_cmps_ngt_f64">;
603 defm V_CMPS_NLE_F64 : VOPC_F64 <vopc<0x6c>, "v_cmps_nle_f64">;
604 defm V_CMPS_NEQ_F64 : VOPC_F64 <vopc<0x6d>, "v_cmps_neq_f64">;
605 defm V_CMPS_NLT_F64 : VOPC_F64 <vopc<0x6e>, "v_cmps_nlt_f64">;
606 defm V_CMPS_TRU_F64 : VOPC_F64 <vopc<0x6f>, "v_cmps_tru_f64">;
608 let hasSideEffects = 1, Defs = [EXEC] in {
610 defm V_CMPSX_F_F64 : VOPC_F64 <vopc<0x70>, "v_cmpsx_f_f64">;
611 defm V_CMPSX_LT_F64 : VOPC_F64 <vopc<0x71>, "v_cmpsx_lt_f64">;
612 defm V_CMPSX_EQ_F64 : VOPC_F64 <vopc<0x72>, "v_cmpsx_eq_f64">;
613 defm V_CMPSX_LE_F64 : VOPC_F64 <vopc<0x73>, "v_cmpsx_le_f64">;
614 defm V_CMPSX_GT_F64 : VOPC_F64 <vopc<0x74>, "v_cmpsx_gt_f64">;
615 defm V_CMPSX_LG_F64 : VOPC_F64 <vopc<0x75>, "v_cmpsx_lg_f64">;
616 defm V_CMPSX_GE_F64 : VOPC_F64 <vopc<0x76>, "v_cmpsx_ge_f64">;
617 defm V_CMPSX_O_F64 : VOPC_F64 <vopc<0x77>, "v_cmpsx_o_f64">;
618 defm V_CMPSX_U_F64 : VOPC_F64 <vopc<0x78>, "v_cmpsx_u_f64">;
619 defm V_CMPSX_NGE_F64 : VOPC_F64 <vopc<0x79>, "v_cmpsx_nge_f64">;
620 defm V_CMPSX_NLG_F64 : VOPC_F64 <vopc<0x7a>, "v_cmpsx_nlg_f64">;
621 defm V_CMPSX_NGT_F64 : VOPC_F64 <vopc<0x7b>, "v_cmpsx_ngt_f64">;
622 defm V_CMPSX_NLE_F64 : VOPC_F64 <vopc<0x7c>, "v_cmpsx_nle_f64">;
623 defm V_CMPSX_NEQ_F64 : VOPC_F64 <vopc<0x7d>, "v_cmpsx_neq_f64">;
624 defm V_CMPSX_NLT_F64 : VOPC_F64 <vopc<0x7e>, "v_cmpsx_nlt_f64">;
625 defm V_CMPSX_TRU_F64 : VOPC_F64 <vopc<0x7f>, "v_cmpsx_tru_f64">;
627 } // End hasSideEffects = 1, Defs = [EXEC]
629 defm V_CMP_F_I32 : VOPC_I32 <vopc<0x80>, "v_cmp_f_i32">;
630 defm V_CMP_LT_I32 : VOPC_I32 <vopc<0x81>, "v_cmp_lt_i32", COND_SLT>;
631 defm V_CMP_EQ_I32 : VOPC_I32 <vopc<0x82>, "v_cmp_eq_i32", COND_EQ>;
632 defm V_CMP_LE_I32 : VOPC_I32 <vopc<0x83>, "v_cmp_le_i32", COND_SLE>;
633 defm V_CMP_GT_I32 : VOPC_I32 <vopc<0x84>, "v_cmp_gt_i32", COND_SGT>;
634 defm V_CMP_NE_I32 : VOPC_I32 <vopc<0x85>, "v_cmp_ne_i32", COND_NE>;
635 defm V_CMP_GE_I32 : VOPC_I32 <vopc<0x86>, "v_cmp_ge_i32", COND_SGE>;
636 defm V_CMP_T_I32 : VOPC_I32 <vopc<0x87>, "v_cmp_t_i32">;
638 let hasSideEffects = 1 in {
640 defm V_CMPX_F_I32 : VOPCX_I32 <vopc<0x90>, "v_cmpx_f_i32">;
641 defm V_CMPX_LT_I32 : VOPCX_I32 <vopc<0x91>, "v_cmpx_lt_i32">;
642 defm V_CMPX_EQ_I32 : VOPCX_I32 <vopc<0x92>, "v_cmpx_eq_i32">;
643 defm V_CMPX_LE_I32 : VOPCX_I32 <vopc<0x93>, "v_cmpx_le_i32">;
644 defm V_CMPX_GT_I32 : VOPCX_I32 <vopc<0x94>, "v_cmpx_gt_i32">;
645 defm V_CMPX_NE_I32 : VOPCX_I32 <vopc<0x95>, "v_cmpx_ne_i32">;
646 defm V_CMPX_GE_I32 : VOPCX_I32 <vopc<0x96>, "v_cmpx_ge_i32">;
647 defm V_CMPX_T_I32 : VOPCX_I32 <vopc<0x97>, "v_cmpx_t_i32">;
649 } // End hasSideEffects = 1
651 defm V_CMP_F_I64 : VOPC_I64 <vopc<0xa0>, "v_cmp_f_i64">;
652 defm V_CMP_LT_I64 : VOPC_I64 <vopc<0xa1>, "v_cmp_lt_i64", COND_SLT>;
653 defm V_CMP_EQ_I64 : VOPC_I64 <vopc<0xa2>, "v_cmp_eq_i64", COND_EQ>;
654 defm V_CMP_LE_I64 : VOPC_I64 <vopc<0xa3>, "v_cmp_le_i64", COND_SLE>;
655 defm V_CMP_GT_I64 : VOPC_I64 <vopc<0xa4>, "v_cmp_gt_i64", COND_SGT>;
656 defm V_CMP_NE_I64 : VOPC_I64 <vopc<0xa5>, "v_cmp_ne_i64", COND_NE>;
657 defm V_CMP_GE_I64 : VOPC_I64 <vopc<0xa6>, "v_cmp_ge_i64", COND_SGE>;
658 defm V_CMP_T_I64 : VOPC_I64 <vopc<0xa7>, "v_cmp_t_i64">;
660 let hasSideEffects = 1 in {
662 defm V_CMPX_F_I64 : VOPCX_I64 <vopc<0xb0>, "v_cmpx_f_i64">;
663 defm V_CMPX_LT_I64 : VOPCX_I64 <vopc<0xb1>, "v_cmpx_lt_i64">;
664 defm V_CMPX_EQ_I64 : VOPCX_I64 <vopc<0xb2>, "v_cmpx_eq_i64">;
665 defm V_CMPX_LE_I64 : VOPCX_I64 <vopc<0xb3>, "v_cmpx_le_i64">;
666 defm V_CMPX_GT_I64 : VOPCX_I64 <vopc<0xb4>, "v_cmpx_gt_i64">;
667 defm V_CMPX_NE_I64 : VOPCX_I64 <vopc<0xb5>, "v_cmpx_ne_i64">;
668 defm V_CMPX_GE_I64 : VOPCX_I64 <vopc<0xb6>, "v_cmpx_ge_i64">;
669 defm V_CMPX_T_I64 : VOPCX_I64 <vopc<0xb7>, "v_cmpx_t_i64">;
671 } // End hasSideEffects = 1
673 defm V_CMP_F_U32 : VOPC_I32 <vopc<0xc0>, "v_cmp_f_u32">;
674 defm V_CMP_LT_U32 : VOPC_I32 <vopc<0xc1>, "v_cmp_lt_u32", COND_ULT>;
675 defm V_CMP_EQ_U32 : VOPC_I32 <vopc<0xc2>, "v_cmp_eq_u32", COND_EQ>;
676 defm V_CMP_LE_U32 : VOPC_I32 <vopc<0xc3>, "v_cmp_le_u32", COND_ULE>;
677 defm V_CMP_GT_U32 : VOPC_I32 <vopc<0xc4>, "v_cmp_gt_u32", COND_UGT>;
678 defm V_CMP_NE_U32 : VOPC_I32 <vopc<0xc5>, "v_cmp_ne_u32", COND_NE>;
679 defm V_CMP_GE_U32 : VOPC_I32 <vopc<0xc6>, "v_cmp_ge_u32", COND_UGE>;
680 defm V_CMP_T_U32 : VOPC_I32 <vopc<0xc7>, "v_cmp_t_u32">;
682 let hasSideEffects = 1 in {
684 defm V_CMPX_F_U32 : VOPCX_I32 <vopc<0xd0>, "v_cmpx_f_u32">;
685 defm V_CMPX_LT_U32 : VOPCX_I32 <vopc<0xd1>, "v_cmpx_lt_u32">;
686 defm V_CMPX_EQ_U32 : VOPCX_I32 <vopc<0xd2>, "v_cmpx_eq_u32">;
687 defm V_CMPX_LE_U32 : VOPCX_I32 <vopc<0xd3>, "v_cmpx_le_u32">;
688 defm V_CMPX_GT_U32 : VOPCX_I32 <vopc<0xd4>, "v_cmpx_gt_u32">;
689 defm V_CMPX_NE_U32 : VOPCX_I32 <vopc<0xd5>, "v_cmpx_ne_u32">;
690 defm V_CMPX_GE_U32 : VOPCX_I32 <vopc<0xd6>, "v_cmpx_ge_u32">;
691 defm V_CMPX_T_U32 : VOPCX_I32 <vopc<0xd7>, "v_cmpx_t_u32">;
693 } // End hasSideEffects = 1
695 defm V_CMP_F_U64 : VOPC_I64 <vopc<0xe0>, "v_cmp_f_u64">;
696 defm V_CMP_LT_U64 : VOPC_I64 <vopc<0xe1>, "v_cmp_lt_u64", COND_ULT>;
697 defm V_CMP_EQ_U64 : VOPC_I64 <vopc<0xe2>, "v_cmp_eq_u64", COND_EQ>;
698 defm V_CMP_LE_U64 : VOPC_I64 <vopc<0xe3>, "v_cmp_le_u64", COND_ULE>;
699 defm V_CMP_GT_U64 : VOPC_I64 <vopc<0xe4>, "v_cmp_gt_u64", COND_UGT>;
700 defm V_CMP_NE_U64 : VOPC_I64 <vopc<0xe5>, "v_cmp_ne_u64", COND_NE>;
701 defm V_CMP_GE_U64 : VOPC_I64 <vopc<0xe6>, "v_cmp_ge_u64", COND_UGE>;
702 defm V_CMP_T_U64 : VOPC_I64 <vopc<0xe7>, "v_cmp_t_u64">;
704 let hasSideEffects = 1 in {
706 defm V_CMPX_F_U64 : VOPCX_I64 <vopc<0xf0>, "v_cmpx_f_u64">;
707 defm V_CMPX_LT_U64 : VOPCX_I64 <vopc<0xf1>, "v_cmpx_lt_u64">;
708 defm V_CMPX_EQ_U64 : VOPCX_I64 <vopc<0xf2>, "v_cmpx_eq_u64">;
709 defm V_CMPX_LE_U64 : VOPCX_I64 <vopc<0xf3>, "v_cmpx_le_u64">;
710 defm V_CMPX_GT_U64 : VOPCX_I64 <vopc<0xf4>, "v_cmpx_gt_u64">;
711 defm V_CMPX_NE_U64 : VOPCX_I64 <vopc<0xf5>, "v_cmpx_ne_u64">;
712 defm V_CMPX_GE_U64 : VOPCX_I64 <vopc<0xf6>, "v_cmpx_ge_u64">;
713 defm V_CMPX_T_U64 : VOPCX_I64 <vopc<0xf7>, "v_cmpx_t_u64">;
715 } // End hasSideEffects = 1
717 defm V_CMP_CLASS_F32 : VOPC_F32 <vopc<0x88>, "v_cmp_class_f32">;
719 let hasSideEffects = 1 in {
720 defm V_CMPX_CLASS_F32 : VOPCX_F32 <vopc<0x98>, "v_cmpx_class_f32">;
721 } // End hasSideEffects = 1
723 defm V_CMP_CLASS_F64 : VOPC_F64 <vopc<0xa8>, "v_cmp_class_f64">;
725 let hasSideEffects = 1 in {
726 defm V_CMPX_CLASS_F64 : VOPCX_F64 <vopc<0xb8>, "v_cmpx_class_f64">;
727 } // End hasSideEffects = 1
729 } // End isCompare = 1
731 //===----------------------------------------------------------------------===//
733 //===----------------------------------------------------------------------===//
736 def DS_ADD_U32 : DS_1A1D_NORET <0x0, "ds_add_u32", VReg_32>;
737 def DS_SUB_U32 : DS_1A1D_NORET <0x1, "ds_sub_u32", VReg_32>;
738 def DS_RSUB_U32 : DS_1A1D_NORET <0x2, "ds_rsub_u32", VReg_32>;
739 def DS_INC_U32 : DS_1A1D_NORET <0x3, "ds_inc_u32", VReg_32>;
740 def DS_DEC_U32 : DS_1A1D_NORET <0x4, "ds_dec_u32", VReg_32>;
741 def DS_MIN_I32 : DS_1A1D_NORET <0x5, "ds_min_i32", VReg_32>;
742 def DS_MAX_I32 : DS_1A1D_NORET <0x6, "ds_max_i32", VReg_32>;
743 def DS_MIN_U32 : DS_1A1D_NORET <0x7, "ds_min_u32", VReg_32>;
744 def DS_MAX_U32 : DS_1A1D_NORET <0x8, "ds_max_u32", VReg_32>;
745 def DS_AND_B32 : DS_1A1D_NORET <0x9, "ds_and_b32", VReg_32>;
746 def DS_OR_B32 : DS_1A1D_NORET <0xa, "ds_or_b32", VReg_32>;
747 def DS_XOR_B32 : DS_1A1D_NORET <0xb, "ds_xor_b32", VReg_32>;
748 def DS_MSKOR_B32 : DS_1A1D_NORET <0xc, "ds_mskor_b32", VReg_32>;
749 def DS_CMPST_B32 : DS_1A2D_NORET <0x10, "ds_cmpst_b32", VReg_32>;
750 def DS_CMPST_F32 : DS_1A2D_NORET <0x11, "ds_cmpst_f32", VReg_32>;
751 def DS_MIN_F32 : DS_1A1D_NORET <0x12, "ds_min_f32", VReg_32>;
752 def DS_MAX_F32 : DS_1A1D_NORET <0x13, "ds_max_f32", VReg_32>;
754 def DS_ADD_RTN_U32 : DS_1A1D_RET <0x20, "ds_add_rtn_u32", VReg_32, "ds_add_u32">;
755 def DS_SUB_RTN_U32 : DS_1A1D_RET <0x21, "ds_sub_rtn_u32", VReg_32, "ds_sub_u32">;
756 def DS_RSUB_RTN_U32 : DS_1A1D_RET <0x22, "ds_rsub_rtn_u32", VReg_32, "ds_rsub_u32">;
757 def DS_INC_RTN_U32 : DS_1A1D_RET <0x23, "ds_inc_rtn_u32", VReg_32, "ds_inc_u32">;
758 def DS_DEC_RTN_U32 : DS_1A1D_RET <0x24, "ds_dec_rtn_u32", VReg_32, "ds_dec_u32">;
759 def DS_MIN_RTN_I32 : DS_1A1D_RET <0x25, "ds_min_rtn_i32", VReg_32, "ds_min_i32">;
760 def DS_MAX_RTN_I32 : DS_1A1D_RET <0x26, "ds_max_rtn_i32", VReg_32, "ds_max_i32">;
761 def DS_MIN_RTN_U32 : DS_1A1D_RET <0x27, "ds_min_rtn_u32", VReg_32, "ds_min_u32">;
762 def DS_MAX_RTN_U32 : DS_1A1D_RET <0x28, "ds_max_rtn_u32", VReg_32, "ds_max_u32">;
763 def DS_AND_RTN_B32 : DS_1A1D_RET <0x29, "ds_and_rtn_b32", VReg_32, "ds_and_b32">;
764 def DS_OR_RTN_B32 : DS_1A1D_RET <0x2a, "ds_or_rtn_b32", VReg_32, "ds_or_b32">;
765 def DS_XOR_RTN_B32 : DS_1A1D_RET <0x2b, "ds_xor_rtn_b32", VReg_32, "ds_xor_b32">;
766 def DS_MSKOR_RTN_B32 : DS_1A1D_RET <0x2c, "ds_mskor_rtn_b32", VReg_32, "ds_mskor_b32">;
767 def DS_WRXCHG_RTN_B32 : DS_1A1D_RET <0x2d, "ds_wrxchg_rtn_b32", VReg_32>;
768 //def DS_WRXCHG2_RTN_B32 : DS_2A0D_RET <0x2e, "ds_wrxchg2_rtn_b32", VReg_32, "ds_wrxchg2_b32">;
769 //def DS_WRXCHG2ST64_RTN_B32 : DS_2A0D_RET <0x2f, "ds_wrxchg2_rtn_b32", VReg_32, "ds_wrxchg2st64_b32">;
770 def DS_CMPST_RTN_B32 : DS_1A2D_RET <0x30, "ds_cmpst_rtn_b32", VReg_32, "ds_cmpst_b32">;
771 def DS_CMPST_RTN_F32 : DS_1A2D_RET <0x31, "ds_cmpst_rtn_f32", VReg_32, "ds_cmpst_f32">;
772 def DS_MIN_RTN_F32 : DS_1A1D_RET <0x32, "ds_min_rtn_f32", VReg_32, "ds_min_f32">;
773 def DS_MAX_RTN_F32 : DS_1A1D_RET <0x33, "ds_max_rtn_f32", VReg_32, "ds_max_f32">;
775 let SubtargetPredicate = isCI in {
776 def DS_WRAP_RTN_F32 : DS_1A1D_RET <0x34, "ds_wrap_rtn_f32", VReg_32, "ds_wrap_f32">;
780 def DS_ADD_U64 : DS_1A1D_NORET <0x40, "ds_add_u64", VReg_64>;
781 def DS_SUB_U64 : DS_1A1D_NORET <0x41, "ds_sub_u64", VReg_64>;
782 def DS_RSUB_U64 : DS_1A1D_NORET <0x42, "ds_rsub_u64", VReg_64>;
783 def DS_INC_U64 : DS_1A1D_NORET <0x43, "ds_inc_u64", VReg_64>;
784 def DS_DEC_U64 : DS_1A1D_NORET <0x44, "ds_dec_u64", VReg_64>;
785 def DS_MIN_I64 : DS_1A1D_NORET <0x45, "ds_min_i64", VReg_64>;
786 def DS_MAX_I64 : DS_1A1D_NORET <0x46, "ds_max_i64", VReg_64>;
787 def DS_MIN_U64 : DS_1A1D_NORET <0x47, "ds_min_u64", VReg_64>;
788 def DS_MAX_U64 : DS_1A1D_NORET <0x48, "ds_max_u64", VReg_64>;
789 def DS_AND_B64 : DS_1A1D_NORET <0x49, "ds_and_b64", VReg_64>;
790 def DS_OR_B64 : DS_1A1D_NORET <0x4a, "ds_or_b64", VReg_64>;
791 def DS_XOR_B64 : DS_1A1D_NORET <0x4b, "ds_xor_b64", VReg_64>;
792 def DS_MSKOR_B64 : DS_1A1D_NORET <0x4c, "ds_mskor_b64", VReg_64>;
793 def DS_CMPST_B64 : DS_1A2D_NORET <0x50, "ds_cmpst_b64", VReg_64>;
794 def DS_CMPST_F64 : DS_1A2D_NORET <0x51, "ds_cmpst_f64", VReg_64>;
795 def DS_MIN_F64 : DS_1A1D_NORET <0x52, "ds_min_f64", VReg_64>;
796 def DS_MAX_F64 : DS_1A1D_NORET <0x53, "ds_max_f64", VReg_64>;
798 def DS_ADD_RTN_U64 : DS_1A1D_RET <0x60, "ds_add_rtn_u64", VReg_64, "ds_add_u64">;
799 def DS_SUB_RTN_U64 : DS_1A1D_RET <0x61, "ds_sub_rtn_u64", VReg_64, "ds_sub_u64">;
800 def DS_RSUB_RTN_U64 : DS_1A1D_RET <0x62, "ds_rsub_rtn_u64", VReg_64, "ds_rsub_u64">;
801 def DS_INC_RTN_U64 : DS_1A1D_RET <0x63, "ds_inc_rtn_u64", VReg_64, "ds_inc_u64">;
802 def DS_DEC_RTN_U64 : DS_1A1D_RET <0x64, "ds_dec_rtn_u64", VReg_64, "ds_dec_u64">;
803 def DS_MIN_RTN_I64 : DS_1A1D_RET <0x65, "ds_min_rtn_i64", VReg_64, "ds_min_i64">;
804 def DS_MAX_RTN_I64 : DS_1A1D_RET <0x66, "ds_max_rtn_i64", VReg_64, "ds_max_i64">;
805 def DS_MIN_RTN_U64 : DS_1A1D_RET <0x67, "ds_min_rtn_u64", VReg_64, "ds_min_u64">;
806 def DS_MAX_RTN_U64 : DS_1A1D_RET <0x68, "ds_max_rtn_u64", VReg_64, "ds_max_u64">;
807 def DS_AND_RTN_B64 : DS_1A1D_RET <0x69, "ds_and_rtn_b64", VReg_64, "ds_and_b64">;
808 def DS_OR_RTN_B64 : DS_1A1D_RET <0x6a, "ds_or_rtn_b64", VReg_64, "ds_or_b64">;
809 def DS_XOR_RTN_B64 : DS_1A1D_RET <0x6b, "ds_xor_rtn_b64", VReg_64, "ds_xor_b64">;
810 def DS_MSKOR_RTN_B64 : DS_1A1D_RET <0x6c, "ds_mskor_rtn_b64", VReg_64, "ds_mskor_b64">;
811 def DS_WRXCHG_RTN_B64 : DS_1A1D_RET <0x6d, "ds_wrxchg_rtn_b64", VReg_64, "ds_wrxchg_b64">;
812 //def DS_WRXCHG2_RTN_B64 : DS_2A0D_RET <0x6e, "ds_wrxchg2_rtn_b64", VReg_64, "ds_wrxchg2_b64">;
813 //def DS_WRXCHG2ST64_RTN_B64 : DS_2A0D_RET <0x6f, "ds_wrxchg2_rtn_b64", VReg_64, "ds_wrxchg2st64_b64">;
814 def DS_CMPST_RTN_B64 : DS_1A2D_RET <0x70, "ds_cmpst_rtn_b64", VReg_64, "ds_cmpst_b64">;
815 def DS_CMPST_RTN_F64 : DS_1A2D_RET <0x71, "ds_cmpst_rtn_f64", VReg_64, "ds_cmpst_f64">;
816 def DS_MIN_RTN_F64 : DS_1A1D_RET <0x72, "ds_min_f64", VReg_64, "ds_min_f64">;
817 def DS_MAX_RTN_F64 : DS_1A1D_RET <0x73, "ds_max_f64", VReg_64, "ds_max_f64">;
819 //let SubtargetPredicate = isCI in {
820 // DS_CONDXCHG32_RTN_B64
821 // DS_CONDXCHG32_RTN_B128
824 // TODO: _SRC2_* forms
826 def DS_WRITE_B32 : DS_Store_Helper <0x0000000d, "ds_write_b32", VReg_32>;
827 def DS_WRITE_B8 : DS_Store_Helper <0x00000001e, "ds_write_b8", VReg_32>;
828 def DS_WRITE_B16 : DS_Store_Helper <0x00000001f, "ds_write_b16", VReg_32>;
829 def DS_WRITE_B64 : DS_Store_Helper <0x00000004d, "ds_write_b64", VReg_64>;
831 def DS_READ_B32 : DS_Load_Helper <0x00000036, "ds_read_b32", VReg_32>;
832 def DS_READ_I8 : DS_Load_Helper <0x00000039, "ds_read_i8", VReg_32>;
833 def DS_READ_U8 : DS_Load_Helper <0x0000003a, "ds_read_u8", VReg_32>;
834 def DS_READ_I16 : DS_Load_Helper <0x0000003b, "ds_read_i16", VReg_32>;
835 def DS_READ_U16 : DS_Load_Helper <0x0000003c, "ds_read_u16", VReg_32>;
836 def DS_READ_B64 : DS_Load_Helper <0x00000076, "ds_read_b64", VReg_64>;
839 def DS_WRITE2_B32 : DS_Store2_Helper <0x0000000E, "ds_write2_b32", VReg_32>;
840 def DS_WRITE2ST64_B32 : DS_Store2_Helper <0x0000000F, "ds_write2st64_b32", VReg_32>;
841 def DS_WRITE2_B64 : DS_Store2_Helper <0x0000004E, "ds_write2_b64", VReg_64>;
842 def DS_WRITE2ST64_B64 : DS_Store2_Helper <0x0000004F, "ds_write2st64_b64", VReg_64>;
844 def DS_READ2_B32 : DS_Load2_Helper <0x00000037, "ds_read2_b32", VReg_64>;
845 def DS_READ2ST64_B32 : DS_Load2_Helper <0x00000038, "ds_read2st64_b32", VReg_64>;
846 def DS_READ2_B64 : DS_Load2_Helper <0x00000075, "ds_read2_b64", VReg_128>;
847 def DS_READ2ST64_B64 : DS_Load2_Helper <0x00000076, "ds_read2st64_b64", VReg_128>;
849 //===----------------------------------------------------------------------===//
850 // MUBUF Instructions
851 //===----------------------------------------------------------------------===//
853 //def BUFFER_LOAD_FORMAT_X : MUBUF_ <0x00000000, "buffer_load_format_x", []>;
854 //def BUFFER_LOAD_FORMAT_XY : MUBUF_ <0x00000001, "buffer_load_format_xy", []>;
855 //def BUFFER_LOAD_FORMAT_XYZ : MUBUF_ <0x00000002, "buffer_load_format_xyz", []>;
856 defm BUFFER_LOAD_FORMAT_XYZW : MUBUF_Load_Helper <0x00000003, "buffer_load_format_xyzw", VReg_128>;
857 //def BUFFER_STORE_FORMAT_X : MUBUF_ <0x00000004, "buffer_store_format_x", []>;
858 //def BUFFER_STORE_FORMAT_XY : MUBUF_ <0x00000005, "buffer_store_format_xy", []>;
859 //def BUFFER_STORE_FORMAT_XYZ : MUBUF_ <0x00000006, "buffer_store_format_xyz", []>;
860 //def BUFFER_STORE_FORMAT_XYZW : MUBUF_ <0x00000007, "buffer_store_format_xyzw", []>;
861 defm BUFFER_LOAD_UBYTE : MUBUF_Load_Helper <
862 0x00000008, "buffer_load_ubyte", VReg_32, i32, az_extloadi8_global
864 defm BUFFER_LOAD_SBYTE : MUBUF_Load_Helper <
865 0x00000009, "buffer_load_sbyte", VReg_32, i32, sextloadi8_global
867 defm BUFFER_LOAD_USHORT : MUBUF_Load_Helper <
868 0x0000000a, "buffer_load_ushort", VReg_32, i32, az_extloadi16_global
870 defm BUFFER_LOAD_SSHORT : MUBUF_Load_Helper <
871 0x0000000b, "buffer_load_sshort", VReg_32, i32, sextloadi16_global
873 defm BUFFER_LOAD_DWORD : MUBUF_Load_Helper <
874 0x0000000c, "buffer_load_dword", VReg_32, i32, global_load
876 defm BUFFER_LOAD_DWORDX2 : MUBUF_Load_Helper <
877 0x0000000d, "buffer_load_dwordx2", VReg_64, v2i32, global_load
879 defm BUFFER_LOAD_DWORDX4 : MUBUF_Load_Helper <
880 0x0000000e, "buffer_load_dwordx4", VReg_128, v4i32, global_load
883 defm BUFFER_STORE_BYTE : MUBUF_Store_Helper <
884 0x00000018, "buffer_store_byte", VReg_32, i32, truncstorei8_global
887 defm BUFFER_STORE_SHORT : MUBUF_Store_Helper <
888 0x0000001a, "buffer_store_short", VReg_32, i32, truncstorei16_global
891 defm BUFFER_STORE_DWORD : MUBUF_Store_Helper <
892 0x0000001c, "buffer_store_dword", VReg_32, i32, global_store
895 defm BUFFER_STORE_DWORDX2 : MUBUF_Store_Helper <
896 0x0000001d, "buffer_store_dwordx2", VReg_64, v2i32, global_store
899 defm BUFFER_STORE_DWORDX4 : MUBUF_Store_Helper <
900 0x0000001e, "buffer_store_dwordx4", VReg_128, v4i32, global_store
902 //def BUFFER_ATOMIC_SWAP : MUBUF_ <0x00000030, "buffer_atomic_swap", []>;
903 defm BUFFER_ATOMIC_SWAP : MUBUF_Atomic <
904 0x00000030, "buffer_atomic_swap", VReg_32, i32, atomic_swap_global
906 //def BUFFER_ATOMIC_CMPSWAP : MUBUF_ <0x00000031, "buffer_atomic_cmpswap", []>;
907 defm BUFFER_ATOMIC_ADD : MUBUF_Atomic <
908 0x00000032, "buffer_atomic_add", VReg_32, i32, atomic_add_global
910 defm BUFFER_ATOMIC_SUB : MUBUF_Atomic <
911 0x00000033, "buffer_atomic_sub", VReg_32, i32, atomic_sub_global
913 //def BUFFER_ATOMIC_RSUB : MUBUF_ <0x00000034, "buffer_atomic_rsub", []>;
914 defm BUFFER_ATOMIC_SMIN : MUBUF_Atomic <
915 0x00000035, "buffer_atomic_smin", VReg_32, i32, atomic_min_global
917 defm BUFFER_ATOMIC_UMIN : MUBUF_Atomic <
918 0x00000036, "buffer_atomic_umin", VReg_32, i32, atomic_umin_global
920 defm BUFFER_ATOMIC_SMAX : MUBUF_Atomic <
921 0x00000037, "buffer_atomic_smax", VReg_32, i32, atomic_max_global
923 defm BUFFER_ATOMIC_UMAX : MUBUF_Atomic <
924 0x00000038, "buffer_atomic_umax", VReg_32, i32, atomic_umax_global
926 defm BUFFER_ATOMIC_AND : MUBUF_Atomic <
927 0x00000039, "buffer_atomic_and", VReg_32, i32, atomic_and_global
929 defm BUFFER_ATOMIC_OR : MUBUF_Atomic <
930 0x0000003a, "buffer_atomic_or", VReg_32, i32, atomic_or_global
932 defm BUFFER_ATOMIC_XOR : MUBUF_Atomic <
933 0x0000003b, "buffer_atomic_xor", VReg_32, i32, atomic_xor_global
935 //def BUFFER_ATOMIC_INC : MUBUF_ <0x0000003c, "buffer_atomic_inc", []>;
936 //def BUFFER_ATOMIC_DEC : MUBUF_ <0x0000003d, "buffer_atomic_dec", []>;
937 //def BUFFER_ATOMIC_FCMPSWAP : MUBUF_ <0x0000003e, "buffer_atomic_fcmpswap", []>;
938 //def BUFFER_ATOMIC_FMIN : MUBUF_ <0x0000003f, "buffer_atomic_fmin", []>;
939 //def BUFFER_ATOMIC_FMAX : MUBUF_ <0x00000040, "buffer_atomic_fmax", []>;
940 //def BUFFER_ATOMIC_SWAP_X2 : MUBUF_X2 <0x00000050, "buffer_atomic_swap_x2", []>;
941 //def BUFFER_ATOMIC_CMPSWAP_X2 : MUBUF_X2 <0x00000051, "buffer_atomic_cmpswap_x2", []>;
942 //def BUFFER_ATOMIC_ADD_X2 : MUBUF_X2 <0x00000052, "buffer_atomic_add_x2", []>;
943 //def BUFFER_ATOMIC_SUB_X2 : MUBUF_X2 <0x00000053, "buffer_atomic_sub_x2", []>;
944 //def BUFFER_ATOMIC_RSUB_X2 : MUBUF_X2 <0x00000054, "buffer_atomic_rsub_x2", []>;
945 //def BUFFER_ATOMIC_SMIN_X2 : MUBUF_X2 <0x00000055, "buffer_atomic_smin_x2", []>;
946 //def BUFFER_ATOMIC_UMIN_X2 : MUBUF_X2 <0x00000056, "buffer_atomic_umin_x2", []>;
947 //def BUFFER_ATOMIC_SMAX_X2 : MUBUF_X2 <0x00000057, "buffer_atomic_smax_x2", []>;
948 //def BUFFER_ATOMIC_UMAX_X2 : MUBUF_X2 <0x00000058, "buffer_atomic_umax_x2", []>;
949 //def BUFFER_ATOMIC_AND_X2 : MUBUF_X2 <0x00000059, "buffer_atomic_and_x2", []>;
950 //def BUFFER_ATOMIC_OR_X2 : MUBUF_X2 <0x0000005a, "buffer_atomic_or_x2", []>;
951 //def BUFFER_ATOMIC_XOR_X2 : MUBUF_X2 <0x0000005b, "buffer_atomic_xor_x2", []>;
952 //def BUFFER_ATOMIC_INC_X2 : MUBUF_X2 <0x0000005c, "buffer_atomic_inc_x2", []>;
953 //def BUFFER_ATOMIC_DEC_X2 : MUBUF_X2 <0x0000005d, "buffer_atomic_dec_x2", []>;
954 //def BUFFER_ATOMIC_FCMPSWAP_X2 : MUBUF_X2 <0x0000005e, "buffer_atomic_fcmpswap_x2", []>;
955 //def BUFFER_ATOMIC_FMIN_X2 : MUBUF_X2 <0x0000005f, "buffer_atomic_fmin_x2", []>;
956 //def BUFFER_ATOMIC_FMAX_X2 : MUBUF_X2 <0x00000060, "buffer_atomic_fmax_x2", []>;
957 //def BUFFER_WBINVL1_SC : MUBUF_WBINVL1 <0x00000070, "buffer_wbinvl1_sc", []>;
958 //def BUFFER_WBINVL1 : MUBUF_WBINVL1 <0x00000071, "buffer_wbinvl1", []>;
960 //===----------------------------------------------------------------------===//
961 // MTBUF Instructions
962 //===----------------------------------------------------------------------===//
964 //def TBUFFER_LOAD_FORMAT_X : MTBUF_ <0x00000000, "tbuffer_load_format_x", []>;
965 //def TBUFFER_LOAD_FORMAT_XY : MTBUF_ <0x00000001, "tbuffer_load_format_xy", []>;
966 //def TBUFFER_LOAD_FORMAT_XYZ : MTBUF_ <0x00000002, "tbuffer_load_format_xyz", []>;
967 defm TBUFFER_LOAD_FORMAT_XYZW : MTBUF_Load_Helper <0x00000003, "tbuffer_load_format_xyzw", VReg_128>;
968 defm TBUFFER_STORE_FORMAT_X : MTBUF_Store_Helper <0x00000004, "tbuffer_store_format_x", VReg_32>;
969 defm TBUFFER_STORE_FORMAT_XY : MTBUF_Store_Helper <0x00000005, "tbuffer_store_format_xy", VReg_64>;
970 defm TBUFFER_STORE_FORMAT_XYZ : MTBUF_Store_Helper <0x00000006, "tbuffer_store_format_xyz", VReg_128>;
971 defm TBUFFER_STORE_FORMAT_XYZW : MTBUF_Store_Helper <0x00000007, "tbuffer_store_format_xyzw", VReg_128>;
973 //===----------------------------------------------------------------------===//
975 //===----------------------------------------------------------------------===//
977 defm IMAGE_LOAD : MIMG_NoSampler <0x00000000, "image_load">;
978 defm IMAGE_LOAD_MIP : MIMG_NoSampler <0x00000001, "image_load_mip">;
979 //def IMAGE_LOAD_PCK : MIMG_NoPattern_ <"image_load_pck", 0x00000002>;
980 //def IMAGE_LOAD_PCK_SGN : MIMG_NoPattern_ <"image_load_pck_sgn", 0x00000003>;
981 //def IMAGE_LOAD_MIP_PCK : MIMG_NoPattern_ <"image_load_mip_pck", 0x00000004>;
982 //def IMAGE_LOAD_MIP_PCK_SGN : MIMG_NoPattern_ <"image_load_mip_pck_sgn", 0x00000005>;
983 //def IMAGE_STORE : MIMG_NoPattern_ <"image_store", 0x00000008>;
984 //def IMAGE_STORE_MIP : MIMG_NoPattern_ <"image_store_mip", 0x00000009>;
985 //def IMAGE_STORE_PCK : MIMG_NoPattern_ <"image_store_pck", 0x0000000a>;
986 //def IMAGE_STORE_MIP_PCK : MIMG_NoPattern_ <"image_store_mip_pck", 0x0000000b>;
987 defm IMAGE_GET_RESINFO : MIMG_NoSampler <0x0000000e, "image_get_resinfo">;
988 //def IMAGE_ATOMIC_SWAP : MIMG_NoPattern_ <"image_atomic_swap", 0x0000000f>;
989 //def IMAGE_ATOMIC_CMPSWAP : MIMG_NoPattern_ <"image_atomic_cmpswap", 0x00000010>;
990 //def IMAGE_ATOMIC_ADD : MIMG_NoPattern_ <"image_atomic_add", 0x00000011>;
991 //def IMAGE_ATOMIC_SUB : MIMG_NoPattern_ <"image_atomic_sub", 0x00000012>;
992 //def IMAGE_ATOMIC_RSUB : MIMG_NoPattern_ <"image_atomic_rsub", 0x00000013>;
993 //def IMAGE_ATOMIC_SMIN : MIMG_NoPattern_ <"image_atomic_smin", 0x00000014>;
994 //def IMAGE_ATOMIC_UMIN : MIMG_NoPattern_ <"image_atomic_umin", 0x00000015>;
995 //def IMAGE_ATOMIC_SMAX : MIMG_NoPattern_ <"image_atomic_smax", 0x00000016>;
996 //def IMAGE_ATOMIC_UMAX : MIMG_NoPattern_ <"image_atomic_umax", 0x00000017>;
997 //def IMAGE_ATOMIC_AND : MIMG_NoPattern_ <"image_atomic_and", 0x00000018>;
998 //def IMAGE_ATOMIC_OR : MIMG_NoPattern_ <"image_atomic_or", 0x00000019>;
999 //def IMAGE_ATOMIC_XOR : MIMG_NoPattern_ <"image_atomic_xor", 0x0000001a>;
1000 //def IMAGE_ATOMIC_INC : MIMG_NoPattern_ <"image_atomic_inc", 0x0000001b>;
1001 //def IMAGE_ATOMIC_DEC : MIMG_NoPattern_ <"image_atomic_dec", 0x0000001c>;
1002 //def IMAGE_ATOMIC_FCMPSWAP : MIMG_NoPattern_ <"image_atomic_fcmpswap", 0x0000001d>;
1003 //def IMAGE_ATOMIC_FMIN : MIMG_NoPattern_ <"image_atomic_fmin", 0x0000001e>;
1004 //def IMAGE_ATOMIC_FMAX : MIMG_NoPattern_ <"image_atomic_fmax", 0x0000001f>;
1005 defm IMAGE_SAMPLE : MIMG_Sampler <0x00000020, "image_sample">;
1006 defm IMAGE_SAMPLE_CL : MIMG_Sampler <0x00000021, "image_sample_cl">;
1007 defm IMAGE_SAMPLE_D : MIMG_Sampler <0x00000022, "image_sample_d">;
1008 defm IMAGE_SAMPLE_D_CL : MIMG_Sampler <0x00000023, "image_sample_d_cl">;
1009 defm IMAGE_SAMPLE_L : MIMG_Sampler <0x00000024, "image_sample_l">;
1010 defm IMAGE_SAMPLE_B : MIMG_Sampler <0x00000025, "image_sample_b">;
1011 defm IMAGE_SAMPLE_B_CL : MIMG_Sampler <0x00000026, "image_sample_b_cl">;
1012 defm IMAGE_SAMPLE_LZ : MIMG_Sampler <0x00000027, "image_sample_lz">;
1013 defm IMAGE_SAMPLE_C : MIMG_Sampler <0x00000028, "image_sample_c">;
1014 defm IMAGE_SAMPLE_C_CL : MIMG_Sampler <0x00000029, "image_sample_c_cl">;
1015 defm IMAGE_SAMPLE_C_D : MIMG_Sampler <0x0000002a, "image_sample_c_d">;
1016 defm IMAGE_SAMPLE_C_D_CL : MIMG_Sampler <0x0000002b, "image_sample_c_d_cl">;
1017 defm IMAGE_SAMPLE_C_L : MIMG_Sampler <0x0000002c, "image_sample_c_l">;
1018 defm IMAGE_SAMPLE_C_B : MIMG_Sampler <0x0000002d, "image_sample_c_b">;
1019 defm IMAGE_SAMPLE_C_B_CL : MIMG_Sampler <0x0000002e, "image_sample_c_b_cl">;
1020 defm IMAGE_SAMPLE_C_LZ : MIMG_Sampler <0x0000002f, "image_sample_c_lz">;
1021 defm IMAGE_SAMPLE_O : MIMG_Sampler <0x00000030, "image_sample_o">;
1022 defm IMAGE_SAMPLE_CL_O : MIMG_Sampler <0x00000031, "image_sample_cl_o">;
1023 defm IMAGE_SAMPLE_D_O : MIMG_Sampler <0x00000032, "image_sample_d_o">;
1024 defm IMAGE_SAMPLE_D_CL_O : MIMG_Sampler <0x00000033, "image_sample_d_cl_o">;
1025 defm IMAGE_SAMPLE_L_O : MIMG_Sampler <0x00000034, "image_sample_l_o">;
1026 defm IMAGE_SAMPLE_B_O : MIMG_Sampler <0x00000035, "image_sample_b_o">;
1027 defm IMAGE_SAMPLE_B_CL_O : MIMG_Sampler <0x00000036, "image_sample_b_cl_o">;
1028 defm IMAGE_SAMPLE_LZ_O : MIMG_Sampler <0x00000037, "image_sample_lz_o">;
1029 defm IMAGE_SAMPLE_C_O : MIMG_Sampler <0x00000038, "image_sample_c_o">;
1030 defm IMAGE_SAMPLE_C_CL_O : MIMG_Sampler <0x00000039, "image_sample_c_cl_o">;
1031 defm IMAGE_SAMPLE_C_D_O : MIMG_Sampler <0x0000003a, "image_sample_c_d_o">;
1032 defm IMAGE_SAMPLE_C_D_CL_O : MIMG_Sampler <0x0000003b, "image_sample_c_d_cl_o">;
1033 defm IMAGE_SAMPLE_C_L_O : MIMG_Sampler <0x0000003c, "image_sample_c_l_o">;
1034 defm IMAGE_SAMPLE_C_B_O : MIMG_Sampler <0x0000003d, "image_sample_c_b_o">;
1035 defm IMAGE_SAMPLE_C_B_CL_O : MIMG_Sampler <0x0000003e, "image_sample_c_b_cl_o">;
1036 defm IMAGE_SAMPLE_C_LZ_O : MIMG_Sampler <0x0000003f, "image_sample_c_lz_o">;
1037 defm IMAGE_GATHER4 : MIMG_Gather <0x00000040, "image_gather4">;
1038 defm IMAGE_GATHER4_CL : MIMG_Gather <0x00000041, "image_gather4_cl">;
1039 defm IMAGE_GATHER4_L : MIMG_Gather <0x00000044, "image_gather4_l">;
1040 defm IMAGE_GATHER4_B : MIMG_Gather <0x00000045, "image_gather4_b">;
1041 defm IMAGE_GATHER4_B_CL : MIMG_Gather <0x00000046, "image_gather4_b_cl">;
1042 defm IMAGE_GATHER4_LZ : MIMG_Gather <0x00000047, "image_gather4_lz">;
1043 defm IMAGE_GATHER4_C : MIMG_Gather <0x00000048, "image_gather4_c">;
1044 defm IMAGE_GATHER4_C_CL : MIMG_Gather <0x00000049, "image_gather4_c_cl">;
1045 defm IMAGE_GATHER4_C_L : MIMG_Gather <0x0000004c, "image_gather4_c_l">;
1046 defm IMAGE_GATHER4_C_B : MIMG_Gather <0x0000004d, "image_gather4_c_b">;
1047 defm IMAGE_GATHER4_C_B_CL : MIMG_Gather <0x0000004e, "image_gather4_c_b_cl">;
1048 defm IMAGE_GATHER4_C_LZ : MIMG_Gather <0x0000004f, "image_gather4_c_lz">;
1049 defm IMAGE_GATHER4_O : MIMG_Gather <0x00000050, "image_gather4_o">;
1050 defm IMAGE_GATHER4_CL_O : MIMG_Gather <0x00000051, "image_gather4_cl_o">;
1051 defm IMAGE_GATHER4_L_O : MIMG_Gather <0x00000054, "image_gather4_l_o">;
1052 defm IMAGE_GATHER4_B_O : MIMG_Gather <0x00000055, "image_gather4_b_o">;
1053 defm IMAGE_GATHER4_B_CL_O : MIMG_Gather <0x00000056, "image_gather4_b_cl_o">;
1054 defm IMAGE_GATHER4_LZ_O : MIMG_Gather <0x00000057, "image_gather4_lz_o">;
1055 defm IMAGE_GATHER4_C_O : MIMG_Gather <0x00000058, "image_gather4_c_o">;
1056 defm IMAGE_GATHER4_C_CL_O : MIMG_Gather <0x00000059, "image_gather4_c_cl_o">;
1057 defm IMAGE_GATHER4_C_L_O : MIMG_Gather <0x0000005c, "image_gather4_c_l_o">;
1058 defm IMAGE_GATHER4_C_B_O : MIMG_Gather <0x0000005d, "image_gather4_c_b_o">;
1059 defm IMAGE_GATHER4_C_B_CL_O : MIMG_Gather <0x0000005e, "image_gather4_c_b_cl_o">;
1060 defm IMAGE_GATHER4_C_LZ_O : MIMG_Gather <0x0000005f, "image_gather4_c_lz_o">;
1061 defm IMAGE_GET_LOD : MIMG_Sampler <0x00000060, "image_get_lod">;
1062 defm IMAGE_SAMPLE_CD : MIMG_Sampler <0x00000068, "image_sample_cd">;
1063 defm IMAGE_SAMPLE_CD_CL : MIMG_Sampler <0x00000069, "image_sample_cd_cl">;
1064 defm IMAGE_SAMPLE_C_CD : MIMG_Sampler <0x0000006a, "image_sample_c_cd">;
1065 defm IMAGE_SAMPLE_C_CD_CL : MIMG_Sampler <0x0000006b, "image_sample_c_cd_cl">;
1066 defm IMAGE_SAMPLE_CD_O : MIMG_Sampler <0x0000006c, "image_sample_cd_o">;
1067 defm IMAGE_SAMPLE_CD_CL_O : MIMG_Sampler <0x0000006d, "image_sample_cd_cl_o">;
1068 defm IMAGE_SAMPLE_C_CD_O : MIMG_Sampler <0x0000006e, "image_sample_c_cd_o">;
1069 defm IMAGE_SAMPLE_C_CD_CL_O : MIMG_Sampler <0x0000006f, "image_sample_c_cd_cl_o">;
1070 //def IMAGE_RSRC256 : MIMG_NoPattern_RSRC256 <"image_rsrc256", 0x0000007e>;
1071 //def IMAGE_SAMPLER : MIMG_NoPattern_ <"image_sampler", 0x0000007f>;
1073 //===----------------------------------------------------------------------===//
1074 // Flat Instructions
1075 //===----------------------------------------------------------------------===//
1077 let Predicates = [HasFlatAddressSpace] in {
1078 def FLAT_LOAD_UBYTE : FLAT_Load_Helper <0x00000008, "flat_load_ubyte", VReg_32>;
1079 def FLAT_LOAD_SBYTE : FLAT_Load_Helper <0x00000009, "flat_load_sbyte", VReg_32>;
1080 def FLAT_LOAD_USHORT : FLAT_Load_Helper <0x0000000a, "flat_load_ushort", VReg_32>;
1081 def FLAT_LOAD_SSHORT : FLAT_Load_Helper <0x0000000b, "flat_load_sshort", VReg_32>;
1082 def FLAT_LOAD_DWORD : FLAT_Load_Helper <0x0000000c, "flat_load_dword", VReg_32>;
1083 def FLAT_LOAD_DWORDX2 : FLAT_Load_Helper <0x0000000d, "flat_load_dwordx2", VReg_64>;
1084 def FLAT_LOAD_DWORDX4 : FLAT_Load_Helper <0x0000000e, "flat_load_dwordx4", VReg_128>;
1085 def FLAT_LOAD_DWORDX3 : FLAT_Load_Helper <0x00000010, "flat_load_dwordx3", VReg_96>;
1087 def FLAT_STORE_BYTE : FLAT_Store_Helper <
1088 0x00000018, "flat_store_byte", VReg_32
1091 def FLAT_STORE_SHORT : FLAT_Store_Helper <
1092 0x0000001a, "flat_store_short", VReg_32
1095 def FLAT_STORE_DWORD : FLAT_Store_Helper <
1096 0x0000001c, "flat_store_dword", VReg_32
1099 def FLAT_STORE_DWORDX2 : FLAT_Store_Helper <
1100 0x0000001d, "flat_store_dwordx2", VReg_64
1103 def FLAT_STORE_DWORDX4 : FLAT_Store_Helper <
1104 0x0000001e, "flat_store_dwordx4", VReg_128
1107 def FLAT_STORE_DWORDX3 : FLAT_Store_Helper <
1108 0x0000001e, "flat_store_dwordx3", VReg_96
1111 //def FLAT_ATOMIC_SWAP : FLAT_ <0x00000030, "flat_atomic_swap", []>;
1112 //def FLAT_ATOMIC_CMPSWAP : FLAT_ <0x00000031, "flat_atomic_cmpswap", []>;
1113 //def FLAT_ATOMIC_ADD : FLAT_ <0x00000032, "flat_atomic_add", []>;
1114 //def FLAT_ATOMIC_SUB : FLAT_ <0x00000033, "flat_atomic_sub", []>;
1115 //def FLAT_ATOMIC_RSUB : FLAT_ <0x00000034, "flat_atomic_rsub", []>;
1116 //def FLAT_ATOMIC_SMIN : FLAT_ <0x00000035, "flat_atomic_smin", []>;
1117 //def FLAT_ATOMIC_UMIN : FLAT_ <0x00000036, "flat_atomic_umin", []>;
1118 //def FLAT_ATOMIC_SMAX : FLAT_ <0x00000037, "flat_atomic_smax", []>;
1119 //def FLAT_ATOMIC_UMAX : FLAT_ <0x00000038, "flat_atomic_umax", []>;
1120 //def FLAT_ATOMIC_AND : FLAT_ <0x00000039, "flat_atomic_and", []>;
1121 //def FLAT_ATOMIC_OR : FLAT_ <0x0000003a, "flat_atomic_or", []>;
1122 //def FLAT_ATOMIC_XOR : FLAT_ <0x0000003b, "flat_atomic_xor", []>;
1123 //def FLAT_ATOMIC_INC : FLAT_ <0x0000003c, "flat_atomic_inc", []>;
1124 //def FLAT_ATOMIC_DEC : FLAT_ <0x0000003d, "flat_atomic_dec", []>;
1125 //def FLAT_ATOMIC_FCMPSWAP : FLAT_ <0x0000003e, "flat_atomic_fcmpswap", []>;
1126 //def FLAT_ATOMIC_FMIN : FLAT_ <0x0000003f, "flat_atomic_fmin", []>;
1127 //def FLAT_ATOMIC_FMAX : FLAT_ <0x00000040, "flat_atomic_fmax", []>;
1128 //def FLAT_ATOMIC_SWAP_X2 : FLAT_X2 <0x00000050, "flat_atomic_swap_x2", []>;
1129 //def FLAT_ATOMIC_CMPSWAP_X2 : FLAT_X2 <0x00000051, "flat_atomic_cmpswap_x2", []>;
1130 //def FLAT_ATOMIC_ADD_X2 : FLAT_X2 <0x00000052, "flat_atomic_add_x2", []>;
1131 //def FLAT_ATOMIC_SUB_X2 : FLAT_X2 <0x00000053, "flat_atomic_sub_x2", []>;
1132 //def FLAT_ATOMIC_RSUB_X2 : FLAT_X2 <0x00000054, "flat_atomic_rsub_x2", []>;
1133 //def FLAT_ATOMIC_SMIN_X2 : FLAT_X2 <0x00000055, "flat_atomic_smin_x2", []>;
1134 //def FLAT_ATOMIC_UMIN_X2 : FLAT_X2 <0x00000056, "flat_atomic_umin_x2", []>;
1135 //def FLAT_ATOMIC_SMAX_X2 : FLAT_X2 <0x00000057, "flat_atomic_smax_x2", []>;
1136 //def FLAT_ATOMIC_UMAX_X2 : FLAT_X2 <0x00000058, "flat_atomic_umax_x2", []>;
1137 //def FLAT_ATOMIC_AND_X2 : FLAT_X2 <0x00000059, "flat_atomic_and_x2", []>;
1138 //def FLAT_ATOMIC_OR_X2 : FLAT_X2 <0x0000005a, "flat_atomic_or_x2", []>;
1139 //def FLAT_ATOMIC_XOR_X2 : FLAT_X2 <0x0000005b, "flat_atomic_xor_x2", []>;
1140 //def FLAT_ATOMIC_INC_X2 : FLAT_X2 <0x0000005c, "flat_atomic_inc_x2", []>;
1141 //def FLAT_ATOMIC_DEC_X2 : FLAT_X2 <0x0000005d, "flat_atomic_dec_x2", []>;
1142 //def FLAT_ATOMIC_FCMPSWAP_X2 : FLAT_X2 <0x0000005e, "flat_atomic_fcmpswap_x2", []>;
1143 //def FLAT_ATOMIC_FMIN_X2 : FLAT_X2 <0x0000005f, "flat_atomic_fmin_x2", []>;
1144 //def FLAT_ATOMIC_FMAX_X2 : FLAT_X2 <0x00000060, "flat_atomic_fmax_x2", []>;
1146 } // End HasFlatAddressSpace predicate
1147 //===----------------------------------------------------------------------===//
1148 // VOP1 Instructions
1149 //===----------------------------------------------------------------------===//
1151 //def V_NOP : VOP1_ <0x00000000, "v_nop", []>;
1153 let isMoveImm = 1 in {
1154 defm V_MOV_B32 : VOP1Inst <vop1<0x1>, "v_mov_b32", VOP_I32_I32>;
1155 } // End isMoveImm = 1
1157 let Uses = [EXEC] in {
1159 def V_READFIRSTLANE_B32 : VOP1 <
1161 (outs SReg_32:$vdst),
1162 (ins VReg_32:$src0),
1163 "v_readfirstlane_b32 $vdst, $src0",
1169 defm V_CVT_I32_F64 : VOP1Inst <vop1<0x3>, "v_cvt_i32_f64",
1170 VOP_I32_F64, fp_to_sint
1172 defm V_CVT_F64_I32 : VOP1Inst <vop1<0x4>, "v_cvt_f64_i32",
1173 VOP_F64_I32, sint_to_fp
1175 defm V_CVT_F32_I32 : VOP1Inst <vop1<0x5>, "v_cvt_f32_i32",
1176 VOP_F32_I32, sint_to_fp
1178 defm V_CVT_F32_U32 : VOP1Inst <vop1<0x6>, "v_cvt_f32_u32",
1179 VOP_F32_I32, uint_to_fp
1181 defm V_CVT_U32_F32 : VOP1Inst <vop1<0x7>, "v_cvt_u32_f32",
1182 VOP_I32_F32, fp_to_uint
1184 defm V_CVT_I32_F32 : VOP1Inst <vop1<0x8>, "v_cvt_i32_f32",
1185 VOP_I32_F32, fp_to_sint
1187 defm V_MOV_FED_B32 : VOP1Inst <vop1<0x9>, "v_mov_fed_b32", VOP_I32_I32>;
1188 defm V_CVT_F16_F32 : VOP1Inst <vop1<0xa>, "v_cvt_f16_f32",
1189 VOP_I32_F32, fp_to_f16
1191 defm V_CVT_F32_F16 : VOP1Inst <vop1<0xb>, "v_cvt_f32_f16",
1192 VOP_F32_I32, f16_to_fp
1194 //defm V_CVT_RPI_I32_F32 : VOP1_32 <0x0000000c, "v_cvt_rpi_i32_f32", []>;
1195 //defm V_CVT_FLR_I32_F32 : VOP1_32 <0x0000000d, "v_cvt_flr_i32_f32", []>;
1196 //defm V_CVT_OFF_F32_I4 : VOP1_32 <0x0000000e, "v_cvt_off_f32_i4", []>;
1197 defm V_CVT_F32_F64 : VOP1Inst <vop1<0xf>, "v_cvt_f32_f64",
1200 defm V_CVT_F64_F32 : VOP1Inst <vop1<0x10>, "v_cvt_f64_f32",
1201 VOP_F64_F32, fextend
1203 defm V_CVT_F32_UBYTE0 : VOP1Inst <vop1<0x11>, "v_cvt_f32_ubyte0",
1204 VOP_F32_I32, AMDGPUcvt_f32_ubyte0
1206 defm V_CVT_F32_UBYTE1 : VOP1Inst <vop1<0x12>, "v_cvt_f32_ubyte1",
1207 VOP_F32_I32, AMDGPUcvt_f32_ubyte1
1209 defm V_CVT_F32_UBYTE2 : VOP1Inst <vop1<0x13>, "v_cvt_f32_ubyte2",
1210 VOP_F32_I32, AMDGPUcvt_f32_ubyte2
1212 defm V_CVT_F32_UBYTE3 : VOP1Inst <vop1<0x14>, "v_cvt_f32_ubyte3",
1213 VOP_F32_I32, AMDGPUcvt_f32_ubyte3
1215 defm V_CVT_U32_F64 : VOP1Inst <vop1<0x15>, "v_cvt_u32_f64",
1216 VOP_I32_F64, fp_to_uint
1218 defm V_CVT_F64_U32 : VOP1Inst <vop1<0x16>, "v_cvt_f64_u32",
1219 VOP_F64_I32, uint_to_fp
1222 defm V_FRACT_F32 : VOP1Inst <vop1<0x20>, "v_fract_f32",
1223 VOP_F32_F32, AMDGPUfract
1225 defm V_TRUNC_F32 : VOP1Inst <vop1<0x21>, "v_trunc_f32",
1228 defm V_CEIL_F32 : VOP1Inst <vop1<0x22>, "v_ceil_f32",
1231 defm V_RNDNE_F32 : VOP1Inst <vop1<0x23>, "v_rndne_f32",
1234 defm V_FLOOR_F32 : VOP1Inst <vop1<0x24>, "v_floor_f32",
1237 defm V_EXP_F32 : VOP1Inst <vop1<0x25>, "v_exp_f32",
1240 defm V_LOG_CLAMP_F32 : VOP1Inst <vop1<0x26>, "v_log_clamp_f32", VOP_F32_F32>;
1241 defm V_LOG_F32 : VOP1Inst <vop1<0x27>, "v_log_f32",
1245 defm V_RCP_CLAMP_F32 : VOP1Inst <vop1<0x28>, "v_rcp_clamp_f32", VOP_F32_F32>;
1246 defm V_RCP_LEGACY_F32 : VOP1Inst <vop1<0x29>, "v_rcp_legacy_f32", VOP_F32_F32>;
1247 defm V_RCP_F32 : VOP1Inst <vop1<0x2a>, "v_rcp_f32",
1248 VOP_F32_F32, AMDGPUrcp
1250 defm V_RCP_IFLAG_F32 : VOP1Inst <vop1<0x2b>, "v_rcp_iflag_f32", VOP_F32_F32>;
1251 defm V_RSQ_CLAMP_F32 : VOP1Inst <vop1<0x2c>, "v_rsq_clamp_f32",
1252 VOP_F32_F32, AMDGPUrsq_clamped
1254 defm V_RSQ_LEGACY_F32 : VOP1Inst <vop1<0x2d>, "v_rsq_legacy_f32",
1255 VOP_F32_F32, AMDGPUrsq_legacy
1257 defm V_RSQ_F32 : VOP1Inst <vop1<0x2e>, "v_rsq_f32",
1258 VOP_F32_F32, AMDGPUrsq
1260 defm V_RCP_F64 : VOP1Inst <vop1<0x2f>, "v_rcp_f64",
1261 VOP_F64_F64, AMDGPUrcp
1263 defm V_RCP_CLAMP_F64 : VOP1Inst <vop1<0x30>, "v_rcp_clamp_f64", VOP_F64_F64>;
1264 defm V_RSQ_F64 : VOP1Inst <vop1<0x31>, "v_rsq_f64",
1265 VOP_F64_F64, AMDGPUrsq
1267 defm V_RSQ_CLAMP_F64 : VOP1Inst <vop1<0x32>, "v_rsq_clamp_f64",
1268 VOP_F64_F64, AMDGPUrsq_clamped
1270 defm V_SQRT_F32 : VOP1Inst <vop1<0x33>, "v_sqrt_f32",
1273 defm V_SQRT_F64 : VOP1Inst <vop1<0x34>, "v_sqrt_f64",
1276 defm V_SIN_F32 : VOP1Inst <vop1<0x35>, "v_sin_f32",
1277 VOP_F32_F32, AMDGPUsin
1279 defm V_COS_F32 : VOP1Inst <vop1<0x36>, "v_cos_f32",
1280 VOP_F32_F32, AMDGPUcos
1282 defm V_NOT_B32 : VOP1Inst <vop1<0x37>, "v_not_b32", VOP_I32_I32>;
1283 defm V_BFREV_B32 : VOP1Inst <vop1<0x38>, "v_bfrev_b32", VOP_I32_I32>;
1284 defm V_FFBH_U32 : VOP1Inst <vop1<0x39>, "v_ffbh_u32", VOP_I32_I32>;
1285 defm V_FFBL_B32 : VOP1Inst <vop1<0x3a>, "v_ffbl_b32", VOP_I32_I32>;
1286 defm V_FFBH_I32 : VOP1Inst <vop1<0x3b>, "v_ffbh_i32", VOP_I32_I32>;
1287 //defm V_FREXP_EXP_I32_F64 : VOPInst <0x0000003c, "v_frexp_exp_i32_f64", VOP_I32_F32>;
1288 defm V_FREXP_MANT_F64 : VOP1Inst <vop1<0x3d>, "v_frexp_mant_f64", VOP_F64_F64>;
1289 defm V_FRACT_F64 : VOP1Inst <vop1<0x3e>, "v_fract_f64", VOP_F64_F64>;
1290 //defm V_FREXP_EXP_I32_F32 : VOPInst <0x0000003f, "v_frexp_exp_i32_f32", VOP_I32_F32>;
1291 defm V_FREXP_MANT_F32 : VOP1Inst <vop1<0x40>, "v_frexp_mant_f32", VOP_F32_F32>;
1292 //def V_CLREXCP : VOP1_ <0x00000041, "v_clrexcp", []>;
1293 defm V_MOVRELD_B32 : VOP1Inst <vop1<0x42>, "v_movreld_b32", VOP_I32_I32>;
1294 defm V_MOVRELS_B32 : VOP1Inst <vop1<0x43>, "v_movrels_b32", VOP_I32_I32>;
1295 defm V_MOVRELSD_B32 : VOP1Inst <vop1<0x44>, "v_movrelsd_b32", VOP_I32_I32>;
1298 //===----------------------------------------------------------------------===//
1299 // VINTRP Instructions
1300 //===----------------------------------------------------------------------===//
1302 def V_INTERP_P1_F32 : VINTRP <
1304 (outs VReg_32:$dst),
1305 (ins VReg_32:$i, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0),
1306 "v_interp_p1_f32 $dst, $i, $attr_chan, $attr, [$m0]",
1308 let DisableEncoding = "$m0";
1311 def V_INTERP_P2_F32 : VINTRP <
1313 (outs VReg_32:$dst),
1314 (ins VReg_32:$src0, VReg_32:$j, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0),
1315 "v_interp_p2_f32 $dst, [$src0], $j, $attr_chan, $attr, [$m0]",
1318 let Constraints = "$src0 = $dst";
1319 let DisableEncoding = "$src0,$m0";
1323 def V_INTERP_MOV_F32 : VINTRP <
1325 (outs VReg_32:$dst),
1326 (ins InterpSlot:$src0, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0),
1327 "v_interp_mov_f32 $dst, $src0, $attr_chan, $attr, [$m0]",
1329 let DisableEncoding = "$m0";
1332 //===----------------------------------------------------------------------===//
1333 // VOP2 Instructions
1334 //===----------------------------------------------------------------------===//
1336 def V_CNDMASK_B32_e32 : VOP2 <0x00000000, (outs VReg_32:$dst),
1337 (ins VSrc_32:$src0, VReg_32:$src1, VCCReg:$vcc),
1338 "v_cndmask_b32_e32 $dst, $src0, $src1, [$vcc]",
1341 let DisableEncoding = "$vcc";
1344 def V_CNDMASK_B32_e64 : VOP3 <0x00000100, (outs VReg_32:$dst),
1345 (ins VSrc_32:$src0, VSrc_32:$src1, SSrc_64:$src2),
1346 "v_cndmask_b32_e64 $dst, $src0, $src1, $src2",
1347 [(set i32:$dst, (select i1:$src2, i32:$src1, i32:$src0))]
1349 let src0_modifiers = 0;
1350 let src1_modifiers = 0;
1351 let src2_modifiers = 0;
1354 def V_READLANE_B32 : VOP2 <
1356 (outs SReg_32:$vdst),
1357 (ins VReg_32:$src0, SSrc_32:$vsrc1),
1358 "v_readlane_b32 $vdst, $src0, $vsrc1",
1362 def V_WRITELANE_B32 : VOP2 <
1364 (outs VReg_32:$vdst),
1365 (ins SReg_32:$src0, SSrc_32:$vsrc1),
1366 "v_writelane_b32 $vdst, $src0, $vsrc1",
1370 let isCommutable = 1 in {
1371 defm V_ADD_F32 : VOP2Inst <vop2<0x3>, "v_add_f32",
1372 VOP_F32_F32_F32, fadd
1375 defm V_SUB_F32 : VOP2Inst <vop2<0x4>, "v_sub_f32", VOP_F32_F32_F32, fsub>;
1376 defm V_SUBREV_F32 : VOP2Inst <vop2<0x5>, "v_subrev_f32",
1377 VOP_F32_F32_F32, null_frag, "v_sub_f32"
1379 } // End isCommutable = 1
1381 let isCommutable = 1 in {
1383 defm V_MAC_LEGACY_F32 : VOP2Inst <vop2<0x6>, "v_mac_legacy_f32",
1387 defm V_MUL_LEGACY_F32 : VOP2Inst <vop2<0x7>, "v_mul_legacy_f32",
1388 VOP_F32_F32_F32, int_AMDGPU_mul
1391 defm V_MUL_F32 : VOP2Inst <vop2<0x8>, "v_mul_f32",
1392 VOP_F32_F32_F32, fmul
1395 defm V_MUL_I32_I24 : VOP2Inst <vop2<0x9>, "v_mul_i32_i24",
1396 VOP_I32_I32_I32, AMDGPUmul_i24
1398 //defm V_MUL_HI_I32_I24 : VOP2_32 <0x0000000a, "v_mul_hi_i32_i24", []>;
1399 defm V_MUL_U32_U24 : VOP2Inst <vop2<0xb>, "v_mul_u32_u24",
1400 VOP_I32_I32_I32, AMDGPUmul_u24
1402 //defm V_MUL_HI_U32_U24 : VOP2_32 <0x0000000c, "v_mul_hi_u32_u24", []>;
1405 defm V_MIN_LEGACY_F32 : VOP2Inst <vop2<0xd>, "v_min_legacy_f32",
1406 VOP_F32_F32_F32, AMDGPUfmin_legacy
1409 defm V_MAX_LEGACY_F32 : VOP2Inst <vop2<0xe>, "v_max_legacy_f32",
1410 VOP_F32_F32_F32, AMDGPUfmax_legacy
1413 defm V_MIN_F32 : VOP2Inst <vop2<0xf>, "v_min_f32", VOP_F32_F32_F32, fminnum>;
1414 defm V_MAX_F32 : VOP2Inst <vop2<0x10>, "v_max_f32", VOP_F32_F32_F32, fmaxnum>;
1415 defm V_MIN_I32 : VOP2Inst <vop2<0x11>, "v_min_i32", VOP_I32_I32_I32, AMDGPUsmin>;
1416 defm V_MAX_I32 : VOP2Inst <vop2<0x12>, "v_max_i32", VOP_I32_I32_I32, AMDGPUsmax>;
1417 defm V_MIN_U32 : VOP2Inst <vop2<0x13>, "v_min_u32", VOP_I32_I32_I32, AMDGPUumin>;
1418 defm V_MAX_U32 : VOP2Inst <vop2<0x14>, "v_max_u32", VOP_I32_I32_I32, AMDGPUumax>;
1420 defm V_LSHR_B32 : VOP2Inst <vop2<0x15>, "v_lshr_b32", VOP_I32_I32_I32, srl>;
1422 defm V_LSHRREV_B32 : VOP2Inst <
1423 vop2<0x16>, "v_lshrrev_b32", VOP_I32_I32_I32, null_frag, "v_lshr_b32"
1426 defm V_ASHR_I32 : VOP2Inst <vop2<0x17>, "v_ashr_i32",
1427 VOP_I32_I32_I32, sra
1429 defm V_ASHRREV_I32 : VOP2Inst <
1430 vop2<0x18>, "v_ashrrev_i32", VOP_I32_I32_I32, null_frag, "v_ashr_i32"
1433 let hasPostISelHook = 1 in {
1435 defm V_LSHL_B32 : VOP2Inst <vop2<0x19>, "v_lshl_b32", VOP_I32_I32_I32, shl>;
1438 defm V_LSHLREV_B32 : VOP2Inst <
1439 vop2<0x1a>, "v_lshlrev_b32", VOP_I32_I32_I32, null_frag, "v_lshl_b32"
1442 defm V_AND_B32 : VOP2Inst <vop2<0x1b>, "v_and_b32",
1443 VOP_I32_I32_I32, and>;
1444 defm V_OR_B32 : VOP2Inst <vop2<0x1c>, "v_or_b32",
1447 defm V_XOR_B32 : VOP2Inst <vop2<0x1d>, "v_xor_b32",
1448 VOP_I32_I32_I32, xor
1451 } // End isCommutable = 1
1453 defm V_BFM_B32 : VOP2Inst <vop2<0x1e>, "v_bfm_b32",
1454 VOP_I32_I32_I32, AMDGPUbfm>;
1456 let isCommutable = 1 in {
1457 defm V_MAC_F32 : VOP2Inst <vop2<0x1f>, "v_mac_f32", VOP_F32_F32_F32>;
1458 } // End isCommutable = 1
1460 defm V_MADMK_F32 : VOP2Inst <vop2<0x20>, "v_madmk_f32", VOP_F32_F32_F32>;
1462 let isCommutable = 1 in {
1463 defm V_MADAK_F32 : VOP2Inst <vop2<0x21>, "v_madak_f32", VOP_F32_F32_F32>;
1464 } // End isCommutable = 1
1467 defm V_BCNT_U32_B32 : VOP2Inst <vop2<0x22>, "v_bcnt_u32_b32", VOP_I32_I32_I32>;
1468 defm V_MBCNT_LO_U32_B32 : VOP2Inst <vop2<0x23>, "v_mbcnt_lo_u32_b32",
1472 defm V_MBCNT_HI_U32_B32 : VOP2Inst <vop2<0x24>, "v_mbcnt_hi_u32_b32",
1476 let isCommutable = 1, Defs = [VCC] in { // Carry-out goes to VCC
1477 // No patterns so that the scalar instructions are always selected.
1478 // The scalar versions will be replaced with vector when needed later.
1479 defm V_ADD_I32 : VOP2bInst <vop2<0x25>, "v_add_i32",
1480 VOP_I32_I32_I32, add
1482 defm V_SUB_I32 : VOP2bInst <vop2<0x26>, "v_sub_i32",
1483 VOP_I32_I32_I32, sub
1485 defm V_SUBREV_I32 : VOP2bInst <vop2<0x27>, "v_subrev_i32",
1486 VOP_I32_I32_I32, null_frag, "v_sub_i32"
1489 let Uses = [VCC] in { // Carry-in comes from VCC
1490 defm V_ADDC_U32 : VOP2bInst <vop2<0x28>, "v_addc_u32",
1491 VOP_I32_I32_I32_VCC, adde
1493 defm V_SUBB_U32 : VOP2bInst <vop2<0x29>, "v_subb_u32",
1494 VOP_I32_I32_I32_VCC, sube
1496 defm V_SUBBREV_U32 : VOP2bInst <vop2<0x2a>, "v_subbrev_u32",
1497 VOP_I32_I32_I32_VCC, null_frag, "v_subb_u32"
1500 } // End Uses = [VCC]
1501 } // End isCommutable = 1, Defs = [VCC]
1503 defm V_LDEXP_F32 : VOP2Inst <vop2<0x2b>, "v_ldexp_f32",
1504 VOP_F32_F32_I32, AMDGPUldexp
1506 ////def V_CVT_PKACCUM_U8_F32 : VOP2_U8 <0x0000002c, "v_cvt_pkaccum_u8_f32", []>;
1507 ////def V_CVT_PKNORM_I16_F32 : VOP2_I16 <0x0000002d, "v_cvt_pknorm_i16_f32", []>;
1508 ////def V_CVT_PKNORM_U16_F32 : VOP2_U16 <0x0000002e, "v_cvt_pknorm_u16_f32", []>;
1509 defm V_CVT_PKRTZ_F16_F32 : VOP2Inst <vop2<0x2f>, "v_cvt_pkrtz_f16_f32",
1510 VOP_I32_F32_F32, int_SI_packf16
1512 ////def V_CVT_PK_U16_U32 : VOP2_U16 <0x00000030, "v_cvt_pk_u16_u32", []>;
1513 ////def V_CVT_PK_I16_I32 : VOP2_I16 <0x00000031, "v_cvt_pk_i16_i32", []>;
1515 //===----------------------------------------------------------------------===//
1516 // VOP3 Instructions
1517 //===----------------------------------------------------------------------===//
1519 let isCommutable = 1 in {
1520 defm V_MAD_LEGACY_F32 : VOP3Inst <vop3<0x140>, "v_mad_legacy_f32",
1524 defm V_MAD_F32 : VOP3Inst <vop3<0x141>, "v_mad_f32",
1525 VOP_F32_F32_F32_F32, fmad
1528 defm V_MAD_I32_I24 : VOP3Inst <vop3<0x142>, "v_mad_i32_i24",
1529 VOP_I32_I32_I32_I32, AMDGPUmad_i24
1531 defm V_MAD_U32_U24 : VOP3Inst <vop3<0x143>, "v_mad_u32_u24",
1532 VOP_I32_I32_I32_I32, AMDGPUmad_u24
1534 } // End isCommutable = 1
1536 defm V_CUBEID_F32 : VOP3Inst <vop3<0x144>, "v_cubeid_f32",
1539 defm V_CUBESC_F32 : VOP3Inst <vop3<0x145>, "v_cubesc_f32",
1542 defm V_CUBETC_F32 : VOP3Inst <vop3<0x146>, "v_cubetc_f32",
1545 defm V_CUBEMA_F32 : VOP3Inst <vop3<0x147>, "v_cubema_f32",
1548 defm V_BFE_U32 : VOP3Inst <vop3<0x148>, "v_bfe_u32",
1549 VOP_I32_I32_I32_I32, AMDGPUbfe_u32
1551 defm V_BFE_I32 : VOP3Inst <vop3<0x149>, "v_bfe_i32",
1552 VOP_I32_I32_I32_I32, AMDGPUbfe_i32
1554 defm V_BFI_B32 : VOP3Inst <vop3<0x14a>, "v_bfi_b32",
1555 VOP_I32_I32_I32_I32, AMDGPUbfi
1558 let isCommutable = 1 in {
1559 defm V_FMA_F32 : VOP3Inst <vop3<0x14b>, "v_fma_f32",
1560 VOP_F32_F32_F32_F32, fma
1562 defm V_FMA_F64 : VOP3Inst <vop3<0x14c>, "v_fma_f64",
1563 VOP_F64_F64_F64_F64, fma
1565 } // End isCommutable = 1
1567 //def V_LERP_U8 : VOP3_U8 <0x0000014d, "v_lerp_u8", []>;
1568 defm V_ALIGNBIT_B32 : VOP3Inst <vop3<0x14e>, "v_alignbit_b32",
1571 defm V_ALIGNBYTE_B32 : VOP3Inst <vop3<0x14f>, "v_alignbyte_b32",
1574 defm V_MULLIT_F32 : VOP3Inst <vop3<0x150>, "v_mullit_f32",
1575 VOP_F32_F32_F32_F32>;
1576 defm V_MIN3_F32 : VOP3Inst <vop3<0x151>, "v_min3_f32",
1577 VOP_F32_F32_F32_F32, AMDGPUfmin3>;
1579 defm V_MIN3_I32 : VOP3Inst <vop3<0x152>, "v_min3_i32",
1580 VOP_I32_I32_I32_I32, AMDGPUsmin3
1582 defm V_MIN3_U32 : VOP3Inst <vop3<0x153>, "v_min3_u32",
1583 VOP_I32_I32_I32_I32, AMDGPUumin3
1585 defm V_MAX3_F32 : VOP3Inst <vop3<0x154>, "v_max3_f32",
1586 VOP_F32_F32_F32_F32, AMDGPUfmax3
1588 defm V_MAX3_I32 : VOP3Inst <vop3<0x155>, "v_max3_i32",
1589 VOP_I32_I32_I32_I32, AMDGPUsmax3
1591 defm V_MAX3_U32 : VOP3Inst <vop3<0x156>, "v_max3_u32",
1592 VOP_I32_I32_I32_I32, AMDGPUumax3
1594 //def V_MED3_F32 : VOP3_MED3 <0x00000157, "v_med3_f32", []>;
1595 //def V_MED3_I32 : VOP3_MED3 <0x00000158, "v_med3_i32", []>;
1596 //def V_MED3_U32 : VOP3_MED3 <0x00000159, "v_med3_u32", []>;
1597 //def V_SAD_U8 : VOP3_U8 <0x0000015a, "v_sad_u8", []>;
1598 //def V_SAD_HI_U8 : VOP3_U8 <0x0000015b, "v_sad_hi_u8", []>;
1599 //def V_SAD_U16 : VOP3_U16 <0x0000015c, "v_sad_u16", []>;
1600 defm V_SAD_U32 : VOP3Inst <vop3<0x15d>, "v_sad_u32",
1603 ////def V_CVT_PK_U8_F32 : VOP3_U8 <0x0000015e, "v_cvt_pk_u8_f32", []>;
1604 defm V_DIV_FIXUP_F32 : VOP3Inst <
1605 vop3<0x15f>, "v_div_fixup_f32", VOP_F32_F32_F32_F32, AMDGPUdiv_fixup
1607 defm V_DIV_FIXUP_F64 : VOP3Inst <
1608 vop3<0x160>, "v_div_fixup_f64", VOP_F64_F64_F64_F64, AMDGPUdiv_fixup
1611 defm V_LSHL_B64 : VOP3Inst <vop3<0x161>, "v_lshl_b64",
1612 VOP_I64_I64_I32, shl
1614 defm V_LSHR_B64 : VOP3Inst <vop3<0x162>, "v_lshr_b64",
1615 VOP_I64_I64_I32, srl
1617 defm V_ASHR_I64 : VOP3Inst <vop3<0x163>, "v_ashr_i64",
1618 VOP_I64_I64_I32, sra
1621 let isCommutable = 1 in {
1623 defm V_ADD_F64 : VOP3Inst <vop3<0x164>, "v_add_f64",
1624 VOP_F64_F64_F64, fadd
1626 defm V_MUL_F64 : VOP3Inst <vop3<0x165>, "v_mul_f64",
1627 VOP_F64_F64_F64, fmul
1630 defm V_MIN_F64 : VOP3Inst <vop3<0x166>, "v_min_f64",
1631 VOP_F64_F64_F64, fminnum
1633 defm V_MAX_F64 : VOP3Inst <vop3<0x167>, "v_max_f64",
1634 VOP_F64_F64_F64, fmaxnum
1637 } // isCommutable = 1
1639 defm V_LDEXP_F64 : VOP3Inst <vop3<0x168>, "v_ldexp_f64",
1640 VOP_F64_F64_I32, AMDGPUldexp
1643 let isCommutable = 1 in {
1645 defm V_MUL_LO_U32 : VOP3Inst <vop3<0x169>, "v_mul_lo_u32",
1648 defm V_MUL_HI_U32 : VOP3Inst <vop3<0x16a>, "v_mul_hi_u32",
1651 defm V_MUL_LO_I32 : VOP3Inst <vop3<0x16b>, "v_mul_lo_i32",
1654 defm V_MUL_HI_I32 : VOP3Inst <vop3<0x16c>, "v_mul_hi_i32",
1658 } // isCommutable = 1
1660 defm V_DIV_SCALE_F32 : VOP3b_32 <vop3<0x16d>, "v_div_scale_f32", []>;
1662 // Double precision division pre-scale.
1663 defm V_DIV_SCALE_F64 : VOP3b_64 <vop3<0x16e>, "v_div_scale_f64", []>;
1665 let isCommutable = 1 in {
1666 defm V_DIV_FMAS_F32 : VOP3Inst <vop3<0x16f>, "v_div_fmas_f32",
1667 VOP_F32_F32_F32_F32, AMDGPUdiv_fmas
1669 defm V_DIV_FMAS_F64 : VOP3Inst <vop3<0x170>, "v_div_fmas_f64",
1670 VOP_F64_F64_F64_F64, AMDGPUdiv_fmas
1672 } // End isCommutable = 1
1674 //def V_MSAD_U8 : VOP3_U8 <0x00000171, "v_msad_u8", []>;
1675 //def V_QSAD_U8 : VOP3_U8 <0x00000172, "v_qsad_u8", []>;
1676 //def V_MQSAD_U8 : VOP3_U8 <0x00000173, "v_mqsad_u8", []>;
1678 defm V_TRIG_PREOP_F64 : VOP3Inst <
1679 vop3<0x174>, "v_trig_preop_f64", VOP_F64_F64_I32, AMDGPUtrig_preop
1682 //===----------------------------------------------------------------------===//
1683 // Pseudo Instructions
1684 //===----------------------------------------------------------------------===//
1686 let isCodeGenOnly = 1, isPseudo = 1 in {
1688 def V_MOV_I1 : InstSI <
1691 "", [(set i1:$dst, (imm:$src))]
1694 def V_AND_I1 : InstSI <
1695 (outs VReg_1:$dst), (ins VReg_1:$src0, VReg_1:$src1), "",
1696 [(set i1:$dst, (and i1:$src0, i1:$src1))]
1699 def V_OR_I1 : InstSI <
1700 (outs VReg_1:$dst), (ins VReg_1:$src0, VReg_1:$src1), "",
1701 [(set i1:$dst, (or i1:$src0, i1:$src1))]
1704 def V_XOR_I1 : InstSI <
1705 (outs VReg_1:$dst), (ins VReg_1:$src0, VReg_1:$src1), "",
1706 [(set i1:$dst, (xor i1:$src0, i1:$src1))]
1709 let hasSideEffects = 1 in {
1710 def SGPR_USE : InstSI <(outs),(ins), "", []>;
1713 // SI pseudo instructions. These are used by the CFG structurizer pass
1714 // and should be lowered to ISA instructions prior to codegen.
1716 let mayLoad = 1, mayStore = 1, hasSideEffects = 1,
1717 Uses = [EXEC], Defs = [EXEC] in {
1719 let isBranch = 1, isTerminator = 1 in {
1722 (outs SReg_64:$dst),
1723 (ins SReg_64:$vcc, brtarget:$target),
1725 [(set i64:$dst, (int_SI_if i1:$vcc, bb:$target))]
1728 def SI_ELSE : InstSI <
1729 (outs SReg_64:$dst),
1730 (ins SReg_64:$src, brtarget:$target),
1732 [(set i64:$dst, (int_SI_else i64:$src, bb:$target))]
1734 let Constraints = "$src = $dst";
1737 def SI_LOOP : InstSI <
1739 (ins SReg_64:$saved, brtarget:$target),
1740 "si_loop $saved, $target",
1741 [(int_SI_loop i64:$saved, bb:$target)]
1744 } // end isBranch = 1, isTerminator = 1
1746 def SI_BREAK : InstSI <
1747 (outs SReg_64:$dst),
1749 "si_else $dst, $src",
1750 [(set i64:$dst, (int_SI_break i64:$src))]
1753 def SI_IF_BREAK : InstSI <
1754 (outs SReg_64:$dst),
1755 (ins SReg_64:$vcc, SReg_64:$src),
1756 "si_if_break $dst, $vcc, $src",
1757 [(set i64:$dst, (int_SI_if_break i1:$vcc, i64:$src))]
1760 def SI_ELSE_BREAK : InstSI <
1761 (outs SReg_64:$dst),
1762 (ins SReg_64:$src0, SReg_64:$src1),
1763 "si_else_break $dst, $src0, $src1",
1764 [(set i64:$dst, (int_SI_else_break i64:$src0, i64:$src1))]
1767 def SI_END_CF : InstSI <
1769 (ins SReg_64:$saved),
1771 [(int_SI_end_cf i64:$saved)]
1774 def SI_KILL : InstSI <
1778 [(int_AMDGPU_kill f32:$src)]
1781 } // end mayLoad = 1, mayStore = 1, hasSideEffects = 1
1782 // Uses = [EXEC], Defs = [EXEC]
1784 let Uses = [EXEC], Defs = [EXEC,VCC,M0] in {
1786 //defm SI_ : RegisterLoadStore <VReg_32, FRAMEri, ADDRIndirect>;
1788 let UseNamedOperandTable = 1 in {
1790 def SI_RegisterLoad : InstSI <
1791 (outs VReg_32:$dst, SReg_64:$temp),
1792 (ins FRAMEri32:$addr, i32imm:$chan),
1795 let isRegisterLoad = 1;
1799 class SIRegStore<dag outs> : InstSI <
1801 (ins VReg_32:$val, FRAMEri32:$addr, i32imm:$chan),
1804 let isRegisterStore = 1;
1808 let usesCustomInserter = 1 in {
1809 def SI_RegisterStorePseudo : SIRegStore<(outs)>;
1810 } // End usesCustomInserter = 1
1811 def SI_RegisterStore : SIRegStore<(outs SReg_64:$temp)>;
1814 } // End UseNamedOperandTable = 1
1816 def SI_INDIRECT_SRC : InstSI <
1817 (outs VReg_32:$dst, SReg_64:$temp),
1818 (ins unknown:$src, VSrc_32:$idx, i32imm:$off),
1819 "si_indirect_src $dst, $temp, $src, $idx, $off",
1823 class SI_INDIRECT_DST<RegisterClass rc> : InstSI <
1824 (outs rc:$dst, SReg_64:$temp),
1825 (ins unknown:$src, VSrc_32:$idx, i32imm:$off, VReg_32:$val),
1826 "si_indirect_dst $dst, $temp, $src, $idx, $off, $val",
1829 let Constraints = "$src = $dst";
1832 def SI_INDIRECT_DST_V1 : SI_INDIRECT_DST<VReg_32>;
1833 def SI_INDIRECT_DST_V2 : SI_INDIRECT_DST<VReg_64>;
1834 def SI_INDIRECT_DST_V4 : SI_INDIRECT_DST<VReg_128>;
1835 def SI_INDIRECT_DST_V8 : SI_INDIRECT_DST<VReg_256>;
1836 def SI_INDIRECT_DST_V16 : SI_INDIRECT_DST<VReg_512>;
1838 } // Uses = [EXEC,VCC,M0], Defs = [EXEC,VCC,M0]
1840 let usesCustomInserter = 1 in {
1842 def V_SUB_F64 : InstSI <
1843 (outs VReg_64:$dst),
1844 (ins VReg_64:$src0, VReg_64:$src1),
1845 "v_sub_f64 $dst, $src0, $src1",
1846 [(set f64:$dst, (fsub f64:$src0, f64:$src1))]
1849 } // end usesCustomInserter
1851 multiclass SI_SPILL_SGPR <RegisterClass sgpr_class> {
1853 def _SAVE : InstSI <
1855 (ins sgpr_class:$src, i32imm:$frame_idx),
1859 def _RESTORE : InstSI <
1860 (outs sgpr_class:$dst),
1861 (ins i32imm:$frame_idx),
1867 defm SI_SPILL_S32 : SI_SPILL_SGPR <SReg_32>;
1868 defm SI_SPILL_S64 : SI_SPILL_SGPR <SReg_64>;
1869 defm SI_SPILL_S128 : SI_SPILL_SGPR <SReg_128>;
1870 defm SI_SPILL_S256 : SI_SPILL_SGPR <SReg_256>;
1871 defm SI_SPILL_S512 : SI_SPILL_SGPR <SReg_512>;
1873 multiclass SI_SPILL_VGPR <RegisterClass vgpr_class> {
1874 def _SAVE : InstSI <
1876 (ins vgpr_class:$src, i32imm:$frame_idx),
1880 def _RESTORE : InstSI <
1881 (outs vgpr_class:$dst),
1882 (ins i32imm:$frame_idx),
1887 defm SI_SPILL_V32 : SI_SPILL_VGPR <VReg_32>;
1888 defm SI_SPILL_V64 : SI_SPILL_VGPR <VReg_64>;
1889 defm SI_SPILL_V96 : SI_SPILL_VGPR <VReg_96>;
1890 defm SI_SPILL_V128 : SI_SPILL_VGPR <VReg_128>;
1891 defm SI_SPILL_V256 : SI_SPILL_VGPR <VReg_256>;
1892 defm SI_SPILL_V512 : SI_SPILL_VGPR <VReg_512>;
1894 let Defs = [SCC] in {
1896 def SI_CONSTDATA_PTR : InstSI <
1897 (outs SReg_64:$dst),
1899 "", [(set SReg_64:$dst, (i64 SIconstdata_ptr))]
1902 } // End Defs = [SCC]
1904 } // end IsCodeGenOnly, isPseudo
1906 } // end SubtargetPredicate = SI
1908 let Predicates = [isSI] in {
1911 (int_AMDGPU_cndlt f32:$src0, f32:$src1, f32:$src2),
1912 (V_CNDMASK_B32_e64 $src2, $src1,
1913 (V_CMP_GT_F32_e64 SRCMODS.NONE, 0, SRCMODS.NONE, $src0,
1914 DSTCLAMP.NONE, DSTOMOD.NONE))
1919 (SI_KILL 0xbf800000)
1922 /* int_SI_vs_load_input */
1924 (SIload_input v4i32:$tlst, imm:$attr_offset, i32:$buf_idx_vgpr),
1925 (BUFFER_LOAD_FORMAT_XYZW_IDXEN $tlst, $buf_idx_vgpr, imm:$attr_offset, 0, 0, 0, 0)
1930 (int_SI_export imm:$en, imm:$vm, imm:$done, imm:$tgt, imm:$compr,
1931 f32:$src0, f32:$src1, f32:$src2, f32:$src3),
1932 (EXP imm:$en, imm:$tgt, imm:$compr, imm:$done, imm:$vm,
1933 $src0, $src1, $src2, $src3)
1936 //===----------------------------------------------------------------------===//
1938 //===----------------------------------------------------------------------===//
1940 multiclass SMRD_Pattern <SMRD Instr_IMM, SMRD Instr_SGPR, ValueType vt> {
1942 // 1. Offset as 8bit DWORD immediate
1944 (constant_load (add i64:$sbase, (i64 IMM8bitDWORD:$offset))),
1945 (vt (Instr_IMM $sbase, (as_dword_i32imm $offset)))
1948 // 2. Offset loaded in an 32bit SGPR
1950 (constant_load (add i64:$sbase, (i64 IMM32bit:$offset))),
1951 (vt (Instr_SGPR $sbase, (S_MOV_B32 (i32 (as_i32imm $offset)))))
1954 // 3. No offset at all
1956 (constant_load i64:$sbase),
1957 (vt (Instr_IMM $sbase, 0))
1961 defm : SMRD_Pattern <S_LOAD_DWORD_IMM, S_LOAD_DWORD_SGPR, f32>;
1962 defm : SMRD_Pattern <S_LOAD_DWORD_IMM, S_LOAD_DWORD_SGPR, i32>;
1963 defm : SMRD_Pattern <S_LOAD_DWORDX2_IMM, S_LOAD_DWORDX2_SGPR, v2i32>;
1964 defm : SMRD_Pattern <S_LOAD_DWORDX4_IMM, S_LOAD_DWORDX4_SGPR, v4i32>;
1965 defm : SMRD_Pattern <S_LOAD_DWORDX8_IMM, S_LOAD_DWORDX8_SGPR, v32i8>;
1966 defm : SMRD_Pattern <S_LOAD_DWORDX8_IMM, S_LOAD_DWORDX8_SGPR, v8i32>;
1967 defm : SMRD_Pattern <S_LOAD_DWORDX16_IMM, S_LOAD_DWORDX16_SGPR, v16i32>;
1969 // 1. Offset as 8bit DWORD immediate
1971 (SIload_constant v4i32:$sbase, IMM8bitDWORD:$offset),
1972 (S_BUFFER_LOAD_DWORD_IMM $sbase, (as_dword_i32imm $offset))
1975 // 2. Offset loaded in an 32bit SGPR
1977 (SIload_constant v4i32:$sbase, imm:$offset),
1978 (S_BUFFER_LOAD_DWORD_SGPR $sbase, (S_MOV_B32 imm:$offset))
1981 } // Predicates = [isSI] in {
1983 //===----------------------------------------------------------------------===//
1985 //===----------------------------------------------------------------------===//
1988 (i64 (ctpop i64:$src)),
1989 (i64 (REG_SEQUENCE SReg_64,
1990 (S_BCNT1_I32_B64 $src), sub0,
1991 (S_MOV_B32 0), sub1))
1994 //===----------------------------------------------------------------------===//
1996 //===----------------------------------------------------------------------===//
1998 // V_ADD_I32_e32/S_ADD_U32 produces carry in VCC/SCC. For the vector
1999 // case, the sgpr-copies pass will fix this to use the vector version.
2001 (i32 (addc i32:$src0, i32:$src1)),
2002 (S_ADD_U32 $src0, $src1)
2005 let Predicates = [isSI] in {
2007 //===----------------------------------------------------------------------===//
2009 //===----------------------------------------------------------------------===//
2012 (int_AMDGPU_barrier_global),
2016 //===----------------------------------------------------------------------===//
2018 //===----------------------------------------------------------------------===//
2020 let Predicates = [UnsafeFPMath] in {
2021 def : RcpPat<V_RCP_F64_e32, f64>;
2022 defm : RsqPat<V_RSQ_F64_e32, f64>;
2023 defm : RsqPat<V_RSQ_F32_e32, f32>;
2026 //===----------------------------------------------------------------------===//
2028 //===----------------------------------------------------------------------===//
2031 (i32 (add (i32 (ctpop i32:$popcnt)), i32:$val)),
2032 (V_BCNT_U32_B32_e64 $popcnt, $val)
2035 /********** ======================= **********/
2036 /********** Image sampling patterns **********/
2037 /********** ======================= **********/
2040 class SampleRawPattern<SDPatternOperator name, MIMG opcode, ValueType vt> : Pat <
2041 (name vt:$addr, v8i32:$rsrc, v4i32:$sampler, i32:$dmask, i32:$unorm,
2042 i32:$r128, i32:$da, i32:$glc, i32:$slc, i32:$tfe, i32:$lwe),
2043 (opcode (as_i32imm $dmask), (as_i1imm $unorm), (as_i1imm $glc), (as_i1imm $da),
2044 (as_i1imm $r128), (as_i1imm $tfe), (as_i1imm $lwe), (as_i1imm $slc),
2045 $addr, $rsrc, $sampler)
2048 multiclass SampleRawPatterns<SDPatternOperator name, string opcode> {
2049 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V1), i32>;
2050 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V2), v2i32>;
2051 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V4), v4i32>;
2052 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V8), v8i32>;
2053 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V16), v16i32>;
2057 class ImagePattern<SDPatternOperator name, MIMG opcode, ValueType vt> : Pat <
2058 (name vt:$addr, v8i32:$rsrc, i32:$dmask, i32:$unorm,
2059 i32:$r128, i32:$da, i32:$glc, i32:$slc, i32:$tfe, i32:$lwe),
2060 (opcode (as_i32imm $dmask), (as_i1imm $unorm), (as_i1imm $glc), (as_i1imm $da),
2061 (as_i1imm $r128), (as_i1imm $tfe), (as_i1imm $lwe), (as_i1imm $slc),
2065 multiclass ImagePatterns<SDPatternOperator name, string opcode> {
2066 def : ImagePattern<name, !cast<MIMG>(opcode # _V4_V1), i32>;
2067 def : ImagePattern<name, !cast<MIMG>(opcode # _V4_V2), v2i32>;
2068 def : ImagePattern<name, !cast<MIMG>(opcode # _V4_V4), v4i32>;
2072 defm : SampleRawPatterns<int_SI_image_sample, "IMAGE_SAMPLE">;
2073 defm : SampleRawPatterns<int_SI_image_sample_cl, "IMAGE_SAMPLE_CL">;
2074 defm : SampleRawPatterns<int_SI_image_sample_d, "IMAGE_SAMPLE_D">;
2075 defm : SampleRawPatterns<int_SI_image_sample_d_cl, "IMAGE_SAMPLE_D_CL">;
2076 defm : SampleRawPatterns<int_SI_image_sample_l, "IMAGE_SAMPLE_L">;
2077 defm : SampleRawPatterns<int_SI_image_sample_b, "IMAGE_SAMPLE_B">;
2078 defm : SampleRawPatterns<int_SI_image_sample_b_cl, "IMAGE_SAMPLE_B_CL">;
2079 defm : SampleRawPatterns<int_SI_image_sample_lz, "IMAGE_SAMPLE_LZ">;
2080 defm : SampleRawPatterns<int_SI_image_sample_cd, "IMAGE_SAMPLE_CD">;
2081 defm : SampleRawPatterns<int_SI_image_sample_cd_cl, "IMAGE_SAMPLE_CD_CL">;
2083 // Sample with comparison
2084 defm : SampleRawPatterns<int_SI_image_sample_c, "IMAGE_SAMPLE_C">;
2085 defm : SampleRawPatterns<int_SI_image_sample_c_cl, "IMAGE_SAMPLE_C_CL">;
2086 defm : SampleRawPatterns<int_SI_image_sample_c_d, "IMAGE_SAMPLE_C_D">;
2087 defm : SampleRawPatterns<int_SI_image_sample_c_d_cl, "IMAGE_SAMPLE_C_D_CL">;
2088 defm : SampleRawPatterns<int_SI_image_sample_c_l, "IMAGE_SAMPLE_C_L">;
2089 defm : SampleRawPatterns<int_SI_image_sample_c_b, "IMAGE_SAMPLE_C_B">;
2090 defm : SampleRawPatterns<int_SI_image_sample_c_b_cl, "IMAGE_SAMPLE_C_B_CL">;
2091 defm : SampleRawPatterns<int_SI_image_sample_c_lz, "IMAGE_SAMPLE_C_LZ">;
2092 defm : SampleRawPatterns<int_SI_image_sample_c_cd, "IMAGE_SAMPLE_C_CD">;
2093 defm : SampleRawPatterns<int_SI_image_sample_c_cd_cl, "IMAGE_SAMPLE_C_CD_CL">;
2095 // Sample with offsets
2096 defm : SampleRawPatterns<int_SI_image_sample_o, "IMAGE_SAMPLE_O">;
2097 defm : SampleRawPatterns<int_SI_image_sample_cl_o, "IMAGE_SAMPLE_CL_O">;
2098 defm : SampleRawPatterns<int_SI_image_sample_d_o, "IMAGE_SAMPLE_D_O">;
2099 defm : SampleRawPatterns<int_SI_image_sample_d_cl_o, "IMAGE_SAMPLE_D_CL_O">;
2100 defm : SampleRawPatterns<int_SI_image_sample_l_o, "IMAGE_SAMPLE_L_O">;
2101 defm : SampleRawPatterns<int_SI_image_sample_b_o, "IMAGE_SAMPLE_B_O">;
2102 defm : SampleRawPatterns<int_SI_image_sample_b_cl_o, "IMAGE_SAMPLE_B_CL_O">;
2103 defm : SampleRawPatterns<int_SI_image_sample_lz_o, "IMAGE_SAMPLE_LZ_O">;
2104 defm : SampleRawPatterns<int_SI_image_sample_cd_o, "IMAGE_SAMPLE_CD_O">;
2105 defm : SampleRawPatterns<int_SI_image_sample_cd_cl_o, "IMAGE_SAMPLE_CD_CL_O">;
2107 // Sample with comparison and offsets
2108 defm : SampleRawPatterns<int_SI_image_sample_c_o, "IMAGE_SAMPLE_C_O">;
2109 defm : SampleRawPatterns<int_SI_image_sample_c_cl_o, "IMAGE_SAMPLE_C_CL_O">;
2110 defm : SampleRawPatterns<int_SI_image_sample_c_d_o, "IMAGE_SAMPLE_C_D_O">;
2111 defm : SampleRawPatterns<int_SI_image_sample_c_d_cl_o, "IMAGE_SAMPLE_C_D_CL_O">;
2112 defm : SampleRawPatterns<int_SI_image_sample_c_l_o, "IMAGE_SAMPLE_C_L_O">;
2113 defm : SampleRawPatterns<int_SI_image_sample_c_b_o, "IMAGE_SAMPLE_C_B_O">;
2114 defm : SampleRawPatterns<int_SI_image_sample_c_b_cl_o, "IMAGE_SAMPLE_C_B_CL_O">;
2115 defm : SampleRawPatterns<int_SI_image_sample_c_lz_o, "IMAGE_SAMPLE_C_LZ_O">;
2116 defm : SampleRawPatterns<int_SI_image_sample_c_cd_o, "IMAGE_SAMPLE_C_CD_O">;
2117 defm : SampleRawPatterns<int_SI_image_sample_c_cd_cl_o, "IMAGE_SAMPLE_C_CD_CL_O">;
2120 // Only the variants which make sense are defined.
2121 def : SampleRawPattern<int_SI_gather4, IMAGE_GATHER4_V4_V2, v2i32>;
2122 def : SampleRawPattern<int_SI_gather4, IMAGE_GATHER4_V4_V4, v4i32>;
2123 def : SampleRawPattern<int_SI_gather4_cl, IMAGE_GATHER4_CL_V4_V4, v4i32>;
2124 def : SampleRawPattern<int_SI_gather4_l, IMAGE_GATHER4_L_V4_V4, v4i32>;
2125 def : SampleRawPattern<int_SI_gather4_b, IMAGE_GATHER4_B_V4_V4, v4i32>;
2126 def : SampleRawPattern<int_SI_gather4_b_cl, IMAGE_GATHER4_B_CL_V4_V4, v4i32>;
2127 def : SampleRawPattern<int_SI_gather4_b_cl, IMAGE_GATHER4_B_CL_V4_V8, v8i32>;
2128 def : SampleRawPattern<int_SI_gather4_lz, IMAGE_GATHER4_LZ_V4_V2, v2i32>;
2129 def : SampleRawPattern<int_SI_gather4_lz, IMAGE_GATHER4_LZ_V4_V4, v4i32>;
2131 def : SampleRawPattern<int_SI_gather4_c, IMAGE_GATHER4_C_V4_V4, v4i32>;
2132 def : SampleRawPattern<int_SI_gather4_c_cl, IMAGE_GATHER4_C_CL_V4_V4, v4i32>;
2133 def : SampleRawPattern<int_SI_gather4_c_cl, IMAGE_GATHER4_C_CL_V4_V8, v8i32>;
2134 def : SampleRawPattern<int_SI_gather4_c_l, IMAGE_GATHER4_C_L_V4_V4, v4i32>;
2135 def : SampleRawPattern<int_SI_gather4_c_l, IMAGE_GATHER4_C_L_V4_V8, v8i32>;
2136 def : SampleRawPattern<int_SI_gather4_c_b, IMAGE_GATHER4_C_B_V4_V4, v4i32>;
2137 def : SampleRawPattern<int_SI_gather4_c_b, IMAGE_GATHER4_C_B_V4_V8, v8i32>;
2138 def : SampleRawPattern<int_SI_gather4_c_b_cl, IMAGE_GATHER4_C_B_CL_V4_V8, v8i32>;
2139 def : SampleRawPattern<int_SI_gather4_c_lz, IMAGE_GATHER4_C_LZ_V4_V4, v4i32>;
2141 def : SampleRawPattern<int_SI_gather4_o, IMAGE_GATHER4_O_V4_V4, v4i32>;
2142 def : SampleRawPattern<int_SI_gather4_cl_o, IMAGE_GATHER4_CL_O_V4_V4, v4i32>;
2143 def : SampleRawPattern<int_SI_gather4_cl_o, IMAGE_GATHER4_CL_O_V4_V8, v8i32>;
2144 def : SampleRawPattern<int_SI_gather4_l_o, IMAGE_GATHER4_L_O_V4_V4, v4i32>;
2145 def : SampleRawPattern<int_SI_gather4_l_o, IMAGE_GATHER4_L_O_V4_V8, v8i32>;
2146 def : SampleRawPattern<int_SI_gather4_b_o, IMAGE_GATHER4_B_O_V4_V4, v4i32>;
2147 def : SampleRawPattern<int_SI_gather4_b_o, IMAGE_GATHER4_B_O_V4_V8, v8i32>;
2148 def : SampleRawPattern<int_SI_gather4_b_cl_o, IMAGE_GATHER4_B_CL_O_V4_V8, v8i32>;
2149 def : SampleRawPattern<int_SI_gather4_lz_o, IMAGE_GATHER4_LZ_O_V4_V4, v4i32>;
2151 def : SampleRawPattern<int_SI_gather4_c_o, IMAGE_GATHER4_C_O_V4_V4, v4i32>;
2152 def : SampleRawPattern<int_SI_gather4_c_o, IMAGE_GATHER4_C_O_V4_V8, v8i32>;
2153 def : SampleRawPattern<int_SI_gather4_c_cl_o, IMAGE_GATHER4_C_CL_O_V4_V8, v8i32>;
2154 def : SampleRawPattern<int_SI_gather4_c_l_o, IMAGE_GATHER4_C_L_O_V4_V8, v8i32>;
2155 def : SampleRawPattern<int_SI_gather4_c_b_o, IMAGE_GATHER4_C_B_O_V4_V8, v8i32>;
2156 def : SampleRawPattern<int_SI_gather4_c_b_cl_o, IMAGE_GATHER4_C_B_CL_O_V4_V8, v8i32>;
2157 def : SampleRawPattern<int_SI_gather4_c_lz_o, IMAGE_GATHER4_C_LZ_O_V4_V4, v4i32>;
2158 def : SampleRawPattern<int_SI_gather4_c_lz_o, IMAGE_GATHER4_C_LZ_O_V4_V8, v8i32>;
2160 def : SampleRawPattern<int_SI_getlod, IMAGE_GET_LOD_V4_V1, i32>;
2161 def : SampleRawPattern<int_SI_getlod, IMAGE_GET_LOD_V4_V2, v2i32>;
2162 def : SampleRawPattern<int_SI_getlod, IMAGE_GET_LOD_V4_V4, v4i32>;
2164 def : ImagePattern<int_SI_getresinfo, IMAGE_GET_RESINFO_V4_V1, i32>;
2165 defm : ImagePatterns<int_SI_image_load, "IMAGE_LOAD">;
2166 defm : ImagePatterns<int_SI_image_load_mip, "IMAGE_LOAD_MIP">;
2168 /* SIsample for simple 1D texture lookup */
2170 (SIsample i32:$addr, v32i8:$rsrc, v4i32:$sampler, imm),
2171 (IMAGE_SAMPLE_V4_V1 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
2174 class SamplePattern<SDNode name, MIMG opcode, ValueType vt> : Pat <
2175 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, imm),
2176 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
2179 class SampleRectPattern<SDNode name, MIMG opcode, ValueType vt> : Pat <
2180 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_RECT),
2181 (opcode 0xf, 1, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
2184 class SampleArrayPattern<SDNode name, MIMG opcode, ValueType vt> : Pat <
2185 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_ARRAY),
2186 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc, $sampler)
2189 class SampleShadowPattern<SDNode name, MIMG opcode,
2190 ValueType vt> : Pat <
2191 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_SHADOW),
2192 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
2195 class SampleShadowArrayPattern<SDNode name, MIMG opcode,
2196 ValueType vt> : Pat <
2197 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_SHADOW_ARRAY),
2198 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc, $sampler)
2201 /* SIsample* for texture lookups consuming more address parameters */
2202 multiclass SamplePatterns<MIMG sample, MIMG sample_c, MIMG sample_l,
2203 MIMG sample_c_l, MIMG sample_b, MIMG sample_c_b,
2204 MIMG sample_d, MIMG sample_c_d, ValueType addr_type> {
2205 def : SamplePattern <SIsample, sample, addr_type>;
2206 def : SampleRectPattern <SIsample, sample, addr_type>;
2207 def : SampleArrayPattern <SIsample, sample, addr_type>;
2208 def : SampleShadowPattern <SIsample, sample_c, addr_type>;
2209 def : SampleShadowArrayPattern <SIsample, sample_c, addr_type>;
2211 def : SamplePattern <SIsamplel, sample_l, addr_type>;
2212 def : SampleArrayPattern <SIsamplel, sample_l, addr_type>;
2213 def : SampleShadowPattern <SIsamplel, sample_c_l, addr_type>;
2214 def : SampleShadowArrayPattern <SIsamplel, sample_c_l, addr_type>;
2216 def : SamplePattern <SIsampleb, sample_b, addr_type>;
2217 def : SampleArrayPattern <SIsampleb, sample_b, addr_type>;
2218 def : SampleShadowPattern <SIsampleb, sample_c_b, addr_type>;
2219 def : SampleShadowArrayPattern <SIsampleb, sample_c_b, addr_type>;
2221 def : SamplePattern <SIsampled, sample_d, addr_type>;
2222 def : SampleArrayPattern <SIsampled, sample_d, addr_type>;
2223 def : SampleShadowPattern <SIsampled, sample_c_d, addr_type>;
2224 def : SampleShadowArrayPattern <SIsampled, sample_c_d, addr_type>;
2227 defm : SamplePatterns<IMAGE_SAMPLE_V4_V2, IMAGE_SAMPLE_C_V4_V2,
2228 IMAGE_SAMPLE_L_V4_V2, IMAGE_SAMPLE_C_L_V4_V2,
2229 IMAGE_SAMPLE_B_V4_V2, IMAGE_SAMPLE_C_B_V4_V2,
2230 IMAGE_SAMPLE_D_V4_V2, IMAGE_SAMPLE_C_D_V4_V2,
2232 defm : SamplePatterns<IMAGE_SAMPLE_V4_V4, IMAGE_SAMPLE_C_V4_V4,
2233 IMAGE_SAMPLE_L_V4_V4, IMAGE_SAMPLE_C_L_V4_V4,
2234 IMAGE_SAMPLE_B_V4_V4, IMAGE_SAMPLE_C_B_V4_V4,
2235 IMAGE_SAMPLE_D_V4_V4, IMAGE_SAMPLE_C_D_V4_V4,
2237 defm : SamplePatterns<IMAGE_SAMPLE_V4_V8, IMAGE_SAMPLE_C_V4_V8,
2238 IMAGE_SAMPLE_L_V4_V8, IMAGE_SAMPLE_C_L_V4_V8,
2239 IMAGE_SAMPLE_B_V4_V8, IMAGE_SAMPLE_C_B_V4_V8,
2240 IMAGE_SAMPLE_D_V4_V8, IMAGE_SAMPLE_C_D_V4_V8,
2242 defm : SamplePatterns<IMAGE_SAMPLE_V4_V16, IMAGE_SAMPLE_C_V4_V16,
2243 IMAGE_SAMPLE_L_V4_V16, IMAGE_SAMPLE_C_L_V4_V16,
2244 IMAGE_SAMPLE_B_V4_V16, IMAGE_SAMPLE_C_B_V4_V16,
2245 IMAGE_SAMPLE_D_V4_V16, IMAGE_SAMPLE_C_D_V4_V16,
2248 /* int_SI_imageload for texture fetches consuming varying address parameters */
2249 class ImageLoadPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat <
2250 (name addr_type:$addr, v32i8:$rsrc, imm),
2251 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc)
2254 class ImageLoadArrayPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat <
2255 (name addr_type:$addr, v32i8:$rsrc, TEX_ARRAY),
2256 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc)
2259 class ImageLoadMSAAPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat <
2260 (name addr_type:$addr, v32i8:$rsrc, TEX_MSAA),
2261 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc)
2264 class ImageLoadArrayMSAAPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat <
2265 (name addr_type:$addr, v32i8:$rsrc, TEX_ARRAY_MSAA),
2266 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc)
2269 multiclass ImageLoadPatterns<MIMG opcode, ValueType addr_type> {
2270 def : ImageLoadPattern <int_SI_imageload, opcode, addr_type>;
2271 def : ImageLoadArrayPattern <int_SI_imageload, opcode, addr_type>;
2274 multiclass ImageLoadMSAAPatterns<MIMG opcode, ValueType addr_type> {
2275 def : ImageLoadMSAAPattern <int_SI_imageload, opcode, addr_type>;
2276 def : ImageLoadArrayMSAAPattern <int_SI_imageload, opcode, addr_type>;
2279 defm : ImageLoadPatterns<IMAGE_LOAD_MIP_V4_V2, v2i32>;
2280 defm : ImageLoadPatterns<IMAGE_LOAD_MIP_V4_V4, v4i32>;
2282 defm : ImageLoadMSAAPatterns<IMAGE_LOAD_V4_V2, v2i32>;
2283 defm : ImageLoadMSAAPatterns<IMAGE_LOAD_V4_V4, v4i32>;
2285 /* Image resource information */
2287 (int_SI_resinfo i32:$mipid, v32i8:$rsrc, imm),
2288 (IMAGE_GET_RESINFO_V4_V1 0xf, 0, 0, 0, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc)
2292 (int_SI_resinfo i32:$mipid, v32i8:$rsrc, TEX_ARRAY),
2293 (IMAGE_GET_RESINFO_V4_V1 0xf, 0, 0, 1, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc)
2297 (int_SI_resinfo i32:$mipid, v32i8:$rsrc, TEX_ARRAY_MSAA),
2298 (IMAGE_GET_RESINFO_V4_V1 0xf, 0, 0, 1, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc)
2301 /********** ============================================ **********/
2302 /********** Extraction, Insertion, Building and Casting **********/
2303 /********** ============================================ **********/
2305 foreach Index = 0-2 in {
2306 def Extract_Element_v2i32_#Index : Extract_Element <
2307 i32, v2i32, Index, !cast<SubRegIndex>(sub#Index)
2309 def Insert_Element_v2i32_#Index : Insert_Element <
2310 i32, v2i32, Index, !cast<SubRegIndex>(sub#Index)
2313 def Extract_Element_v2f32_#Index : Extract_Element <
2314 f32, v2f32, Index, !cast<SubRegIndex>(sub#Index)
2316 def Insert_Element_v2f32_#Index : Insert_Element <
2317 f32, v2f32, Index, !cast<SubRegIndex>(sub#Index)
2321 foreach Index = 0-3 in {
2322 def Extract_Element_v4i32_#Index : Extract_Element <
2323 i32, v4i32, Index, !cast<SubRegIndex>(sub#Index)
2325 def Insert_Element_v4i32_#Index : Insert_Element <
2326 i32, v4i32, Index, !cast<SubRegIndex>(sub#Index)
2329 def Extract_Element_v4f32_#Index : Extract_Element <
2330 f32, v4f32, Index, !cast<SubRegIndex>(sub#Index)
2332 def Insert_Element_v4f32_#Index : Insert_Element <
2333 f32, v4f32, Index, !cast<SubRegIndex>(sub#Index)
2337 foreach Index = 0-7 in {
2338 def Extract_Element_v8i32_#Index : Extract_Element <
2339 i32, v8i32, Index, !cast<SubRegIndex>(sub#Index)
2341 def Insert_Element_v8i32_#Index : Insert_Element <
2342 i32, v8i32, Index, !cast<SubRegIndex>(sub#Index)
2345 def Extract_Element_v8f32_#Index : Extract_Element <
2346 f32, v8f32, Index, !cast<SubRegIndex>(sub#Index)
2348 def Insert_Element_v8f32_#Index : Insert_Element <
2349 f32, v8f32, Index, !cast<SubRegIndex>(sub#Index)
2353 foreach Index = 0-15 in {
2354 def Extract_Element_v16i32_#Index : Extract_Element <
2355 i32, v16i32, Index, !cast<SubRegIndex>(sub#Index)
2357 def Insert_Element_v16i32_#Index : Insert_Element <
2358 i32, v16i32, Index, !cast<SubRegIndex>(sub#Index)
2361 def Extract_Element_v16f32_#Index : Extract_Element <
2362 f32, v16f32, Index, !cast<SubRegIndex>(sub#Index)
2364 def Insert_Element_v16f32_#Index : Insert_Element <
2365 f32, v16f32, Index, !cast<SubRegIndex>(sub#Index)
2369 def : BitConvert <i32, f32, SReg_32>;
2370 def : BitConvert <i32, f32, VReg_32>;
2372 def : BitConvert <f32, i32, SReg_32>;
2373 def : BitConvert <f32, i32, VReg_32>;
2375 def : BitConvert <i64, f64, VReg_64>;
2377 def : BitConvert <f64, i64, VReg_64>;
2379 def : BitConvert <v2f32, v2i32, VReg_64>;
2380 def : BitConvert <v2i32, v2f32, VReg_64>;
2381 def : BitConvert <v2i32, i64, VReg_64>;
2382 def : BitConvert <i64, v2i32, VReg_64>;
2383 def : BitConvert <v2f32, i64, VReg_64>;
2384 def : BitConvert <i64, v2f32, VReg_64>;
2385 def : BitConvert <v2i32, f64, VReg_64>;
2386 def : BitConvert <f64, v2i32, VReg_64>;
2387 def : BitConvert <v4f32, v4i32, VReg_128>;
2388 def : BitConvert <v4i32, v4f32, VReg_128>;
2390 def : BitConvert <v8f32, v8i32, SReg_256>;
2391 def : BitConvert <v8i32, v8f32, SReg_256>;
2392 def : BitConvert <v8i32, v32i8, SReg_256>;
2393 def : BitConvert <v32i8, v8i32, SReg_256>;
2394 def : BitConvert <v8i32, v32i8, VReg_256>;
2395 def : BitConvert <v8i32, v8f32, VReg_256>;
2396 def : BitConvert <v8f32, v8i32, VReg_256>;
2397 def : BitConvert <v32i8, v8i32, VReg_256>;
2399 def : BitConvert <v16i32, v16f32, VReg_512>;
2400 def : BitConvert <v16f32, v16i32, VReg_512>;
2402 /********** =================== **********/
2403 /********** Src & Dst modifiers **********/
2404 /********** =================== **********/
2407 (AMDGPUclamp (VOP3Mods0Clamp f32:$src0, i32:$src0_modifiers, i32:$omod),
2408 (f32 FP_ZERO), (f32 FP_ONE)),
2409 (V_ADD_F32_e64 $src0_modifiers, $src0, 0, 0, 1, $omod)
2412 /********** ================================ **********/
2413 /********** Floating point absolute/negative **********/
2414 /********** ================================ **********/
2416 // Prevent expanding both fneg and fabs.
2418 // FIXME: Should use S_OR_B32
2420 (fneg (fabs f32:$src)),
2421 (V_OR_B32_e32 $src, (V_MOV_B32_e32 0x80000000)) /* Set sign bit */
2424 // FIXME: Should use S_OR_B32
2426 (fneg (fabs f64:$src)),
2427 (REG_SEQUENCE VReg_64,
2428 (i32 (EXTRACT_SUBREG f64:$src, sub0)),
2430 (V_OR_B32_e32 (EXTRACT_SUBREG f64:$src, sub1),
2431 (V_MOV_B32_e32 0x80000000)), // Set sign bit.
2437 (V_AND_B32_e32 $src, (V_MOV_B32_e32 0x7fffffff))
2442 (V_XOR_B32_e32 $src, (V_MOV_B32_e32 0x80000000))
2447 (REG_SEQUENCE VReg_64,
2448 (i32 (EXTRACT_SUBREG f64:$src, sub0)),
2450 (V_AND_B32_e32 (EXTRACT_SUBREG f64:$src, sub1),
2451 (V_MOV_B32_e32 0x7fffffff)), // Set sign bit.
2457 (REG_SEQUENCE VReg_64,
2458 (i32 (EXTRACT_SUBREG f64:$src, sub0)),
2460 (V_XOR_B32_e32 (EXTRACT_SUBREG f64:$src, sub1),
2461 (V_MOV_B32_e32 0x80000000)),
2465 /********** ================== **********/
2466 /********** Immediate Patterns **********/
2467 /********** ================== **********/
2470 (SGPRImm<(i32 imm)>:$imm),
2471 (S_MOV_B32 imm:$imm)
2475 (SGPRImm<(f32 fpimm)>:$imm),
2476 (S_MOV_B32 fpimm:$imm)
2481 (V_MOV_B32_e32 imm:$imm)
2486 (V_MOV_B32_e32 fpimm:$imm)
2490 (i64 InlineImm<i64>:$imm),
2491 (S_MOV_B64 InlineImm<i64>:$imm)
2494 /********** ===================== **********/
2495 /********** Interpolation Paterns **********/
2496 /********** ===================== **********/
2499 (int_SI_fs_constant imm:$attr_chan, imm:$attr, i32:$params),
2500 (V_INTERP_MOV_F32 INTERP.P0, imm:$attr_chan, imm:$attr, $params)
2504 (int_SI_fs_interp imm:$attr_chan, imm:$attr, M0Reg:$params, v2i32:$ij),
2505 (V_INTERP_P2_F32 (V_INTERP_P1_F32 (EXTRACT_SUBREG v2i32:$ij, sub0),
2506 imm:$attr_chan, imm:$attr, i32:$params),
2507 (EXTRACT_SUBREG $ij, sub1),
2508 imm:$attr_chan, imm:$attr, $params)
2511 /********** ================== **********/
2512 /********** Intrinsic Patterns **********/
2513 /********** ================== **********/
2515 /* llvm.AMDGPU.pow */
2516 def : POW_Common <V_LOG_F32_e32, V_EXP_F32_e32, V_MUL_LEGACY_F32_e32>;
2519 (int_AMDGPU_div f32:$src0, f32:$src1),
2520 (V_MUL_LEGACY_F32_e32 $src0, (V_RCP_LEGACY_F32_e32 $src1))
2524 (fdiv f64:$src0, f64:$src1),
2525 (V_MUL_F64 0 /* src0_modifiers */, $src0,
2526 0 /* src1_modifiers */, (V_RCP_F64_e32 $src1),
2527 0 /* clamp */, 0 /* omod */)
2531 (int_AMDGPU_cube v4f32:$src),
2532 (REG_SEQUENCE VReg_128,
2533 (V_CUBETC_F32 0 /* src0_modifiers */, (EXTRACT_SUBREG $src, sub0),
2534 0 /* src1_modifiers */, (EXTRACT_SUBREG $src, sub1),
2535 0 /* src2_modifiers */, (EXTRACT_SUBREG $src, sub2),
2536 0 /* clamp */, 0 /* omod */), sub0,
2537 (V_CUBESC_F32 0 /* src0_modifiers */, (EXTRACT_SUBREG $src, sub0),
2538 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub1),
2539 0 /* src2_modifiers */,(EXTRACT_SUBREG $src, sub2),
2540 0 /* clamp */, 0 /* omod */), sub1,
2541 (V_CUBEMA_F32 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub0),
2542 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub1),
2543 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub2),
2544 0 /* clamp */, 0 /* omod */), sub2,
2545 (V_CUBEID_F32 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub0),
2546 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub1),
2547 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub2),
2548 0 /* clamp */, 0 /* omod */), sub3)
2552 (i32 (sext i1:$src0)),
2553 (V_CNDMASK_B32_e64 (i32 0), (i32 -1), $src0)
2556 class Ext32Pat <SDNode ext> : Pat <
2557 (i32 (ext i1:$src0)),
2558 (V_CNDMASK_B32_e64 (i32 0), (i32 1), $src0)
2561 def : Ext32Pat <zext>;
2562 def : Ext32Pat <anyext>;
2564 // Offset in an 32Bit VGPR
2566 (SIload_constant v4i32:$sbase, i32:$voff),
2567 (BUFFER_LOAD_DWORD_OFFEN $sbase, $voff, 0, 0, 0, 0, 0)
2570 // The multiplication scales from [0,1] to the unsigned integer range
2572 (AMDGPUurecip i32:$src0),
2574 (V_MUL_F32_e32 CONST.FP_UINT_MAX_PLUS_1,
2575 (V_RCP_IFLAG_F32_e32 (V_CVT_F32_U32_e32 $src0))))
2580 (V_MBCNT_HI_U32_B32_e32 0xffffffff,
2581 (V_MBCNT_LO_U32_B32_e64 0xffffffff, 0))
2584 //===----------------------------------------------------------------------===//
2586 //===----------------------------------------------------------------------===//
2588 def : IMad24Pat<V_MAD_I32_I24>;
2589 def : UMad24Pat<V_MAD_U32_U24>;
2592 (mulhu i32:$src0, i32:$src1),
2593 (V_MUL_HI_U32 $src0, $src1)
2597 (mulhs i32:$src0, i32:$src1),
2598 (V_MUL_HI_I32 $src0, $src1)
2601 def : Vop3ModPat<V_MAD_F32, VOP_F32_F32_F32_F32, AMDGPUmad>;
2604 defm : BFIPatterns <V_BFI_B32, S_MOV_B32, SReg_64>;
2605 def : ROTRPattern <V_ALIGNBIT_B32>;
2607 /********** ======================= **********/
2608 /********** Load/Store Patterns **********/
2609 /********** ======================= **********/
2611 class DSReadPat <DS inst, ValueType vt, PatFrag frag> : Pat <
2612 (vt (frag (DS1Addr1Offset i32:$ptr, i32:$offset))),
2613 (inst (i1 0), $ptr, (as_i16imm $offset))
2616 def : DSReadPat <DS_READ_I8, i32, sextloadi8_local>;
2617 def : DSReadPat <DS_READ_U8, i32, az_extloadi8_local>;
2618 def : DSReadPat <DS_READ_I16, i32, sextloadi16_local>;
2619 def : DSReadPat <DS_READ_U16, i32, az_extloadi16_local>;
2620 def : DSReadPat <DS_READ_B32, i32, local_load>;
2622 let AddedComplexity = 100 in {
2624 def : DSReadPat <DS_READ_B64, v2i32, local_load_aligned8bytes>;
2626 } // End AddedComplexity = 100
2629 (v2i32 (local_load (DS64Bit4ByteAligned i32:$ptr, i8:$offset0,
2631 (DS_READ2_B32 (i1 0), $ptr, $offset0, $offset1)
2634 class DSWritePat <DS inst, ValueType vt, PatFrag frag> : Pat <
2635 (frag vt:$value, (DS1Addr1Offset i32:$ptr, i32:$offset)),
2636 (inst (i1 0), $ptr, $value, (as_i16imm $offset))
2639 def : DSWritePat <DS_WRITE_B8, i32, truncstorei8_local>;
2640 def : DSWritePat <DS_WRITE_B16, i32, truncstorei16_local>;
2641 def : DSWritePat <DS_WRITE_B32, i32, local_store>;
2643 let AddedComplexity = 100 in {
2645 def : DSWritePat <DS_WRITE_B64, v2i32, local_store_aligned8bytes>;
2646 } // End AddedComplexity = 100
2649 (local_store v2i32:$value, (DS64Bit4ByteAligned i32:$ptr, i8:$offset0,
2651 (DS_WRITE2_B32 (i1 0), $ptr, (EXTRACT_SUBREG $value, sub0),
2652 (EXTRACT_SUBREG $value, sub1), $offset0, $offset1)
2655 class DSAtomicRetPat<DS inst, ValueType vt, PatFrag frag> : Pat <
2656 (frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$value),
2657 (inst (i1 0), $ptr, $value, (as_i16imm $offset))
2660 // Special case of DSAtomicRetPat for add / sub 1 -> inc / dec
2662 // We need to use something for the data0, so we set a register to
2663 // -1. For the non-rtn variants, the manual says it does
2664 // DS[A] = (DS[A] >= D0) ? 0 : DS[A] + 1, and setting D0 to uint_max
2665 // will always do the increment so I'm assuming it's the same.
2667 // We also load this -1 with s_mov_b32 / s_mov_b64 even though this
2668 // needs to be a VGPR. The SGPR copy pass will fix this, and it's
2669 // easier since there is no v_mov_b64.
2670 class DSAtomicIncRetPat<DS inst, ValueType vt,
2671 Instruction LoadImm, PatFrag frag> : Pat <
2672 (frag (DS1Addr1Offset i32:$ptr, i32:$offset), (vt 1)),
2673 (inst (i1 0), $ptr, (LoadImm (vt -1)), (as_i16imm $offset))
2677 class DSAtomicCmpXChg <DS inst, ValueType vt, PatFrag frag> : Pat <
2678 (frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$cmp, vt:$swap),
2679 (inst (i1 0), $ptr, $cmp, $swap, (as_i16imm $offset))
2684 def : DSAtomicIncRetPat<DS_INC_RTN_U32, i32,
2685 S_MOV_B32, atomic_load_add_local>;
2686 def : DSAtomicIncRetPat<DS_DEC_RTN_U32, i32,
2687 S_MOV_B32, atomic_load_sub_local>;
2689 def : DSAtomicRetPat<DS_WRXCHG_RTN_B32, i32, atomic_swap_local>;
2690 def : DSAtomicRetPat<DS_ADD_RTN_U32, i32, atomic_load_add_local>;
2691 def : DSAtomicRetPat<DS_SUB_RTN_U32, i32, atomic_load_sub_local>;
2692 def : DSAtomicRetPat<DS_AND_RTN_B32, i32, atomic_load_and_local>;
2693 def : DSAtomicRetPat<DS_OR_RTN_B32, i32, atomic_load_or_local>;
2694 def : DSAtomicRetPat<DS_XOR_RTN_B32, i32, atomic_load_xor_local>;
2695 def : DSAtomicRetPat<DS_MIN_RTN_I32, i32, atomic_load_min_local>;
2696 def : DSAtomicRetPat<DS_MAX_RTN_I32, i32, atomic_load_max_local>;
2697 def : DSAtomicRetPat<DS_MIN_RTN_U32, i32, atomic_load_umin_local>;
2698 def : DSAtomicRetPat<DS_MAX_RTN_U32, i32, atomic_load_umax_local>;
2700 def : DSAtomicCmpXChg<DS_CMPST_RTN_B32, i32, atomic_cmp_swap_32_local>;
2703 def : DSAtomicIncRetPat<DS_INC_RTN_U64, i64,
2704 S_MOV_B64, atomic_load_add_local>;
2705 def : DSAtomicIncRetPat<DS_DEC_RTN_U64, i64,
2706 S_MOV_B64, atomic_load_sub_local>;
2708 def : DSAtomicRetPat<DS_WRXCHG_RTN_B64, i64, atomic_swap_local>;
2709 def : DSAtomicRetPat<DS_ADD_RTN_U64, i64, atomic_load_add_local>;
2710 def : DSAtomicRetPat<DS_SUB_RTN_U64, i64, atomic_load_sub_local>;
2711 def : DSAtomicRetPat<DS_AND_RTN_B64, i64, atomic_load_and_local>;
2712 def : DSAtomicRetPat<DS_OR_RTN_B64, i64, atomic_load_or_local>;
2713 def : DSAtomicRetPat<DS_XOR_RTN_B64, i64, atomic_load_xor_local>;
2714 def : DSAtomicRetPat<DS_MIN_RTN_I64, i64, atomic_load_min_local>;
2715 def : DSAtomicRetPat<DS_MAX_RTN_I64, i64, atomic_load_max_local>;
2716 def : DSAtomicRetPat<DS_MIN_RTN_U64, i64, atomic_load_umin_local>;
2717 def : DSAtomicRetPat<DS_MAX_RTN_U64, i64, atomic_load_umax_local>;
2719 def : DSAtomicCmpXChg<DS_CMPST_RTN_B64, i64, atomic_cmp_swap_64_local>;
2722 //===----------------------------------------------------------------------===//
2724 //===----------------------------------------------------------------------===//
2726 multiclass MUBUFLoad_Pattern <MUBUF Instr_ADDR64, ValueType vt,
2727 PatFrag constant_ld> {
2729 (vt (constant_ld (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i16:$offset))),
2730 (Instr_ADDR64 $srsrc, $vaddr, $offset)
2734 defm : MUBUFLoad_Pattern <BUFFER_LOAD_SBYTE_ADDR64, i32, sextloadi8_constant>;
2735 defm : MUBUFLoad_Pattern <BUFFER_LOAD_UBYTE_ADDR64, i32, az_extloadi8_constant>;
2736 defm : MUBUFLoad_Pattern <BUFFER_LOAD_SSHORT_ADDR64, i32, sextloadi16_constant>;
2737 defm : MUBUFLoad_Pattern <BUFFER_LOAD_USHORT_ADDR64, i32, az_extloadi16_constant>;
2738 defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORD_ADDR64, i32, constant_load>;
2739 defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX2_ADDR64, v2i32, constant_load>;
2740 defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX4_ADDR64, v4i32, constant_load>;
2742 class MUBUFScratchLoadPat <MUBUF Instr, ValueType vt, PatFrag ld> : Pat <
2743 (vt (ld (MUBUFScratch v4i32:$srsrc, i32:$vaddr,
2744 i32:$soffset, u16imm:$offset))),
2745 (Instr $srsrc, $vaddr, $soffset, $offset, 0, 0, 0)
2748 def : MUBUFScratchLoadPat <BUFFER_LOAD_SBYTE_OFFEN, i32, sextloadi8_private>;
2749 def : MUBUFScratchLoadPat <BUFFER_LOAD_UBYTE_OFFEN, i32, extloadi8_private>;
2750 def : MUBUFScratchLoadPat <BUFFER_LOAD_SSHORT_OFFEN, i32, sextloadi16_private>;
2751 def : MUBUFScratchLoadPat <BUFFER_LOAD_USHORT_OFFEN, i32, extloadi16_private>;
2752 def : MUBUFScratchLoadPat <BUFFER_LOAD_DWORD_OFFEN, i32, load_private>;
2753 def : MUBUFScratchLoadPat <BUFFER_LOAD_DWORDX2_OFFEN, v2i32, load_private>;
2754 def : MUBUFScratchLoadPat <BUFFER_LOAD_DWORDX4_OFFEN, v4i32, load_private>;
2756 // BUFFER_LOAD_DWORD*, addr64=0
2757 multiclass MUBUF_Load_Dword <ValueType vt, MUBUF offset, MUBUF offen, MUBUF idxen,
2761 (vt (int_SI_buffer_load_dword v4i32:$rsrc, (i32 imm), i32:$soffset,
2762 imm:$offset, 0, 0, imm:$glc, imm:$slc,
2764 (offset $rsrc, (as_i16imm $offset), $soffset, (as_i1imm $glc),
2765 (as_i1imm $slc), (as_i1imm $tfe))
2769 (vt (int_SI_buffer_load_dword v4i32:$rsrc, i32:$vaddr, i32:$soffset,
2770 imm:$offset, 1, 0, imm:$glc, imm:$slc,
2772 (offen $rsrc, $vaddr, $soffset, (as_i16imm $offset), (as_i1imm $glc), (as_i1imm $slc),
2777 (vt (int_SI_buffer_load_dword v4i32:$rsrc, i32:$vaddr, i32:$soffset,
2778 imm:$offset, 0, 1, imm:$glc, imm:$slc,
2780 (idxen $rsrc, $vaddr, (as_i16imm $offset), $soffset, (as_i1imm $glc),
2781 (as_i1imm $slc), (as_i1imm $tfe))
2785 (vt (int_SI_buffer_load_dword v4i32:$rsrc, v2i32:$vaddr, i32:$soffset,
2786 imm, 1, 1, imm:$glc, imm:$slc,
2788 (bothen $rsrc, $vaddr, $soffset, (as_i1imm $glc), (as_i1imm $slc),
2793 defm : MUBUF_Load_Dword <i32, BUFFER_LOAD_DWORD_OFFSET, BUFFER_LOAD_DWORD_OFFEN,
2794 BUFFER_LOAD_DWORD_IDXEN, BUFFER_LOAD_DWORD_BOTHEN>;
2795 defm : MUBUF_Load_Dword <v2i32, BUFFER_LOAD_DWORDX2_OFFSET, BUFFER_LOAD_DWORDX2_OFFEN,
2796 BUFFER_LOAD_DWORDX2_IDXEN, BUFFER_LOAD_DWORDX2_BOTHEN>;
2797 defm : MUBUF_Load_Dword <v4i32, BUFFER_LOAD_DWORDX4_OFFSET, BUFFER_LOAD_DWORDX4_OFFEN,
2798 BUFFER_LOAD_DWORDX4_IDXEN, BUFFER_LOAD_DWORDX4_BOTHEN>;
2800 class MUBUFScratchStorePat <MUBUF Instr, ValueType vt, PatFrag st> : Pat <
2801 (st vt:$value, (MUBUFScratch v4i32:$srsrc, i32:$vaddr, i32:$soffset,
2803 (Instr $value, $srsrc, $vaddr, $soffset, $offset, 0, 0, 0)
2806 def : MUBUFScratchStorePat <BUFFER_STORE_BYTE_OFFEN, i32, truncstorei8_private>;
2807 def : MUBUFScratchStorePat <BUFFER_STORE_SHORT_OFFEN, i32, truncstorei16_private>;
2808 def : MUBUFScratchStorePat <BUFFER_STORE_DWORD_OFFEN, i32, store_private>;
2809 def : MUBUFScratchStorePat <BUFFER_STORE_DWORDX2_OFFEN, v2i32, store_private>;
2810 def : MUBUFScratchStorePat <BUFFER_STORE_DWORDX4_OFFEN, v4i32, store_private>;
2813 class MUBUFStore_Pattern <MUBUF Instr, ValueType vt, PatFrag st> : Pat <
2814 (st vt:$value, (MUBUFScratch v4i32:$srsrc, i64:$vaddr, u16imm:$offset)),
2815 (Instr $value, $srsrc, $vaddr, $offset)
2818 def : MUBUFStore_Pattern <BUFFER_STORE_BYTE_ADDR64, i32, truncstorei8_private>;
2819 def : MUBUFStore_Pattern <BUFFER_STORE_SHORT_ADDR64, i32, truncstorei16_private>;
2820 def : MUBUFStore_Pattern <BUFFER_STORE_DWORD_ADDR64, i32, store_private>;
2821 def : MUBUFStore_Pattern <BUFFER_STORE_DWORDX2_ADDR64, v2i32, store_private>;
2822 def : MUBUFStore_Pattern <BUFFER_STORE_DWORDX4_ADDR64, v4i32, store_private>;
2826 //===----------------------------------------------------------------------===//
2828 //===----------------------------------------------------------------------===//
2830 // TBUFFER_STORE_FORMAT_*, addr64=0
2831 class MTBUF_StoreResource <ValueType vt, int num_channels, MTBUF opcode> : Pat<
2832 (SItbuffer_store v4i32:$rsrc, vt:$vdata, num_channels, i32:$vaddr,
2833 i32:$soffset, imm:$inst_offset, imm:$dfmt,
2834 imm:$nfmt, imm:$offen, imm:$idxen,
2835 imm:$glc, imm:$slc, imm:$tfe),
2837 $vdata, (as_i16imm $inst_offset), (as_i1imm $offen), (as_i1imm $idxen),
2838 (as_i1imm $glc), 0, (as_i8imm $dfmt), (as_i8imm $nfmt), $vaddr, $rsrc,
2839 (as_i1imm $slc), (as_i1imm $tfe), $soffset)
2842 def : MTBUF_StoreResource <i32, 1, TBUFFER_STORE_FORMAT_X>;
2843 def : MTBUF_StoreResource <v2i32, 2, TBUFFER_STORE_FORMAT_XY>;
2844 def : MTBUF_StoreResource <v4i32, 3, TBUFFER_STORE_FORMAT_XYZ>;
2845 def : MTBUF_StoreResource <v4i32, 4, TBUFFER_STORE_FORMAT_XYZW>;
2847 let SubtargetPredicate = isCI in {
2849 // Sea island new arithmetic instructinos
2850 defm V_TRUNC_F64 : VOP1Inst <vop1<0x17>, "v_trunc_f64",
2853 defm V_CEIL_F64 : VOP1Inst <vop1<0x18>, "v_ceil_f64",
2856 defm V_FLOOR_F64 : VOP1Inst <vop1<0x1A>, "v_floor_f64",
2859 defm V_RNDNE_F64 : VOP1Inst <vop1<0x19>, "v_rndne_f64",
2863 defm V_QSAD_PK_U16_U8 : VOP3Inst <vop3<0x173>, "v_qsad_pk_u16_u8",
2866 defm V_MQSAD_U16_U8 : VOP3Inst <vop3<0x172>, "v_mqsad_u16_u8",
2869 defm V_MQSAD_U32_U8 : VOP3Inst <vop3<0x175>, "v_mqsad_u32_u8",
2873 let isCommutable = 1 in {
2874 defm V_MAD_U64_U32 : VOP3Inst <vop3<0x176>, "v_mad_u64_u32",
2878 // XXX - Does this set VCC?
2879 defm V_MAD_I64_I32 : VOP3Inst <vop3<0x177>, "v_mad_i64_i32",
2882 } // End isCommutable = 1
2884 // Remaining instructions:
2886 // S_CBRANCH_CDBGUSER
2887 // S_CBRANCH_CDBGSYS
2888 // S_CBRANCH_CDBGSYS_OR_USER
2889 // S_CBRANCH_CDBGSYS_AND_USER
2894 // DS_GWS_SEMA_RELEASE_ALL
2896 // DS_CNDXCHG32_RTN_B64
2899 // DS_CONDXCHG32_RTN_B128
2902 // BUFFER_LOAD_DWORDX3
2903 // BUFFER_STORE_DWORDX3
2907 //===----------------------------------------------------------------------===//
2909 //===----------------------------------------------------------------------===//
2911 class FLATLoad_Pattern <FLAT Instr_ADDR64, ValueType vt,
2913 Pat <(vt (flat_ld i64:$ptr)),
2917 def : FLATLoad_Pattern <FLAT_LOAD_SBYTE, i32, sextloadi8_flat>;
2918 def : FLATLoad_Pattern <FLAT_LOAD_UBYTE, i32, az_extloadi8_flat>;
2919 def : FLATLoad_Pattern <FLAT_LOAD_SSHORT, i32, sextloadi16_flat>;
2920 def : FLATLoad_Pattern <FLAT_LOAD_USHORT, i32, az_extloadi16_flat>;
2921 def : FLATLoad_Pattern <FLAT_LOAD_DWORD, i32, flat_load>;
2922 def : FLATLoad_Pattern <FLAT_LOAD_DWORDX2, i64, flat_load>;
2923 def : FLATLoad_Pattern <FLAT_LOAD_DWORDX2, i64, az_extloadi32_flat>;
2924 def : FLATLoad_Pattern <FLAT_LOAD_DWORDX2, v2i32, flat_load>;
2925 def : FLATLoad_Pattern <FLAT_LOAD_DWORDX4, v4i32, flat_load>;
2927 class FLATStore_Pattern <FLAT Instr, ValueType vt, PatFrag st> :
2928 Pat <(st vt:$value, i64:$ptr),
2929 (Instr $value, $ptr)
2932 def : FLATStore_Pattern <FLAT_STORE_BYTE, i32, truncstorei8_flat>;
2933 def : FLATStore_Pattern <FLAT_STORE_SHORT, i32, truncstorei16_flat>;
2934 def : FLATStore_Pattern <FLAT_STORE_DWORD, i32, flat_store>;
2935 def : FLATStore_Pattern <FLAT_STORE_DWORDX2, i64, flat_store>;
2936 def : FLATStore_Pattern <FLAT_STORE_DWORDX2, v2i32, flat_store>;
2937 def : FLATStore_Pattern <FLAT_STORE_DWORDX4, v4i32, flat_store>;
2939 /********** ====================== **********/
2940 /********** Indirect adressing **********/
2941 /********** ====================== **********/
2943 multiclass SI_INDIRECT_Pattern <ValueType vt, ValueType eltvt, SI_INDIRECT_DST IndDst> {
2945 // 1. Extract with offset
2947 (vector_extract vt:$vec, (add i32:$idx, imm:$off)),
2948 (eltvt (SI_INDIRECT_SRC (IMPLICIT_DEF), $vec, $idx, imm:$off))
2951 // 2. Extract without offset
2953 (vector_extract vt:$vec, i32:$idx),
2954 (eltvt (SI_INDIRECT_SRC (IMPLICIT_DEF), $vec, $idx, 0))
2957 // 3. Insert with offset
2959 (vector_insert vt:$vec, eltvt:$val, (add i32:$idx, imm:$off)),
2960 (IndDst (IMPLICIT_DEF), $vec, $idx, imm:$off, $val)
2963 // 4. Insert without offset
2965 (vector_insert vt:$vec, eltvt:$val, i32:$idx),
2966 (IndDst (IMPLICIT_DEF), $vec, $idx, 0, $val)
2970 defm : SI_INDIRECT_Pattern <v2f32, f32, SI_INDIRECT_DST_V2>;
2971 defm : SI_INDIRECT_Pattern <v4f32, f32, SI_INDIRECT_DST_V4>;
2972 defm : SI_INDIRECT_Pattern <v8f32, f32, SI_INDIRECT_DST_V8>;
2973 defm : SI_INDIRECT_Pattern <v16f32, f32, SI_INDIRECT_DST_V16>;
2975 defm : SI_INDIRECT_Pattern <v2i32, i32, SI_INDIRECT_DST_V2>;
2976 defm : SI_INDIRECT_Pattern <v4i32, i32, SI_INDIRECT_DST_V4>;
2977 defm : SI_INDIRECT_Pattern <v8i32, i32, SI_INDIRECT_DST_V8>;
2978 defm : SI_INDIRECT_Pattern <v16i32, i32, SI_INDIRECT_DST_V16>;
2980 //===----------------------------------------------------------------------===//
2981 // Conversion Patterns
2982 //===----------------------------------------------------------------------===//
2984 def : Pat<(i32 (sext_inreg i32:$src, i1)),
2985 (S_BFE_I32 i32:$src, 65536)>; // 0 | 1 << 16
2987 // Handle sext_inreg in i64
2989 (i64 (sext_inreg i64:$src, i1)),
2990 (S_BFE_I64 i64:$src, 0x10000) // 0 | 1 << 16
2994 (i64 (sext_inreg i64:$src, i8)),
2995 (S_BFE_I64 i64:$src, 0x80000) // 0 | 8 << 16
2999 (i64 (sext_inreg i64:$src, i16)),
3000 (S_BFE_I64 i64:$src, 0x100000) // 0 | 16 << 16
3004 (i64 (sext_inreg i64:$src, i32)),
3005 (S_BFE_I64 i64:$src, 0x200000) // 0 | 32 << 16
3008 class ZExt_i64_i32_Pat <SDNode ext> : Pat <
3009 (i64 (ext i32:$src)),
3010 (REG_SEQUENCE SReg_64, $src, sub0, (S_MOV_B32 0), sub1)
3013 class ZExt_i64_i1_Pat <SDNode ext> : Pat <
3014 (i64 (ext i1:$src)),
3015 (REG_SEQUENCE VReg_64,
3016 (V_CNDMASK_B32_e64 (i32 0), (i32 1), $src), sub0,
3017 (S_MOV_B32 0), sub1)
3021 def : ZExt_i64_i32_Pat<zext>;
3022 def : ZExt_i64_i32_Pat<anyext>;
3023 def : ZExt_i64_i1_Pat<zext>;
3024 def : ZExt_i64_i1_Pat<anyext>;
3027 (i64 (sext i32:$src)),
3028 (REG_SEQUENCE SReg_64, $src, sub0,
3029 (S_ASHR_I32 $src, 31), sub1)
3033 (i64 (sext i1:$src)),
3034 (REG_SEQUENCE VReg_64,
3035 (V_CNDMASK_B32_e64 0, -1, $src), sub0,
3036 (V_CNDMASK_B32_e64 0, -1, $src), sub1)
3040 (f32 (sint_to_fp i1:$src)),
3041 (V_CNDMASK_B32_e64 (i32 0), CONST.FP32_NEG_ONE, $src)
3045 (f32 (uint_to_fp i1:$src)),
3046 (V_CNDMASK_B32_e64 (i32 0), CONST.FP32_ONE, $src)
3050 (f64 (sint_to_fp i1:$src)),
3051 (V_CVT_F64_I32_e32 (V_CNDMASK_B32_e64 (i32 0), (i32 -1), $src))
3055 (f64 (uint_to_fp i1:$src)),
3056 (V_CVT_F64_U32_e32 (V_CNDMASK_B32_e64 (i32 0), (i32 1), $src))
3059 //===----------------------------------------------------------------------===//
3060 // Miscellaneous Patterns
3061 //===----------------------------------------------------------------------===//
3064 (i32 (trunc i64:$a)),
3065 (EXTRACT_SUBREG $a, sub0)
3069 (i1 (trunc i32:$a)),
3070 (V_CMP_EQ_I32_e64 (V_AND_B32_e64 (i32 1), $a), 1)
3074 (i32 (bswap i32:$a)),
3075 (V_BFI_B32 (S_MOV_B32 0x00ff00ff),
3076 (V_ALIGNBIT_B32 $a, $a, 24),
3077 (V_ALIGNBIT_B32 $a, $a, 8))
3080 //============================================================================//
3081 // Miscellaneous Optimization Patterns
3082 //============================================================================//
3084 def : SHA256MaPattern <V_BFI_B32, V_XOR_B32_e64>;
3086 } // End isSI predicate