1 //===-- SIInstrInfo.td - SI Instruction Infos -------------*- tablegen -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 def isCI : Predicate<"Subtarget->getGeneration() "
10 ">= AMDGPUSubtarget::SEA_ISLANDS">;
11 def isVI : Predicate <
12 "Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
13 AssemblerPredicate<"FeatureGCN3Encoding">;
15 def DisableInst : Predicate <"false">, AssemblerPredicate<"FeatureDisable">;
22 class vopc <bits<8> si, bits<8> vi = !add(0x40, si)> : vop {
23 field bits<8> SI = si;
24 field bits<8> VI = vi;
26 field bits<9> SI3 = {0, si{7-0}};
27 field bits<10> VI3 = {0, 0, vi{7-0}};
30 class vop1 <bits<8> si, bits<8> vi = si> : vop {
31 field bits<8> SI = si;
32 field bits<8> VI = vi;
34 field bits<9> SI3 = {1, 1, si{6-0}};
35 field bits<10> VI3 = !add(0x140, vi);
38 class vop2 <bits<6> si, bits<6> vi = si> : vop {
39 field bits<6> SI = si;
40 field bits<6> VI = vi;
42 field bits<9> SI3 = {1, 0, 0, si{5-0}};
43 field bits<10> VI3 = {0, 1, 0, 0, vi{5-0}};
46 // Specify a VOP2 opcode for SI and VOP3 opcode for VI
47 // that doesn't have VOP2 encoding on VI
48 class vop23 <bits<6> si, bits<10> vi> : vop2 <si> {
52 class vop3 <bits<9> si, bits<10> vi = {0, si}> : vop {
57 class sop1 <bits<8> si, bits<8> vi = si> {
58 field bits<8> SI = si;
59 field bits<8> VI = vi;
62 class sop2 <bits<7> si, bits<7> vi = si> {
63 field bits<7> SI = si;
64 field bits<7> VI = vi;
67 class sopk <bits<5> si, bits<5> vi = si> {
68 field bits<5> SI = si;
69 field bits<5> VI = vi;
72 // Execpt for the NONE field, this must be kept in sync with the SISubtarget enum
73 // in AMDGPUInstrInfo.cpp
80 //===----------------------------------------------------------------------===//
82 //===----------------------------------------------------------------------===//
84 def SIload_constant : SDNode<"AMDGPUISD::LOAD_CONSTANT",
85 SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i32>]>,
86 [SDNPMayLoad, SDNPMemOperand]
89 def SItbuffer_store : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT",
91 [SDTCisVT<0, v4i32>, // rsrc(SGPR)
92 SDTCisVT<1, iAny>, // vdata(VGPR)
93 SDTCisVT<2, i32>, // num_channels(imm)
94 SDTCisVT<3, i32>, // vaddr(VGPR)
95 SDTCisVT<4, i32>, // soffset(SGPR)
96 SDTCisVT<5, i32>, // inst_offset(imm)
97 SDTCisVT<6, i32>, // dfmt(imm)
98 SDTCisVT<7, i32>, // nfmt(imm)
99 SDTCisVT<8, i32>, // offen(imm)
100 SDTCisVT<9, i32>, // idxen(imm)
101 SDTCisVT<10, i32>, // glc(imm)
102 SDTCisVT<11, i32>, // slc(imm)
103 SDTCisVT<12, i32> // tfe(imm)
105 [SDNPMayStore, SDNPMemOperand, SDNPHasChain]
108 def SIload_input : SDNode<"AMDGPUISD::LOAD_INPUT",
109 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i16>,
113 class SDSample<string opcode> : SDNode <opcode,
114 SDTypeProfile<1, 4, [SDTCisVT<0, v4f32>, SDTCisVT<2, v32i8>,
115 SDTCisVT<3, v4i32>, SDTCisVT<4, i32>]>
118 def SIsample : SDSample<"AMDGPUISD::SAMPLE">;
119 def SIsampleb : SDSample<"AMDGPUISD::SAMPLEB">;
120 def SIsampled : SDSample<"AMDGPUISD::SAMPLED">;
121 def SIsamplel : SDSample<"AMDGPUISD::SAMPLEL">;
123 def SIconstdata_ptr : SDNode<
124 "AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 0, [SDTCisVT<0, i64>]>
127 //===----------------------------------------------------------------------===//
128 // SDNodes and PatFrag for local loads and stores to enable s_mov_b32 m0, -1
129 // to be glued to the memory instructions.
130 //===----------------------------------------------------------------------===//
132 def SIld_local : SDNode <"ISD::LOAD", SDTLoad,
133 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand, SDNPInGlue]
136 def si_ld_local : PatFrag <(ops node:$ptr), (SIld_local node:$ptr), [{
137 return isLocalLoad(cast<LoadSDNode>(N));
140 def si_load_local : PatFrag <(ops node:$ptr), (si_ld_local node:$ptr), [{
141 return cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED &&
142 cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD;
145 def si_load_local_align8 : Aligned8Bytes <
146 (ops node:$ptr), (si_load_local node:$ptr)
149 def si_sextload_local : PatFrag <(ops node:$ptr), (si_ld_local node:$ptr), [{
150 return cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD;
152 def si_az_extload_local : AZExtLoadBase <si_ld_local>;
154 multiclass SIExtLoadLocal <PatFrag ld_node> {
156 def _i8 : PatFrag <(ops node:$ptr), (ld_node node:$ptr),
157 [{return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;}]
160 def _i16 : PatFrag <(ops node:$ptr), (ld_node node:$ptr),
161 [{return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;}]
165 defm si_sextload_local : SIExtLoadLocal <si_sextload_local>;
166 defm si_az_extload_local : SIExtLoadLocal <si_az_extload_local>;
168 def SIst_local : SDNode <"ISD::STORE", SDTStore,
169 [SDNPHasChain, SDNPMayStore, SDNPMemOperand, SDNPInGlue]
172 def si_st_local : PatFrag <
173 (ops node:$val, node:$ptr), (SIst_local node:$val, node:$ptr), [{
174 return isLocalStore(cast<StoreSDNode>(N));
177 def si_store_local : PatFrag <
178 (ops node:$val, node:$ptr), (si_st_local node:$val, node:$ptr), [{
179 return cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED &&
180 !cast<StoreSDNode>(N)->isTruncatingStore();
183 def si_store_local_align8 : Aligned8Bytes <
184 (ops node:$val, node:$ptr), (si_store_local node:$val, node:$ptr)
187 def si_truncstore_local : PatFrag <
188 (ops node:$val, node:$ptr), (si_st_local node:$val, node:$ptr), [{
189 return cast<StoreSDNode>(N)->isTruncatingStore();
192 def si_truncstore_local_i8 : PatFrag <
193 (ops node:$val, node:$ptr), (si_truncstore_local node:$val, node:$ptr), [{
194 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
197 def si_truncstore_local_i16 : PatFrag <
198 (ops node:$val, node:$ptr), (si_truncstore_local node:$val, node:$ptr), [{
199 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
202 multiclass SIAtomicM0Glue2 <string op_name> {
204 def _glue : SDNode <"ISD::ATOMIC_"#op_name, SDTAtomic2,
205 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand, SDNPInGlue]
208 def _local : local_binary_atomic_op <!cast<SDNode>(NAME#"_glue")>;
211 defm si_atomic_load_add : SIAtomicM0Glue2 <"LOAD_ADD">;
212 defm si_atomic_load_and : SIAtomicM0Glue2 <"LOAD_AND">;
213 defm si_atomic_load_min : SIAtomicM0Glue2 <"LOAD_MIN">;
214 defm si_atomic_load_max : SIAtomicM0Glue2 <"LOAD_MAX">;
215 defm si_atomic_load_or : SIAtomicM0Glue2 <"LOAD_OR">;
216 defm si_atomic_load_sub : SIAtomicM0Glue2 <"LOAD_SUB">;
217 defm si_atomic_load_xor : SIAtomicM0Glue2 <"LOAD_XOR">;
218 defm si_atomic_load_umin : SIAtomicM0Glue2 <"LOAD_UMIN">;
219 defm si_atomic_load_umax : SIAtomicM0Glue2 <"LOAD_UMAX">;
220 defm si_atomic_swap : SIAtomicM0Glue2 <"SWAP">;
222 def si_atomic_cmp_swap_glue : SDNode <"ISD::ATOMIC_CMP_SWAP", SDTAtomic3,
223 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand, SDNPInGlue]
226 defm si_atomic_cmp_swap : AtomicCmpSwapLocal <si_atomic_cmp_swap_glue>;
228 // Transformation function, extract the lower 32bit of a 64bit immediate
229 def LO32 : SDNodeXForm<imm, [{
230 return CurDAG->getTargetConstant(N->getZExtValue() & 0xffffffff, SDLoc(N),
234 def LO32f : SDNodeXForm<fpimm, [{
235 APInt V = N->getValueAPF().bitcastToAPInt().trunc(32);
236 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
239 // Transformation function, extract the upper 32bit of a 64bit immediate
240 def HI32 : SDNodeXForm<imm, [{
241 return CurDAG->getTargetConstant(N->getZExtValue() >> 32, SDLoc(N), MVT::i32);
244 def HI32f : SDNodeXForm<fpimm, [{
245 APInt V = N->getValueAPF().bitcastToAPInt().lshr(32).trunc(32);
246 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), SDLoc(N),
250 def IMM8bitDWORD : PatLeaf <(imm),
251 [{return (N->getZExtValue() & ~0x3FC) == 0;}]
254 def as_dword_i32imm : SDNodeXForm<imm, [{
255 return CurDAG->getTargetConstant(N->getZExtValue() >> 2, SDLoc(N), MVT::i32);
258 def as_i1imm : SDNodeXForm<imm, [{
259 return CurDAG->getTargetConstant(N->getZExtValue(), SDLoc(N), MVT::i1);
262 def as_i8imm : SDNodeXForm<imm, [{
263 return CurDAG->getTargetConstant(N->getZExtValue(), SDLoc(N), MVT::i8);
266 def as_i16imm : SDNodeXForm<imm, [{
267 return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i16);
270 def as_i32imm: SDNodeXForm<imm, [{
271 return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i32);
274 def as_i64imm: SDNodeXForm<imm, [{
275 return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i64);
278 // Copied from the AArch64 backend:
279 def bitcast_fpimm_to_i32 : SDNodeXForm<fpimm, [{
280 return CurDAG->getTargetConstant(
281 N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i32);
284 // Copied from the AArch64 backend:
285 def bitcast_fpimm_to_i64 : SDNodeXForm<fpimm, [{
286 return CurDAG->getTargetConstant(
287 N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i64);
290 def IMM8bit : PatLeaf <(imm),
291 [{return isUInt<8>(N->getZExtValue());}]
294 def IMM12bit : PatLeaf <(imm),
295 [{return isUInt<12>(N->getZExtValue());}]
298 def IMM16bit : PatLeaf <(imm),
299 [{return isUInt<16>(N->getZExtValue());}]
302 def IMM20bit : PatLeaf <(imm),
303 [{return isUInt<20>(N->getZExtValue());}]
306 def IMM32bit : PatLeaf <(imm),
307 [{return isUInt<32>(N->getZExtValue());}]
310 def mubuf_vaddr_offset : PatFrag<
311 (ops node:$ptr, node:$offset, node:$imm_offset),
312 (add (add node:$ptr, node:$offset), node:$imm_offset)
315 class InlineImm <ValueType vt> : PatLeaf <(vt imm), [{
316 return isInlineImmediate(N);
319 class InlineFPImm <ValueType vt> : PatLeaf <(vt fpimm), [{
320 return isInlineImmediate(N);
323 class SGPRImm <dag frag> : PatLeaf<frag, [{
324 if (Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS) {
327 const SIRegisterInfo *SIRI =
328 static_cast<const SIRegisterInfo *>(Subtarget->getRegisterInfo());
329 for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
331 if (SIRI->isSGPRClass(getOperandRegClass(*U, U.getOperandNo()))) {
338 //===----------------------------------------------------------------------===//
340 //===----------------------------------------------------------------------===//
342 def FRAMEri32 : Operand<iPTR> {
343 let MIOperandInfo = (ops i32:$ptr, i32imm:$index);
346 def SoppBrTarget : AsmOperandClass {
347 let Name = "SoppBrTarget";
348 let ParserMethod = "parseSOppBrTarget";
351 def sopp_brtarget : Operand<OtherVT> {
352 let EncoderMethod = "getSOPPBrEncoding";
353 let OperandType = "OPERAND_PCREL";
354 let ParserMatchClass = SoppBrTarget;
357 include "SIInstrFormats.td"
358 include "VIInstrFormats.td"
360 def MubufOffsetMatchClass : AsmOperandClass {
361 let Name = "MubufOffset";
362 let ParserMethod = "parseMubufOptionalOps";
363 let RenderMethod = "addImmOperands";
366 class DSOffsetBaseMatchClass <string parser> : AsmOperandClass {
367 let Name = "DSOffset"#parser;
368 let ParserMethod = parser;
369 let RenderMethod = "addImmOperands";
370 let PredicateMethod = "isDSOffset";
373 def DSOffsetMatchClass : DSOffsetBaseMatchClass <"parseDSOptionalOps">;
374 def DSOffsetGDSMatchClass : DSOffsetBaseMatchClass <"parseDSOffsetOptional">;
376 def DSOffset01MatchClass : AsmOperandClass {
377 let Name = "DSOffset1";
378 let ParserMethod = "parseDSOff01OptionalOps";
379 let RenderMethod = "addImmOperands";
380 let PredicateMethod = "isDSOffset01";
383 class GDSBaseMatchClass <string parser> : AsmOperandClass {
384 let Name = "GDS"#parser;
385 let PredicateMethod = "isImm";
386 let ParserMethod = parser;
387 let RenderMethod = "addImmOperands";
390 def GDSMatchClass : GDSBaseMatchClass <"parseDSOptionalOps">;
391 def GDS01MatchClass : GDSBaseMatchClass <"parseDSOff01OptionalOps">;
393 def GLCMatchClass : AsmOperandClass {
395 let PredicateMethod = "isImm";
396 let ParserMethod = "parseMubufOptionalOps";
397 let RenderMethod = "addImmOperands";
400 def SLCMatchClass : AsmOperandClass {
402 let PredicateMethod = "isImm";
403 let ParserMethod = "parseMubufOptionalOps";
404 let RenderMethod = "addImmOperands";
407 def TFEMatchClass : AsmOperandClass {
409 let PredicateMethod = "isImm";
410 let ParserMethod = "parseMubufOptionalOps";
411 let RenderMethod = "addImmOperands";
414 def OModMatchClass : AsmOperandClass {
416 let PredicateMethod = "isImm";
417 let ParserMethod = "parseVOP3OptionalOps";
418 let RenderMethod = "addImmOperands";
421 def ClampMatchClass : AsmOperandClass {
423 let PredicateMethod = "isImm";
424 let ParserMethod = "parseVOP3OptionalOps";
425 let RenderMethod = "addImmOperands";
428 let OperandType = "OPERAND_IMMEDIATE" in {
430 def offen : Operand<i1> {
431 let PrintMethod = "printOffen";
433 def idxen : Operand<i1> {
434 let PrintMethod = "printIdxen";
436 def addr64 : Operand<i1> {
437 let PrintMethod = "printAddr64";
439 def mbuf_offset : Operand<i16> {
440 let PrintMethod = "printMBUFOffset";
441 let ParserMatchClass = MubufOffsetMatchClass;
443 class ds_offset_base <AsmOperandClass mc> : Operand<i16> {
444 let PrintMethod = "printDSOffset";
445 let ParserMatchClass = mc;
447 def ds_offset : ds_offset_base <DSOffsetMatchClass>;
448 def ds_offset_gds : ds_offset_base <DSOffsetGDSMatchClass>;
450 def ds_offset0 : Operand<i8> {
451 let PrintMethod = "printDSOffset0";
452 let ParserMatchClass = DSOffset01MatchClass;
454 def ds_offset1 : Operand<i8> {
455 let PrintMethod = "printDSOffset1";
456 let ParserMatchClass = DSOffset01MatchClass;
458 class gds_base <AsmOperandClass mc> : Operand <i1> {
459 let PrintMethod = "printGDS";
460 let ParserMatchClass = mc;
462 def gds : gds_base <GDSMatchClass>;
464 def gds01 : gds_base <GDS01MatchClass>;
466 def glc : Operand <i1> {
467 let PrintMethod = "printGLC";
468 let ParserMatchClass = GLCMatchClass;
470 def slc : Operand <i1> {
471 let PrintMethod = "printSLC";
472 let ParserMatchClass = SLCMatchClass;
474 def tfe : Operand <i1> {
475 let PrintMethod = "printTFE";
476 let ParserMatchClass = TFEMatchClass;
479 def omod : Operand <i32> {
480 let PrintMethod = "printOModSI";
481 let ParserMatchClass = OModMatchClass;
484 def ClampMod : Operand <i1> {
485 let PrintMethod = "printClampSI";
486 let ParserMatchClass = ClampMatchClass;
489 } // End OperandType = "OPERAND_IMMEDIATE"
491 def VOPDstS64 : VOPDstOperand <SReg_64>;
493 //===----------------------------------------------------------------------===//
495 //===----------------------------------------------------------------------===//
497 def DS1Addr1Offset : ComplexPattern<i32, 2, "SelectDS1Addr1Offset">;
498 def DS64Bit4ByteAligned : ComplexPattern<i32, 3, "SelectDS64Bit4ByteAligned">;
500 def MUBUFAddr32 : ComplexPattern<i64, 9, "SelectMUBUFAddr32">;
501 def MUBUFAddr64 : ComplexPattern<i64, 7, "SelectMUBUFAddr64">;
502 def MUBUFAddr64Atomic : ComplexPattern<i64, 5, "SelectMUBUFAddr64">;
503 def MUBUFScratch : ComplexPattern<i64, 4, "SelectMUBUFScratch">;
504 def MUBUFOffset : ComplexPattern<i64, 6, "SelectMUBUFOffset">;
505 def MUBUFOffsetAtomic : ComplexPattern<i64, 4, "SelectMUBUFOffset">;
507 def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">;
508 def VOP3Mods0Clamp : ComplexPattern<untyped, 3, "SelectVOP3Mods0Clamp">;
509 def VOP3Mods0Clamp0OMod : ComplexPattern<untyped, 4, "SelectVOP3Mods0Clamp0OMod">;
510 def VOP3Mods : ComplexPattern<untyped, 2, "SelectVOP3Mods">;
512 //===----------------------------------------------------------------------===//
513 // SI assembler operands
514 //===----------------------------------------------------------------------===//
535 //===----------------------------------------------------------------------===//
537 // SI Instruction multiclass helpers.
539 // Instructions with _32 take 32-bit operands.
540 // Instructions with _64 take 64-bit operands.
542 // VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit
543 // encoding is the standard encoding, but instruction that make use of
544 // any of the instruction modifiers must use the 64-bit encoding.
546 // Instructions with _e32 use the 32-bit encoding.
547 // Instructions with _e64 use the 64-bit encoding.
549 //===----------------------------------------------------------------------===//
551 class SIMCInstr <string pseudo, int subtarget> {
552 string PseudoInstr = pseudo;
553 int Subtarget = subtarget;
556 //===----------------------------------------------------------------------===//
558 //===----------------------------------------------------------------------===//
560 class EXPCommon : InstSI<
562 (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm,
563 VGPR_32:$src0, VGPR_32:$src1, VGPR_32:$src2, VGPR_32:$src3),
564 "exp $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3",
573 let isPseudo = 1, isCodeGenOnly = 1 in {
574 def "" : EXPCommon, SIMCInstr <"exp", SISubtarget.NONE> ;
577 def _si : EXPCommon, SIMCInstr <"exp", SISubtarget.SI>, EXPe;
579 def _vi : EXPCommon, SIMCInstr <"exp", SISubtarget.VI>, EXPe_vi;
582 //===----------------------------------------------------------------------===//
584 //===----------------------------------------------------------------------===//
586 class SOP1_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
587 SOP1 <outs, ins, "", pattern>,
588 SIMCInstr<opName, SISubtarget.NONE> {
590 let isCodeGenOnly = 1;
593 class SOP1_Real_si <sop1 op, string opName, dag outs, dag ins, string asm> :
594 SOP1 <outs, ins, asm, []>,
596 SIMCInstr<opName, SISubtarget.SI> {
597 let isCodeGenOnly = 0;
598 let AssemblerPredicates = [isSICI];
601 class SOP1_Real_vi <sop1 op, string opName, dag outs, dag ins, string asm> :
602 SOP1 <outs, ins, asm, []>,
604 SIMCInstr<opName, SISubtarget.VI> {
605 let isCodeGenOnly = 0;
606 let AssemblerPredicates = [isVI];
609 multiclass SOP1_m <sop1 op, string opName, dag outs, dag ins, string asm,
612 def "" : SOP1_Pseudo <opName, outs, ins, pattern>;
614 def _si : SOP1_Real_si <op, opName, outs, ins, asm>;
616 def _vi : SOP1_Real_vi <op, opName, outs, ins, asm>;
620 multiclass SOP1_32 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
621 op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0),
622 opName#" $dst, $src0", pattern
625 multiclass SOP1_64 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
626 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0),
627 opName#" $dst, $src0", pattern
630 // no input, 64-bit output.
631 multiclass SOP1_64_0 <sop1 op, string opName, list<dag> pattern> {
632 def "" : SOP1_Pseudo <opName, (outs SReg_64:$dst), (ins), pattern>;
634 def _si : SOP1_Real_si <op, opName, (outs SReg_64:$dst), (ins),
639 def _vi : SOP1_Real_vi <op, opName, (outs SReg_64:$dst), (ins),
645 // 64-bit input, no output
646 multiclass SOP1_1 <sop1 op, string opName, list<dag> pattern> {
647 def "" : SOP1_Pseudo <opName, (outs), (ins SReg_64:$src0), pattern>;
649 def _si : SOP1_Real_si <op, opName, (outs), (ins SReg_64:$src0),
654 def _vi : SOP1_Real_vi <op, opName, (outs), (ins SReg_64:$src0),
660 // 64-bit input, 32-bit output.
661 multiclass SOP1_32_64 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
662 op, opName, (outs SReg_32:$dst), (ins SSrc_64:$src0),
663 opName#" $dst, $src0", pattern
666 class SOP2_Pseudo<string opName, dag outs, dag ins, list<dag> pattern> :
667 SOP2<outs, ins, "", pattern>,
668 SIMCInstr<opName, SISubtarget.NONE> {
670 let isCodeGenOnly = 1;
673 // Pseudo instructions have no encodings, but adding this field here allows
675 // let sdst = xxx in {
676 // for multiclasses that include both real and pseudo instructions.
677 field bits<7> sdst = 0;
680 class SOP2_Real_si<sop2 op, string opName, dag outs, dag ins, string asm> :
681 SOP2<outs, ins, asm, []>,
683 SIMCInstr<opName, SISubtarget.SI> {
684 let AssemblerPredicates = [isSICI];
687 class SOP2_Real_vi<sop2 op, string opName, dag outs, dag ins, string asm> :
688 SOP2<outs, ins, asm, []>,
690 SIMCInstr<opName, SISubtarget.VI> {
691 let AssemblerPredicates = [isVI];
694 multiclass SOP2_SELECT_32 <sop2 op, string opName, list<dag> pattern> {
695 def "" : SOP2_Pseudo <opName, (outs SReg_32:$dst),
696 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc), pattern>;
698 def _si : SOP2_Real_si <op, opName, (outs SReg_32:$dst),
699 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc),
700 opName#" $dst, $src0, $src1 [$scc]">;
702 def _vi : SOP2_Real_vi <op, opName, (outs SReg_32:$dst),
703 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc),
704 opName#" $dst, $src0, $src1 [$scc]">;
707 multiclass SOP2_m <sop2 op, string opName, dag outs, dag ins, string asm,
710 def "" : SOP2_Pseudo <opName, outs, ins, pattern>;
712 def _si : SOP2_Real_si <op, opName, outs, ins, asm>;
714 def _vi : SOP2_Real_vi <op, opName, outs, ins, asm>;
718 multiclass SOP2_32 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
719 op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0, SSrc_32:$src1),
720 opName#" $dst, $src0, $src1", pattern
723 multiclass SOP2_64 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
724 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_64:$src1),
725 opName#" $dst, $src0, $src1", pattern
728 multiclass SOP2_64_32 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
729 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_32:$src1),
730 opName#" $dst, $src0, $src1", pattern
733 class SOPC_Helper <bits<7> op, RegisterOperand rc, ValueType vt,
734 string opName, PatLeaf cond> : SOPC <
735 op, (outs SCCReg:$dst), (ins rc:$src0, rc:$src1),
736 opName#" $src0, $src1", []>;
738 class SOPC_32<bits<7> op, string opName, PatLeaf cond = COND_NULL>
739 : SOPC_Helper<op, SSrc_32, i32, opName, cond>;
741 class SOPC_64<bits<7> op, string opName, PatLeaf cond = COND_NULL>
742 : SOPC_Helper<op, SSrc_64, i64, opName, cond>;
744 class SOPK_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
745 SOPK <outs, ins, "", pattern>,
746 SIMCInstr<opName, SISubtarget.NONE> {
748 let isCodeGenOnly = 1;
751 class SOPK_Real_si <sopk op, string opName, dag outs, dag ins, string asm> :
752 SOPK <outs, ins, asm, []>,
754 SIMCInstr<opName, SISubtarget.SI> {
755 let AssemblerPredicates = [isSICI];
756 let isCodeGenOnly = 0;
759 class SOPK_Real_vi <sopk op, string opName, dag outs, dag ins, string asm> :
760 SOPK <outs, ins, asm, []>,
762 SIMCInstr<opName, SISubtarget.VI> {
763 let AssemblerPredicates = [isVI];
764 let isCodeGenOnly = 0;
767 multiclass SOPK_m <sopk op, string opName, dag outs, dag ins, string opAsm,
768 string asm = opName#opAsm> {
769 def "" : SOPK_Pseudo <opName, outs, ins, []>;
771 def _si : SOPK_Real_si <op, opName, outs, ins, asm>;
773 def _vi : SOPK_Real_vi <op, opName, outs, ins, asm>;
777 multiclass SOPK_32 <sopk op, string opName, list<dag> pattern> {
778 def "" : SOPK_Pseudo <opName, (outs SReg_32:$dst), (ins u16imm:$src0),
781 def _si : SOPK_Real_si <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
782 opName#" $dst, $src0">;
784 def _vi : SOPK_Real_vi <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
785 opName#" $dst, $src0">;
788 multiclass SOPK_SCC <sopk op, string opName, list<dag> pattern> {
789 def "" : SOPK_Pseudo <opName, (outs SCCReg:$dst),
790 (ins SReg_32:$src0, u16imm:$src1), pattern>;
792 let DisableEncoding = "$dst" in {
793 def _si : SOPK_Real_si <op, opName, (outs SCCReg:$dst),
794 (ins SReg_32:$sdst, u16imm:$simm16), opName#" $sdst, $simm16">;
796 def _vi : SOPK_Real_vi <op, opName, (outs SCCReg:$dst),
797 (ins SReg_32:$sdst, u16imm:$simm16), opName#" $sdst, $simm16">;
801 multiclass SOPK_32TIE <sopk op, string opName, list<dag> pattern> : SOPK_m <
802 op, opName, (outs SReg_32:$sdst), (ins SReg_32:$src0, u16imm:$simm16),
806 multiclass SOPK_IMM32 <sopk op, string opName, dag outs, dag ins,
807 string argAsm, string asm = opName#argAsm> {
809 def "" : SOPK_Pseudo <opName, outs, ins, []>;
811 def _si : SOPK <outs, ins, asm, []>,
813 SIMCInstr<opName, SISubtarget.SI> {
814 let AssemblerPredicates = [isSICI];
815 let isCodeGenOnly = 0;
818 def _vi : SOPK <outs, ins, asm, []>,
820 SIMCInstr<opName, SISubtarget.VI> {
821 let AssemblerPredicates = [isVI];
822 let isCodeGenOnly = 0;
825 //===----------------------------------------------------------------------===//
827 //===----------------------------------------------------------------------===//
829 class SMRD_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
830 SMRD <outs, ins, "", pattern>,
831 SIMCInstr<opName, SISubtarget.NONE> {
833 let isCodeGenOnly = 1;
836 class SMRD_Real_si <bits<5> op, string opName, bit imm, dag outs, dag ins,
838 SMRD <outs, ins, asm, []>,
840 SIMCInstr<opName, SISubtarget.SI> {
841 let AssemblerPredicates = [isSICI];
844 class SMRD_Real_vi <bits<8> op, string opName, bit imm, dag outs, dag ins,
846 SMRD <outs, ins, asm, []>,
848 SIMCInstr<opName, SISubtarget.VI> {
849 let AssemblerPredicates = [isVI];
852 multiclass SMRD_m <bits<5> op, string opName, bit imm, dag outs, dag ins,
853 string asm, list<dag> pattern> {
855 def "" : SMRD_Pseudo <opName, outs, ins, pattern>;
857 def _si : SMRD_Real_si <op, opName, imm, outs, ins, asm>;
859 // glc is only applicable to scalar stores, which are not yet
862 def _vi : SMRD_Real_vi <{0, 0, 0, op}, opName, imm, outs, ins, asm>;
866 multiclass SMRD_Helper <bits<5> op, string opName, RegisterClass baseClass,
867 RegisterClass dstClass> {
869 op, opName#"_IMM", 1, (outs dstClass:$dst),
870 (ins baseClass:$sbase, u32imm:$offset),
871 opName#" $dst, $sbase, $offset", []
874 defm _SGPR : SMRD_m <
875 op, opName#"_SGPR", 0, (outs dstClass:$dst),
876 (ins baseClass:$sbase, SReg_32:$soff),
877 opName#" $dst, $sbase, $soff", []
881 //===----------------------------------------------------------------------===//
882 // Vector ALU classes
883 //===----------------------------------------------------------------------===//
885 // This must always be right before the operand being input modified.
886 def InputMods : OperandWithDefaultOps <i32, (ops (i32 0))> {
887 let PrintMethod = "printOperandAndMods";
890 def InputModsMatchClass : AsmOperandClass {
891 let Name = "RegWithInputMods";
894 def InputModsNoDefault : Operand <i32> {
895 let PrintMethod = "printOperandAndMods";
896 let ParserMatchClass = InputModsMatchClass;
899 class getNumSrcArgs<ValueType Src1, ValueType Src2> {
901 !if (!eq(Src1.Value, untyped.Value), 1, // VOP1
902 !if (!eq(Src2.Value, untyped.Value), 2, // VOP2
906 // Returns the register class to use for the destination of VOP[123C]
907 // instructions for the given VT.
908 class getVALUDstForVT<ValueType VT> {
909 RegisterOperand ret = !if(!eq(VT.Size, 32), VOPDstOperand<VGPR_32>,
910 !if(!eq(VT.Size, 64), VOPDstOperand<VReg_64>,
911 VOPDstOperand<SReg_64>)); // else VT == i1
914 // Returns the register class to use for source 0 of VOP[12C]
915 // instructions for the given VT.
916 class getVOPSrc0ForVT<ValueType VT> {
917 RegisterOperand ret = !if(!eq(VT.Size, 32), VSrc_32, VSrc_64);
920 // Returns the register class to use for source 1 of VOP[12C] for the
922 class getVOPSrc1ForVT<ValueType VT> {
923 RegisterClass ret = !if(!eq(VT.Size, 32), VGPR_32, VReg_64);
926 // Returns the register class to use for sources of VOP3 instructions for the
928 class getVOP3SrcForVT<ValueType VT> {
929 RegisterOperand ret = !if(!eq(VT.Size, 32), VCSrc_32, VCSrc_64);
932 // Returns 1 if the source arguments have modifiers, 0 if they do not.
933 class hasModifiers<ValueType SrcVT> {
934 bit ret = !if(!eq(SrcVT.Value, f32.Value), 1,
935 !if(!eq(SrcVT.Value, f64.Value), 1, 0));
938 // Returns the input arguments for VOP[12C] instructions for the given SrcVT.
939 class getIns32 <RegisterOperand Src0RC, RegisterClass Src1RC, int NumSrcArgs> {
940 dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0), // VOP1
941 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
945 // Returns the input arguments for VOP3 instructions for the given SrcVT.
946 class getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC,
947 RegisterOperand Src2RC, int NumSrcArgs,
951 !if (!eq(NumSrcArgs, 1),
952 !if (!eq(HasModifiers, 1),
953 // VOP1 with modifiers
954 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
955 ClampMod:$clamp, omod:$omod)
957 // VOP1 without modifiers
960 !if (!eq(NumSrcArgs, 2),
961 !if (!eq(HasModifiers, 1),
962 // VOP 2 with modifiers
963 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
964 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
965 ClampMod:$clamp, omod:$omod)
967 // VOP2 without modifiers
968 (ins Src0RC:$src0, Src1RC:$src1)
970 /* NumSrcArgs == 3 */,
971 !if (!eq(HasModifiers, 1),
972 // VOP3 with modifiers
973 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
974 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
975 InputModsNoDefault:$src2_modifiers, Src2RC:$src2,
976 ClampMod:$clamp, omod:$omod)
978 // VOP3 without modifiers
979 (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2)
983 // Returns the assembly string for the inputs and outputs of a VOP[12C]
984 // instruction. This does not add the _e32 suffix, so it can be reused
986 class getAsm32 <int NumSrcArgs> {
987 string src1 = ", $src1";
988 string src2 = ", $src2";
989 string ret = "$dst, $src0"#
990 !if(!eq(NumSrcArgs, 1), "", src1)#
991 !if(!eq(NumSrcArgs, 3), src2, "");
994 // Returns the assembly string for the inputs and outputs of a VOP3
996 class getAsm64 <int NumSrcArgs, bit HasModifiers> {
997 string src0 = !if(!eq(NumSrcArgs, 1), "$src0_modifiers", "$src0_modifiers,");
998 string src1 = !if(!eq(NumSrcArgs, 1), "",
999 !if(!eq(NumSrcArgs, 2), " $src1_modifiers",
1000 " $src1_modifiers,"));
1001 string src2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers", "");
1003 !if(!eq(HasModifiers, 0),
1004 getAsm32<NumSrcArgs>.ret,
1005 "$dst, "#src0#src1#src2#"$clamp"#"$omod");
1009 class VOPProfile <list<ValueType> _ArgVT> {
1011 field list<ValueType> ArgVT = _ArgVT;
1013 field ValueType DstVT = ArgVT[0];
1014 field ValueType Src0VT = ArgVT[1];
1015 field ValueType Src1VT = ArgVT[2];
1016 field ValueType Src2VT = ArgVT[3];
1017 field RegisterOperand DstRC = getVALUDstForVT<DstVT>.ret;
1018 field RegisterOperand Src0RC32 = getVOPSrc0ForVT<Src0VT>.ret;
1019 field RegisterClass Src1RC32 = getVOPSrc1ForVT<Src1VT>.ret;
1020 field RegisterOperand Src0RC64 = getVOP3SrcForVT<Src0VT>.ret;
1021 field RegisterOperand Src1RC64 = getVOP3SrcForVT<Src1VT>.ret;
1022 field RegisterOperand Src2RC64 = getVOP3SrcForVT<Src2VT>.ret;
1024 field int NumSrcArgs = getNumSrcArgs<Src1VT, Src2VT>.ret;
1025 field bit HasModifiers = hasModifiers<Src0VT>.ret;
1027 field dag Outs = (outs DstRC:$dst);
1029 field dag Ins32 = getIns32<Src0RC32, Src1RC32, NumSrcArgs>.ret;
1030 field dag Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
1033 field string Asm32 = getAsm32<NumSrcArgs>.ret;
1034 field string Asm64 = getAsm64<NumSrcArgs, HasModifiers>.ret;
1037 // FIXME: I think these F16 profiles will need to use f16 types in order
1038 // for the instruction patterns to work.
1039 def VOP_F16_F16 : VOPProfile <[f32, f32, untyped, untyped]>;
1040 def VOP_F16_I16 : VOPProfile <[f32, i32, untyped, untyped]>;
1041 def VOP_I16_F16 : VOPProfile <[i32, f32, untyped, untyped]>;
1043 def VOP_F32_F32 : VOPProfile <[f32, f32, untyped, untyped]>;
1044 def VOP_F32_F64 : VOPProfile <[f32, f64, untyped, untyped]>;
1045 def VOP_F32_I32 : VOPProfile <[f32, i32, untyped, untyped]>;
1046 def VOP_F64_F32 : VOPProfile <[f64, f32, untyped, untyped]>;
1047 def VOP_F64_F64 : VOPProfile <[f64, f64, untyped, untyped]>;
1048 def VOP_F64_I32 : VOPProfile <[f64, i32, untyped, untyped]>;
1049 def VOP_I32_F32 : VOPProfile <[i32, f32, untyped, untyped]>;
1050 def VOP_I32_F64 : VOPProfile <[i32, f64, untyped, untyped]>;
1051 def VOP_I32_I32 : VOPProfile <[i32, i32, untyped, untyped]>;
1053 def VOP_F32_F32_F32 : VOPProfile <[f32, f32, f32, untyped]>;
1054 def VOP_F32_F32_I32 : VOPProfile <[f32, f32, i32, untyped]>;
1055 def VOP_F64_F64_F64 : VOPProfile <[f64, f64, f64, untyped]>;
1056 def VOP_F64_F64_I32 : VOPProfile <[f64, f64, i32, untyped]>;
1057 def VOP_I32_F32_F32 : VOPProfile <[i32, f32, f32, untyped]>;
1058 def VOP_I32_F32_I32 : VOPProfile <[i32, f32, i32, untyped]>;
1059 def VOP_I32_I32_I32 : VOPProfile <[i32, i32, i32, untyped]>;
1060 def VOP_I32_I32_I32_VCC : VOPProfile <[i32, i32, i32, untyped]> {
1061 let Src0RC32 = VCSrc_32;
1064 def VOP_I1_F32_I32 : VOPProfile <[i1, f32, i32, untyped]> {
1065 let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
1066 let Asm64 = "$dst, $src0_modifiers, $src1";
1069 def VOP_I1_F64_I32 : VOPProfile <[i1, f64, i32, untyped]> {
1070 let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
1071 let Asm64 = "$dst, $src0_modifiers, $src1";
1074 def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>;
1075 def VOP_I64_I32_I64 : VOPProfile <[i64, i32, i64, untyped]>;
1076 def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>;
1077 def VOP_CNDMASK : VOPProfile <[i32, i32, i32, untyped]> {
1078 let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1, VCCReg:$src2);
1079 let Ins64 = (ins Src0RC64:$src0, Src1RC64:$src1, SSrc_64:$src2);
1080 let Asm64 = "$dst, $src0, $src1, $src2";
1083 def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>;
1084 def VOP_MADK : VOPProfile <[f32, f32, f32, f32]> {
1085 field dag Ins = (ins VCSrc_32:$src0, VGPR_32:$vsrc1, u32imm:$src2);
1086 field string Asm = "$dst, $src0, $vsrc1, $src2";
1088 def VOP_F64_F64_F64_F64 : VOPProfile <[f64, f64, f64, f64]>;
1089 def VOP_I32_I32_I32_I32 : VOPProfile <[i32, i32, i32, i32]>;
1090 def VOP_I64_I32_I32_I64 : VOPProfile <[i64, i32, i32, i64]>;
1093 class VOP <string opName> {
1094 string OpName = opName;
1097 class VOP2_REV <string revOp, bit isOrig> {
1098 string RevOp = revOp;
1099 bit IsOrig = isOrig;
1102 class AtomicNoRet <string noRetOp, bit isRet> {
1103 string NoRetOp = noRetOp;
1107 class VOP1_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
1108 VOP1Common <outs, ins, "", pattern>,
1110 SIMCInstr <opName#"_e32", SISubtarget.NONE>,
1111 MnemonicAlias<opName#"_e32", opName> {
1113 let isCodeGenOnly = 1;
1119 class VOP1_Real_si <string opName, vop1 op, dag outs, dag ins, string asm> :
1120 VOP1<op.SI, outs, ins, asm, []>,
1121 SIMCInstr <opName#"_e32", SISubtarget.SI> {
1122 let AssemblerPredicate = SIAssemblerPredicate;
1125 class VOP1_Real_vi <string opName, vop1 op, dag outs, dag ins, string asm> :
1126 VOP1<op.VI, outs, ins, asm, []>,
1127 SIMCInstr <opName#"_e32", SISubtarget.VI> {
1128 let AssemblerPredicates = [isVI];
1131 multiclass VOP1_m <vop1 op, dag outs, dag ins, string asm, list<dag> pattern,
1133 def "" : VOP1_Pseudo <outs, ins, pattern, opName>;
1135 def _si : VOP1_Real_si <opName, op, outs, ins, asm>;
1137 def _vi : VOP1_Real_vi <opName, op, outs, ins, asm>;
1140 multiclass VOP1SI_m <vop1 op, dag outs, dag ins, string asm, list<dag> pattern,
1142 def "" : VOP1_Pseudo <outs, ins, pattern, opName>;
1144 def _si : VOP1_Real_si <opName, op, outs, ins, asm>;
1147 class VOP2_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
1148 VOP2Common <outs, ins, "", pattern>,
1150 SIMCInstr<opName#"_e32", SISubtarget.NONE>,
1151 MnemonicAlias<opName#"_e32", opName> {
1153 let isCodeGenOnly = 1;
1156 class VOP2_Real_si <string opName, vop2 op, dag outs, dag ins, string asm> :
1157 VOP2 <op.SI, outs, ins, opName#asm, []>,
1158 SIMCInstr <opName#"_e32", SISubtarget.SI> {
1159 let AssemblerPredicates = [isSICI];
1162 class VOP2_Real_vi <string opName, vop2 op, dag outs, dag ins, string asm> :
1163 VOP2 <op.VI, outs, ins, opName#asm, []>,
1164 SIMCInstr <opName#"_e32", SISubtarget.VI> {
1165 let AssemblerPredicates = [isVI];
1168 multiclass VOP2SI_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern,
1169 string opName, string revOp> {
1170 def "" : VOP2_Pseudo <outs, ins, pattern, opName>,
1171 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
1173 def _si : VOP2_Real_si <opName, op, outs, ins, asm>;
1176 multiclass VOP2_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern,
1177 string opName, string revOp> {
1178 def "" : VOP2_Pseudo <outs, ins, pattern, opName>,
1179 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
1181 def _si : VOP2_Real_si <opName, op, outs, ins, asm>;
1183 def _vi : VOP2_Real_vi <opName, op, outs, ins, asm>;
1187 class VOP3DisableFields <bit HasSrc1, bit HasSrc2, bit HasModifiers> {
1189 bits<2> src0_modifiers = !if(HasModifiers, ?, 0);
1190 bits<2> src1_modifiers = !if(HasModifiers, !if(HasSrc1, ?, 0), 0);
1191 bits<2> src2_modifiers = !if(HasModifiers, !if(HasSrc2, ?, 0), 0);
1192 bits<2> omod = !if(HasModifiers, ?, 0);
1193 bits<1> clamp = !if(HasModifiers, ?, 0);
1194 bits<9> src1 = !if(HasSrc1, ?, 0);
1195 bits<9> src2 = !if(HasSrc2, ?, 0);
1198 class VOP3DisableModFields <bit HasSrc0Mods,
1199 bit HasSrc1Mods = 0,
1200 bit HasSrc2Mods = 0,
1201 bit HasOutputMods = 0> {
1202 bits<2> src0_modifiers = !if(HasSrc0Mods, ?, 0);
1203 bits<2> src1_modifiers = !if(HasSrc1Mods, ?, 0);
1204 bits<2> src2_modifiers = !if(HasSrc2Mods, ?, 0);
1205 bits<2> omod = !if(HasOutputMods, ?, 0);
1206 bits<1> clamp = !if(HasOutputMods, ?, 0);
1209 class VOP3_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
1210 VOP3Common <outs, ins, "", pattern>,
1212 SIMCInstr<opName#"_e64", SISubtarget.NONE>,
1213 MnemonicAlias<opName#"_e64", opName> {
1215 let isCodeGenOnly = 1;
1218 class VOP3_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
1219 VOP3Common <outs, ins, asm, []>,
1221 SIMCInstr<opName#"_e64", SISubtarget.SI> {
1222 let AssemblerPredicates = [isSICI];
1225 class VOP3_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName> :
1226 VOP3Common <outs, ins, asm, []>,
1228 SIMCInstr <opName#"_e64", SISubtarget.VI> {
1229 let AssemblerPredicates = [isVI];
1232 class VOP3b_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
1233 VOP3Common <outs, ins, asm, []>,
1235 SIMCInstr<opName#"_e64", SISubtarget.SI> {
1236 let AssemblerPredicates = [isSICI];
1239 class VOP3b_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName> :
1240 VOP3Common <outs, ins, asm, []>,
1242 SIMCInstr <opName#"_e64", SISubtarget.VI> {
1243 let AssemblerPredicates = [isVI];
1246 multiclass VOP3_m <vop op, dag outs, dag ins, string asm, list<dag> pattern,
1247 string opName, int NumSrcArgs, bit HasMods = 1> {
1249 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1251 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1252 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
1253 !if(!eq(NumSrcArgs, 2), 0, 1),
1255 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1256 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
1257 !if(!eq(NumSrcArgs, 2), 0, 1),
1261 // VOP3_m without source modifiers
1262 multiclass VOP3_m_nomods <vop op, dag outs, dag ins, string asm, list<dag> pattern,
1263 string opName, int NumSrcArgs, bit HasMods = 1> {
1265 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1267 let src0_modifiers = 0,
1272 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>;
1273 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>;
1277 multiclass VOP3_1_m <vop op, dag outs, dag ins, string asm,
1278 list<dag> pattern, string opName, bit HasMods = 1> {
1280 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1282 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1283 VOP3DisableFields<0, 0, HasMods>;
1285 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1286 VOP3DisableFields<0, 0, HasMods>;
1289 multiclass VOP3SI_1_m <vop op, dag outs, dag ins, string asm,
1290 list<dag> pattern, string opName, bit HasMods = 1> {
1292 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1294 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1295 VOP3DisableFields<0, 0, HasMods>;
1296 // No VI instruction. This class is for SI only.
1299 multiclass VOP3_2_m <vop op, dag outs, dag ins, string asm,
1300 list<dag> pattern, string opName, string revOp,
1301 bit HasMods = 1, bit UseFullOp = 0> {
1303 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1304 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
1306 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1307 VOP3DisableFields<1, 0, HasMods>;
1309 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1310 VOP3DisableFields<1, 0, HasMods>;
1313 multiclass VOP3SI_2_m <vop op, dag outs, dag ins, string asm,
1314 list<dag> pattern, string opName, string revOp,
1315 bit HasMods = 1, bit UseFullOp = 0> {
1317 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1318 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
1320 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1321 VOP3DisableFields<1, 0, HasMods>;
1323 // No VI instruction. This class is for SI only.
1326 // XXX - Is v_div_scale_{f32|f64} only available in vop3b without
1327 // option of implicit vcc use?
1328 multiclass VOP3b_2_m <vop op, dag outs, dag ins, string asm,
1329 list<dag> pattern, string opName, string revOp,
1330 bit HasMods = 1, bit UseFullOp = 0> {
1331 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1332 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
1334 // The VOP2 variant puts the carry out into VCC, the VOP3 variant
1335 // can write it into any SGPR. We currently don't use the carry out,
1336 // so for now hardcode it to VCC as well.
1337 let sdst = SIOperand.VCC, Defs = [VCC] in {
1338 def _si : VOP3b_Real_si <op.SI3, outs, ins, asm, opName>,
1339 VOP3DisableFields<1, 0, HasMods>;
1341 def _vi : VOP3b_Real_vi <op.VI3, outs, ins, asm, opName>,
1342 VOP3DisableFields<1, 0, HasMods>;
1343 } // End sdst = SIOperand.VCC, Defs = [VCC]
1346 multiclass VOP3b_3_m <vop op, dag outs, dag ins, string asm,
1347 list<dag> pattern, string opName, string revOp,
1348 bit HasMods = 1, bit UseFullOp = 0> {
1349 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1352 def _si : VOP3b_Real_si <op.SI3, outs, ins, asm, opName>,
1353 VOP3DisableFields<1, 1, HasMods>;
1355 def _vi : VOP3b_Real_vi <op.VI3, outs, ins, asm, opName>,
1356 VOP3DisableFields<1, 1, HasMods>;
1359 multiclass VOP3_C_m <vop op, dag outs, dag ins, string asm,
1360 list<dag> pattern, string opName,
1361 bit HasMods, bit defExec, string revOp> {
1363 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1364 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
1366 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1367 VOP3DisableFields<1, 0, HasMods> {
1368 let Defs = !if(defExec, [EXEC], []);
1371 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1372 VOP3DisableFields<1, 0, HasMods> {
1373 let Defs = !if(defExec, [EXEC], []);
1377 // An instruction that is VOP2 on SI and VOP3 on VI, no modifiers.
1378 multiclass VOP2SI_3VI_m <vop3 op, string opName, dag outs, dag ins,
1379 string asm, list<dag> pattern = []> {
1380 let isPseudo = 1, isCodeGenOnly = 1 in {
1381 def "" : VOPAnyCommon <outs, ins, "", pattern>,
1382 SIMCInstr<opName, SISubtarget.NONE>;
1385 def _si : VOP2 <op.SI3{5-0}, outs, ins, asm, []>,
1386 SIMCInstr <opName, SISubtarget.SI> {
1387 let AssemblerPredicates = [isSICI];
1390 def _vi : VOP3Common <outs, ins, asm, []>,
1392 VOP3DisableFields <1, 0, 0>,
1393 SIMCInstr <opName, SISubtarget.VI> {
1394 let AssemblerPredicates = [isVI];
1398 multiclass VOP1_Helper <vop1 op, string opName, dag outs,
1399 dag ins32, string asm32, list<dag> pat32,
1400 dag ins64, string asm64, list<dag> pat64,
1403 defm _e32 : VOP1_m <op, outs, ins32, opName#asm32, pat32, opName>;
1405 defm _e64 : VOP3_1_m <op, outs, ins64, opName#asm64, pat64, opName, HasMods>;
1408 multiclass VOP1Inst <vop1 op, string opName, VOPProfile P,
1409 SDPatternOperator node = null_frag> : VOP1_Helper <
1411 P.Ins32, P.Asm32, [],
1414 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
1415 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
1416 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
1420 multiclass VOP1InstSI <vop1 op, string opName, VOPProfile P,
1421 SDPatternOperator node = null_frag> {
1423 defm _e32 : VOP1SI_m <op, P.Outs, P.Ins32, opName#P.Asm32, [], opName>;
1425 defm _e64 : VOP3SI_1_m <op, P.Outs, P.Ins64, opName#P.Asm64,
1427 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
1428 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
1429 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
1430 opName, P.HasModifiers>;
1433 multiclass VOP2_Helper <vop2 op, string opName, dag outs,
1434 dag ins32, string asm32, list<dag> pat32,
1435 dag ins64, string asm64, list<dag> pat64,
1436 string revOp, bit HasMods> {
1437 defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOp>;
1439 defm _e64 : VOP3_2_m <op,
1440 outs, ins64, opName#asm64, pat64, opName, revOp, HasMods
1444 multiclass VOP2Inst <vop2 op, string opName, VOPProfile P,
1445 SDPatternOperator node = null_frag,
1446 string revOp = opName> : VOP2_Helper <
1448 P.Ins32, P.Asm32, [],
1452 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1453 i1:$clamp, i32:$omod)),
1454 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1455 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1456 revOp, P.HasModifiers
1459 multiclass VOP2InstSI <vop2 op, string opName, VOPProfile P,
1460 SDPatternOperator node = null_frag,
1461 string revOp = opName> {
1462 defm _e32 : VOP2SI_m <op, P.Outs, P.Ins32, P.Asm32, [], opName, revOp>;
1464 defm _e64 : VOP3SI_2_m <op, P.Outs, P.Ins64, opName#P.Asm64,
1467 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1468 i1:$clamp, i32:$omod)),
1469 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1470 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1471 opName, revOp, P.HasModifiers>;
1474 multiclass VOP2b_Helper <vop2 op, string opName, dag outs,
1475 dag ins32, string asm32, list<dag> pat32,
1476 dag ins64, string asm64, list<dag> pat64,
1477 string revOp, bit HasMods> {
1479 defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOp>;
1481 defm _e64 : VOP3b_2_m <op,
1482 outs, ins64, opName#asm64, pat64, opName, revOp, HasMods
1486 multiclass VOP2bInst <vop2 op, string opName, VOPProfile P,
1487 SDPatternOperator node = null_frag,
1488 string revOp = opName> : VOP2b_Helper <
1490 P.Ins32, P.Asm32, [],
1494 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1495 i1:$clamp, i32:$omod)),
1496 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1497 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1498 revOp, P.HasModifiers
1501 // A VOP2 instruction that is VOP3-only on VI.
1502 multiclass VOP2_VI3_Helper <vop23 op, string opName, dag outs,
1503 dag ins32, string asm32, list<dag> pat32,
1504 dag ins64, string asm64, list<dag> pat64,
1505 string revOp, bit HasMods> {
1506 defm _e32 : VOP2SI_m <op, outs, ins32, asm32, pat32, opName, revOp>;
1508 defm _e64 : VOP3_2_m <op, outs, ins64, opName#asm64, pat64, opName,
1512 multiclass VOP2_VI3_Inst <vop23 op, string opName, VOPProfile P,
1513 SDPatternOperator node = null_frag,
1514 string revOp = opName>
1517 P.Ins32, P.Asm32, [],
1521 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1522 i1:$clamp, i32:$omod)),
1523 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1524 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1525 revOp, P.HasModifiers
1528 multiclass VOP2MADK <vop2 op, string opName, list<dag> pattern = []> {
1530 def "" : VOP2_Pseudo <VOP_MADK.Outs, VOP_MADK.Ins, pattern, opName>;
1532 let isCodeGenOnly = 0 in {
1533 def _si : VOP2Common <VOP_MADK.Outs, VOP_MADK.Ins,
1534 !strconcat(opName, VOP_MADK.Asm), []>,
1535 SIMCInstr <opName#"_e32", SISubtarget.SI>,
1538 def _vi : VOP2Common <VOP_MADK.Outs, VOP_MADK.Ins,
1539 !strconcat(opName, VOP_MADK.Asm), []>,
1540 SIMCInstr <opName#"_e32", SISubtarget.VI>,
1542 } // End isCodeGenOnly = 0
1545 class VOPC_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
1546 VOPCCommon <ins, "", pattern>,
1548 SIMCInstr<opName#"_e32", SISubtarget.NONE>,
1549 MnemonicAlias<opName#"_e32", opName> {
1551 let isCodeGenOnly = 1;
1554 multiclass VOPC_m <vopc op, dag outs, dag ins, string asm, list<dag> pattern,
1555 string opName, bit DefExec, string revOpName = ""> {
1556 def "" : VOPC_Pseudo <outs, ins, pattern, opName>;
1558 def _si : VOPC<op.SI, ins, asm, []>,
1559 SIMCInstr <opName#"_e32", SISubtarget.SI> {
1560 let Defs = !if(DefExec, [EXEC], []);
1561 let hasSideEffects = DefExec;
1564 def _vi : VOPC<op.VI, ins, asm, []>,
1565 SIMCInstr <opName#"_e32", SISubtarget.VI> {
1566 let Defs = !if(DefExec, [EXEC], []);
1567 let hasSideEffects = DefExec;
1571 multiclass VOPC_Helper <vopc op, string opName,
1572 dag ins32, string asm32, list<dag> pat32,
1573 dag out64, dag ins64, string asm64, list<dag> pat64,
1574 bit HasMods, bit DefExec, string revOp> {
1575 defm _e32 : VOPC_m <op, (outs), ins32, opName#asm32, pat32, opName, DefExec>;
1577 defm _e64 : VOP3_C_m <op, out64, ins64, opName#asm64, pat64,
1578 opName, HasMods, DefExec, revOp>;
1581 // Special case for class instructions which only have modifiers on
1582 // the 1st source operand.
1583 multiclass VOPC_Class_Helper <vopc op, string opName,
1584 dag ins32, string asm32, list<dag> pat32,
1585 dag out64, dag ins64, string asm64, list<dag> pat64,
1586 bit HasMods, bit DefExec, string revOp> {
1587 defm _e32 : VOPC_m <op, (outs), ins32, opName#asm32, pat32, opName, DefExec>;
1589 defm _e64 : VOP3_C_m <op, out64, ins64, opName#asm64, pat64,
1590 opName, HasMods, DefExec, revOp>,
1591 VOP3DisableModFields<1, 0, 0>;
1594 multiclass VOPCInst <vopc op, string opName,
1595 VOPProfile P, PatLeaf cond = COND_NULL,
1596 string revOp = opName,
1597 bit DefExec = 0> : VOPC_Helper <
1599 P.Ins32, P.Asm32, [],
1600 (outs VOPDstS64:$dst), P.Ins64, P.Asm64,
1603 (setcc (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1604 i1:$clamp, i32:$omod)),
1605 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1607 [(set i1:$dst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]),
1608 P.HasModifiers, DefExec, revOp
1611 multiclass VOPCClassInst <vopc op, string opName, VOPProfile P,
1612 bit DefExec = 0> : VOPC_Class_Helper <
1614 P.Ins32, P.Asm32, [],
1615 (outs VOPDstS64:$dst), P.Ins64, P.Asm64,
1618 (AMDGPUfp_class (P.Src0VT (VOP3Mods0Clamp0OMod P.Src0VT:$src0, i32:$src0_modifiers)), P.Src1VT:$src1))],
1619 [(set i1:$dst, (AMDGPUfp_class P.Src0VT:$src0, P.Src1VT:$src1))]),
1620 P.HasModifiers, DefExec, opName
1624 multiclass VOPC_F32 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
1625 VOPCInst <op, opName, VOP_F32_F32_F32, cond, revOp>;
1627 multiclass VOPC_F64 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
1628 VOPCInst <op, opName, VOP_F64_F64_F64, cond, revOp>;
1630 multiclass VOPC_I32 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
1631 VOPCInst <op, opName, VOP_I32_I32_I32, cond, revOp>;
1633 multiclass VOPC_I64 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
1634 VOPCInst <op, opName, VOP_I64_I64_I64, cond, revOp>;
1637 multiclass VOPCX <vopc op, string opName, VOPProfile P,
1638 PatLeaf cond = COND_NULL,
1640 : VOPCInst <op, opName, P, cond, revOp, 1>;
1642 multiclass VOPCX_F32 <vopc op, string opName, string revOp = opName> :
1643 VOPCX <op, opName, VOP_F32_F32_F32, COND_NULL, revOp>;
1645 multiclass VOPCX_F64 <vopc op, string opName, string revOp = opName> :
1646 VOPCX <op, opName, VOP_F64_F64_F64, COND_NULL, revOp>;
1648 multiclass VOPCX_I32 <vopc op, string opName, string revOp = opName> :
1649 VOPCX <op, opName, VOP_I32_I32_I32, COND_NULL, revOp>;
1651 multiclass VOPCX_I64 <vopc op, string opName, string revOp = opName> :
1652 VOPCX <op, opName, VOP_I64_I64_I64, COND_NULL, revOp>;
1654 multiclass VOP3_Helper <vop3 op, string opName, dag outs, dag ins, string asm,
1655 list<dag> pat, int NumSrcArgs, bit HasMods> : VOP3_m <
1656 op, outs, ins, opName#" "#asm, pat, opName, NumSrcArgs, HasMods
1659 multiclass VOPC_CLASS_F32 <vopc op, string opName> :
1660 VOPCClassInst <op, opName, VOP_I1_F32_I32, 0>;
1662 multiclass VOPCX_CLASS_F32 <vopc op, string opName> :
1663 VOPCClassInst <op, opName, VOP_I1_F32_I32, 1>;
1665 multiclass VOPC_CLASS_F64 <vopc op, string opName> :
1666 VOPCClassInst <op, opName, VOP_I1_F64_I32, 0>;
1668 multiclass VOPCX_CLASS_F64 <vopc op, string opName> :
1669 VOPCClassInst <op, opName, VOP_I1_F64_I32, 1>;
1671 multiclass VOP3Inst <vop3 op, string opName, VOPProfile P,
1672 SDPatternOperator node = null_frag> : VOP3_Helper <
1673 op, opName, (outs P.DstRC.RegClass:$dst), P.Ins64, P.Asm64,
1674 !if(!eq(P.NumSrcArgs, 3),
1677 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1678 i1:$clamp, i32:$omod)),
1679 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1680 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))],
1681 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1,
1683 !if(!eq(P.NumSrcArgs, 2),
1686 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1687 i1:$clamp, i32:$omod)),
1688 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1689 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))])
1690 /* P.NumSrcArgs == 1 */,
1693 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1694 i1:$clamp, i32:$omod))))],
1695 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]))),
1696 P.NumSrcArgs, P.HasModifiers
1699 // Special case for v_div_fmas_{f32|f64}, since it seems to be the
1700 // only VOP instruction that implicitly reads VCC.
1701 multiclass VOP3_VCC_Inst <vop3 op, string opName,
1703 SDPatternOperator node = null_frag> : VOP3_Helper <
1705 (outs P.DstRC.RegClass:$dst),
1706 (ins InputModsNoDefault:$src0_modifiers, P.Src0RC64:$src0,
1707 InputModsNoDefault:$src1_modifiers, P.Src1RC64:$src1,
1708 InputModsNoDefault:$src2_modifiers, P.Src2RC64:$src2,
1711 " $dst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod",
1713 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1714 i1:$clamp, i32:$omod)),
1715 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1716 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers)),
1721 multiclass VOP3b_Helper <vop op, RegisterClass vrc, RegisterOperand arc,
1722 string opName, list<dag> pattern> :
1724 op, (outs vrc:$vdst, SReg_64:$sdst),
1725 (ins InputModsNoDefault:$src0_modifiers, arc:$src0,
1726 InputModsNoDefault:$src1_modifiers, arc:$src1,
1727 InputModsNoDefault:$src2_modifiers, arc:$src2,
1728 ClampMod:$clamp, omod:$omod),
1729 opName#" $vdst, $sdst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod", pattern,
1730 opName, opName, 1, 1
1733 multiclass VOP3b_64 <vop3 op, string opName, list<dag> pattern> :
1734 VOP3b_Helper <op, VReg_64, VSrc_64, opName, pattern>;
1736 multiclass VOP3b_32 <vop3 op, string opName, list<dag> pattern> :
1737 VOP3b_Helper <op, VGPR_32, VSrc_32, opName, pattern>;
1740 class Vop3ModPat<Instruction Inst, VOPProfile P, SDPatternOperator node> : Pat<
1741 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),
1742 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1743 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))),
1744 (Inst i32:$src0_modifiers, P.Src0VT:$src0,
1745 i32:$src1_modifiers, P.Src1VT:$src1,
1746 i32:$src2_modifiers, P.Src2VT:$src2,
1750 //===----------------------------------------------------------------------===//
1751 // Interpolation opcodes
1752 //===----------------------------------------------------------------------===//
1754 class VINTRP_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1755 VINTRPCommon <outs, ins, "", pattern>,
1756 SIMCInstr<opName, SISubtarget.NONE> {
1758 let isCodeGenOnly = 1;
1761 class VINTRP_Real_si <bits <2> op, string opName, dag outs, dag ins,
1763 VINTRPCommon <outs, ins, asm, []>,
1765 SIMCInstr<opName, SISubtarget.SI>;
1767 class VINTRP_Real_vi <bits <2> op, string opName, dag outs, dag ins,
1769 VINTRPCommon <outs, ins, asm, []>,
1771 SIMCInstr<opName, SISubtarget.VI>;
1773 multiclass VINTRP_m <bits <2> op, string opName, dag outs, dag ins, string asm,
1774 list<dag> pattern = [],
1775 string disableEncoding = "", string constraints = ""> {
1776 let DisableEncoding = disableEncoding,
1777 Constraints = constraints in {
1778 def "" : VINTRP_Pseudo <opName, outs, ins, pattern>;
1780 def _si : VINTRP_Real_si <op, opName, outs, ins, asm>;
1782 def _vi : VINTRP_Real_vi <op, opName, outs, ins, asm>;
1786 //===----------------------------------------------------------------------===//
1787 // Vector I/O classes
1788 //===----------------------------------------------------------------------===//
1790 class DS_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1791 DS <outs, ins, "", pattern>,
1792 SIMCInstr <opName, SISubtarget.NONE> {
1794 let isCodeGenOnly = 1;
1797 class DS_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
1798 DS <outs, ins, asm, []>,
1800 SIMCInstr <opName, SISubtarget.SI> {
1801 let isCodeGenOnly = 0;
1804 class DS_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
1805 DS <outs, ins, asm, []>,
1807 SIMCInstr <opName, SISubtarget.VI>;
1809 class DS_Off16_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
1810 DS_Real_si <op,opName, outs, ins, asm> {
1812 // Single load interpret the 2 i8imm operands as a single i16 offset.
1814 let offset0 = offset{7-0};
1815 let offset1 = offset{15-8};
1816 let isCodeGenOnly = 0;
1819 class DS_Off16_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
1820 DS_Real_vi <op, opName, outs, ins, asm> {
1822 // Single load interpret the 2 i8imm operands as a single i16 offset.
1824 let offset0 = offset{7-0};
1825 let offset1 = offset{15-8};
1828 multiclass DS_1A_RET <bits<8> op, string opName, RegisterClass rc,
1829 dag outs = (outs rc:$vdst),
1830 dag ins = (ins VGPR_32:$addr, ds_offset:$offset, gds:$gds),
1831 string asm = opName#" $vdst, $addr"#"$offset$gds"> {
1833 def "" : DS_Pseudo <opName, outs, ins, []>;
1835 let data0 = 0, data1 = 0 in {
1836 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1837 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1841 multiclass DS_1A_Off8_RET <bits<8> op, string opName, RegisterClass rc,
1842 dag outs = (outs rc:$vdst),
1843 dag ins = (ins VGPR_32:$addr, ds_offset0:$offset0, ds_offset1:$offset1,
1845 string asm = opName#" $vdst, $addr"#"$offset0"#"$offset1$gds"> {
1847 def "" : DS_Pseudo <opName, outs, ins, []>;
1849 let data0 = 0, data1 = 0, AsmMatchConverter = "cvtDSOffset01" in {
1850 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1851 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1855 multiclass DS_1A1D_NORET <bits<8> op, string opName, RegisterClass rc,
1857 dag ins = (ins VGPR_32:$addr, rc:$data0, ds_offset:$offset, gds:$gds),
1858 string asm = opName#" $addr, $data0"#"$offset$gds"> {
1860 def "" : DS_Pseudo <opName, outs, ins, []>,
1861 AtomicNoRet<opName, 0>;
1863 let data1 = 0, vdst = 0 in {
1864 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1865 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1869 multiclass DS_1A1D_Off8_NORET <bits<8> op, string opName, RegisterClass rc,
1871 dag ins = (ins VGPR_32:$addr, rc:$data0, rc:$data1,
1872 ds_offset0:$offset0, ds_offset1:$offset1, gds01:$gds),
1873 string asm = opName#" $addr, $data0, $data1"#"$offset0"#"$offset1"#"$gds"> {
1875 def "" : DS_Pseudo <opName, outs, ins, []>;
1877 let vdst = 0, AsmMatchConverter = "cvtDSOffset01" in {
1878 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1879 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1883 multiclass DS_1A1D_RET <bits<8> op, string opName, RegisterClass rc,
1884 string noRetOp = "",
1885 dag outs = (outs rc:$vdst),
1886 dag ins = (ins VGPR_32:$addr, rc:$data0, ds_offset:$offset, gds:$gds),
1887 string asm = opName#" $vdst, $addr, $data0"#"$offset$gds"> {
1889 def "" : DS_Pseudo <opName, outs, ins, []>,
1890 AtomicNoRet<noRetOp, 1>;
1893 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1894 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1898 multiclass DS_1A2D_RET_m <bits<8> op, string opName, RegisterClass rc,
1899 string noRetOp = "", dag ins,
1900 dag outs = (outs rc:$vdst),
1901 string asm = opName#" $vdst, $addr, $data0, $data1"#"$offset"#"$gds"> {
1903 def "" : DS_Pseudo <opName, outs, ins, []>,
1904 AtomicNoRet<noRetOp, 1>;
1906 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1907 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1910 multiclass DS_1A2D_RET <bits<8> op, string asm, RegisterClass rc,
1911 string noRetOp = "", RegisterClass src = rc> :
1912 DS_1A2D_RET_m <op, asm, rc, noRetOp,
1913 (ins VGPR_32:$addr, src:$data0, src:$data1,
1914 ds_offset:$offset, gds:$gds)
1917 multiclass DS_1A2D_NORET <bits<8> op, string opName, RegisterClass rc,
1918 string noRetOp = opName,
1920 dag ins = (ins VGPR_32:$addr, rc:$data0, rc:$data1,
1921 ds_offset:$offset, gds:$gds),
1922 string asm = opName#" $addr, $data0, $data1"#"$offset"#"$gds"> {
1924 def "" : DS_Pseudo <opName, outs, ins, []>,
1925 AtomicNoRet<noRetOp, 0>;
1928 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1929 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1933 multiclass DS_0A_RET <bits<8> op, string opName,
1934 dag outs = (outs VGPR_32:$vdst),
1935 dag ins = (ins ds_offset:$offset, gds:$gds),
1936 string asm = opName#" $vdst"#"$offset"#"$gds"> {
1938 let mayLoad = 1, mayStore = 1 in {
1939 def "" : DS_Pseudo <opName, outs, ins, []>;
1941 let addr = 0, data0 = 0, data1 = 0 in {
1942 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1943 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1944 } // end addr = 0, data0 = 0, data1 = 0
1945 } // end mayLoad = 1, mayStore = 1
1948 multiclass DS_1A_RET_GDS <bits<8> op, string opName,
1949 dag outs = (outs VGPR_32:$vdst),
1950 dag ins = (ins VGPR_32:$addr, ds_offset_gds:$offset),
1951 string asm = opName#" $vdst, $addr"#"$offset gds"> {
1953 def "" : DS_Pseudo <opName, outs, ins, []>;
1955 let data0 = 0, data1 = 0, gds = 1 in {
1956 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1957 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1958 } // end data0 = 0, data1 = 0, gds = 1
1961 multiclass DS_1A_GDS <bits<8> op, string opName,
1963 dag ins = (ins VGPR_32:$addr),
1964 string asm = opName#" $addr gds"> {
1966 def "" : DS_Pseudo <opName, outs, ins, []>;
1968 let vdst = 0, data0 = 0, data1 = 0, offset0 = 0, offset1 = 0, gds = 1 in {
1969 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1970 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1971 } // end vdst = 0, data = 0, data1 = 0, gds = 1
1974 multiclass DS_1A <bits<8> op, string opName,
1976 dag ins = (ins VGPR_32:$addr, ds_offset:$offset, gds:$gds),
1977 string asm = opName#" $addr"#"$offset"#"$gds"> {
1979 let mayLoad = 1, mayStore = 1 in {
1980 def "" : DS_Pseudo <opName, outs, ins, []>;
1982 let vdst = 0, data0 = 0, data1 = 0 in {
1983 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1984 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1985 } // let vdst = 0, data0 = 0, data1 = 0
1986 } // end mayLoad = 1, mayStore = 1
1989 //===----------------------------------------------------------------------===//
1991 //===----------------------------------------------------------------------===//
1993 class MTBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1994 MTBUF <outs, ins, "", pattern>,
1995 SIMCInstr<opName, SISubtarget.NONE> {
1997 let isCodeGenOnly = 1;
2000 class MTBUF_Real_si <bits<3> op, string opName, dag outs, dag ins,
2002 MTBUF <outs, ins, asm, []>,
2004 SIMCInstr<opName, SISubtarget.SI>;
2006 class MTBUF_Real_vi <bits<4> op, string opName, dag outs, dag ins, string asm> :
2007 MTBUF <outs, ins, asm, []>,
2009 SIMCInstr <opName, SISubtarget.VI>;
2011 multiclass MTBUF_m <bits<3> op, string opName, dag outs, dag ins, string asm,
2012 list<dag> pattern> {
2014 def "" : MTBUF_Pseudo <opName, outs, ins, pattern>;
2016 def _si : MTBUF_Real_si <op, opName, outs, ins, asm>;
2018 def _vi : MTBUF_Real_vi <{0, op{2}, op{1}, op{0}}, opName, outs, ins, asm>;
2022 let mayStore = 1, mayLoad = 0 in {
2024 multiclass MTBUF_Store_Helper <bits<3> op, string opName,
2025 RegisterClass regClass> : MTBUF_m <
2027 (ins regClass:$vdata, u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
2028 i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr,
2029 SReg_128:$srsrc, i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
2030 opName#" $vdata, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
2031 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
2034 } // mayStore = 1, mayLoad = 0
2036 let mayLoad = 1, mayStore = 0 in {
2038 multiclass MTBUF_Load_Helper <bits<3> op, string opName,
2039 RegisterClass regClass> : MTBUF_m <
2040 op, opName, (outs regClass:$dst),
2041 (ins u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
2042 i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr, SReg_128:$srsrc,
2043 i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
2044 opName#" $dst, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
2045 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
2048 } // mayLoad = 1, mayStore = 0
2050 //===----------------------------------------------------------------------===//
2052 //===----------------------------------------------------------------------===//
2054 class mubuf <bits<7> si, bits<7> vi = si> {
2055 field bits<7> SI = si;
2056 field bits<7> VI = vi;
2059 let isCodeGenOnly = 0 in {
2061 class MUBUF_si <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
2062 MUBUF <outs, ins, asm, pattern>, MUBUFe <op> {
2066 } // End let isCodeGenOnly = 0
2068 class MUBUF_vi <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
2069 MUBUF <outs, ins, asm, pattern>, MUBUFe_vi <op> {
2073 class MUBUFAddr64Table <bit is_addr64, string suffix = ""> {
2074 bit IsAddr64 = is_addr64;
2075 string OpName = NAME # suffix;
2078 class MUBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
2079 MUBUF <outs, ins, "", pattern>,
2080 SIMCInstr<opName, SISubtarget.NONE> {
2082 let isCodeGenOnly = 1;
2084 // dummy fields, so that we can use let statements around multiclasses
2094 class MUBUF_Real_si <mubuf op, string opName, dag outs, dag ins,
2096 MUBUF <outs, ins, asm, []>,
2098 SIMCInstr<opName, SISubtarget.SI> {
2102 class MUBUF_Real_vi <mubuf op, string opName, dag outs, dag ins,
2104 MUBUF <outs, ins, asm, []>,
2106 SIMCInstr<opName, SISubtarget.VI> {
2110 multiclass MUBUF_m <mubuf op, string opName, dag outs, dag ins, string asm,
2111 list<dag> pattern> {
2113 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
2114 MUBUFAddr64Table <0>;
2116 let addr64 = 0, isCodeGenOnly = 0 in {
2117 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
2120 def _vi : MUBUF_Real_vi <op, opName, outs, ins, asm>;
2123 multiclass MUBUFAddr64_m <mubuf op, string opName, dag outs,
2124 dag ins, string asm, list<dag> pattern> {
2126 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
2127 MUBUFAddr64Table <1>;
2129 let addr64 = 1, isCodeGenOnly = 0 in {
2130 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
2133 // There is no VI version. If the pseudo is selected, it should be lowered
2134 // for VI appropriately.
2137 multiclass MUBUFAtomicOffset_m <mubuf op, string opName, dag outs, dag ins,
2138 string asm, list<dag> pattern, bit is_return> {
2140 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
2141 MUBUFAddr64Table <0, !if(is_return, "_RTN", "")>,
2142 AtomicNoRet<NAME#"_OFFSET", is_return>;
2144 let offen = 0, idxen = 0, tfe = 0, vaddr = 0 in {
2146 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
2149 def _vi : MUBUF_Real_vi <op, opName, outs, ins, asm>;
2153 multiclass MUBUFAtomicAddr64_m <mubuf op, string opName, dag outs, dag ins,
2154 string asm, list<dag> pattern, bit is_return> {
2156 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
2157 MUBUFAddr64Table <1, !if(is_return, "_RTN", "")>,
2158 AtomicNoRet<NAME#"_ADDR64", is_return>;
2160 let offen = 0, idxen = 0, addr64 = 1, tfe = 0 in {
2161 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
2164 // There is no VI version. If the pseudo is selected, it should be lowered
2165 // for VI appropriately.
2168 multiclass MUBUF_Atomic <mubuf op, string name, RegisterClass rc,
2169 ValueType vt, SDPatternOperator atomic> {
2171 let mayStore = 1, mayLoad = 1, hasPostISelHook = 1 in {
2173 // No return variants
2176 defm _ADDR64 : MUBUFAtomicAddr64_m <
2177 op, name#"_addr64", (outs),
2178 (ins rc:$vdata, SReg_128:$srsrc, VReg_64:$vaddr,
2179 SCSrc_32:$soffset, mbuf_offset:$offset, slc:$slc),
2180 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#"$slc", [], 0
2183 defm _OFFSET : MUBUFAtomicOffset_m <
2184 op, name#"_offset", (outs),
2185 (ins rc:$vdata, SReg_128:$srsrc, SCSrc_32:$soffset, mbuf_offset:$offset,
2187 name#" $vdata, $srsrc, $soffset"#"$offset"#"$slc", [], 0
2191 // Variant that return values
2192 let glc = 1, Constraints = "$vdata = $vdata_in",
2193 DisableEncoding = "$vdata_in" in {
2195 defm _RTN_ADDR64 : MUBUFAtomicAddr64_m <
2196 op, name#"_rtn_addr64", (outs rc:$vdata),
2197 (ins rc:$vdata_in, SReg_128:$srsrc, VReg_64:$vaddr,
2198 SCSrc_32:$soffset, mbuf_offset:$offset, slc:$slc),
2199 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#" glc"#"$slc",
2201 (atomic (MUBUFAddr64Atomic v4i32:$srsrc, i64:$vaddr, i32:$soffset,
2202 i16:$offset, i1:$slc), vt:$vdata_in))], 1
2205 defm _RTN_OFFSET : MUBUFAtomicOffset_m <
2206 op, name#"_rtn_offset", (outs rc:$vdata),
2207 (ins rc:$vdata_in, SReg_128:$srsrc, SCSrc_32:$soffset,
2208 mbuf_offset:$offset, slc:$slc),
2209 name#" $vdata, $srsrc, $soffset"#"$offset"#" glc $slc",
2211 (atomic (MUBUFOffsetAtomic v4i32:$srsrc, i32:$soffset, i16:$offset,
2212 i1:$slc), vt:$vdata_in))], 1
2217 } // mayStore = 1, mayLoad = 1, hasPostISelHook = 1
2220 multiclass MUBUF_Load_Helper <mubuf op, string name, RegisterClass regClass,
2221 ValueType load_vt = i32,
2222 SDPatternOperator ld = null_frag> {
2224 let mayLoad = 1, mayStore = 0 in {
2225 let offen = 0, idxen = 0, vaddr = 0 in {
2226 defm _OFFSET : MUBUF_m <op, name#"_offset", (outs regClass:$vdata),
2227 (ins SReg_128:$srsrc, SCSrc_32:$soffset,
2228 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
2229 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
2230 [(set load_vt:$vdata, (ld (MUBUFOffset v4i32:$srsrc,
2231 i32:$soffset, i16:$offset,
2232 i1:$glc, i1:$slc, i1:$tfe)))]>;
2235 let offen = 1, idxen = 0 in {
2236 defm _OFFEN : MUBUF_m <op, name#"_offen", (outs regClass:$vdata),
2237 (ins VGPR_32:$vaddr, SReg_128:$srsrc,
2238 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, slc:$slc,
2240 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2243 let offen = 0, idxen = 1 in {
2244 defm _IDXEN : MUBUF_m <op, name#"_idxen", (outs regClass:$vdata),
2245 (ins VGPR_32:$vaddr, SReg_128:$srsrc,
2246 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc,
2247 slc:$slc, tfe:$tfe),
2248 name#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2251 let offen = 1, idxen = 1 in {
2252 defm _BOTHEN : MUBUF_m <op, name#"_bothen", (outs regClass:$vdata),
2253 (ins VReg_64:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset,
2254 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
2255 name#" $vdata, $vaddr, $srsrc, $soffset idxen offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2258 let offen = 0, idxen = 0 in {
2259 defm _ADDR64 : MUBUFAddr64_m <op, name#"_addr64", (outs regClass:$vdata),
2260 (ins VReg_64:$vaddr, SReg_128:$srsrc,
2261 SCSrc_32:$soffset, mbuf_offset:$offset,
2262 glc:$glc, slc:$slc, tfe:$tfe),
2263 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#
2264 "$glc"#"$slc"#"$tfe",
2265 [(set load_vt:$vdata, (ld (MUBUFAddr64 v4i32:$srsrc,
2266 i64:$vaddr, i32:$soffset,
2267 i16:$offset, i1:$glc, i1:$slc,
2273 multiclass MUBUF_Store_Helper <mubuf op, string name, RegisterClass vdataClass,
2274 ValueType store_vt = i32, SDPatternOperator st = null_frag> {
2275 let mayLoad = 0, mayStore = 1 in {
2276 defm : MUBUF_m <op, name, (outs),
2277 (ins vdataClass:$vdata, VGPR_32:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset,
2278 mbuf_offset:$offset, offen:$offen, idxen:$idxen, glc:$glc, slc:$slc,
2280 name#" $vdata, $vaddr, $srsrc, $soffset"#"$offen"#"$idxen"#"$offset"#
2281 "$glc"#"$slc"#"$tfe", []>;
2283 let offen = 0, idxen = 0, vaddr = 0 in {
2284 defm _OFFSET : MUBUF_m <op, name#"_offset",(outs),
2285 (ins vdataClass:$vdata, SReg_128:$srsrc, SCSrc_32:$soffset,
2286 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
2287 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
2288 [(st store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset,
2289 i16:$offset, i1:$glc, i1:$slc, i1:$tfe))]>;
2290 } // offen = 0, idxen = 0, vaddr = 0
2292 let offen = 1, idxen = 0 in {
2293 defm _OFFEN : MUBUF_m <op, name#"_offen", (outs),
2294 (ins vdataClass:$vdata, VGPR_32:$vaddr, SReg_128:$srsrc,
2295 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc,
2296 slc:$slc, tfe:$tfe),
2297 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#
2298 "$glc"#"$slc"#"$tfe", []>;
2299 } // end offen = 1, idxen = 0
2301 let offen = 0, idxen = 1 in {
2302 defm _IDXEN : MUBUF_m <op, name#"_idxen", (outs),
2303 (ins vdataClass:$vdata, VGPR_32:$vaddr, SReg_128:$srsrc,
2304 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc,
2305 slc:$slc, tfe:$tfe),
2306 name#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2309 let offen = 1, idxen = 1 in {
2310 defm _BOTHEN : MUBUF_m <op, name#"_bothen", (outs),
2311 (ins vdataClass:$vdata, VReg_64:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset,
2312 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
2313 name#" $vdata, $vaddr, $srsrc, $soffset idxen offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2316 let offen = 0, idxen = 0 in {
2317 defm _ADDR64 : MUBUFAddr64_m <op, name#"_addr64", (outs),
2318 (ins vdataClass:$vdata, VReg_64:$vaddr, SReg_128:$srsrc,
2320 mbuf_offset:$offset, glc:$glc, slc:$slc,
2322 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#
2323 "$offset"#"$glc"#"$slc"#"$tfe",
2324 [(st store_vt:$vdata,
2325 (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr,
2326 i32:$soffset, i16:$offset,
2327 i1:$glc, i1:$slc, i1:$tfe))]>;
2329 } // End mayLoad = 0, mayStore = 1
2332 class FLAT_Load_Helper <bits<7> op, string asm, RegisterClass regClass> :
2333 FLAT <op, (outs regClass:$vdst),
2334 (ins VReg_64:$addr),
2335 asm#" $vdst, $addr, [M0, FLAT_SCRATCH]", []> {
2343 class FLAT_Store_Helper <bits<7> op, string name, RegisterClass vdataClass> :
2344 FLAT <op, (outs), (ins vdataClass:$data, VReg_64:$addr),
2345 name#" $data, $addr, [M0, FLAT_SCRATCH]",
2358 class MIMG_Mask <string op, int channels> {
2360 int Channels = channels;
2363 class MIMG_NoSampler_Helper <bits<7> op, string asm,
2364 RegisterClass dst_rc,
2365 RegisterClass src_rc> : MIMG <
2367 (outs dst_rc:$vdata),
2368 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
2369 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
2371 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2372 #" $tfe, $lwe, $slc, $vaddr, $srsrc",
2377 let hasPostISelHook = 1;
2380 multiclass MIMG_NoSampler_Src_Helper <bits<7> op, string asm,
2381 RegisterClass dst_rc,
2383 def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPR_32>,
2384 MIMG_Mask<asm#"_V1", channels>;
2385 def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>,
2386 MIMG_Mask<asm#"_V2", channels>;
2387 def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>,
2388 MIMG_Mask<asm#"_V4", channels>;
2391 multiclass MIMG_NoSampler <bits<7> op, string asm> {
2392 defm _V1 : MIMG_NoSampler_Src_Helper <op, asm, VGPR_32, 1>;
2393 defm _V2 : MIMG_NoSampler_Src_Helper <op, asm, VReg_64, 2>;
2394 defm _V3 : MIMG_NoSampler_Src_Helper <op, asm, VReg_96, 3>;
2395 defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 4>;
2398 class MIMG_Sampler_Helper <bits<7> op, string asm,
2399 RegisterClass dst_rc,
2400 RegisterClass src_rc, int wqm> : MIMG <
2402 (outs dst_rc:$vdata),
2403 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
2404 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
2405 SReg_256:$srsrc, SReg_128:$ssamp),
2406 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2407 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
2411 let hasPostISelHook = 1;
2415 multiclass MIMG_Sampler_Src_Helper <bits<7> op, string asm,
2416 RegisterClass dst_rc,
2417 int channels, int wqm> {
2418 def _V1 : MIMG_Sampler_Helper <op, asm, dst_rc, VGPR_32, wqm>,
2419 MIMG_Mask<asm#"_V1", channels>;
2420 def _V2 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_64, wqm>,
2421 MIMG_Mask<asm#"_V2", channels>;
2422 def _V4 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_128, wqm>,
2423 MIMG_Mask<asm#"_V4", channels>;
2424 def _V8 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_256, wqm>,
2425 MIMG_Mask<asm#"_V8", channels>;
2426 def _V16 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_512, wqm>,
2427 MIMG_Mask<asm#"_V16", channels>;
2430 multiclass MIMG_Sampler <bits<7> op, string asm> {
2431 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, 0>;
2432 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2, 0>;
2433 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3, 0>;
2434 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4, 0>;
2437 multiclass MIMG_Sampler_WQM <bits<7> op, string asm> {
2438 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, 1>;
2439 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2, 1>;
2440 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3, 1>;
2441 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4, 1>;
2444 class MIMG_Gather_Helper <bits<7> op, string asm,
2445 RegisterClass dst_rc,
2446 RegisterClass src_rc, int wqm> : MIMG <
2448 (outs dst_rc:$vdata),
2449 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
2450 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
2451 SReg_256:$srsrc, SReg_128:$ssamp),
2452 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2453 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
2458 // DMASK was repurposed for GATHER4. 4 components are always
2459 // returned and DMASK works like a swizzle - it selects
2460 // the component to fetch. The only useful DMASK values are
2461 // 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
2462 // (red,red,red,red) etc.) The ISA document doesn't mention
2464 // Therefore, disable all code which updates DMASK by setting these two:
2466 let hasPostISelHook = 0;
2470 multiclass MIMG_Gather_Src_Helper <bits<7> op, string asm,
2471 RegisterClass dst_rc,
2472 int channels, int wqm> {
2473 def _V1 : MIMG_Gather_Helper <op, asm, dst_rc, VGPR_32, wqm>,
2474 MIMG_Mask<asm#"_V1", channels>;
2475 def _V2 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_64, wqm>,
2476 MIMG_Mask<asm#"_V2", channels>;
2477 def _V4 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_128, wqm>,
2478 MIMG_Mask<asm#"_V4", channels>;
2479 def _V8 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_256, wqm>,
2480 MIMG_Mask<asm#"_V8", channels>;
2481 def _V16 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_512, wqm>,
2482 MIMG_Mask<asm#"_V16", channels>;
2485 multiclass MIMG_Gather <bits<7> op, string asm> {
2486 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1, 0>;
2487 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2, 0>;
2488 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3, 0>;
2489 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4, 0>;
2492 multiclass MIMG_Gather_WQM <bits<7> op, string asm> {
2493 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1, 1>;
2494 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2, 1>;
2495 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3, 1>;
2496 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4, 1>;
2499 //===----------------------------------------------------------------------===//
2500 // Vector instruction mappings
2501 //===----------------------------------------------------------------------===//
2503 // Maps an opcode in e32 form to its e64 equivalent
2504 def getVOPe64 : InstrMapping {
2505 let FilterClass = "VOP";
2506 let RowFields = ["OpName"];
2507 let ColFields = ["Size"];
2509 let ValueCols = [["8"]];
2512 // Maps an opcode in e64 form to its e32 equivalent
2513 def getVOPe32 : InstrMapping {
2514 let FilterClass = "VOP";
2515 let RowFields = ["OpName"];
2516 let ColFields = ["Size"];
2518 let ValueCols = [["4"]];
2521 def getMaskedMIMGOp : InstrMapping {
2522 let FilterClass = "MIMG_Mask";
2523 let RowFields = ["Op"];
2524 let ColFields = ["Channels"];
2526 let ValueCols = [["1"], ["2"], ["3"] ];
2529 // Maps an commuted opcode to its original version
2530 def getCommuteOrig : InstrMapping {
2531 let FilterClass = "VOP2_REV";
2532 let RowFields = ["RevOp"];
2533 let ColFields = ["IsOrig"];
2535 let ValueCols = [["1"]];
2538 // Maps an original opcode to its commuted version
2539 def getCommuteRev : InstrMapping {
2540 let FilterClass = "VOP2_REV";
2541 let RowFields = ["RevOp"];
2542 let ColFields = ["IsOrig"];
2544 let ValueCols = [["0"]];
2547 def getCommuteCmpOrig : InstrMapping {
2548 let FilterClass = "VOP2_REV";
2549 let RowFields = ["RevOp"];
2550 let ColFields = ["IsOrig"];
2552 let ValueCols = [["1"]];
2555 // Maps an original opcode to its commuted version
2556 def getCommuteCmpRev : InstrMapping {
2557 let FilterClass = "VOP2_REV";
2558 let RowFields = ["RevOp"];
2559 let ColFields = ["IsOrig"];
2561 let ValueCols = [["0"]];
2565 def getMCOpcodeGen : InstrMapping {
2566 let FilterClass = "SIMCInstr";
2567 let RowFields = ["PseudoInstr"];
2568 let ColFields = ["Subtarget"];
2569 let KeyCol = [!cast<string>(SISubtarget.NONE)];
2570 let ValueCols = [[!cast<string>(SISubtarget.SI)],[!cast<string>(SISubtarget.VI)]];
2573 def getAddr64Inst : InstrMapping {
2574 let FilterClass = "MUBUFAddr64Table";
2575 let RowFields = ["OpName"];
2576 let ColFields = ["IsAddr64"];
2578 let ValueCols = [["1"]];
2581 // Maps an atomic opcode to its version with a return value.
2582 def getAtomicRetOp : InstrMapping {
2583 let FilterClass = "AtomicNoRet";
2584 let RowFields = ["NoRetOp"];
2585 let ColFields = ["IsRet"];
2587 let ValueCols = [["1"]];
2590 // Maps an atomic opcode to its returnless version.
2591 def getAtomicNoRetOp : InstrMapping {
2592 let FilterClass = "AtomicNoRet";
2593 let RowFields = ["NoRetOp"];
2594 let ColFields = ["IsRet"];
2596 let ValueCols = [["0"]];
2599 include "SIInstructions.td"
2600 include "CIInstructions.td"
2601 include "VIInstructions.td"