1 //===-- SIInstrInfo.td - SI Instruction Infos -------------*- tablegen -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Execpt for the NONE field, this must be kept in sync with the SISubtarget enum
11 // in AMDGPUMCInstLower.h
17 //===----------------------------------------------------------------------===//
19 //===----------------------------------------------------------------------===//
21 def SIload_constant : SDNode<"AMDGPUISD::LOAD_CONSTANT",
22 SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i32>]>,
23 [SDNPMayLoad, SDNPMemOperand]
26 def SItbuffer_store : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT",
28 [SDTCisVT<0, v4i32>, // rsrc(SGPR)
29 SDTCisVT<1, iAny>, // vdata(VGPR)
30 SDTCisVT<2, i32>, // num_channels(imm)
31 SDTCisVT<3, i32>, // vaddr(VGPR)
32 SDTCisVT<4, i32>, // soffset(SGPR)
33 SDTCisVT<5, i32>, // inst_offset(imm)
34 SDTCisVT<6, i32>, // dfmt(imm)
35 SDTCisVT<7, i32>, // nfmt(imm)
36 SDTCisVT<8, i32>, // offen(imm)
37 SDTCisVT<9, i32>, // idxen(imm)
38 SDTCisVT<10, i32>, // glc(imm)
39 SDTCisVT<11, i32>, // slc(imm)
40 SDTCisVT<12, i32> // tfe(imm)
42 [SDNPMayStore, SDNPMemOperand, SDNPHasChain]
45 def SIload_input : SDNode<"AMDGPUISD::LOAD_INPUT",
46 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i16>,
50 class SDSample<string opcode> : SDNode <opcode,
51 SDTypeProfile<1, 4, [SDTCisVT<0, v4f32>, SDTCisVT<2, v32i8>,
52 SDTCisVT<3, v4i32>, SDTCisVT<4, i32>]>
55 def SIsample : SDSample<"AMDGPUISD::SAMPLE">;
56 def SIsampleb : SDSample<"AMDGPUISD::SAMPLEB">;
57 def SIsampled : SDSample<"AMDGPUISD::SAMPLED">;
58 def SIsamplel : SDSample<"AMDGPUISD::SAMPLEL">;
60 def SIconstdata_ptr : SDNode<
61 "AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 0, [SDTCisVT<0, i64>]>
64 // Transformation function, extract the lower 32bit of a 64bit immediate
65 def LO32 : SDNodeXForm<imm, [{
66 return CurDAG->getTargetConstant(N->getZExtValue() & 0xffffffff, MVT::i32);
69 def LO32f : SDNodeXForm<fpimm, [{
70 APInt V = N->getValueAPF().bitcastToAPInt().trunc(32);
71 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
74 // Transformation function, extract the upper 32bit of a 64bit immediate
75 def HI32 : SDNodeXForm<imm, [{
76 return CurDAG->getTargetConstant(N->getZExtValue() >> 32, MVT::i32);
79 def HI32f : SDNodeXForm<fpimm, [{
80 APInt V = N->getValueAPF().bitcastToAPInt().lshr(32).trunc(32);
81 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
84 def IMM8bitDWORD : PatLeaf <(imm),
85 [{return (N->getZExtValue() & ~0x3FC) == 0;}]
88 def as_dword_i32imm : SDNodeXForm<imm, [{
89 return CurDAG->getTargetConstant(N->getZExtValue() >> 2, MVT::i32);
92 def as_i1imm : SDNodeXForm<imm, [{
93 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i1);
96 def as_i8imm : SDNodeXForm<imm, [{
97 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i8);
100 def as_i16imm : SDNodeXForm<imm, [{
101 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i16);
104 def as_i32imm: SDNodeXForm<imm, [{
105 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i32);
108 def IMM8bit : PatLeaf <(imm),
109 [{return isUInt<8>(N->getZExtValue());}]
112 def IMM12bit : PatLeaf <(imm),
113 [{return isUInt<12>(N->getZExtValue());}]
116 def IMM16bit : PatLeaf <(imm),
117 [{return isUInt<16>(N->getZExtValue());}]
120 def IMM32bit : PatLeaf <(imm),
121 [{return isUInt<32>(N->getZExtValue());}]
124 def mubuf_vaddr_offset : PatFrag<
125 (ops node:$ptr, node:$offset, node:$imm_offset),
126 (add (add node:$ptr, node:$offset), node:$imm_offset)
129 class InlineImm <ValueType vt> : PatLeaf <(vt imm), [{
130 return isInlineImmediate(N);
133 class SGPRImm <dag frag> : PatLeaf<frag, [{
134 if (TM.getSubtarget<AMDGPUSubtarget>().getGeneration() <
135 AMDGPUSubtarget::SOUTHERN_ISLANDS) {
138 const SIRegisterInfo *SIRI =
139 static_cast<const SIRegisterInfo*>(TM.getSubtargetImpl()->getRegisterInfo());
140 for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
142 if (SIRI->isSGPRClass(getOperandRegClass(*U, U.getOperandNo()))) {
149 //===----------------------------------------------------------------------===//
151 //===----------------------------------------------------------------------===//
153 def FRAMEri32 : Operand<iPTR> {
154 let MIOperandInfo = (ops i32:$ptr, i32imm:$index);
157 def sopp_brtarget : Operand<OtherVT> {
158 let EncoderMethod = "getSOPPBrEncoding";
159 let OperandType = "OPERAND_PCREL";
162 include "SIInstrFormats.td"
164 let OperandType = "OPERAND_IMMEDIATE" in {
166 def offen : Operand<i1> {
167 let PrintMethod = "printOffen";
169 def idxen : Operand<i1> {
170 let PrintMethod = "printIdxen";
172 def addr64 : Operand<i1> {
173 let PrintMethod = "printAddr64";
175 def mbuf_offset : Operand<i16> {
176 let PrintMethod = "printMBUFOffset";
178 def glc : Operand <i1> {
179 let PrintMethod = "printGLC";
181 def slc : Operand <i1> {
182 let PrintMethod = "printSLC";
184 def tfe : Operand <i1> {
185 let PrintMethod = "printTFE";
188 def omod : Operand <i32> {
189 let PrintMethod = "printOModSI";
192 def ClampMod : Operand <i1> {
193 let PrintMethod = "printClampSI";
196 } // End OperandType = "OPERAND_IMMEDIATE"
198 //===----------------------------------------------------------------------===//
200 //===----------------------------------------------------------------------===//
202 def DS1Addr1Offset : ComplexPattern<i32, 2, "SelectDS1Addr1Offset">;
203 def DS64Bit4ByteAligned : ComplexPattern<i32, 3, "SelectDS64Bit4ByteAligned">;
205 def MUBUFAddr32 : ComplexPattern<i64, 9, "SelectMUBUFAddr32">;
206 def MUBUFAddr64 : ComplexPattern<i64, 3, "SelectMUBUFAddr64">;
207 def MUBUFAddr64Atomic : ComplexPattern<i64, 4, "SelectMUBUFAddr64">;
208 def MUBUFScratch : ComplexPattern<i64, 4, "SelectMUBUFScratch">;
209 def MUBUFOffset : ComplexPattern<i64, 6, "SelectMUBUFOffset">;
210 def MUBUFOffsetAtomic : ComplexPattern<i64, 4, "SelectMUBUFOffset">;
212 def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">;
213 def VOP3Mods : ComplexPattern<untyped, 2, "SelectVOP3Mods">;
215 //===----------------------------------------------------------------------===//
216 // SI assembler operands
217 //===----------------------------------------------------------------------===//
237 //===----------------------------------------------------------------------===//
239 // SI Instruction multiclass helpers.
241 // Instructions with _32 take 32-bit operands.
242 // Instructions with _64 take 64-bit operands.
244 // VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit
245 // encoding is the standard encoding, but instruction that make use of
246 // any of the instruction modifiers must use the 64-bit encoding.
248 // Instructions with _e32 use the 32-bit encoding.
249 // Instructions with _e64 use the 64-bit encoding.
251 //===----------------------------------------------------------------------===//
253 class SIMCInstr <string pseudo, int subtarget> {
254 string PseudoInstr = pseudo;
255 int Subtarget = subtarget;
258 //===----------------------------------------------------------------------===//
260 //===----------------------------------------------------------------------===//
262 class EXPCommon : InstSI<
264 (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm,
265 VReg_32:$src0, VReg_32:$src1, VReg_32:$src2, VReg_32:$src3),
266 "EXP $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3",
275 let isPseudo = 1 in {
276 def "" : EXPCommon, SIMCInstr <"EXP", SISubtarget.NONE> ;
279 def _si : EXPCommon, SIMCInstr <"EXP", SISubtarget.SI>, EXPe;
282 //===----------------------------------------------------------------------===//
284 //===----------------------------------------------------------------------===//
286 class SOP1_32 <bits<8> op, string opName, list<dag> pattern> : SOP1 <
287 op, (outs SReg_32:$dst), (ins SSrc_32:$src0),
288 opName#" $dst, $src0", pattern
291 class SOP1_64 <bits<8> op, string opName, list<dag> pattern> : SOP1 <
292 op, (outs SReg_64:$dst), (ins SSrc_64:$src0),
293 opName#" $dst, $src0", pattern
296 // 64-bit input, 32-bit output.
297 class SOP1_32_64 <bits<8> op, string opName, list<dag> pattern> : SOP1 <
298 op, (outs SReg_32:$dst), (ins SSrc_64:$src0),
299 opName#" $dst, $src0", pattern
302 class SOP2_32 <bits<7> op, string opName, list<dag> pattern> : SOP2 <
303 op, (outs SReg_32:$dst), (ins SSrc_32:$src0, SSrc_32:$src1),
304 opName#" $dst, $src0, $src1", pattern
307 class SOP2_64 <bits<7> op, string opName, list<dag> pattern> : SOP2 <
308 op, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_64:$src1),
309 opName#" $dst, $src0, $src1", pattern
312 class SOP2_SHIFT_64 <bits<7> op, string opName, list<dag> pattern> : SOP2 <
313 op, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_32:$src1),
314 opName#" $dst, $src0, $src1", pattern
318 class SOPC_Helper <bits<7> op, RegisterClass rc, ValueType vt,
319 string opName, PatLeaf cond> : SOPC <
320 op, (outs SCCReg:$dst), (ins rc:$src0, rc:$src1),
321 opName#" $dst, $src0, $src1", []>;
323 class SOPC_32<bits<7> op, string opName, PatLeaf cond = COND_NULL>
324 : SOPC_Helper<op, SSrc_32, i32, opName, cond>;
326 class SOPC_64<bits<7> op, string opName, PatLeaf cond = COND_NULL>
327 : SOPC_Helper<op, SSrc_64, i64, opName, cond>;
329 class SOPK_32 <bits<5> op, string opName, list<dag> pattern> : SOPK <
330 op, (outs SReg_32:$dst), (ins i16imm:$src0),
331 opName#" $dst, $src0", pattern
334 class SOPK_64 <bits<5> op, string opName, list<dag> pattern> : SOPK <
335 op, (outs SReg_64:$dst), (ins i16imm:$src0),
336 opName#" $dst, $src0", pattern
339 //===----------------------------------------------------------------------===//
341 //===----------------------------------------------------------------------===//
343 class SMRD_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
344 SMRD <outs, ins, "", pattern>,
345 SIMCInstr<opName, SISubtarget.NONE> {
349 class SMRD_Real_si <bits<5> op, string opName, bit imm, dag outs, dag ins,
351 SMRD <outs, ins, asm, []>,
353 SIMCInstr<opName, SISubtarget.SI>;
355 multiclass SMRD_m <bits<5> op, string opName, bit imm, dag outs, dag ins,
356 string asm, list<dag> pattern> {
358 def "" : SMRD_Pseudo <opName, outs, ins, pattern>;
360 def _si : SMRD_Real_si <op, opName, imm, outs, ins, asm>;
364 multiclass SMRD_Helper <bits<5> op, string opName, RegisterClass baseClass,
365 RegisterClass dstClass> {
367 op, opName#"_IMM", 1, (outs dstClass:$dst),
368 (ins baseClass:$sbase, u32imm:$offset),
369 opName#" $dst, $sbase, $offset", []
372 defm _SGPR : SMRD_m <
373 op, opName#"_SGPR", 0, (outs dstClass:$dst),
374 (ins baseClass:$sbase, SReg_32:$soff),
375 opName#" $dst, $sbase, $soff", []
379 //===----------------------------------------------------------------------===//
380 // Vector ALU classes
381 //===----------------------------------------------------------------------===//
383 // This must always be right before the operand being input modified.
384 def InputMods : OperandWithDefaultOps <i32, (ops (i32 0))> {
385 let PrintMethod = "printOperandAndMods";
387 def InputModsNoDefault : Operand <i32> {
388 let PrintMethod = "printOperandAndMods";
391 class getNumSrcArgs<ValueType Src1, ValueType Src2> {
393 !if (!eq(Src1.Value, untyped.Value), 1, // VOP1
394 !if (!eq(Src2.Value, untyped.Value), 2, // VOP2
398 // Returns the register class to use for the destination of VOP[123C]
399 // instructions for the given VT.
400 class getVALUDstForVT<ValueType VT> {
401 RegisterClass ret = !if(!eq(VT.Size, 32), VReg_32, VReg_64);
404 // Returns the register class to use for source 0 of VOP[12C]
405 // instructions for the given VT.
406 class getVOPSrc0ForVT<ValueType VT> {
407 RegisterClass ret = !if(!eq(VT.Size, 32), VSrc_32, VSrc_64);
410 // Returns the register class to use for source 1 of VOP[12C] for the
412 class getVOPSrc1ForVT<ValueType VT> {
413 RegisterClass ret = !if(!eq(VT.Size, 32), VReg_32, VReg_64);
416 // Returns the register classes for the source arguments of a VOP[12C]
417 // instruction for the given SrcVTs.
418 class getInRC32 <list<ValueType> SrcVT> {
419 list<RegisterClass> ret = [
420 getVOPSrc0ForVT<SrcVT[0]>.ret,
421 getVOPSrc1ForVT<SrcVT[1]>.ret
425 // Returns the register class to use for sources of VOP3 instructions for the
427 class getVOP3SrcForVT<ValueType VT> {
428 RegisterClass ret = !if(!eq(VT.Size, 32), VCSrc_32, VCSrc_64);
431 // Returns the register classes for the source arguments of a VOP3
432 // instruction for the given SrcVTs.
433 class getInRC64 <list<ValueType> SrcVT> {
434 list<RegisterClass> ret = [
435 getVOP3SrcForVT<SrcVT[0]>.ret,
436 getVOP3SrcForVT<SrcVT[1]>.ret,
437 getVOP3SrcForVT<SrcVT[2]>.ret
441 // Returns 1 if the source arguments have modifiers, 0 if they do not.
442 class hasModifiers<ValueType SrcVT> {
443 bit ret = !if(!eq(SrcVT.Value, f32.Value), 1,
444 !if(!eq(SrcVT.Value, f64.Value), 1, 0));
447 // Returns the input arguments for VOP[12C] instructions for the given SrcVT.
448 class getIns32 <RegisterClass Src0RC, RegisterClass Src1RC, int NumSrcArgs> {
449 dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0), // VOP1
450 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
454 // Returns the input arguments for VOP3 instructions for the given SrcVT.
455 class getIns64 <RegisterClass Src0RC, RegisterClass Src1RC,
456 RegisterClass Src2RC, int NumSrcArgs,
460 !if (!eq(NumSrcArgs, 1),
461 !if (!eq(HasModifiers, 1),
462 // VOP1 with modifiers
463 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
464 ClampMod:$clamp, omod:$omod)
466 // VOP1 without modifiers
469 !if (!eq(NumSrcArgs, 2),
470 !if (!eq(HasModifiers, 1),
471 // VOP 2 with modifiers
472 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
473 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
474 ClampMod:$clamp, omod:$omod)
476 // VOP2 without modifiers
477 (ins Src0RC:$src0, Src1RC:$src1)
479 /* NumSrcArgs == 3 */,
480 !if (!eq(HasModifiers, 1),
481 // VOP3 with modifiers
482 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
483 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
484 InputModsNoDefault:$src2_modifiers, Src2RC:$src2,
485 ClampMod:$clamp, omod:$omod)
487 // VOP3 without modifiers
488 (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2)
492 // Returns the assembly string for the inputs and outputs of a VOP[12C]
493 // instruction. This does not add the _e32 suffix, so it can be reused
495 class getAsm32 <int NumSrcArgs> {
496 string src1 = ", $src1";
497 string src2 = ", $src2";
498 string ret = " $dst, $src0"#
499 !if(!eq(NumSrcArgs, 1), "", src1)#
500 !if(!eq(NumSrcArgs, 3), src2, "");
503 // Returns the assembly string for the inputs and outputs of a VOP3
505 class getAsm64 <int NumSrcArgs, bit HasModifiers> {
506 string src0 = "$src0_modifiers,";
507 string src1 = !if(!eq(NumSrcArgs, 1), "",
508 !if(!eq(NumSrcArgs, 2), " $src1_modifiers",
509 " $src1_modifiers,"));
510 string src2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers", "");
512 !if(!eq(HasModifiers, 0),
513 getAsm32<NumSrcArgs>.ret,
514 " $dst, "#src0#src1#src2#"$clamp"#"$omod");
518 class VOPProfile <list<ValueType> _ArgVT> {
520 field list<ValueType> ArgVT = _ArgVT;
522 field ValueType DstVT = ArgVT[0];
523 field ValueType Src0VT = ArgVT[1];
524 field ValueType Src1VT = ArgVT[2];
525 field ValueType Src2VT = ArgVT[3];
526 field RegisterClass DstRC = getVALUDstForVT<DstVT>.ret;
527 field RegisterClass Src0RC32 = getVOPSrc0ForVT<Src0VT>.ret;
528 field RegisterClass Src1RC32 = getVOPSrc1ForVT<Src1VT>.ret;
529 field RegisterClass Src0RC64 = getVOP3SrcForVT<Src0VT>.ret;
530 field RegisterClass Src1RC64 = getVOP3SrcForVT<Src1VT>.ret;
531 field RegisterClass Src2RC64 = getVOP3SrcForVT<Src2VT>.ret;
533 field int NumSrcArgs = getNumSrcArgs<Src1VT, Src2VT>.ret;
534 field bit HasModifiers = hasModifiers<Src0VT>.ret;
536 field dag Outs = (outs DstRC:$dst);
538 field dag Ins32 = getIns32<Src0RC32, Src1RC32, NumSrcArgs>.ret;
539 field dag Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
542 field string Asm32 = "_e32"#getAsm32<NumSrcArgs>.ret;
543 field string Asm64 = getAsm64<NumSrcArgs, HasModifiers>.ret;
546 def VOP_F32_F32 : VOPProfile <[f32, f32, untyped, untyped]>;
547 def VOP_F32_F64 : VOPProfile <[f32, f64, untyped, untyped]>;
548 def VOP_F32_I32 : VOPProfile <[f32, i32, untyped, untyped]>;
549 def VOP_F64_F32 : VOPProfile <[f64, f32, untyped, untyped]>;
550 def VOP_F64_F64 : VOPProfile <[f64, f64, untyped, untyped]>;
551 def VOP_F64_I32 : VOPProfile <[f64, i32, untyped, untyped]>;
552 def VOP_I32_F32 : VOPProfile <[i32, f32, untyped, untyped]>;
553 def VOP_I32_F64 : VOPProfile <[i32, f64, untyped, untyped]>;
554 def VOP_I32_I32 : VOPProfile <[i32, i32, untyped, untyped]>;
556 def VOP_F32_F32_F32 : VOPProfile <[f32, f32, f32, untyped]>;
557 def VOP_F32_F32_I32 : VOPProfile <[f32, f32, i32, untyped]>;
558 def VOP_F64_F64_F64 : VOPProfile <[f64, f64, f64, untyped]>;
559 def VOP_F64_F64_I32 : VOPProfile <[f64, f64, i32, untyped]>;
560 def VOP_I32_F32_F32 : VOPProfile <[i32, f32, f32, untyped]>;
561 def VOP_I32_I32_I32 : VOPProfile <[i32, i32, i32, untyped]>;
562 def VOP_I32_I32_I32_VCC : VOPProfile <[i32, i32, i32, untyped]> {
563 let Src0RC32 = VCSrc_32;
565 def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>;
566 def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>;
568 def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>;
569 def VOP_F64_F64_F64_F64 : VOPProfile <[f64, f64, f64, f64]>;
570 def VOP_I32_I32_I32_I32 : VOPProfile <[i32, i32, i32, i32]>;
571 def VOP_I64_I32_I32_I64 : VOPProfile <[i64, i32, i32, i64]>;
574 class VOP <string opName> {
575 string OpName = opName;
578 class VOP2_REV <string revOp, bit isOrig> {
579 string RevOp = revOp;
583 class AtomicNoRet <string noRetOp, bit isRet> {
584 string NoRetOp = noRetOp;
588 class VOP3DisableFields <bit HasSrc1, bit HasSrc2, bit HasModifiers> {
590 bits<2> src0_modifiers = !if(HasModifiers, ?, 0);
591 bits<2> src1_modifiers = !if(HasModifiers, !if(HasSrc1, ?, 0), 0);
592 bits<2> src2_modifiers = !if(HasModifiers, !if(HasSrc2, ? ,0) ,0);
593 bits<2> omod = !if(HasModifiers, ?, 0);
594 bits<1> clamp = !if(HasModifiers, ?, 0);
595 bits<9> src1 = !if(HasSrc1, ?, 0);
596 bits<9> src2 = !if(HasSrc2, ?, 0);
599 class VOP3_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
600 VOP3Common <outs, ins, "", pattern>,
602 SIMCInstr<opName, SISubtarget.NONE> {
606 class VOP3_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
607 VOP3 <op, outs, ins, asm, []>,
608 SIMCInstr<opName, SISubtarget.SI>;
610 multiclass VOP3_m <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern,
611 string opName, int NumSrcArgs, bit HasMods = 1> {
613 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
615 def _si : VOP3_Real_si <op, outs, ins, asm, opName>,
616 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
617 !if(!eq(NumSrcArgs, 2), 0, 1),
622 multiclass VOP3_1_m <bits<8> op, dag outs, dag ins, string asm,
623 list<dag> pattern, string opName, bit HasMods = 1> {
625 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
627 def _si : VOP3_Real_si <
628 {1, 1, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
629 outs, ins, asm, opName>,
630 VOP3DisableFields<0, 0, HasMods>;
633 multiclass VOP3_2_m <bits<9> op, dag outs, dag ins, string asm,
634 list<dag> pattern, string opName, string revOp,
635 bit HasMods = 1, bit UseFullOp = 0> {
637 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
638 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
640 def _si : VOP3_Real_si <op,
641 outs, ins, asm, opName>,
642 VOP2_REV<revOp#"_e64_si", !eq(revOp, opName)>,
643 VOP3DisableFields<1, 0, HasMods>;
646 multiclass VOP3b_2_m <bits<9> op, dag outs, dag ins, string asm,
647 list<dag> pattern, string opName, string revOp,
648 bit HasMods = 1, bit UseFullOp = 0> {
649 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
650 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
652 // The VOP2 variant puts the carry out into VCC, the VOP3 variant
653 // can write it into any SGPR. We currently don't use the carry out,
654 // so for now hardcode it to VCC as well.
655 let sdst = SIOperand.VCC, Defs = [VCC] in {
656 def _si : VOP3b <op, outs, ins, asm, pattern>,
657 VOP3DisableFields<1, 0, HasMods>,
658 SIMCInstr<opName, SISubtarget.SI>,
659 VOP2_REV<revOp#"_e64_si", !eq(revOp, opName)>;
660 } // End sdst = SIOperand.VCC, Defs = [VCC]
663 multiclass VOP3_C_m <bits<8> op, dag outs, dag ins, string asm,
664 list<dag> pattern, string opName,
665 bit HasMods, bit defExec> {
667 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
669 def _si : VOP3_Real_si <
670 {0, op{7}, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
671 outs, ins, asm, opName>,
672 VOP3DisableFields<1, 0, HasMods> {
673 let Defs = !if(defExec, [EXEC], []);
677 multiclass VOP1_Helper <bits<8> op, string opName, dag outs,
678 dag ins32, string asm32, list<dag> pat32,
679 dag ins64, string asm64, list<dag> pat64,
682 def _e32 : VOP1 <op, outs, ins32, opName#asm32, pat32>, VOP<opName>;
684 defm _e64 : VOP3_1_m <op, outs, ins64, opName#"_e64"#asm64, pat64, opName, HasMods>;
687 multiclass VOP1Inst <bits<8> op, string opName, VOPProfile P,
688 SDPatternOperator node = null_frag> : VOP1_Helper <
690 P.Ins32, P.Asm32, [],
693 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
694 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
695 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
699 class VOP2_e32 <bits<6> op, string opName, dag outs, dag ins, string asm,
700 list<dag> pattern, string revOp> :
701 VOP2 <op, outs, ins, opName#asm, pattern>,
703 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
705 multiclass VOP2_Helper <bits<6> op, string opName, dag outs,
706 dag ins32, string asm32, list<dag> pat32,
707 dag ins64, string asm64, list<dag> pat64,
708 string revOp, bit HasMods> {
709 def _e32 : VOP2_e32 <op, opName, outs, ins32, asm32, pat32, revOp>;
711 defm _e64 : VOP3_2_m <
712 {1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
713 outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods
717 multiclass VOP2Inst <bits<6> op, string opName, VOPProfile P,
718 SDPatternOperator node = null_frag,
719 string revOp = opName> : VOP2_Helper <
721 P.Ins32, P.Asm32, [],
725 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
726 i1:$clamp, i32:$omod)),
727 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
728 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
729 revOp, P.HasModifiers
732 multiclass VOP2b_Helper <bits<6> op, string opName, dag outs,
733 dag ins32, string asm32, list<dag> pat32,
734 dag ins64, string asm64, list<dag> pat64,
735 string revOp, bit HasMods> {
737 def _e32 : VOP2_e32 <op, opName, outs, ins32, asm32, pat32, revOp>;
739 defm _e64 : VOP3b_2_m <
740 {1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
741 outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods
745 multiclass VOP2bInst <bits<6> op, string opName, VOPProfile P,
746 SDPatternOperator node = null_frag,
747 string revOp = opName> : VOP2b_Helper <
749 P.Ins32, P.Asm32, [],
753 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
754 i1:$clamp, i32:$omod)),
755 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
756 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
757 revOp, P.HasModifiers
760 multiclass VOPC_Helper <bits<8> op, string opName,
761 dag ins32, string asm32, list<dag> pat32,
762 dag out64, dag ins64, string asm64, list<dag> pat64,
763 bit HasMods, bit DefExec> {
764 def _e32 : VOPC <op, ins32, opName#asm32, pat32>, VOP <opName> {
765 let Defs = !if(DefExec, [EXEC], []);
768 defm _e64 : VOP3_C_m <op, out64, ins64, opName#"_e64"#asm64, pat64, opName,
772 multiclass VOPCInst <bits<8> op, string opName,
773 VOPProfile P, PatLeaf cond = COND_NULL,
774 bit DefExec = 0> : VOPC_Helper <
776 P.Ins32, P.Asm32, [],
777 (outs SReg_64:$dst), P.Ins64, P.Asm64,
780 (setcc (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
781 i1:$clamp, i32:$omod)),
782 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
784 [(set i1:$dst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]),
785 P.HasModifiers, DefExec
788 multiclass VOPC_F32 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
789 VOPCInst <op, opName, VOP_F32_F32_F32, cond>;
791 multiclass VOPC_F64 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
792 VOPCInst <op, opName, VOP_F64_F64_F64, cond>;
794 multiclass VOPC_I32 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
795 VOPCInst <op, opName, VOP_I32_I32_I32, cond>;
797 multiclass VOPC_I64 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
798 VOPCInst <op, opName, VOP_I64_I64_I64, cond>;
801 multiclass VOPCX <bits<8> op, string opName, VOPProfile P,
802 PatLeaf cond = COND_NULL>
803 : VOPCInst <op, opName, P, cond, 1>;
805 multiclass VOPCX_F32 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
806 VOPCX <op, opName, VOP_F32_F32_F32, cond>;
808 multiclass VOPCX_F64 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
809 VOPCX <op, opName, VOP_F64_F64_F64, cond>;
811 multiclass VOPCX_I32 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
812 VOPCX <op, opName, VOP_I32_I32_I32, cond>;
814 multiclass VOPCX_I64 <bits<8> op, string opName, PatLeaf cond = COND_NULL> :
815 VOPCX <op, opName, VOP_I64_I64_I64, cond>;
817 multiclass VOP3_Helper <bits<9> op, string opName, dag outs, dag ins, string asm,
818 list<dag> pat, int NumSrcArgs, bit HasMods> : VOP3_m <
819 op, outs, ins, opName#asm, pat, opName, NumSrcArgs, HasMods
822 multiclass VOP3Inst <bits<9> op, string opName, VOPProfile P,
823 SDPatternOperator node = null_frag> : VOP3_Helper <
824 op, opName, P.Outs, P.Ins64, P.Asm64,
825 !if(!eq(P.NumSrcArgs, 3),
828 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
829 i1:$clamp, i32:$omod)),
830 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
831 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))],
832 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1,
834 !if(!eq(P.NumSrcArgs, 2),
837 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
838 i1:$clamp, i32:$omod)),
839 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
840 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))])
841 /* P.NumSrcArgs == 1 */,
844 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
845 i1:$clamp, i32:$omod))))],
846 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]))),
847 P.NumSrcArgs, P.HasModifiers
850 multiclass VOP3b_Helper <bits<9> op, RegisterClass vrc, RegisterClass arc,
851 string opName, list<dag> pattern> :
853 op, (outs vrc:$dst0, SReg_64:$dst1),
854 (ins InputModsNoDefault:$src0_modifiers, arc:$src0,
855 InputModsNoDefault:$src1_modifiers, arc:$src1,
856 InputModsNoDefault:$src2_modifiers, arc:$src2,
857 ClampMod:$clamp, i32imm:$omod),
858 opName#" $dst0, $dst1, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod", pattern,
862 multiclass VOP3b_64 <bits<9> op, string opName, list<dag> pattern> :
863 VOP3b_Helper <op, VReg_64, VSrc_64, opName, pattern>;
865 multiclass VOP3b_32 <bits<9> op, string opName, list<dag> pattern> :
866 VOP3b_Helper <op, VReg_32, VSrc_32, opName, pattern>;
869 class Vop3ModPat<Instruction Inst, VOPProfile P, SDPatternOperator node> : Pat<
870 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),
871 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
872 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))),
873 (Inst i32:$src0_modifiers, P.Src0VT:$src0,
874 i32:$src1_modifiers, P.Src1VT:$src1,
875 i32:$src2_modifiers, P.Src2VT:$src2,
879 //===----------------------------------------------------------------------===//
880 // Vector I/O classes
881 //===----------------------------------------------------------------------===//
883 class DS_1A <bits<8> op, dag outs, dag ins, string asm, list<dag> pat> :
884 DS <op, outs, ins, asm, pat> {
887 // Single load interpret the 2 i8imm operands as a single i16 offset.
888 let offset0 = offset{7-0};
889 let offset1 = offset{15-8};
892 class DS_Load_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A <
894 (outs regClass:$vdst),
895 (ins i1imm:$gds, VReg_32:$addr, u16imm:$offset),
896 asm#" $vdst, $addr, $offset, [M0]",
904 class DS_Load2_Helper <bits<8> op, string asm, RegisterClass regClass> : DS <
906 (outs regClass:$vdst),
907 (ins i1imm:$gds, VReg_32:$addr, u8imm:$offset0, u8imm:$offset1),
908 asm#" $vdst, $addr, $offset0, $offset1, [M0]",
916 class DS_Store_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A <
919 (ins i1imm:$gds, VReg_32:$addr, regClass:$data0, u16imm:$offset),
920 asm#" $addr, $data0, $offset [M0]",
928 class DS_Store2_Helper <bits<8> op, string asm, RegisterClass regClass> : DS <
931 (ins i1imm:$gds, VReg_32:$addr, regClass:$data0, regClass:$data1,
932 u8imm:$offset0, u8imm:$offset1),
933 asm#" $addr, $data0, $data1, $offset0, $offset1 [M0]",
940 // 1 address, 1 data.
941 class DS_1A1D_RET <bits<8> op, string asm, RegisterClass rc, string noRetOp = ""> : DS_1A <
944 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, u16imm:$offset),
945 asm#" $vdst, $addr, $data0, $offset, [M0]", []>,
946 AtomicNoRet<noRetOp, 1> {
952 let hasPostISelHook = 1; // Adjusted to no return version.
955 // 1 address, 2 data.
956 class DS_1A2D_RET <bits<8> op, string asm, RegisterClass rc, string noRetOp = ""> : DS_1A <
959 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, rc:$data1, u16imm:$offset),
960 asm#" $vdst, $addr, $data0, $data1, $offset, [M0]",
962 AtomicNoRet<noRetOp, 1> {
966 let hasPostISelHook = 1; // Adjusted to no return version.
969 // 1 address, 2 data.
970 class DS_1A2D_NORET <bits<8> op, string asm, RegisterClass rc, string noRetOp = asm> : DS_1A <
973 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, rc:$data1, u16imm:$offset),
974 asm#" $addr, $data0, $data1, $offset, [M0]",
976 AtomicNoRet<noRetOp, 0> {
981 // 1 address, 1 data.
982 class DS_1A1D_NORET <bits<8> op, string asm, RegisterClass rc, string noRetOp = asm> : DS_1A <
985 (ins i1imm:$gds, VReg_32:$addr, rc:$data0, u16imm:$offset),
986 asm#" $addr, $data0, $offset, [M0]",
988 AtomicNoRet<noRetOp, 0> {
995 //===----------------------------------------------------------------------===//
997 //===----------------------------------------------------------------------===//
999 class MTBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1000 MTBUF <outs, ins, "", pattern>,
1001 SIMCInstr<opName, SISubtarget.NONE> {
1005 class MTBUF_Real_si <bits<3> op, string opName, dag outs, dag ins,
1007 MTBUF <outs, ins, asm, []>,
1009 SIMCInstr<opName, SISubtarget.SI>;
1011 multiclass MTBUF_m <bits<3> op, string opName, dag outs, dag ins, string asm,
1012 list<dag> pattern> {
1014 def "" : MTBUF_Pseudo <opName, outs, ins, pattern>;
1016 def _si : MTBUF_Real_si <op, opName, outs, ins, asm>;
1020 let mayStore = 1, mayLoad = 0 in {
1022 multiclass MTBUF_Store_Helper <bits<3> op, string opName,
1023 RegisterClass regClass> : MTBUF_m <
1025 (ins regClass:$vdata, u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
1026 i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr,
1027 SReg_128:$srsrc, i1imm:$slc, i1imm:$tfe, SSrc_32:$soffset),
1028 opName#" $vdata, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1029 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
1032 } // mayStore = 1, mayLoad = 0
1034 let mayLoad = 1, mayStore = 0 in {
1036 multiclass MTBUF_Load_Helper <bits<3> op, string opName,
1037 RegisterClass regClass> : MTBUF_m <
1038 op, opName, (outs regClass:$dst),
1039 (ins u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
1040 i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr, SReg_128:$srsrc,
1041 i1imm:$slc, i1imm:$tfe, SSrc_32:$soffset),
1042 opName#" $dst, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1043 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
1046 } // mayLoad = 1, mayStore = 0
1048 class MUBUFAddr64Table <bit is_addr64, string suffix = ""> {
1050 bit IsAddr64 = is_addr64;
1051 string OpName = NAME # suffix;
1054 class MUBUFAtomicAddr64 <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern>
1055 : MUBUF <op, outs, ins, asm, pattern> {
1065 class MUBUFAtomicOffset <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern>
1066 : MUBUF <op, outs, ins, asm, pattern> {
1076 multiclass MUBUF_Atomic <bits<7> op, string name, RegisterClass rc,
1077 ValueType vt, SDPatternOperator atomic> {
1079 let mayStore = 1, mayLoad = 1, hasPostISelHook = 1 in {
1081 // No return variants
1084 def _ADDR64 : MUBUFAtomicAddr64 <
1086 (ins rc:$vdata, SReg_128:$srsrc, VReg_64:$vaddr,
1087 mbuf_offset:$offset, slc:$slc),
1088 name#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset"#"$slc", []
1089 >, MUBUFAddr64Table<1>, AtomicNoRet<NAME#"_ADDR64", 0>;
1091 def _OFFSET : MUBUFAtomicOffset <
1093 (ins rc:$vdata, SReg_128:$srsrc, mbuf_offset:$offset,
1094 SSrc_32:$soffset, slc:$slc),
1095 name#" $vdata, $srsrc, $soffset"#"$offset"#"$slc", []
1096 >, MUBUFAddr64Table<0>, AtomicNoRet<NAME#"_OFFSET", 0>;
1099 // Variant that return values
1100 let glc = 1, Constraints = "$vdata = $vdata_in",
1101 DisableEncoding = "$vdata_in" in {
1103 def _RTN_ADDR64 : MUBUFAtomicAddr64 <
1104 op, (outs rc:$vdata),
1105 (ins rc:$vdata_in, SReg_128:$srsrc, VReg_64:$vaddr,
1106 mbuf_offset:$offset, slc:$slc),
1107 name#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset"#" glc"#"$slc",
1109 (atomic (MUBUFAddr64Atomic v4i32:$srsrc, i64:$vaddr, i16:$offset,
1110 i1:$slc), vt:$vdata_in))]
1111 >, MUBUFAddr64Table<1, "_RTN">, AtomicNoRet<NAME#"_ADDR64", 1>;
1113 def _RTN_OFFSET : MUBUFAtomicOffset <
1114 op, (outs rc:$vdata),
1115 (ins rc:$vdata_in, SReg_128:$srsrc, mbuf_offset:$offset,
1116 SSrc_32:$soffset, slc:$slc),
1117 name#" $vdata, $srsrc, $soffset"#"$offset"#" glc $slc",
1119 (atomic (MUBUFOffsetAtomic v4i32:$srsrc, i32:$soffset, i16:$offset,
1120 i1:$slc), vt:$vdata_in))]
1121 >, MUBUFAddr64Table<0, "_RTN">, AtomicNoRet<NAME#"_OFFSET", 1>;
1125 } // mayStore = 1, mayLoad = 1, hasPostISelHook = 1
1128 multiclass MUBUF_Load_Helper <bits<7> op, string asm, RegisterClass regClass,
1129 ValueType load_vt = i32,
1130 SDPatternOperator ld = null_frag> {
1132 let lds = 0, mayLoad = 1 in {
1136 let offen = 0, idxen = 0, vaddr = 0 in {
1137 def _OFFSET : MUBUF <op, (outs regClass:$vdata),
1138 (ins SReg_128:$srsrc,
1139 mbuf_offset:$offset, SSrc_32:$soffset, glc:$glc,
1140 slc:$slc, tfe:$tfe),
1141 asm#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1142 [(set load_vt:$vdata, (ld (MUBUFOffset v4i32:$srsrc,
1143 i32:$soffset, i16:$offset,
1144 i1:$glc, i1:$slc, i1:$tfe)))]>,
1145 MUBUFAddr64Table<0>;
1148 let offen = 1, idxen = 0 in {
1149 def _OFFEN : MUBUF <op, (outs regClass:$vdata),
1150 (ins SReg_128:$srsrc, VReg_32:$vaddr,
1151 SSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, slc:$slc,
1153 asm#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1156 let offen = 0, idxen = 1 in {
1157 def _IDXEN : MUBUF <op, (outs regClass:$vdata),
1158 (ins SReg_128:$srsrc, VReg_32:$vaddr,
1159 mbuf_offset:$offset, SSrc_32:$soffset, glc:$glc,
1160 slc:$slc, tfe:$tfe),
1161 asm#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
1164 let offen = 1, idxen = 1 in {
1165 def _BOTHEN : MUBUF <op, (outs regClass:$vdata),
1166 (ins SReg_128:$srsrc, VReg_64:$vaddr,
1167 SSrc_32:$soffset, glc:$glc, slc:$slc, tfe:$tfe),
1168 asm#" $vdata, $vaddr, $srsrc, $soffset, idxen offen"#"$glc"#"$slc"#"$tfe", []>;
1172 let offen = 0, idxen = 0, addr64 = 1, glc = 0, slc = 0, tfe = 0, soffset = 128 /* ZERO */ in {
1173 def _ADDR64 : MUBUF <op, (outs regClass:$vdata),
1174 (ins SReg_128:$srsrc, VReg_64:$vaddr, mbuf_offset:$offset),
1175 asm#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset",
1176 [(set load_vt:$vdata, (ld (MUBUFAddr64 v4i32:$srsrc,
1177 i64:$vaddr, i16:$offset)))]>, MUBUFAddr64Table<1>;
1182 multiclass MUBUF_Store_Helper <bits<7> op, string name, RegisterClass vdataClass,
1183 ValueType store_vt, SDPatternOperator st> {
1185 let addr64 = 0, lds = 0 in {
1189 (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_32:$vaddr, SSrc_32:$soffset,
1190 mbuf_offset:$offset, offen:$offen, idxen:$idxen, glc:$glc, slc:$slc,
1192 name#" $vdata, $vaddr, $srsrc, $soffset"#"$offen"#"$idxen"#"$offset"#
1193 "$glc"#"$slc"#"$tfe",
1197 let offen = 0, idxen = 0, vaddr = 0 in {
1198 def _OFFSET : MUBUF <
1200 (ins vdataClass:$vdata, SReg_128:$srsrc, mbuf_offset:$offset,
1201 SSrc_32:$soffset, glc:$glc, slc:$slc, tfe:$tfe),
1202 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
1203 [(st store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset,
1204 i16:$offset, i1:$glc, i1:$slc,
1206 >, MUBUFAddr64Table<0>;
1207 } // offen = 0, idxen = 0, vaddr = 0
1209 let offen = 1, idxen = 0 in {
1210 def _OFFEN : MUBUF <
1212 (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_32:$vaddr, SSrc_32:$soffset,
1213 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
1214 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#
1215 "$glc"#"$slc"#"$tfe",
1218 } // end offen = 1, idxen = 0
1220 } // End addr64 = 0, lds = 0
1222 def _ADDR64 : MUBUF <
1224 (ins vdataClass:$vdata, SReg_128:$srsrc, VReg_64:$vaddr, mbuf_offset:$offset),
1225 name#" $vdata, $vaddr, $srsrc, 0 addr64"#"$offset",
1226 [(st store_vt:$vdata,
1227 (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i16:$offset))]>, MUBUFAddr64Table<1>
1241 let soffset = 128; // ZERO
1245 class FLAT_Load_Helper <bits<7> op, string asm, RegisterClass regClass> :
1246 FLAT <op, (outs regClass:$data),
1247 (ins VReg_64:$addr),
1248 asm#" $data, $addr, [M0, FLAT_SCRATCH]", []> {
1255 class FLAT_Store_Helper <bits<7> op, string name, RegisterClass vdataClass> :
1256 FLAT <op, (outs), (ins vdataClass:$data, VReg_64:$addr),
1257 name#" $data, $addr, [M0, FLAT_SCRATCH]",
1269 class MIMG_Mask <string op, int channels> {
1271 int Channels = channels;
1274 class MIMG_NoSampler_Helper <bits<7> op, string asm,
1275 RegisterClass dst_rc,
1276 RegisterClass src_rc> : MIMG <
1278 (outs dst_rc:$vdata),
1279 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1280 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1282 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1283 #" $tfe, $lwe, $slc, $vaddr, $srsrc",
1288 let hasPostISelHook = 1;
1291 multiclass MIMG_NoSampler_Src_Helper <bits<7> op, string asm,
1292 RegisterClass dst_rc,
1294 def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_32>,
1295 MIMG_Mask<asm#"_V1", channels>;
1296 def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>,
1297 MIMG_Mask<asm#"_V2", channels>;
1298 def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>,
1299 MIMG_Mask<asm#"_V4", channels>;
1302 multiclass MIMG_NoSampler <bits<7> op, string asm> {
1303 defm _V1 : MIMG_NoSampler_Src_Helper <op, asm, VReg_32, 1>;
1304 defm _V2 : MIMG_NoSampler_Src_Helper <op, asm, VReg_64, 2>;
1305 defm _V3 : MIMG_NoSampler_Src_Helper <op, asm, VReg_96, 3>;
1306 defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 4>;
1309 class MIMG_Sampler_Helper <bits<7> op, string asm,
1310 RegisterClass dst_rc,
1311 RegisterClass src_rc> : MIMG <
1313 (outs dst_rc:$vdata),
1314 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1315 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1316 SReg_256:$srsrc, SReg_128:$ssamp),
1317 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1318 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
1322 let hasPostISelHook = 1;
1325 multiclass MIMG_Sampler_Src_Helper <bits<7> op, string asm,
1326 RegisterClass dst_rc,
1328 def _V1 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_32>,
1329 MIMG_Mask<asm#"_V1", channels>;
1330 def _V2 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_64>,
1331 MIMG_Mask<asm#"_V2", channels>;
1332 def _V4 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_128>,
1333 MIMG_Mask<asm#"_V4", channels>;
1334 def _V8 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_256>,
1335 MIMG_Mask<asm#"_V8", channels>;
1336 def _V16 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_512>,
1337 MIMG_Mask<asm#"_V16", channels>;
1340 multiclass MIMG_Sampler <bits<7> op, string asm> {
1341 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VReg_32, 1>;
1342 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2>;
1343 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3>;
1344 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4>;
1347 class MIMG_Gather_Helper <bits<7> op, string asm,
1348 RegisterClass dst_rc,
1349 RegisterClass src_rc> : MIMG <
1351 (outs dst_rc:$vdata),
1352 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
1353 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
1354 SReg_256:$srsrc, SReg_128:$ssamp),
1355 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
1356 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
1361 // DMASK was repurposed for GATHER4. 4 components are always
1362 // returned and DMASK works like a swizzle - it selects
1363 // the component to fetch. The only useful DMASK values are
1364 // 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
1365 // (red,red,red,red) etc.) The ISA document doesn't mention
1367 // Therefore, disable all code which updates DMASK by setting these two:
1369 let hasPostISelHook = 0;
1372 multiclass MIMG_Gather_Src_Helper <bits<7> op, string asm,
1373 RegisterClass dst_rc,
1375 def _V1 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_32>,
1376 MIMG_Mask<asm#"_V1", channels>;
1377 def _V2 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_64>,
1378 MIMG_Mask<asm#"_V2", channels>;
1379 def _V4 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_128>,
1380 MIMG_Mask<asm#"_V4", channels>;
1381 def _V8 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_256>,
1382 MIMG_Mask<asm#"_V8", channels>;
1383 def _V16 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_512>,
1384 MIMG_Mask<asm#"_V16", channels>;
1387 multiclass MIMG_Gather <bits<7> op, string asm> {
1388 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VReg_32, 1>;
1389 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2>;
1390 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3>;
1391 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4>;
1394 //===----------------------------------------------------------------------===//
1395 // Vector instruction mappings
1396 //===----------------------------------------------------------------------===//
1398 // Maps an opcode in e32 form to its e64 equivalent
1399 def getVOPe64 : InstrMapping {
1400 let FilterClass = "VOP";
1401 let RowFields = ["OpName"];
1402 let ColFields = ["Size"];
1404 let ValueCols = [["8"]];
1407 // Maps an opcode in e64 form to its e32 equivalent
1408 def getVOPe32 : InstrMapping {
1409 let FilterClass = "VOP";
1410 let RowFields = ["OpName"];
1411 let ColFields = ["Size"];
1413 let ValueCols = [["4"]];
1416 // Maps an original opcode to its commuted version
1417 def getCommuteRev : InstrMapping {
1418 let FilterClass = "VOP2_REV";
1419 let RowFields = ["RevOp"];
1420 let ColFields = ["IsOrig"];
1422 let ValueCols = [["0"]];
1425 def getMaskedMIMGOp : InstrMapping {
1426 let FilterClass = "MIMG_Mask";
1427 let RowFields = ["Op"];
1428 let ColFields = ["Channels"];
1430 let ValueCols = [["1"], ["2"], ["3"] ];
1433 // Maps an commuted opcode to its original version
1434 def getCommuteOrig : InstrMapping {
1435 let FilterClass = "VOP2_REV";
1436 let RowFields = ["RevOp"];
1437 let ColFields = ["IsOrig"];
1439 let ValueCols = [["1"]];
1442 def isDS : InstrMapping {
1443 let FilterClass = "DS";
1444 let RowFields = ["Inst"];
1445 let ColFields = ["Size"];
1447 let ValueCols = [["8"]];
1450 def getMCOpcode : InstrMapping {
1451 let FilterClass = "SIMCInstr";
1452 let RowFields = ["PseudoInstr"];
1453 let ColFields = ["Subtarget"];
1454 let KeyCol = [!cast<string>(SISubtarget.NONE)];
1455 let ValueCols = [[!cast<string>(SISubtarget.SI)]];
1458 def getAddr64Inst : InstrMapping {
1459 let FilterClass = "MUBUFAddr64Table";
1460 let RowFields = ["OpName"];
1461 let ColFields = ["IsAddr64"];
1463 let ValueCols = [["1"]];
1466 // Maps an atomic opcode to its version with a return value.
1467 def getAtomicRetOp : InstrMapping {
1468 let FilterClass = "AtomicNoRet";
1469 let RowFields = ["NoRetOp"];
1470 let ColFields = ["IsRet"];
1472 let ValueCols = [["1"]];
1475 // Maps an atomic opcode to its returnless version.
1476 def getAtomicNoRetOp : InstrMapping {
1477 let FilterClass = "AtomicNoRet";
1478 let RowFields = ["NoRetOp"];
1479 let ColFields = ["IsRet"];
1481 let ValueCols = [["0"]];
1484 include "SIInstructions.td"