1 //===-- SIInstrInfo.td - SI Instruction Infos -------------*- tablegen -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 def isCI : Predicate<"Subtarget->getGeneration() "
10 ">= AMDGPUSubtarget::SEA_ISLANDS">;
11 def isVI : Predicate <
12 "Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
13 AssemblerPredicate<"FeatureGCN3Encoding">;
15 def DisableInst : Predicate <"false">, AssemblerPredicate<"FeatureDisable">;
22 class vopc <bits<8> si, bits<8> vi = !add(0x40, si)> : vop {
23 field bits<8> SI = si;
24 field bits<8> VI = vi;
26 field bits<9> SI3 = {0, si{7-0}};
27 field bits<10> VI3 = {0, 0, vi{7-0}};
30 class vop1 <bits<8> si, bits<8> vi = si> : vop {
31 field bits<8> SI = si;
32 field bits<8> VI = vi;
34 field bits<9> SI3 = {1, 1, si{6-0}};
35 field bits<10> VI3 = !add(0x140, vi);
38 class vop2 <bits<6> si, bits<6> vi = si> : vop {
39 field bits<6> SI = si;
40 field bits<6> VI = vi;
42 field bits<9> SI3 = {1, 0, 0, si{5-0}};
43 field bits<10> VI3 = {0, 1, 0, 0, vi{5-0}};
46 // Specify a VOP2 opcode for SI and VOP3 opcode for VI
47 // that doesn't have VOP2 encoding on VI
48 class vop23 <bits<6> si, bits<10> vi> : vop2 <si> {
52 class vop3 <bits<9> si, bits<10> vi = {0, si}> : vop {
57 class sop1 <bits<8> si, bits<8> vi = si> {
58 field bits<8> SI = si;
59 field bits<8> VI = vi;
62 class sop2 <bits<7> si, bits<7> vi = si> {
63 field bits<7> SI = si;
64 field bits<7> VI = vi;
67 class sopk <bits<5> si, bits<5> vi = si> {
68 field bits<5> SI = si;
69 field bits<5> VI = vi;
72 // Execpt for the NONE field, this must be kept in sync with the SISubtarget enum
73 // in AMDGPUInstrInfo.cpp
80 //===----------------------------------------------------------------------===//
82 //===----------------------------------------------------------------------===//
84 def SIload_constant : SDNode<"AMDGPUISD::LOAD_CONSTANT",
85 SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i32>]>,
86 [SDNPMayLoad, SDNPMemOperand]
89 def SItbuffer_store : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT",
91 [SDTCisVT<0, v4i32>, // rsrc(SGPR)
92 SDTCisVT<1, iAny>, // vdata(VGPR)
93 SDTCisVT<2, i32>, // num_channels(imm)
94 SDTCisVT<3, i32>, // vaddr(VGPR)
95 SDTCisVT<4, i32>, // soffset(SGPR)
96 SDTCisVT<5, i32>, // inst_offset(imm)
97 SDTCisVT<6, i32>, // dfmt(imm)
98 SDTCisVT<7, i32>, // nfmt(imm)
99 SDTCisVT<8, i32>, // offen(imm)
100 SDTCisVT<9, i32>, // idxen(imm)
101 SDTCisVT<10, i32>, // glc(imm)
102 SDTCisVT<11, i32>, // slc(imm)
103 SDTCisVT<12, i32> // tfe(imm)
105 [SDNPMayStore, SDNPMemOperand, SDNPHasChain]
108 def SIload_input : SDNode<"AMDGPUISD::LOAD_INPUT",
109 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i16>,
113 class SDSample<string opcode> : SDNode <opcode,
114 SDTypeProfile<1, 4, [SDTCisVT<0, v4f32>, SDTCisVT<2, v32i8>,
115 SDTCisVT<3, v4i32>, SDTCisVT<4, i32>]>
118 def SIsample : SDSample<"AMDGPUISD::SAMPLE">;
119 def SIsampleb : SDSample<"AMDGPUISD::SAMPLEB">;
120 def SIsampled : SDSample<"AMDGPUISD::SAMPLED">;
121 def SIsamplel : SDSample<"AMDGPUISD::SAMPLEL">;
123 def SIconstdata_ptr : SDNode<
124 "AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 0, [SDTCisVT<0, i64>]>
127 // Transformation function, extract the lower 32bit of a 64bit immediate
128 def LO32 : SDNodeXForm<imm, [{
129 return CurDAG->getTargetConstant(N->getZExtValue() & 0xffffffff, MVT::i32);
132 def LO32f : SDNodeXForm<fpimm, [{
133 APInt V = N->getValueAPF().bitcastToAPInt().trunc(32);
134 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
137 // Transformation function, extract the upper 32bit of a 64bit immediate
138 def HI32 : SDNodeXForm<imm, [{
139 return CurDAG->getTargetConstant(N->getZExtValue() >> 32, MVT::i32);
142 def HI32f : SDNodeXForm<fpimm, [{
143 APInt V = N->getValueAPF().bitcastToAPInt().lshr(32).trunc(32);
144 return CurDAG->getTargetConstantFP(APFloat(APFloat::IEEEsingle, V), MVT::f32);
147 def IMM8bitDWORD : PatLeaf <(imm),
148 [{return (N->getZExtValue() & ~0x3FC) == 0;}]
151 def as_dword_i32imm : SDNodeXForm<imm, [{
152 return CurDAG->getTargetConstant(N->getZExtValue() >> 2, MVT::i32);
155 def as_i1imm : SDNodeXForm<imm, [{
156 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i1);
159 def as_i8imm : SDNodeXForm<imm, [{
160 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i8);
163 def as_i16imm : SDNodeXForm<imm, [{
164 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i16);
167 def as_i32imm: SDNodeXForm<imm, [{
168 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i32);
171 def as_i64imm: SDNodeXForm<imm, [{
172 return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i64);
175 // Copied from the AArch64 backend:
176 def bitcast_fpimm_to_i32 : SDNodeXForm<fpimm, [{
177 return CurDAG->getTargetConstant(
178 N->getValueAPF().bitcastToAPInt().getZExtValue(), MVT::i32);
181 // Copied from the AArch64 backend:
182 def bitcast_fpimm_to_i64 : SDNodeXForm<fpimm, [{
183 return CurDAG->getTargetConstant(
184 N->getValueAPF().bitcastToAPInt().getZExtValue(), MVT::i64);
187 def IMM8bit : PatLeaf <(imm),
188 [{return isUInt<8>(N->getZExtValue());}]
191 def IMM12bit : PatLeaf <(imm),
192 [{return isUInt<12>(N->getZExtValue());}]
195 def IMM16bit : PatLeaf <(imm),
196 [{return isUInt<16>(N->getZExtValue());}]
199 def IMM20bit : PatLeaf <(imm),
200 [{return isUInt<20>(N->getZExtValue());}]
203 def IMM32bit : PatLeaf <(imm),
204 [{return isUInt<32>(N->getZExtValue());}]
207 def mubuf_vaddr_offset : PatFrag<
208 (ops node:$ptr, node:$offset, node:$imm_offset),
209 (add (add node:$ptr, node:$offset), node:$imm_offset)
212 class InlineImm <ValueType vt> : PatLeaf <(vt imm), [{
213 return isInlineImmediate(N);
216 class InlineFPImm <ValueType vt> : PatLeaf <(vt fpimm), [{
217 return isInlineImmediate(N);
220 class SGPRImm <dag frag> : PatLeaf<frag, [{
221 if (Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS) {
224 const SIRegisterInfo *SIRI =
225 static_cast<const SIRegisterInfo *>(Subtarget->getRegisterInfo());
226 for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
228 if (SIRI->isSGPRClass(getOperandRegClass(*U, U.getOperandNo()))) {
235 //===----------------------------------------------------------------------===//
237 //===----------------------------------------------------------------------===//
239 def FRAMEri32 : Operand<iPTR> {
240 let MIOperandInfo = (ops i32:$ptr, i32imm:$index);
243 def SoppBrTarget : AsmOperandClass {
244 let Name = "SoppBrTarget";
245 let ParserMethod = "parseSOppBrTarget";
248 def sopp_brtarget : Operand<OtherVT> {
249 let EncoderMethod = "getSOPPBrEncoding";
250 let OperandType = "OPERAND_PCREL";
251 let ParserMatchClass = SoppBrTarget;
254 include "SIInstrFormats.td"
255 include "VIInstrFormats.td"
257 def MubufOffsetMatchClass : AsmOperandClass {
258 let Name = "MubufOffset";
259 let ParserMethod = "parseMubufOptionalOps";
260 let RenderMethod = "addImmOperands";
263 class DSOffsetBaseMatchClass <string parser> : AsmOperandClass {
264 let Name = "DSOffset"#parser;
265 let ParserMethod = parser;
266 let RenderMethod = "addImmOperands";
267 let PredicateMethod = "isDSOffset";
270 def DSOffsetMatchClass : DSOffsetBaseMatchClass <"parseDSOptionalOps">;
271 def DSOffsetGDSMatchClass : DSOffsetBaseMatchClass <"parseDSOffsetOptional">;
273 def DSOffset01MatchClass : AsmOperandClass {
274 let Name = "DSOffset1";
275 let ParserMethod = "parseDSOff01OptionalOps";
276 let RenderMethod = "addImmOperands";
277 let PredicateMethod = "isDSOffset01";
280 class GDSBaseMatchClass <string parser> : AsmOperandClass {
281 let Name = "GDS"#parser;
282 let PredicateMethod = "isImm";
283 let ParserMethod = parser;
284 let RenderMethod = "addImmOperands";
287 def GDSMatchClass : GDSBaseMatchClass <"parseDSOptionalOps">;
288 def GDS01MatchClass : GDSBaseMatchClass <"parseDSOff01OptionalOps">;
290 def GLCMatchClass : AsmOperandClass {
292 let PredicateMethod = "isImm";
293 let ParserMethod = "parseMubufOptionalOps";
294 let RenderMethod = "addImmOperands";
297 def SLCMatchClass : AsmOperandClass {
299 let PredicateMethod = "isImm";
300 let ParserMethod = "parseMubufOptionalOps";
301 let RenderMethod = "addImmOperands";
304 def TFEMatchClass : AsmOperandClass {
306 let PredicateMethod = "isImm";
307 let ParserMethod = "parseMubufOptionalOps";
308 let RenderMethod = "addImmOperands";
311 def OModMatchClass : AsmOperandClass {
313 let PredicateMethod = "isImm";
314 let ParserMethod = "parseVOP3OptionalOps";
315 let RenderMethod = "addImmOperands";
318 def ClampMatchClass : AsmOperandClass {
320 let PredicateMethod = "isImm";
321 let ParserMethod = "parseVOP3OptionalOps";
322 let RenderMethod = "addImmOperands";
325 let OperandType = "OPERAND_IMMEDIATE" in {
327 def offen : Operand<i1> {
328 let PrintMethod = "printOffen";
330 def idxen : Operand<i1> {
331 let PrintMethod = "printIdxen";
333 def addr64 : Operand<i1> {
334 let PrintMethod = "printAddr64";
336 def mbuf_offset : Operand<i16> {
337 let PrintMethod = "printMBUFOffset";
338 let ParserMatchClass = MubufOffsetMatchClass;
340 class ds_offset_base <AsmOperandClass mc> : Operand<i16> {
341 let PrintMethod = "printDSOffset";
342 let ParserMatchClass = mc;
344 def ds_offset : ds_offset_base <DSOffsetMatchClass>;
345 def ds_offset_gds : ds_offset_base <DSOffsetGDSMatchClass>;
347 def ds_offset0 : Operand<i8> {
348 let PrintMethod = "printDSOffset0";
349 let ParserMatchClass = DSOffset01MatchClass;
351 def ds_offset1 : Operand<i8> {
352 let PrintMethod = "printDSOffset1";
353 let ParserMatchClass = DSOffset01MatchClass;
355 class gds_base <AsmOperandClass mc> : Operand <i1> {
356 let PrintMethod = "printGDS";
357 let ParserMatchClass = mc;
359 def gds : gds_base <GDSMatchClass>;
361 def gds01 : gds_base <GDS01MatchClass>;
363 def glc : Operand <i1> {
364 let PrintMethod = "printGLC";
365 let ParserMatchClass = GLCMatchClass;
367 def slc : Operand <i1> {
368 let PrintMethod = "printSLC";
369 let ParserMatchClass = SLCMatchClass;
371 def tfe : Operand <i1> {
372 let PrintMethod = "printTFE";
373 let ParserMatchClass = TFEMatchClass;
376 def omod : Operand <i32> {
377 let PrintMethod = "printOModSI";
378 let ParserMatchClass = OModMatchClass;
381 def ClampMod : Operand <i1> {
382 let PrintMethod = "printClampSI";
383 let ParserMatchClass = ClampMatchClass;
386 } // End OperandType = "OPERAND_IMMEDIATE"
388 def VOPDstS64 : VOPDstOperand <SReg_64>;
390 //===----------------------------------------------------------------------===//
392 //===----------------------------------------------------------------------===//
394 def DS1Addr1Offset : ComplexPattern<i32, 2, "SelectDS1Addr1Offset">;
395 def DS64Bit4ByteAligned : ComplexPattern<i32, 3, "SelectDS64Bit4ByteAligned">;
397 def MUBUFAddr32 : ComplexPattern<i64, 9, "SelectMUBUFAddr32">;
398 def MUBUFAddr64 : ComplexPattern<i64, 7, "SelectMUBUFAddr64">;
399 def MUBUFAddr64Atomic : ComplexPattern<i64, 5, "SelectMUBUFAddr64">;
400 def MUBUFScratch : ComplexPattern<i64, 4, "SelectMUBUFScratch">;
401 def MUBUFOffset : ComplexPattern<i64, 6, "SelectMUBUFOffset">;
402 def MUBUFOffsetAtomic : ComplexPattern<i64, 4, "SelectMUBUFOffset">;
404 def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">;
405 def VOP3Mods0Clamp : ComplexPattern<untyped, 3, "SelectVOP3Mods0Clamp">;
406 def VOP3Mods0Clamp0OMod : ComplexPattern<untyped, 4, "SelectVOP3Mods0Clamp0OMod">;
407 def VOP3Mods : ComplexPattern<untyped, 2, "SelectVOP3Mods">;
409 //===----------------------------------------------------------------------===//
410 // SI assembler operands
411 //===----------------------------------------------------------------------===//
432 //===----------------------------------------------------------------------===//
434 // SI Instruction multiclass helpers.
436 // Instructions with _32 take 32-bit operands.
437 // Instructions with _64 take 64-bit operands.
439 // VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit
440 // encoding is the standard encoding, but instruction that make use of
441 // any of the instruction modifiers must use the 64-bit encoding.
443 // Instructions with _e32 use the 32-bit encoding.
444 // Instructions with _e64 use the 64-bit encoding.
446 //===----------------------------------------------------------------------===//
448 class SIMCInstr <string pseudo, int subtarget> {
449 string PseudoInstr = pseudo;
450 int Subtarget = subtarget;
453 //===----------------------------------------------------------------------===//
455 //===----------------------------------------------------------------------===//
457 class EXPCommon : InstSI<
459 (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm,
460 VGPR_32:$src0, VGPR_32:$src1, VGPR_32:$src2, VGPR_32:$src3),
461 "exp $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3",
470 let isPseudo = 1, isCodeGenOnly = 1 in {
471 def "" : EXPCommon, SIMCInstr <"exp", SISubtarget.NONE> ;
474 def _si : EXPCommon, SIMCInstr <"exp", SISubtarget.SI>, EXPe;
476 def _vi : EXPCommon, SIMCInstr <"exp", SISubtarget.VI>, EXPe_vi;
479 //===----------------------------------------------------------------------===//
481 //===----------------------------------------------------------------------===//
483 class SOP1_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
484 SOP1 <outs, ins, "", pattern>,
485 SIMCInstr<opName, SISubtarget.NONE> {
487 let isCodeGenOnly = 1;
490 class SOP1_Real_si <sop1 op, string opName, dag outs, dag ins, string asm> :
491 SOP1 <outs, ins, asm, []>,
493 SIMCInstr<opName, SISubtarget.SI> {
494 let isCodeGenOnly = 0;
495 let AssemblerPredicates = [isSICI];
498 class SOP1_Real_vi <sop1 op, string opName, dag outs, dag ins, string asm> :
499 SOP1 <outs, ins, asm, []>,
501 SIMCInstr<opName, SISubtarget.VI> {
502 let isCodeGenOnly = 0;
503 let AssemblerPredicates = [isVI];
506 multiclass SOP1_m <sop1 op, string opName, dag outs, dag ins, string asm,
509 def "" : SOP1_Pseudo <opName, outs, ins, pattern>;
511 def _si : SOP1_Real_si <op, opName, outs, ins, asm>;
513 def _vi : SOP1_Real_vi <op, opName, outs, ins, asm>;
517 multiclass SOP1_32 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
518 op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0),
519 opName#" $dst, $src0", pattern
522 multiclass SOP1_64 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
523 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0),
524 opName#" $dst, $src0", pattern
527 // no input, 64-bit output.
528 multiclass SOP1_64_0 <sop1 op, string opName, list<dag> pattern> {
529 def "" : SOP1_Pseudo <opName, (outs SReg_64:$dst), (ins), pattern>;
531 def _si : SOP1_Real_si <op, opName, (outs SReg_64:$dst), (ins),
536 def _vi : SOP1_Real_vi <op, opName, (outs SReg_64:$dst), (ins),
542 // 64-bit input, no output
543 multiclass SOP1_1 <sop1 op, string opName, list<dag> pattern> {
544 def "" : SOP1_Pseudo <opName, (outs), (ins SReg_64:$src0), pattern>;
546 def _si : SOP1_Real_si <op, opName, (outs), (ins SReg_64:$src0),
551 def _vi : SOP1_Real_vi <op, opName, (outs), (ins SReg_64:$src0),
557 // 64-bit input, 32-bit output.
558 multiclass SOP1_32_64 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
559 op, opName, (outs SReg_32:$dst), (ins SSrc_64:$src0),
560 opName#" $dst, $src0", pattern
563 class SOP2_Pseudo<string opName, dag outs, dag ins, list<dag> pattern> :
564 SOP2<outs, ins, "", pattern>,
565 SIMCInstr<opName, SISubtarget.NONE> {
567 let isCodeGenOnly = 1;
570 // Pseudo instructions have no encodings, but adding this field here allows
572 // let sdst = xxx in {
573 // for multiclasses that include both real and pseudo instructions.
574 field bits<7> sdst = 0;
577 class SOP2_Real_si<sop2 op, string opName, dag outs, dag ins, string asm> :
578 SOP2<outs, ins, asm, []>,
580 SIMCInstr<opName, SISubtarget.SI> {
581 let AssemblerPredicates = [isSICI];
584 class SOP2_Real_vi<sop2 op, string opName, dag outs, dag ins, string asm> :
585 SOP2<outs, ins, asm, []>,
587 SIMCInstr<opName, SISubtarget.VI> {
588 let AssemblerPredicates = [isVI];
591 multiclass SOP2_SELECT_32 <sop2 op, string opName, list<dag> pattern> {
592 def "" : SOP2_Pseudo <opName, (outs SReg_32:$dst),
593 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc), pattern>;
595 def _si : SOP2_Real_si <op, opName, (outs SReg_32:$dst),
596 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc),
597 opName#" $dst, $src0, $src1 [$scc]">;
599 def _vi : SOP2_Real_vi <op, opName, (outs SReg_32:$dst),
600 (ins SSrc_32:$src0, SSrc_32:$src1, SCCReg:$scc),
601 opName#" $dst, $src0, $src1 [$scc]">;
604 multiclass SOP2_m <sop2 op, string opName, dag outs, dag ins, string asm,
607 def "" : SOP2_Pseudo <opName, outs, ins, pattern>;
609 def _si : SOP2_Real_si <op, opName, outs, ins, asm>;
611 def _vi : SOP2_Real_vi <op, opName, outs, ins, asm>;
615 multiclass SOP2_32 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
616 op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0, SSrc_32:$src1),
617 opName#" $dst, $src0, $src1", pattern
620 multiclass SOP2_64 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
621 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_64:$src1),
622 opName#" $dst, $src0, $src1", pattern
625 multiclass SOP2_64_32 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
626 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_32:$src1),
627 opName#" $dst, $src0, $src1", pattern
630 class SOPC_Helper <bits<7> op, RegisterOperand rc, ValueType vt,
631 string opName, PatLeaf cond> : SOPC <
632 op, (outs SCCReg:$dst), (ins rc:$src0, rc:$src1),
633 opName#" $src0, $src1", []>;
635 class SOPC_32<bits<7> op, string opName, PatLeaf cond = COND_NULL>
636 : SOPC_Helper<op, SSrc_32, i32, opName, cond>;
638 class SOPC_64<bits<7> op, string opName, PatLeaf cond = COND_NULL>
639 : SOPC_Helper<op, SSrc_64, i64, opName, cond>;
641 class SOPK_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
642 SOPK <outs, ins, "", pattern>,
643 SIMCInstr<opName, SISubtarget.NONE> {
645 let isCodeGenOnly = 1;
648 class SOPK_Real_si <sopk op, string opName, dag outs, dag ins, string asm> :
649 SOPK <outs, ins, asm, []>,
651 SIMCInstr<opName, SISubtarget.SI> {
652 let AssemblerPredicates = [isSICI];
653 let isCodeGenOnly = 0;
656 class SOPK_Real_vi <sopk op, string opName, dag outs, dag ins, string asm> :
657 SOPK <outs, ins, asm, []>,
659 SIMCInstr<opName, SISubtarget.VI> {
660 let AssemblerPredicates = [isVI];
661 let isCodeGenOnly = 0;
664 multiclass SOPK_m <sopk op, string opName, dag outs, dag ins, string opAsm,
665 string asm = opName#opAsm> {
666 def "" : SOPK_Pseudo <opName, outs, ins, []>;
668 def _si : SOPK_Real_si <op, opName, outs, ins, asm>;
670 def _vi : SOPK_Real_vi <op, opName, outs, ins, asm>;
674 multiclass SOPK_32 <sopk op, string opName, list<dag> pattern> {
675 def "" : SOPK_Pseudo <opName, (outs SReg_32:$dst), (ins u16imm:$src0),
678 def _si : SOPK_Real_si <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
679 opName#" $dst, $src0">;
681 def _vi : SOPK_Real_vi <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
682 opName#" $dst, $src0">;
685 multiclass SOPK_SCC <sopk op, string opName, list<dag> pattern> {
686 def "" : SOPK_Pseudo <opName, (outs SCCReg:$dst),
687 (ins SReg_32:$src0, u16imm:$src1), pattern>;
689 let DisableEncoding = "$dst" in {
690 def _si : SOPK_Real_si <op, opName, (outs SCCReg:$dst),
691 (ins SReg_32:$sdst, u16imm:$simm16), opName#" $sdst, $simm16">;
693 def _vi : SOPK_Real_vi <op, opName, (outs SCCReg:$dst),
694 (ins SReg_32:$sdst, u16imm:$simm16), opName#" $sdst, $simm16">;
698 multiclass SOPK_32TIE <sopk op, string opName, list<dag> pattern> : SOPK_m <
699 op, opName, (outs SReg_32:$sdst), (ins SReg_32:$src0, u16imm:$simm16),
703 multiclass SOPK_IMM32 <sopk op, string opName, dag outs, dag ins,
704 string argAsm, string asm = opName#argAsm> {
706 def "" : SOPK_Pseudo <opName, outs, ins, []>;
708 def _si : SOPK <outs, ins, asm, []>,
710 SIMCInstr<opName, SISubtarget.SI> {
711 let AssemblerPredicates = [isSICI];
712 let isCodeGenOnly = 0;
715 def _vi : SOPK <outs, ins, asm, []>,
717 SIMCInstr<opName, SISubtarget.VI> {
718 let AssemblerPredicates = [isVI];
719 let isCodeGenOnly = 0;
722 //===----------------------------------------------------------------------===//
724 //===----------------------------------------------------------------------===//
726 class SMRD_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
727 SMRD <outs, ins, "", pattern>,
728 SIMCInstr<opName, SISubtarget.NONE> {
730 let isCodeGenOnly = 1;
733 class SMRD_Real_si <bits<5> op, string opName, bit imm, dag outs, dag ins,
735 SMRD <outs, ins, asm, []>,
737 SIMCInstr<opName, SISubtarget.SI> {
738 let AssemblerPredicates = [isSICI];
741 class SMRD_Real_vi <bits<8> op, string opName, bit imm, dag outs, dag ins,
743 SMRD <outs, ins, asm, []>,
745 SIMCInstr<opName, SISubtarget.VI> {
746 let AssemblerPredicates = [isVI];
749 multiclass SMRD_m <bits<5> op, string opName, bit imm, dag outs, dag ins,
750 string asm, list<dag> pattern> {
752 def "" : SMRD_Pseudo <opName, outs, ins, pattern>;
754 def _si : SMRD_Real_si <op, opName, imm, outs, ins, asm>;
756 // glc is only applicable to scalar stores, which are not yet
759 def _vi : SMRD_Real_vi <{0, 0, 0, op}, opName, imm, outs, ins, asm>;
763 multiclass SMRD_Helper <bits<5> op, string opName, RegisterClass baseClass,
764 RegisterClass dstClass> {
766 op, opName#"_IMM", 1, (outs dstClass:$dst),
767 (ins baseClass:$sbase, u32imm:$offset),
768 opName#" $dst, $sbase, $offset", []
771 defm _SGPR : SMRD_m <
772 op, opName#"_SGPR", 0, (outs dstClass:$dst),
773 (ins baseClass:$sbase, SReg_32:$soff),
774 opName#" $dst, $sbase, $soff", []
778 //===----------------------------------------------------------------------===//
779 // Vector ALU classes
780 //===----------------------------------------------------------------------===//
782 // This must always be right before the operand being input modified.
783 def InputMods : OperandWithDefaultOps <i32, (ops (i32 0))> {
784 let PrintMethod = "printOperandAndMods";
787 def InputModsMatchClass : AsmOperandClass {
788 let Name = "RegWithInputMods";
791 def InputModsNoDefault : Operand <i32> {
792 let PrintMethod = "printOperandAndMods";
793 let ParserMatchClass = InputModsMatchClass;
796 class getNumSrcArgs<ValueType Src1, ValueType Src2> {
798 !if (!eq(Src1.Value, untyped.Value), 1, // VOP1
799 !if (!eq(Src2.Value, untyped.Value), 2, // VOP2
803 // Returns the register class to use for the destination of VOP[123C]
804 // instructions for the given VT.
805 class getVALUDstForVT<ValueType VT> {
806 RegisterOperand ret = !if(!eq(VT.Size, 32), VOPDstOperand<VGPR_32>,
807 !if(!eq(VT.Size, 64), VOPDstOperand<VReg_64>,
808 VOPDstOperand<SReg_64>)); // else VT == i1
811 // Returns the register class to use for source 0 of VOP[12C]
812 // instructions for the given VT.
813 class getVOPSrc0ForVT<ValueType VT> {
814 RegisterOperand ret = !if(!eq(VT.Size, 32), VSrc_32, VSrc_64);
817 // Returns the register class to use for source 1 of VOP[12C] for the
819 class getVOPSrc1ForVT<ValueType VT> {
820 RegisterClass ret = !if(!eq(VT.Size, 32), VGPR_32, VReg_64);
823 // Returns the register class to use for sources of VOP3 instructions for the
825 class getVOP3SrcForVT<ValueType VT> {
826 RegisterOperand ret = !if(!eq(VT.Size, 32), VCSrc_32, VCSrc_64);
829 // Returns 1 if the source arguments have modifiers, 0 if they do not.
830 class hasModifiers<ValueType SrcVT> {
831 bit ret = !if(!eq(SrcVT.Value, f32.Value), 1,
832 !if(!eq(SrcVT.Value, f64.Value), 1, 0));
835 // Returns the input arguments for VOP[12C] instructions for the given SrcVT.
836 class getIns32 <RegisterOperand Src0RC, RegisterClass Src1RC, int NumSrcArgs> {
837 dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0), // VOP1
838 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
842 // Returns the input arguments for VOP3 instructions for the given SrcVT.
843 class getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC,
844 RegisterOperand Src2RC, int NumSrcArgs,
848 !if (!eq(NumSrcArgs, 1),
849 !if (!eq(HasModifiers, 1),
850 // VOP1 with modifiers
851 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
852 ClampMod:$clamp, omod:$omod)
854 // VOP1 without modifiers
857 !if (!eq(NumSrcArgs, 2),
858 !if (!eq(HasModifiers, 1),
859 // VOP 2 with modifiers
860 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
861 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
862 ClampMod:$clamp, omod:$omod)
864 // VOP2 without modifiers
865 (ins Src0RC:$src0, Src1RC:$src1)
867 /* NumSrcArgs == 3 */,
868 !if (!eq(HasModifiers, 1),
869 // VOP3 with modifiers
870 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
871 InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
872 InputModsNoDefault:$src2_modifiers, Src2RC:$src2,
873 ClampMod:$clamp, omod:$omod)
875 // VOP3 without modifiers
876 (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2)
880 // Returns the assembly string for the inputs and outputs of a VOP[12C]
881 // instruction. This does not add the _e32 suffix, so it can be reused
883 class getAsm32 <int NumSrcArgs> {
884 string src1 = ", $src1";
885 string src2 = ", $src2";
886 string ret = "$dst, $src0"#
887 !if(!eq(NumSrcArgs, 1), "", src1)#
888 !if(!eq(NumSrcArgs, 3), src2, "");
891 // Returns the assembly string for the inputs and outputs of a VOP3
893 class getAsm64 <int NumSrcArgs, bit HasModifiers> {
894 string src0 = !if(!eq(NumSrcArgs, 1), "$src0_modifiers", "$src0_modifiers,");
895 string src1 = !if(!eq(NumSrcArgs, 1), "",
896 !if(!eq(NumSrcArgs, 2), " $src1_modifiers",
897 " $src1_modifiers,"));
898 string src2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers", "");
900 !if(!eq(HasModifiers, 0),
901 getAsm32<NumSrcArgs>.ret,
902 "$dst, "#src0#src1#src2#"$clamp"#"$omod");
906 class VOPProfile <list<ValueType> _ArgVT> {
908 field list<ValueType> ArgVT = _ArgVT;
910 field ValueType DstVT = ArgVT[0];
911 field ValueType Src0VT = ArgVT[1];
912 field ValueType Src1VT = ArgVT[2];
913 field ValueType Src2VT = ArgVT[3];
914 field RegisterOperand DstRC = getVALUDstForVT<DstVT>.ret;
915 field RegisterOperand Src0RC32 = getVOPSrc0ForVT<Src0VT>.ret;
916 field RegisterClass Src1RC32 = getVOPSrc1ForVT<Src1VT>.ret;
917 field RegisterOperand Src0RC64 = getVOP3SrcForVT<Src0VT>.ret;
918 field RegisterOperand Src1RC64 = getVOP3SrcForVT<Src1VT>.ret;
919 field RegisterOperand Src2RC64 = getVOP3SrcForVT<Src2VT>.ret;
921 field int NumSrcArgs = getNumSrcArgs<Src1VT, Src2VT>.ret;
922 field bit HasModifiers = hasModifiers<Src0VT>.ret;
924 field dag Outs = (outs DstRC:$dst);
926 field dag Ins32 = getIns32<Src0RC32, Src1RC32, NumSrcArgs>.ret;
927 field dag Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
930 field string Asm32 = getAsm32<NumSrcArgs>.ret;
931 field string Asm64 = getAsm64<NumSrcArgs, HasModifiers>.ret;
934 // FIXME: I think these F16 profiles will need to use f16 types in order
935 // for the instruction patterns to work.
936 def VOP_F16_F16 : VOPProfile <[f32, f32, untyped, untyped]>;
937 def VOP_F16_I16 : VOPProfile <[f32, i32, untyped, untyped]>;
938 def VOP_I16_F16 : VOPProfile <[i32, f32, untyped, untyped]>;
940 def VOP_F32_F32 : VOPProfile <[f32, f32, untyped, untyped]>;
941 def VOP_F32_F64 : VOPProfile <[f32, f64, untyped, untyped]>;
942 def VOP_F32_I32 : VOPProfile <[f32, i32, untyped, untyped]>;
943 def VOP_F64_F32 : VOPProfile <[f64, f32, untyped, untyped]>;
944 def VOP_F64_F64 : VOPProfile <[f64, f64, untyped, untyped]>;
945 def VOP_F64_I32 : VOPProfile <[f64, i32, untyped, untyped]>;
946 def VOP_I32_F32 : VOPProfile <[i32, f32, untyped, untyped]>;
947 def VOP_I32_F64 : VOPProfile <[i32, f64, untyped, untyped]>;
948 def VOP_I32_I32 : VOPProfile <[i32, i32, untyped, untyped]>;
950 def VOP_F32_F32_F32 : VOPProfile <[f32, f32, f32, untyped]>;
951 def VOP_F32_F32_I32 : VOPProfile <[f32, f32, i32, untyped]>;
952 def VOP_F64_F64_F64 : VOPProfile <[f64, f64, f64, untyped]>;
953 def VOP_F64_F64_I32 : VOPProfile <[f64, f64, i32, untyped]>;
954 def VOP_I32_F32_F32 : VOPProfile <[i32, f32, f32, untyped]>;
955 def VOP_I32_F32_I32 : VOPProfile <[i32, f32, i32, untyped]>;
956 def VOP_I32_I32_I32 : VOPProfile <[i32, i32, i32, untyped]>;
957 def VOP_I32_I32_I32_VCC : VOPProfile <[i32, i32, i32, untyped]> {
958 let Src0RC32 = VCSrc_32;
961 def VOP_I1_F32_I32 : VOPProfile <[i1, f32, i32, untyped]> {
962 let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
963 let Asm64 = "$dst, $src0_modifiers, $src1";
966 def VOP_I1_F64_I32 : VOPProfile <[i1, f64, i32, untyped]> {
967 let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
968 let Asm64 = "$dst, $src0_modifiers, $src1";
971 def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>;
972 def VOP_I64_I32_I64 : VOPProfile <[i64, i32, i64, untyped]>;
973 def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>;
974 def VOP_CNDMASK : VOPProfile <[i32, i32, i32, untyped]> {
975 let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1, VCCReg:$src2);
976 let Ins64 = (ins Src0RC64:$src0, Src1RC64:$src1, SSrc_64:$src2);
977 let Asm64 = "$dst, $src0, $src1, $src2";
980 def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>;
981 def VOP_MADK : VOPProfile <[f32, f32, f32, f32]> {
982 field dag Ins = (ins VCSrc_32:$src0, VGPR_32:$vsrc1, u32imm:$src2);
983 field string Asm = "$dst, $src0, $vsrc1, $src2";
985 def VOP_F64_F64_F64_F64 : VOPProfile <[f64, f64, f64, f64]>;
986 def VOP_I32_I32_I32_I32 : VOPProfile <[i32, i32, i32, i32]>;
987 def VOP_I64_I32_I32_I64 : VOPProfile <[i64, i32, i32, i64]>;
990 class VOP <string opName> {
991 string OpName = opName;
994 class VOP2_REV <string revOp, bit isOrig> {
995 string RevOp = revOp;
999 class AtomicNoRet <string noRetOp, bit isRet> {
1000 string NoRetOp = noRetOp;
1004 class VOP1_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
1005 VOP1Common <outs, ins, "", pattern>,
1007 SIMCInstr <opName#"_e32", SISubtarget.NONE>,
1008 MnemonicAlias<opName#"_e32", opName> {
1010 let isCodeGenOnly = 1;
1016 class VOP1_Real_si <string opName, vop1 op, dag outs, dag ins, string asm> :
1017 VOP1<op.SI, outs, ins, asm, []>,
1018 SIMCInstr <opName#"_e32", SISubtarget.SI> {
1019 let AssemblerPredicate = SIAssemblerPredicate;
1022 class VOP1_Real_vi <string opName, vop1 op, dag outs, dag ins, string asm> :
1023 VOP1<op.VI, outs, ins, asm, []>,
1024 SIMCInstr <opName#"_e32", SISubtarget.VI> {
1025 let AssemblerPredicates = [isVI];
1028 multiclass VOP1_m <vop1 op, dag outs, dag ins, string asm, list<dag> pattern,
1030 def "" : VOP1_Pseudo <outs, ins, pattern, opName>;
1032 def _si : VOP1_Real_si <opName, op, outs, ins, asm>;
1034 def _vi : VOP1_Real_vi <opName, op, outs, ins, asm>;
1037 multiclass VOP1SI_m <vop1 op, dag outs, dag ins, string asm, list<dag> pattern,
1039 def "" : VOP1_Pseudo <outs, ins, pattern, opName>;
1041 def _si : VOP1_Real_si <opName, op, outs, ins, asm>;
1044 class VOP2_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
1045 VOP2Common <outs, ins, "", pattern>,
1047 SIMCInstr<opName#"_e32", SISubtarget.NONE>,
1048 MnemonicAlias<opName#"_e32", opName> {
1050 let isCodeGenOnly = 1;
1053 class VOP2_Real_si <string opName, vop2 op, dag outs, dag ins, string asm> :
1054 VOP2 <op.SI, outs, ins, opName#asm, []>,
1055 SIMCInstr <opName#"_e32", SISubtarget.SI> {
1056 let AssemblerPredicates = [isSICI];
1059 class VOP2_Real_vi <string opName, vop2 op, dag outs, dag ins, string asm> :
1060 VOP2 <op.VI, outs, ins, opName#asm, []>,
1061 SIMCInstr <opName#"_e32", SISubtarget.VI> {
1062 let AssemblerPredicates = [isVI];
1065 multiclass VOP2SI_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern,
1066 string opName, string revOp> {
1067 def "" : VOP2_Pseudo <outs, ins, pattern, opName>,
1068 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
1070 def _si : VOP2_Real_si <opName, op, outs, ins, asm>;
1073 multiclass VOP2_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern,
1074 string opName, string revOp> {
1075 def "" : VOP2_Pseudo <outs, ins, pattern, opName>,
1076 VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
1078 def _si : VOP2_Real_si <opName, op, outs, ins, asm>;
1080 def _vi : VOP2_Real_vi <opName, op, outs, ins, asm>;
1084 class VOP3DisableFields <bit HasSrc1, bit HasSrc2, bit HasModifiers> {
1086 bits<2> src0_modifiers = !if(HasModifiers, ?, 0);
1087 bits<2> src1_modifiers = !if(HasModifiers, !if(HasSrc1, ?, 0), 0);
1088 bits<2> src2_modifiers = !if(HasModifiers, !if(HasSrc2, ?, 0), 0);
1089 bits<2> omod = !if(HasModifiers, ?, 0);
1090 bits<1> clamp = !if(HasModifiers, ?, 0);
1091 bits<9> src1 = !if(HasSrc1, ?, 0);
1092 bits<9> src2 = !if(HasSrc2, ?, 0);
1095 class VOP3DisableModFields <bit HasSrc0Mods,
1096 bit HasSrc1Mods = 0,
1097 bit HasSrc2Mods = 0,
1098 bit HasOutputMods = 0> {
1099 bits<2> src0_modifiers = !if(HasSrc0Mods, ?, 0);
1100 bits<2> src1_modifiers = !if(HasSrc1Mods, ?, 0);
1101 bits<2> src2_modifiers = !if(HasSrc2Mods, ?, 0);
1102 bits<2> omod = !if(HasOutputMods, ?, 0);
1103 bits<1> clamp = !if(HasOutputMods, ?, 0);
1106 class VOP3_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
1107 VOP3Common <outs, ins, "", pattern>,
1109 SIMCInstr<opName#"_e64", SISubtarget.NONE>,
1110 MnemonicAlias<opName#"_e64", opName> {
1112 let isCodeGenOnly = 1;
1115 class VOP3_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
1116 VOP3Common <outs, ins, asm, []>,
1118 SIMCInstr<opName#"_e64", SISubtarget.SI> {
1119 let AssemblerPredicates = [isSICI];
1122 class VOP3_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName> :
1123 VOP3Common <outs, ins, asm, []>,
1125 SIMCInstr <opName#"_e64", SISubtarget.VI> {
1126 let AssemblerPredicates = [isVI];
1129 class VOP3b_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
1130 VOP3Common <outs, ins, asm, []>,
1132 SIMCInstr<opName#"_e64", SISubtarget.SI> {
1133 let AssemblerPredicates = [isSICI];
1136 class VOP3b_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName> :
1137 VOP3Common <outs, ins, asm, []>,
1139 SIMCInstr <opName#"_e64", SISubtarget.VI> {
1140 let AssemblerPredicates = [isVI];
1143 multiclass VOP3_m <vop op, dag outs, dag ins, string asm, list<dag> pattern,
1144 string opName, int NumSrcArgs, bit HasMods = 1> {
1146 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1148 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1149 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
1150 !if(!eq(NumSrcArgs, 2), 0, 1),
1152 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1153 VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
1154 !if(!eq(NumSrcArgs, 2), 0, 1),
1158 // VOP3_m without source modifiers
1159 multiclass VOP3_m_nomods <vop op, dag outs, dag ins, string asm, list<dag> pattern,
1160 string opName, int NumSrcArgs, bit HasMods = 1> {
1162 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1164 let src0_modifiers = 0,
1169 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>;
1170 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>;
1174 multiclass VOP3_1_m <vop op, dag outs, dag ins, string asm,
1175 list<dag> pattern, string opName, bit HasMods = 1> {
1177 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1179 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1180 VOP3DisableFields<0, 0, HasMods>;
1182 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1183 VOP3DisableFields<0, 0, HasMods>;
1186 multiclass VOP3SI_1_m <vop op, dag outs, dag ins, string asm,
1187 list<dag> pattern, string opName, bit HasMods = 1> {
1189 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1191 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1192 VOP3DisableFields<0, 0, HasMods>;
1193 // No VI instruction. This class is for SI only.
1196 multiclass VOP3_2_m <vop op, dag outs, dag ins, string asm,
1197 list<dag> pattern, string opName, string revOp,
1198 bit HasMods = 1, bit UseFullOp = 0> {
1200 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1201 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
1203 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1204 VOP3DisableFields<1, 0, HasMods>;
1206 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1207 VOP3DisableFields<1, 0, HasMods>;
1210 multiclass VOP3SI_2_m <vop op, dag outs, dag ins, string asm,
1211 list<dag> pattern, string opName, string revOp,
1212 bit HasMods = 1, bit UseFullOp = 0> {
1214 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1215 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
1217 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1218 VOP3DisableFields<1, 0, HasMods>;
1220 // No VI instruction. This class is for SI only.
1223 // XXX - Is v_div_scale_{f32|f64} only available in vop3b without
1224 // option of implicit vcc use?
1225 multiclass VOP3b_2_m <vop op, dag outs, dag ins, string asm,
1226 list<dag> pattern, string opName, string revOp,
1227 bit HasMods = 1, bit UseFullOp = 0> {
1228 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1229 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
1231 // The VOP2 variant puts the carry out into VCC, the VOP3 variant
1232 // can write it into any SGPR. We currently don't use the carry out,
1233 // so for now hardcode it to VCC as well.
1234 let sdst = SIOperand.VCC, Defs = [VCC] in {
1235 def _si : VOP3b_Real_si <op.SI3, outs, ins, asm, opName>,
1236 VOP3DisableFields<1, 0, HasMods>;
1238 def _vi : VOP3b_Real_vi <op.VI3, outs, ins, asm, opName>,
1239 VOP3DisableFields<1, 0, HasMods>;
1240 } // End sdst = SIOperand.VCC, Defs = [VCC]
1243 multiclass VOP3b_3_m <vop op, dag outs, dag ins, string asm,
1244 list<dag> pattern, string opName, string revOp,
1245 bit HasMods = 1, bit UseFullOp = 0> {
1246 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1249 def _si : VOP3b_Real_si <op.SI3, outs, ins, asm, opName>,
1250 VOP3DisableFields<1, 1, HasMods>;
1252 def _vi : VOP3b_Real_vi <op.VI3, outs, ins, asm, opName>,
1253 VOP3DisableFields<1, 1, HasMods>;
1256 multiclass VOP3_C_m <vop op, dag outs, dag ins, string asm,
1257 list<dag> pattern, string opName,
1258 bit HasMods, bit defExec, string revOp> {
1260 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1261 VOP2_REV<revOp#"_e64", !eq(revOp, opName)>;
1263 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1264 VOP3DisableFields<1, 0, HasMods> {
1265 let Defs = !if(defExec, [EXEC], []);
1268 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1269 VOP3DisableFields<1, 0, HasMods> {
1270 let Defs = !if(defExec, [EXEC], []);
1274 // An instruction that is VOP2 on SI and VOP3 on VI, no modifiers.
1275 multiclass VOP2SI_3VI_m <vop3 op, string opName, dag outs, dag ins,
1276 string asm, list<dag> pattern = []> {
1277 let isPseudo = 1, isCodeGenOnly = 1 in {
1278 def "" : VOPAnyCommon <outs, ins, "", pattern>,
1279 SIMCInstr<opName, SISubtarget.NONE>;
1282 def _si : VOP2 <op.SI3{5-0}, outs, ins, asm, []>,
1283 SIMCInstr <opName, SISubtarget.SI> {
1284 let AssemblerPredicates = [isSICI];
1287 def _vi : VOP3Common <outs, ins, asm, []>,
1289 VOP3DisableFields <1, 0, 0>,
1290 SIMCInstr <opName, SISubtarget.VI> {
1291 let AssemblerPredicates = [isVI];
1295 multiclass VOP1_Helper <vop1 op, string opName, dag outs,
1296 dag ins32, string asm32, list<dag> pat32,
1297 dag ins64, string asm64, list<dag> pat64,
1300 defm _e32 : VOP1_m <op, outs, ins32, opName#asm32, pat32, opName>;
1302 defm _e64 : VOP3_1_m <op, outs, ins64, opName#asm64, pat64, opName, HasMods>;
1305 multiclass VOP1Inst <vop1 op, string opName, VOPProfile P,
1306 SDPatternOperator node = null_frag> : VOP1_Helper <
1308 P.Ins32, P.Asm32, [],
1311 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
1312 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
1313 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
1317 multiclass VOP1InstSI <vop1 op, string opName, VOPProfile P,
1318 SDPatternOperator node = null_frag> {
1320 defm _e32 : VOP1SI_m <op, P.Outs, P.Ins32, opName#P.Asm32, [], opName>;
1322 defm _e64 : VOP3SI_1_m <op, P.Outs, P.Ins64, opName#P.Asm64,
1324 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
1325 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
1326 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
1327 opName, P.HasModifiers>;
1330 multiclass VOP2_Helper <vop2 op, string opName, dag outs,
1331 dag ins32, string asm32, list<dag> pat32,
1332 dag ins64, string asm64, list<dag> pat64,
1333 string revOp, bit HasMods> {
1334 defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOp>;
1336 defm _e64 : VOP3_2_m <op,
1337 outs, ins64, opName#asm64, pat64, opName, revOp, HasMods
1341 multiclass VOP2Inst <vop2 op, string opName, VOPProfile P,
1342 SDPatternOperator node = null_frag,
1343 string revOp = opName> : VOP2_Helper <
1345 P.Ins32, P.Asm32, [],
1349 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1350 i1:$clamp, i32:$omod)),
1351 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1352 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1353 revOp, P.HasModifiers
1356 multiclass VOP2InstSI <vop2 op, string opName, VOPProfile P,
1357 SDPatternOperator node = null_frag,
1358 string revOp = opName> {
1359 defm _e32 : VOP2SI_m <op, P.Outs, P.Ins32, P.Asm32, [], opName, revOp>;
1361 defm _e64 : VOP3SI_2_m <op, P.Outs, P.Ins64, opName#P.Asm64,
1364 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1365 i1:$clamp, i32:$omod)),
1366 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1367 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1368 opName, revOp, P.HasModifiers>;
1371 multiclass VOP2b_Helper <vop2 op, string opName, dag outs,
1372 dag ins32, string asm32, list<dag> pat32,
1373 dag ins64, string asm64, list<dag> pat64,
1374 string revOp, bit HasMods> {
1376 defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOp>;
1378 defm _e64 : VOP3b_2_m <op,
1379 outs, ins64, opName#asm64, pat64, opName, revOp, HasMods
1383 multiclass VOP2bInst <vop2 op, string opName, VOPProfile P,
1384 SDPatternOperator node = null_frag,
1385 string revOp = opName> : VOP2b_Helper <
1387 P.Ins32, P.Asm32, [],
1391 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1392 i1:$clamp, i32:$omod)),
1393 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1394 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1395 revOp, P.HasModifiers
1398 // A VOP2 instruction that is VOP3-only on VI.
1399 multiclass VOP2_VI3_Helper <vop23 op, string opName, dag outs,
1400 dag ins32, string asm32, list<dag> pat32,
1401 dag ins64, string asm64, list<dag> pat64,
1402 string revOp, bit HasMods> {
1403 defm _e32 : VOP2SI_m <op, outs, ins32, asm32, pat32, opName, revOp>;
1405 defm _e64 : VOP3_2_m <op, outs, ins64, opName#asm64, pat64, opName,
1409 multiclass VOP2_VI3_Inst <vop23 op, string opName, VOPProfile P,
1410 SDPatternOperator node = null_frag,
1411 string revOp = opName>
1414 P.Ins32, P.Asm32, [],
1418 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1419 i1:$clamp, i32:$omod)),
1420 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1421 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1422 revOp, P.HasModifiers
1425 multiclass VOP2MADK <vop2 op, string opName, list<dag> pattern = []> {
1427 def "" : VOP2_Pseudo <VOP_MADK.Outs, VOP_MADK.Ins, pattern, opName>;
1429 let isCodeGenOnly = 0 in {
1430 def _si : VOP2Common <VOP_MADK.Outs, VOP_MADK.Ins,
1431 !strconcat(opName, VOP_MADK.Asm), []>,
1432 SIMCInstr <opName#"_e32", SISubtarget.SI>,
1435 def _vi : VOP2Common <VOP_MADK.Outs, VOP_MADK.Ins,
1436 !strconcat(opName, VOP_MADK.Asm), []>,
1437 SIMCInstr <opName#"_e32", SISubtarget.VI>,
1439 } // End isCodeGenOnly = 0
1442 class VOPC_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
1443 VOPCCommon <ins, "", pattern>,
1445 SIMCInstr<opName#"_e32", SISubtarget.NONE>,
1446 MnemonicAlias<opName#"_e32", opName> {
1448 let isCodeGenOnly = 1;
1451 multiclass VOPC_m <vopc op, dag outs, dag ins, string asm, list<dag> pattern,
1452 string opName, bit DefExec, string revOpName = ""> {
1453 def "" : VOPC_Pseudo <outs, ins, pattern, opName>;
1455 def _si : VOPC<op.SI, ins, asm, []>,
1456 SIMCInstr <opName#"_e32", SISubtarget.SI> {
1457 let Defs = !if(DefExec, [EXEC], []);
1458 let hasSideEffects = DefExec;
1461 def _vi : VOPC<op.VI, ins, asm, []>,
1462 SIMCInstr <opName#"_e32", SISubtarget.VI> {
1463 let Defs = !if(DefExec, [EXEC], []);
1464 let hasSideEffects = DefExec;
1468 multiclass VOPC_Helper <vopc op, string opName,
1469 dag ins32, string asm32, list<dag> pat32,
1470 dag out64, dag ins64, string asm64, list<dag> pat64,
1471 bit HasMods, bit DefExec, string revOp> {
1472 defm _e32 : VOPC_m <op, (outs), ins32, opName#asm32, pat32, opName, DefExec>;
1474 defm _e64 : VOP3_C_m <op, out64, ins64, opName#asm64, pat64,
1475 opName, HasMods, DefExec, revOp>;
1478 // Special case for class instructions which only have modifiers on
1479 // the 1st source operand.
1480 multiclass VOPC_Class_Helper <vopc op, string opName,
1481 dag ins32, string asm32, list<dag> pat32,
1482 dag out64, dag ins64, string asm64, list<dag> pat64,
1483 bit HasMods, bit DefExec, string revOp> {
1484 defm _e32 : VOPC_m <op, (outs), ins32, opName#asm32, pat32, opName, DefExec>;
1486 defm _e64 : VOP3_C_m <op, out64, ins64, opName#asm64, pat64,
1487 opName, HasMods, DefExec, revOp>,
1488 VOP3DisableModFields<1, 0, 0>;
1491 multiclass VOPCInst <vopc op, string opName,
1492 VOPProfile P, PatLeaf cond = COND_NULL,
1493 string revOp = opName,
1494 bit DefExec = 0> : VOPC_Helper <
1496 P.Ins32, P.Asm32, [],
1497 (outs VOPDstS64:$dst), P.Ins64, P.Asm64,
1500 (setcc (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1501 i1:$clamp, i32:$omod)),
1502 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1504 [(set i1:$dst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]),
1505 P.HasModifiers, DefExec, revOp
1508 multiclass VOPCClassInst <vopc op, string opName, VOPProfile P,
1509 bit DefExec = 0> : VOPC_Class_Helper <
1511 P.Ins32, P.Asm32, [],
1512 (outs VOPDstS64:$dst), P.Ins64, P.Asm64,
1515 (AMDGPUfp_class (P.Src0VT (VOP3Mods0Clamp0OMod P.Src0VT:$src0, i32:$src0_modifiers)), P.Src1VT:$src1))],
1516 [(set i1:$dst, (AMDGPUfp_class P.Src0VT:$src0, P.Src1VT:$src1))]),
1517 P.HasModifiers, DefExec, opName
1521 multiclass VOPC_F32 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
1522 VOPCInst <op, opName, VOP_F32_F32_F32, cond, revOp>;
1524 multiclass VOPC_F64 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
1525 VOPCInst <op, opName, VOP_F64_F64_F64, cond, revOp>;
1527 multiclass VOPC_I32 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
1528 VOPCInst <op, opName, VOP_I32_I32_I32, cond, revOp>;
1530 multiclass VOPC_I64 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
1531 VOPCInst <op, opName, VOP_I64_I64_I64, cond, revOp>;
1534 multiclass VOPCX <vopc op, string opName, VOPProfile P,
1535 PatLeaf cond = COND_NULL,
1537 : VOPCInst <op, opName, P, cond, revOp, 1>;
1539 multiclass VOPCX_F32 <vopc op, string opName, string revOp = opName> :
1540 VOPCX <op, opName, VOP_F32_F32_F32, COND_NULL, revOp>;
1542 multiclass VOPCX_F64 <vopc op, string opName, string revOp = opName> :
1543 VOPCX <op, opName, VOP_F64_F64_F64, COND_NULL, revOp>;
1545 multiclass VOPCX_I32 <vopc op, string opName, string revOp = opName> :
1546 VOPCX <op, opName, VOP_I32_I32_I32, COND_NULL, revOp>;
1548 multiclass VOPCX_I64 <vopc op, string opName, string revOp = opName> :
1549 VOPCX <op, opName, VOP_I64_I64_I64, COND_NULL, revOp>;
1551 multiclass VOP3_Helper <vop3 op, string opName, dag outs, dag ins, string asm,
1552 list<dag> pat, int NumSrcArgs, bit HasMods> : VOP3_m <
1553 op, outs, ins, opName#" "#asm, pat, opName, NumSrcArgs, HasMods
1556 multiclass VOPC_CLASS_F32 <vopc op, string opName> :
1557 VOPCClassInst <op, opName, VOP_I1_F32_I32, 0>;
1559 multiclass VOPCX_CLASS_F32 <vopc op, string opName> :
1560 VOPCClassInst <op, opName, VOP_I1_F32_I32, 1>;
1562 multiclass VOPC_CLASS_F64 <vopc op, string opName> :
1563 VOPCClassInst <op, opName, VOP_I1_F64_I32, 0>;
1565 multiclass VOPCX_CLASS_F64 <vopc op, string opName> :
1566 VOPCClassInst <op, opName, VOP_I1_F64_I32, 1>;
1568 multiclass VOP3Inst <vop3 op, string opName, VOPProfile P,
1569 SDPatternOperator node = null_frag> : VOP3_Helper <
1570 op, opName, (outs P.DstRC.RegClass:$dst), P.Ins64, P.Asm64,
1571 !if(!eq(P.NumSrcArgs, 3),
1574 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1575 i1:$clamp, i32:$omod)),
1576 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1577 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))],
1578 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1,
1580 !if(!eq(P.NumSrcArgs, 2),
1583 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1584 i1:$clamp, i32:$omod)),
1585 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
1586 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))])
1587 /* P.NumSrcArgs == 1 */,
1590 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1591 i1:$clamp, i32:$omod))))],
1592 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]))),
1593 P.NumSrcArgs, P.HasModifiers
1596 // Special case for v_div_fmas_{f32|f64}, since it seems to be the
1597 // only VOP instruction that implicitly reads VCC.
1598 multiclass VOP3_VCC_Inst <vop3 op, string opName,
1600 SDPatternOperator node = null_frag> : VOP3_Helper <
1602 (outs P.DstRC.RegClass:$dst),
1603 (ins InputModsNoDefault:$src0_modifiers, P.Src0RC64:$src0,
1604 InputModsNoDefault:$src1_modifiers, P.Src1RC64:$src1,
1605 InputModsNoDefault:$src2_modifiers, P.Src2RC64:$src2,
1608 " $dst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod",
1610 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
1611 i1:$clamp, i32:$omod)),
1612 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1613 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers)),
1618 multiclass VOP3b_Helper <vop op, RegisterClass vrc, RegisterOperand arc,
1619 string opName, list<dag> pattern> :
1621 op, (outs vrc:$vdst, SReg_64:$sdst),
1622 (ins InputModsNoDefault:$src0_modifiers, arc:$src0,
1623 InputModsNoDefault:$src1_modifiers, arc:$src1,
1624 InputModsNoDefault:$src2_modifiers, arc:$src2,
1625 ClampMod:$clamp, omod:$omod),
1626 opName#" $vdst, $sdst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod", pattern,
1627 opName, opName, 1, 1
1630 multiclass VOP3b_64 <vop3 op, string opName, list<dag> pattern> :
1631 VOP3b_Helper <op, VReg_64, VSrc_64, opName, pattern>;
1633 multiclass VOP3b_32 <vop3 op, string opName, list<dag> pattern> :
1634 VOP3b_Helper <op, VGPR_32, VSrc_32, opName, pattern>;
1637 class Vop3ModPat<Instruction Inst, VOPProfile P, SDPatternOperator node> : Pat<
1638 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),
1639 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
1640 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))),
1641 (Inst i32:$src0_modifiers, P.Src0VT:$src0,
1642 i32:$src1_modifiers, P.Src1VT:$src1,
1643 i32:$src2_modifiers, P.Src2VT:$src2,
1647 //===----------------------------------------------------------------------===//
1648 // Interpolation opcodes
1649 //===----------------------------------------------------------------------===//
1651 class VINTRP_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1652 VINTRPCommon <outs, ins, "", pattern>,
1653 SIMCInstr<opName, SISubtarget.NONE> {
1655 let isCodeGenOnly = 1;
1658 class VINTRP_Real_si <bits <2> op, string opName, dag outs, dag ins,
1660 VINTRPCommon <outs, ins, asm, []>,
1662 SIMCInstr<opName, SISubtarget.SI>;
1664 class VINTRP_Real_vi <bits <2> op, string opName, dag outs, dag ins,
1666 VINTRPCommon <outs, ins, asm, []>,
1668 SIMCInstr<opName, SISubtarget.VI>;
1670 multiclass VINTRP_m <bits <2> op, string opName, dag outs, dag ins, string asm,
1671 string disableEncoding = "", string constraints = "",
1672 list<dag> pattern = []> {
1673 let DisableEncoding = disableEncoding,
1674 Constraints = constraints in {
1675 def "" : VINTRP_Pseudo <opName, outs, ins, pattern>;
1677 def _si : VINTRP_Real_si <op, opName, outs, ins, asm>;
1679 def _vi : VINTRP_Real_vi <op, opName, outs, ins, asm>;
1683 //===----------------------------------------------------------------------===//
1684 // Vector I/O classes
1685 //===----------------------------------------------------------------------===//
1687 class DS_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1688 DS <outs, ins, "", pattern>,
1689 SIMCInstr <opName, SISubtarget.NONE> {
1691 let isCodeGenOnly = 1;
1694 class DS_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
1695 DS <outs, ins, asm, []>,
1697 SIMCInstr <opName, SISubtarget.SI> {
1698 let isCodeGenOnly = 0;
1701 class DS_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
1702 DS <outs, ins, asm, []>,
1704 SIMCInstr <opName, SISubtarget.VI>;
1706 class DS_Off16_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
1707 DS_Real_si <op,opName, outs, ins, asm> {
1709 // Single load interpret the 2 i8imm operands as a single i16 offset.
1711 let offset0 = offset{7-0};
1712 let offset1 = offset{15-8};
1713 let isCodeGenOnly = 0;
1716 class DS_Off16_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
1717 DS_Real_vi <op, opName, outs, ins, asm> {
1719 // Single load interpret the 2 i8imm operands as a single i16 offset.
1721 let offset0 = offset{7-0};
1722 let offset1 = offset{15-8};
1725 multiclass DS_1A_RET <bits<8> op, string opName, RegisterClass rc,
1726 dag outs = (outs rc:$vdst),
1727 dag ins = (ins VGPR_32:$addr, ds_offset:$offset, gds:$gds, M0Reg:$m0),
1728 string asm = opName#" $vdst, $addr"#"$offset$gds"> {
1730 def "" : DS_Pseudo <opName, outs, ins, []>;
1732 let data0 = 0, data1 = 0 in {
1733 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1734 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1738 multiclass DS_1A_Off8_RET <bits<8> op, string opName, RegisterClass rc,
1739 dag outs = (outs rc:$vdst),
1740 dag ins = (ins VGPR_32:$addr, ds_offset0:$offset0, ds_offset1:$offset1,
1741 gds01:$gds, M0Reg:$m0),
1742 string asm = opName#" $vdst, $addr"#"$offset0"#"$offset1$gds"> {
1744 def "" : DS_Pseudo <opName, outs, ins, []>;
1746 let data0 = 0, data1 = 0, AsmMatchConverter = "cvtDSOffset01" in {
1747 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1748 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1752 multiclass DS_1A1D_NORET <bits<8> op, string opName, RegisterClass rc,
1754 dag ins = (ins VGPR_32:$addr, rc:$data0, ds_offset:$offset, gds:$gds,
1756 string asm = opName#" $addr, $data0"#"$offset$gds"> {
1758 def "" : DS_Pseudo <opName, outs, ins, []>,
1759 AtomicNoRet<opName, 0>;
1761 let data1 = 0, vdst = 0 in {
1762 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1763 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1767 multiclass DS_1A1D_Off8_NORET <bits<8> op, string opName, RegisterClass rc,
1769 dag ins = (ins VGPR_32:$addr, rc:$data0, rc:$data1,
1770 ds_offset0:$offset0, ds_offset1:$offset1, gds01:$gds, M0Reg:$m0),
1771 string asm = opName#" $addr, $data0, $data1"#"$offset0"#"$offset1"#"$gds"> {
1773 def "" : DS_Pseudo <opName, outs, ins, []>;
1775 let vdst = 0, AsmMatchConverter = "cvtDSOffset01" in {
1776 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1777 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1781 multiclass DS_1A1D_RET <bits<8> op, string opName, RegisterClass rc,
1782 string noRetOp = "",
1783 dag outs = (outs rc:$vdst),
1784 dag ins = (ins VGPR_32:$addr, rc:$data0, ds_offset:$offset, gds:$gds,
1786 string asm = opName#" $vdst, $addr, $data0"#"$offset$gds"> {
1788 def "" : DS_Pseudo <opName, outs, ins, []>,
1789 AtomicNoRet<noRetOp, 1>;
1792 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1793 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1797 multiclass DS_1A2D_RET_m <bits<8> op, string opName, RegisterClass rc,
1798 string noRetOp = "", dag ins,
1799 dag outs = (outs rc:$vdst),
1800 string asm = opName#" $vdst, $addr, $data0, $data1"#"$offset"#"$gds"> {
1802 def "" : DS_Pseudo <opName, outs, ins, []>,
1803 AtomicNoRet<noRetOp, 1>;
1805 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1806 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1809 multiclass DS_1A2D_RET <bits<8> op, string asm, RegisterClass rc,
1810 string noRetOp = "", RegisterClass src = rc> :
1811 DS_1A2D_RET_m <op, asm, rc, noRetOp,
1812 (ins VGPR_32:$addr, src:$data0, src:$data1,
1813 ds_offset:$offset, gds:$gds, M0Reg:$m0)
1816 multiclass DS_1A2D_NORET <bits<8> op, string opName, RegisterClass rc,
1817 string noRetOp = opName,
1819 dag ins = (ins VGPR_32:$addr, rc:$data0, rc:$data1,
1820 ds_offset:$offset, gds:$gds, M0Reg:$m0),
1821 string asm = opName#" $addr, $data0, $data1"#"$offset"#"$gds"> {
1823 def "" : DS_Pseudo <opName, outs, ins, []>,
1824 AtomicNoRet<noRetOp, 0>;
1827 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1828 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1832 multiclass DS_0A_RET <bits<8> op, string opName,
1833 dag outs = (outs VGPR_32:$vdst),
1834 dag ins = (ins ds_offset:$offset, gds:$gds, M0Reg:$m0),
1835 string asm = opName#" $vdst"#"$offset"#"$gds"> {
1837 let mayLoad = 1, mayStore = 1 in {
1838 def "" : DS_Pseudo <opName, outs, ins, []>;
1840 let addr = 0, data0 = 0, data1 = 0 in {
1841 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1842 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1843 } // end addr = 0, data0 = 0, data1 = 0
1844 } // end mayLoad = 1, mayStore = 1
1847 multiclass DS_1A_RET_GDS <bits<8> op, string opName,
1848 dag outs = (outs VGPR_32:$vdst),
1849 dag ins = (ins VGPR_32:$addr, ds_offset_gds:$offset, M0Reg:$m0),
1850 string asm = opName#" $vdst, $addr"#"$offset gds"> {
1852 def "" : DS_Pseudo <opName, outs, ins, []>;
1854 let data0 = 0, data1 = 0, gds = 1 in {
1855 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1856 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1857 } // end data0 = 0, data1 = 0, gds = 1
1860 multiclass DS_1A_GDS <bits<8> op, string opName,
1862 dag ins = (ins VGPR_32:$addr, M0Reg:$m0),
1863 string asm = opName#" $addr gds"> {
1865 def "" : DS_Pseudo <opName, outs, ins, []>;
1867 let vdst = 0, data0 = 0, data1 = 0, offset0 = 0, offset1 = 0, gds = 1 in {
1868 def _si : DS_Real_si <op, opName, outs, ins, asm>;
1869 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
1870 } // end vdst = 0, data = 0, data1 = 0, gds = 1
1873 multiclass DS_1A <bits<8> op, string opName,
1875 dag ins = (ins VGPR_32:$addr, ds_offset:$offset, M0Reg:$m0, gds:$gds),
1876 string asm = opName#" $addr"#"$offset"#"$gds"> {
1878 let mayLoad = 1, mayStore = 1 in {
1879 def "" : DS_Pseudo <opName, outs, ins, []>;
1881 let vdst = 0, data0 = 0, data1 = 0 in {
1882 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
1883 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
1884 } // let vdst = 0, data0 = 0, data1 = 0
1885 } // end mayLoad = 1, mayStore = 1
1888 //===----------------------------------------------------------------------===//
1890 //===----------------------------------------------------------------------===//
1892 class MTBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1893 MTBUF <outs, ins, "", pattern>,
1894 SIMCInstr<opName, SISubtarget.NONE> {
1896 let isCodeGenOnly = 1;
1899 class MTBUF_Real_si <bits<3> op, string opName, dag outs, dag ins,
1901 MTBUF <outs, ins, asm, []>,
1903 SIMCInstr<opName, SISubtarget.SI>;
1905 class MTBUF_Real_vi <bits<4> op, string opName, dag outs, dag ins, string asm> :
1906 MTBUF <outs, ins, asm, []>,
1908 SIMCInstr <opName, SISubtarget.VI>;
1910 multiclass MTBUF_m <bits<3> op, string opName, dag outs, dag ins, string asm,
1911 list<dag> pattern> {
1913 def "" : MTBUF_Pseudo <opName, outs, ins, pattern>;
1915 def _si : MTBUF_Real_si <op, opName, outs, ins, asm>;
1917 def _vi : MTBUF_Real_vi <{0, op{2}, op{1}, op{0}}, opName, outs, ins, asm>;
1921 let mayStore = 1, mayLoad = 0 in {
1923 multiclass MTBUF_Store_Helper <bits<3> op, string opName,
1924 RegisterClass regClass> : MTBUF_m <
1926 (ins regClass:$vdata, u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
1927 i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr,
1928 SReg_128:$srsrc, i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
1929 opName#" $vdata, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1930 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
1933 } // mayStore = 1, mayLoad = 0
1935 let mayLoad = 1, mayStore = 0 in {
1937 multiclass MTBUF_Load_Helper <bits<3> op, string opName,
1938 RegisterClass regClass> : MTBUF_m <
1939 op, opName, (outs regClass:$dst),
1940 (ins u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
1941 i8imm:$dfmt, i8imm:$nfmt, VGPR_32:$vaddr, SReg_128:$srsrc,
1942 i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
1943 opName#" $dst, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
1944 #" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
1947 } // mayLoad = 1, mayStore = 0
1949 //===----------------------------------------------------------------------===//
1951 //===----------------------------------------------------------------------===//
1953 class mubuf <bits<7> si, bits<7> vi = si> {
1954 field bits<7> SI = si;
1955 field bits<7> VI = vi;
1958 let isCodeGenOnly = 0 in {
1960 class MUBUF_si <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
1961 MUBUF <outs, ins, asm, pattern>, MUBUFe <op> {
1965 } // End let isCodeGenOnly = 0
1967 class MUBUF_vi <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
1968 MUBUF <outs, ins, asm, pattern>, MUBUFe_vi <op> {
1972 class MUBUFAddr64Table <bit is_addr64, string suffix = ""> {
1973 bit IsAddr64 = is_addr64;
1974 string OpName = NAME # suffix;
1977 class MUBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1978 MUBUF <outs, ins, "", pattern>,
1979 SIMCInstr<opName, SISubtarget.NONE> {
1981 let isCodeGenOnly = 1;
1983 // dummy fields, so that we can use let statements around multiclasses
1993 class MUBUF_Real_si <mubuf op, string opName, dag outs, dag ins,
1995 MUBUF <outs, ins, asm, []>,
1997 SIMCInstr<opName, SISubtarget.SI> {
2001 class MUBUF_Real_vi <mubuf op, string opName, dag outs, dag ins,
2003 MUBUF <outs, ins, asm, []>,
2005 SIMCInstr<opName, SISubtarget.VI> {
2009 multiclass MUBUF_m <mubuf op, string opName, dag outs, dag ins, string asm,
2010 list<dag> pattern> {
2012 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
2013 MUBUFAddr64Table <0>;
2015 let addr64 = 0, isCodeGenOnly = 0 in {
2016 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
2019 def _vi : MUBUF_Real_vi <op, opName, outs, ins, asm>;
2022 multiclass MUBUFAddr64_m <mubuf op, string opName, dag outs,
2023 dag ins, string asm, list<dag> pattern> {
2025 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
2026 MUBUFAddr64Table <1>;
2028 let addr64 = 1, isCodeGenOnly = 0 in {
2029 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
2032 // There is no VI version. If the pseudo is selected, it should be lowered
2033 // for VI appropriately.
2036 multiclass MUBUFAtomicOffset_m <mubuf op, string opName, dag outs, dag ins,
2037 string asm, list<dag> pattern, bit is_return> {
2039 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
2040 MUBUFAddr64Table <0, !if(is_return, "_RTN", "")>,
2041 AtomicNoRet<NAME#"_OFFSET", is_return>;
2043 let offen = 0, idxen = 0, tfe = 0, vaddr = 0 in {
2045 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
2048 def _vi : MUBUF_Real_vi <op, opName, outs, ins, asm>;
2052 multiclass MUBUFAtomicAddr64_m <mubuf op, string opName, dag outs, dag ins,
2053 string asm, list<dag> pattern, bit is_return> {
2055 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
2056 MUBUFAddr64Table <1, !if(is_return, "_RTN", "")>,
2057 AtomicNoRet<NAME#"_ADDR64", is_return>;
2059 let offen = 0, idxen = 0, addr64 = 1, tfe = 0 in {
2060 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
2063 // There is no VI version. If the pseudo is selected, it should be lowered
2064 // for VI appropriately.
2067 multiclass MUBUF_Atomic <mubuf op, string name, RegisterClass rc,
2068 ValueType vt, SDPatternOperator atomic> {
2070 let mayStore = 1, mayLoad = 1, hasPostISelHook = 1 in {
2072 // No return variants
2075 defm _ADDR64 : MUBUFAtomicAddr64_m <
2076 op, name#"_addr64", (outs),
2077 (ins rc:$vdata, SReg_128:$srsrc, VReg_64:$vaddr,
2078 SCSrc_32:$soffset, mbuf_offset:$offset, slc:$slc),
2079 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#"$slc", [], 0
2082 defm _OFFSET : MUBUFAtomicOffset_m <
2083 op, name#"_offset", (outs),
2084 (ins rc:$vdata, SReg_128:$srsrc, SCSrc_32:$soffset, mbuf_offset:$offset,
2086 name#" $vdata, $srsrc, $soffset"#"$offset"#"$slc", [], 0
2090 // Variant that return values
2091 let glc = 1, Constraints = "$vdata = $vdata_in",
2092 DisableEncoding = "$vdata_in" in {
2094 defm _RTN_ADDR64 : MUBUFAtomicAddr64_m <
2095 op, name#"_rtn_addr64", (outs rc:$vdata),
2096 (ins rc:$vdata_in, SReg_128:$srsrc, VReg_64:$vaddr,
2097 SCSrc_32:$soffset, mbuf_offset:$offset, slc:$slc),
2098 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#" glc"#"$slc",
2100 (atomic (MUBUFAddr64Atomic v4i32:$srsrc, i64:$vaddr, i32:$soffset,
2101 i16:$offset, i1:$slc), vt:$vdata_in))], 1
2104 defm _RTN_OFFSET : MUBUFAtomicOffset_m <
2105 op, name#"_rtn_offset", (outs rc:$vdata),
2106 (ins rc:$vdata_in, SReg_128:$srsrc, SCSrc_32:$soffset,
2107 mbuf_offset:$offset, slc:$slc),
2108 name#" $vdata, $srsrc, $soffset"#"$offset"#" glc $slc",
2110 (atomic (MUBUFOffsetAtomic v4i32:$srsrc, i32:$soffset, i16:$offset,
2111 i1:$slc), vt:$vdata_in))], 1
2116 } // mayStore = 1, mayLoad = 1, hasPostISelHook = 1
2119 multiclass MUBUF_Load_Helper <mubuf op, string name, RegisterClass regClass,
2120 ValueType load_vt = i32,
2121 SDPatternOperator ld = null_frag> {
2123 let mayLoad = 1, mayStore = 0 in {
2124 let offen = 0, idxen = 0, vaddr = 0 in {
2125 defm _OFFSET : MUBUF_m <op, name#"_offset", (outs regClass:$vdata),
2126 (ins SReg_128:$srsrc, SCSrc_32:$soffset,
2127 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
2128 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
2129 [(set load_vt:$vdata, (ld (MUBUFOffset v4i32:$srsrc,
2130 i32:$soffset, i16:$offset,
2131 i1:$glc, i1:$slc, i1:$tfe)))]>;
2134 let offen = 1, idxen = 0 in {
2135 defm _OFFEN : MUBUF_m <op, name#"_offen", (outs regClass:$vdata),
2136 (ins VGPR_32:$vaddr, SReg_128:$srsrc,
2137 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, slc:$slc,
2139 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2142 let offen = 0, idxen = 1 in {
2143 defm _IDXEN : MUBUF_m <op, name#"_idxen", (outs regClass:$vdata),
2144 (ins VGPR_32:$vaddr, SReg_128:$srsrc,
2145 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc,
2146 slc:$slc, tfe:$tfe),
2147 name#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2150 let offen = 1, idxen = 1 in {
2151 defm _BOTHEN : MUBUF_m <op, name#"_bothen", (outs regClass:$vdata),
2152 (ins VReg_64:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset,
2153 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
2154 name#" $vdata, $vaddr, $srsrc, $soffset idxen offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2157 let offen = 0, idxen = 0 in {
2158 defm _ADDR64 : MUBUFAddr64_m <op, name#"_addr64", (outs regClass:$vdata),
2159 (ins VReg_64:$vaddr, SReg_128:$srsrc,
2160 SCSrc_32:$soffset, mbuf_offset:$offset,
2161 glc:$glc, slc:$slc, tfe:$tfe),
2162 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#
2163 "$glc"#"$slc"#"$tfe",
2164 [(set load_vt:$vdata, (ld (MUBUFAddr64 v4i32:$srsrc,
2165 i64:$vaddr, i32:$soffset,
2166 i16:$offset, i1:$glc, i1:$slc,
2172 multiclass MUBUF_Store_Helper <mubuf op, string name, RegisterClass vdataClass,
2173 ValueType store_vt = i32, SDPatternOperator st = null_frag> {
2174 let mayLoad = 0, mayStore = 1 in {
2175 defm : MUBUF_m <op, name, (outs),
2176 (ins vdataClass:$vdata, VGPR_32:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset,
2177 mbuf_offset:$offset, offen:$offen, idxen:$idxen, glc:$glc, slc:$slc,
2179 name#" $vdata, $vaddr, $srsrc, $soffset"#"$offen"#"$idxen"#"$offset"#
2180 "$glc"#"$slc"#"$tfe", []>;
2182 let offen = 0, idxen = 0, vaddr = 0 in {
2183 defm _OFFSET : MUBUF_m <op, name#"_offset",(outs),
2184 (ins vdataClass:$vdata, SReg_128:$srsrc, SCSrc_32:$soffset,
2185 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
2186 name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
2187 [(st store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset,
2188 i16:$offset, i1:$glc, i1:$slc, i1:$tfe))]>;
2189 } // offen = 0, idxen = 0, vaddr = 0
2191 let offen = 1, idxen = 0 in {
2192 defm _OFFEN : MUBUF_m <op, name#"_offen", (outs),
2193 (ins vdataClass:$vdata, VGPR_32:$vaddr, SReg_128:$srsrc,
2194 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc,
2195 slc:$slc, tfe:$tfe),
2196 name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#
2197 "$glc"#"$slc"#"$tfe", []>;
2198 } // end offen = 1, idxen = 0
2200 let offen = 0, idxen = 1 in {
2201 defm _IDXEN : MUBUF_m <op, name#"_idxen", (outs),
2202 (ins vdataClass:$vdata, VGPR_32:$vaddr, SReg_128:$srsrc,
2203 SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc,
2204 slc:$slc, tfe:$tfe),
2205 name#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2208 let offen = 1, idxen = 1 in {
2209 defm _BOTHEN : MUBUF_m <op, name#"_bothen", (outs),
2210 (ins vdataClass:$vdata, VReg_64:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset,
2211 mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
2212 name#" $vdata, $vaddr, $srsrc, $soffset idxen offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2215 let offen = 0, idxen = 0 in {
2216 defm _ADDR64 : MUBUFAddr64_m <op, name#"_addr64", (outs),
2217 (ins vdataClass:$vdata, VReg_64:$vaddr, SReg_128:$srsrc,
2219 mbuf_offset:$offset, glc:$glc, slc:$slc,
2221 name#" $vdata, $vaddr, $srsrc, $soffset addr64"#
2222 "$offset"#"$glc"#"$slc"#"$tfe",
2223 [(st store_vt:$vdata,
2224 (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr,
2225 i32:$soffset, i16:$offset,
2226 i1:$glc, i1:$slc, i1:$tfe))]>;
2228 } // End mayLoad = 0, mayStore = 1
2231 class FLAT_Load_Helper <bits<7> op, string asm, RegisterClass regClass> :
2232 FLAT <op, (outs regClass:$vdst),
2233 (ins VReg_64:$addr),
2234 asm#" $vdst, $addr, [M0, FLAT_SCRATCH]", []> {
2242 class FLAT_Store_Helper <bits<7> op, string name, RegisterClass vdataClass> :
2243 FLAT <op, (outs), (ins vdataClass:$data, VReg_64:$addr),
2244 name#" $data, $addr, [M0, FLAT_SCRATCH]",
2257 class MIMG_Mask <string op, int channels> {
2259 int Channels = channels;
2262 class MIMG_NoSampler_Helper <bits<7> op, string asm,
2263 RegisterClass dst_rc,
2264 RegisterClass src_rc> : MIMG <
2266 (outs dst_rc:$vdata),
2267 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
2268 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
2270 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2271 #" $tfe, $lwe, $slc, $vaddr, $srsrc",
2276 let hasPostISelHook = 1;
2279 multiclass MIMG_NoSampler_Src_Helper <bits<7> op, string asm,
2280 RegisterClass dst_rc,
2282 def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPR_32>,
2283 MIMG_Mask<asm#"_V1", channels>;
2284 def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>,
2285 MIMG_Mask<asm#"_V2", channels>;
2286 def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>,
2287 MIMG_Mask<asm#"_V4", channels>;
2290 multiclass MIMG_NoSampler <bits<7> op, string asm> {
2291 defm _V1 : MIMG_NoSampler_Src_Helper <op, asm, VGPR_32, 1>;
2292 defm _V2 : MIMG_NoSampler_Src_Helper <op, asm, VReg_64, 2>;
2293 defm _V3 : MIMG_NoSampler_Src_Helper <op, asm, VReg_96, 3>;
2294 defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 4>;
2297 class MIMG_Sampler_Helper <bits<7> op, string asm,
2298 RegisterClass dst_rc,
2299 RegisterClass src_rc, int wqm> : MIMG <
2301 (outs dst_rc:$vdata),
2302 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
2303 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
2304 SReg_256:$srsrc, SReg_128:$ssamp),
2305 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2306 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
2310 let hasPostISelHook = 1;
2314 multiclass MIMG_Sampler_Src_Helper <bits<7> op, string asm,
2315 RegisterClass dst_rc,
2316 int channels, int wqm> {
2317 def _V1 : MIMG_Sampler_Helper <op, asm, dst_rc, VGPR_32, wqm>,
2318 MIMG_Mask<asm#"_V1", channels>;
2319 def _V2 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_64, wqm>,
2320 MIMG_Mask<asm#"_V2", channels>;
2321 def _V4 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_128, wqm>,
2322 MIMG_Mask<asm#"_V4", channels>;
2323 def _V8 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_256, wqm>,
2324 MIMG_Mask<asm#"_V8", channels>;
2325 def _V16 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_512, wqm>,
2326 MIMG_Mask<asm#"_V16", channels>;
2329 multiclass MIMG_Sampler <bits<7> op, string asm> {
2330 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, 0>;
2331 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2, 0>;
2332 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3, 0>;
2333 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4, 0>;
2336 multiclass MIMG_Sampler_WQM <bits<7> op, string asm> {
2337 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, 1>;
2338 defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2, 1>;
2339 defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3, 1>;
2340 defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4, 1>;
2343 class MIMG_Gather_Helper <bits<7> op, string asm,
2344 RegisterClass dst_rc,
2345 RegisterClass src_rc, int wqm> : MIMG <
2347 (outs dst_rc:$vdata),
2348 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
2349 i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
2350 SReg_256:$srsrc, SReg_128:$ssamp),
2351 asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2352 #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
2357 // DMASK was repurposed for GATHER4. 4 components are always
2358 // returned and DMASK works like a swizzle - it selects
2359 // the component to fetch. The only useful DMASK values are
2360 // 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
2361 // (red,red,red,red) etc.) The ISA document doesn't mention
2363 // Therefore, disable all code which updates DMASK by setting these two:
2365 let hasPostISelHook = 0;
2369 multiclass MIMG_Gather_Src_Helper <bits<7> op, string asm,
2370 RegisterClass dst_rc,
2371 int channels, int wqm> {
2372 def _V1 : MIMG_Gather_Helper <op, asm, dst_rc, VGPR_32, wqm>,
2373 MIMG_Mask<asm#"_V1", channels>;
2374 def _V2 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_64, wqm>,
2375 MIMG_Mask<asm#"_V2", channels>;
2376 def _V4 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_128, wqm>,
2377 MIMG_Mask<asm#"_V4", channels>;
2378 def _V8 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_256, wqm>,
2379 MIMG_Mask<asm#"_V8", channels>;
2380 def _V16 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_512, wqm>,
2381 MIMG_Mask<asm#"_V16", channels>;
2384 multiclass MIMG_Gather <bits<7> op, string asm> {
2385 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1, 0>;
2386 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2, 0>;
2387 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3, 0>;
2388 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4, 0>;
2391 multiclass MIMG_Gather_WQM <bits<7> op, string asm> {
2392 defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1, 1>;
2393 defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2, 1>;
2394 defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3, 1>;
2395 defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4, 1>;
2398 //===----------------------------------------------------------------------===//
2399 // Vector instruction mappings
2400 //===----------------------------------------------------------------------===//
2402 // Maps an opcode in e32 form to its e64 equivalent
2403 def getVOPe64 : InstrMapping {
2404 let FilterClass = "VOP";
2405 let RowFields = ["OpName"];
2406 let ColFields = ["Size"];
2408 let ValueCols = [["8"]];
2411 // Maps an opcode in e64 form to its e32 equivalent
2412 def getVOPe32 : InstrMapping {
2413 let FilterClass = "VOP";
2414 let RowFields = ["OpName"];
2415 let ColFields = ["Size"];
2417 let ValueCols = [["4"]];
2420 def getMaskedMIMGOp : InstrMapping {
2421 let FilterClass = "MIMG_Mask";
2422 let RowFields = ["Op"];
2423 let ColFields = ["Channels"];
2425 let ValueCols = [["1"], ["2"], ["3"] ];
2428 // Maps an commuted opcode to its original version
2429 def getCommuteOrig : InstrMapping {
2430 let FilterClass = "VOP2_REV";
2431 let RowFields = ["RevOp"];
2432 let ColFields = ["IsOrig"];
2434 let ValueCols = [["1"]];
2437 // Maps an original opcode to its commuted version
2438 def getCommuteRev : InstrMapping {
2439 let FilterClass = "VOP2_REV";
2440 let RowFields = ["RevOp"];
2441 let ColFields = ["IsOrig"];
2443 let ValueCols = [["0"]];
2446 def getCommuteCmpOrig : InstrMapping {
2447 let FilterClass = "VOP2_REV";
2448 let RowFields = ["RevOp"];
2449 let ColFields = ["IsOrig"];
2451 let ValueCols = [["1"]];
2454 // Maps an original opcode to its commuted version
2455 def getCommuteCmpRev : InstrMapping {
2456 let FilterClass = "VOP2_REV";
2457 let RowFields = ["RevOp"];
2458 let ColFields = ["IsOrig"];
2460 let ValueCols = [["0"]];
2464 def getMCOpcodeGen : InstrMapping {
2465 let FilterClass = "SIMCInstr";
2466 let RowFields = ["PseudoInstr"];
2467 let ColFields = ["Subtarget"];
2468 let KeyCol = [!cast<string>(SISubtarget.NONE)];
2469 let ValueCols = [[!cast<string>(SISubtarget.SI)],[!cast<string>(SISubtarget.VI)]];
2472 def getAddr64Inst : InstrMapping {
2473 let FilterClass = "MUBUFAddr64Table";
2474 let RowFields = ["OpName"];
2475 let ColFields = ["IsAddr64"];
2477 let ValueCols = [["1"]];
2480 // Maps an atomic opcode to its version with a return value.
2481 def getAtomicRetOp : InstrMapping {
2482 let FilterClass = "AtomicNoRet";
2483 let RowFields = ["NoRetOp"];
2484 let ColFields = ["IsRet"];
2486 let ValueCols = [["1"]];
2489 // Maps an atomic opcode to its returnless version.
2490 def getAtomicNoRetOp : InstrMapping {
2491 let FilterClass = "AtomicNoRet";
2492 let RowFields = ["NoRetOp"];
2493 let ColFields = ["IsRet"];
2495 let ValueCols = [["0"]];
2498 include "SIInstructions.td"
2499 include "CIInstructions.td"
2500 include "VIInstructions.td"