1 //===-- SIInstrInfo.h - SI Instruction Info Interface -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Interface definition for SIInstrInfo.
13 //===----------------------------------------------------------------------===//
19 #include "AMDGPUInstrInfo.h"
20 #include "SIRegisterInfo.h"
24 class SIInstrInfo : public AMDGPUInstrInfo {
26 const SIRegisterInfo RI;
29 explicit SIInstrInfo(AMDGPUTargetMachine &tm);
31 const SIRegisterInfo &getRegisterInfo() const {
35 virtual void copyPhysReg(MachineBasicBlock &MBB,
36 MachineBasicBlock::iterator MI, DebugLoc DL,
37 unsigned DestReg, unsigned SrcReg,
40 void storeRegToStackSlot(MachineBasicBlock &MBB,
41 MachineBasicBlock::iterator MI,
42 unsigned SrcReg, bool isKill, int FrameIndex,
43 const TargetRegisterClass *RC,
44 const TargetRegisterInfo *TRI) const;
46 void loadRegFromStackSlot(MachineBasicBlock &MBB,
47 MachineBasicBlock::iterator MI,
48 unsigned DestReg, int FrameIndex,
49 const TargetRegisterClass *RC,
50 const TargetRegisterInfo *TRI) const;
52 unsigned commuteOpcode(unsigned Opcode) const;
54 virtual MachineInstr *commuteInstruction(MachineInstr *MI,
55 bool NewMI=false) const;
57 virtual unsigned getIEQOpcode() const {
58 llvm_unreachable("Unimplemented");
61 MachineInstr *buildMovInstr(MachineBasicBlock *MBB,
62 MachineBasicBlock::iterator I,
63 unsigned DstReg, unsigned SrcReg) const;
64 virtual bool isMov(unsigned Opcode) const;
66 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
67 bool isDS(uint16_t Opcode) const;
68 int isMIMG(uint16_t Opcode) const;
69 int isSMRD(uint16_t Opcode) const;
70 bool isVOP1(uint16_t Opcode) const;
71 bool isVOP2(uint16_t Opcode) const;
72 bool isVOP3(uint16_t Opcode) const;
73 bool isVOPC(uint16_t Opcode) const;
74 bool isInlineConstant(const MachineOperand &MO) const;
75 bool isLiteralConstant(const MachineOperand &MO) const;
77 virtual bool verifyInstruction(const MachineInstr *MI,
78 StringRef &ErrInfo) const;
80 bool isSALUInstr(const MachineInstr &MI) const;
81 static unsigned getVALUOp(const MachineInstr &MI);
82 bool isSALUOpSupportedOnVALU(const MachineInstr &MI) const;
84 /// \brief Return the correct register class for \p OpNo. For target-specific
85 /// instructions, this will return the register class that has been defined
86 /// in tablegen. For generic instructions, like REG_SEQUENCE it will return
87 /// the register class of its machine operand.
88 /// to infer the correct register class base on the other operands.
89 const TargetRegisterClass *getOpRegClass(const MachineInstr &MI,
90 unsigned OpNo) const;\
92 /// \returns true if it is legal for the operand at index \p OpNo
94 bool canReadVGPR(const MachineInstr &MI, unsigned OpNo) const;
96 /// \brief Legalize the \p OpIndex operand of this instruction by inserting
97 /// a MOV. For example:
98 /// ADD_I32_e32 VGPR0, 15
101 /// ADD_I32_e32 VGPR0, VGPR1
103 /// If the operand being legalized is a register, then a COPY will be used
105 void legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const;
107 /// \brief Legalize all operands in this instruction. This function may
108 /// create new instruction and insert them before \p MI.
109 void legalizeOperands(MachineInstr *MI) const;
111 /// \brief Replace this instruction's opcode with the equivalent VALU
112 /// opcode. This function will also move the users of \p MI to the
113 /// VALU if necessary.
114 void moveToVALU(MachineInstr &MI) const;
116 virtual unsigned calculateIndirectAddress(unsigned RegIndex,
117 unsigned Channel) const;
119 virtual const TargetRegisterClass *getIndirectAddrRegClass() const;
121 virtual MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
122 MachineBasicBlock::iterator I,
125 unsigned OffsetReg) const;
127 virtual MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
128 MachineBasicBlock::iterator I,
131 unsigned OffsetReg) const;
132 void reserveIndirectRegisters(BitVector &Reserved,
133 const MachineFunction &MF) const;
135 void LoadM0(MachineInstr *MoveRel, MachineBasicBlock::iterator I,
136 unsigned SavReg, unsigned IndexReg) const;
141 int getVOPe64(uint16_t Opcode);
142 int getCommuteRev(uint16_t Opcode);
143 int getCommuteOrig(uint16_t Opcode);
145 } // End namespace AMDGPU
147 } // End namespace llvm
149 namespace SIInstrFlags {
151 // First 4 bits are the instruction encoding
158 #endif //SIINSTRINFO_H