1 //===-- SIInstrInfo.h - SI Instruction Info Interface -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Interface definition for SIInstrInfo.
13 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_LIB_TARGET_R600_SIINSTRINFO_H
17 #define LLVM_LIB_TARGET_R600_SIINSTRINFO_H
19 #include "AMDGPUInstrInfo.h"
20 #include "SIDefines.h"
21 #include "SIRegisterInfo.h"
25 class SIInstrInfo : public AMDGPUInstrInfo {
27 const SIRegisterInfo RI;
29 unsigned buildExtractSubReg(MachineBasicBlock::iterator MI,
30 MachineRegisterInfo &MRI,
31 MachineOperand &SuperReg,
32 const TargetRegisterClass *SuperRC,
34 const TargetRegisterClass *SubRC) const;
35 MachineOperand buildExtractSubRegOrImm(MachineBasicBlock::iterator MI,
36 MachineRegisterInfo &MRI,
37 MachineOperand &SuperReg,
38 const TargetRegisterClass *SuperRC,
40 const TargetRegisterClass *SubRC) const;
42 unsigned split64BitImm(SmallVectorImpl<MachineInstr *> &Worklist,
43 MachineBasicBlock::iterator MI,
44 MachineRegisterInfo &MRI,
45 const TargetRegisterClass *RC,
46 const MachineOperand &Op) const;
48 void swapOperands(MachineBasicBlock::iterator Inst) const;
50 void splitScalar64BitUnaryOp(SmallVectorImpl<MachineInstr *> &Worklist,
51 MachineInstr *Inst, unsigned Opcode) const;
53 void splitScalar64BitBinaryOp(SmallVectorImpl<MachineInstr *> &Worklist,
54 MachineInstr *Inst, unsigned Opcode) const;
56 void splitScalar64BitBCNT(SmallVectorImpl<MachineInstr *> &Worklist,
57 MachineInstr *Inst) const;
58 void splitScalar64BitBFE(SmallVectorImpl<MachineInstr *> &Worklist,
59 MachineInstr *Inst) const;
61 void addDescImplicitUseDef(const MCInstrDesc &Desc, MachineInstr *MI) const;
63 bool checkInstOffsetsDoNotOverlap(MachineInstr *MIa,
64 MachineInstr *MIb) const;
66 unsigned findUsedSGPR(const MachineInstr *MI, int OpIndices[3]) const;
69 explicit SIInstrInfo(const AMDGPUSubtarget &st);
71 const SIRegisterInfo &getRegisterInfo() const override {
75 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
77 int64_t &Offset2) const override;
79 bool getLdStBaseRegImmOfs(MachineInstr *LdSt,
80 unsigned &BaseReg, unsigned &Offset,
81 const TargetRegisterInfo *TRI) const final;
83 bool shouldClusterLoads(MachineInstr *FirstLdSt,
84 MachineInstr *SecondLdSt,
85 unsigned NumLoads) const final;
87 void copyPhysReg(MachineBasicBlock &MBB,
88 MachineBasicBlock::iterator MI, DebugLoc DL,
89 unsigned DestReg, unsigned SrcReg,
90 bool KillSrc) const override;
92 unsigned calculateLDSSpillAddress(MachineBasicBlock &MBB,
93 MachineBasicBlock::iterator MI,
99 void storeRegToStackSlot(MachineBasicBlock &MBB,
100 MachineBasicBlock::iterator MI,
101 unsigned SrcReg, bool isKill, int FrameIndex,
102 const TargetRegisterClass *RC,
103 const TargetRegisterInfo *TRI) const override;
105 void loadRegFromStackSlot(MachineBasicBlock &MBB,
106 MachineBasicBlock::iterator MI,
107 unsigned DestReg, int FrameIndex,
108 const TargetRegisterClass *RC,
109 const TargetRegisterInfo *TRI) const override;
111 bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
113 unsigned commuteOpcode(unsigned Opcode) const;
115 MachineInstr *commuteInstruction(MachineInstr *MI,
116 bool NewMI = false) const override;
117 bool findCommutedOpIndices(MachineInstr *MI,
119 unsigned &SrcOpIdx2) const override;
121 bool isTriviallyReMaterializable(const MachineInstr *MI,
122 AliasAnalysis *AA = nullptr) const;
124 bool areMemAccessesTriviallyDisjoint(
125 MachineInstr *MIa, MachineInstr *MIb,
126 AliasAnalysis *AA = nullptr) const override;
128 MachineInstr *buildMovInstr(MachineBasicBlock *MBB,
129 MachineBasicBlock::iterator I,
130 unsigned DstReg, unsigned SrcReg) const override;
131 bool isMov(unsigned Opcode) const override;
133 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override;
135 bool isSALU(uint16_t Opcode) const {
136 return get(Opcode).TSFlags & SIInstrFlags::SALU;
139 bool isVALU(uint16_t Opcode) const {
140 return get(Opcode).TSFlags & SIInstrFlags::VALU;
143 bool isSOP1(uint16_t Opcode) const {
144 return get(Opcode).TSFlags & SIInstrFlags::SOP1;
147 bool isSOP2(uint16_t Opcode) const {
148 return get(Opcode).TSFlags & SIInstrFlags::SOP2;
151 bool isSOPC(uint16_t Opcode) const {
152 return get(Opcode).TSFlags & SIInstrFlags::SOPC;
155 bool isSOPK(uint16_t Opcode) const {
156 return get(Opcode).TSFlags & SIInstrFlags::SOPK;
159 bool isSOPP(uint16_t Opcode) const {
160 return get(Opcode).TSFlags & SIInstrFlags::SOPP;
163 bool isVOP1(uint16_t Opcode) const {
164 return get(Opcode).TSFlags & SIInstrFlags::VOP1;
167 bool isVOP2(uint16_t Opcode) const {
168 return get(Opcode).TSFlags & SIInstrFlags::VOP2;
171 bool isVOP3(uint16_t Opcode) const {
172 return get(Opcode).TSFlags & SIInstrFlags::VOP3;
175 bool isVOPC(uint16_t Opcode) const {
176 return get(Opcode).TSFlags & SIInstrFlags::VOPC;
179 bool isMUBUF(uint16_t Opcode) const {
180 return get(Opcode).TSFlags & SIInstrFlags::MUBUF;
183 bool isMTBUF(uint16_t Opcode) const {
184 return get(Opcode).TSFlags & SIInstrFlags::MTBUF;
187 bool isSMRD(uint16_t Opcode) const {
188 return get(Opcode).TSFlags & SIInstrFlags::SMRD;
191 bool isDS(uint16_t Opcode) const {
192 return get(Opcode).TSFlags & SIInstrFlags::DS;
195 bool isMIMG(uint16_t Opcode) const {
196 return get(Opcode).TSFlags & SIInstrFlags::MIMG;
199 bool isFLAT(uint16_t Opcode) const {
200 return get(Opcode).TSFlags & SIInstrFlags::FLAT;
203 bool isInlineConstant(const APInt &Imm) const;
204 bool isInlineConstant(const MachineOperand &MO) const;
205 bool isLiteralConstant(const MachineOperand &MO) const;
207 bool isImmOperandLegal(const MachineInstr *MI, unsigned OpNo,
208 const MachineOperand &MO) const;
210 /// \brief Return true if the given offset Size in bytes can be folded into
211 /// the immediate offsets of a memory instruction for the given address space.
212 bool canFoldOffset(unsigned OffsetSize, unsigned AS) const;
214 /// \brief Return true if this 64-bit VALU instruction has a 32-bit encoding.
215 /// This function will return false if you pass it a 32-bit instruction.
216 bool hasVALU32BitEncoding(unsigned Opcode) const;
218 /// \brief Returns true if this operand uses the constant bus.
219 bool usesConstantBus(const MachineRegisterInfo &MRI,
220 const MachineOperand &MO) const;
222 /// \brief Return true if this instruction has any modifiers.
223 /// e.g. src[012]_mod, omod, clamp.
224 bool hasModifiers(unsigned Opcode) const;
226 bool hasModifiersSet(const MachineInstr &MI,
227 unsigned OpName) const;
229 bool verifyInstruction(const MachineInstr *MI,
230 StringRef &ErrInfo) const override;
232 static unsigned getVALUOp(const MachineInstr &MI);
234 bool isSALUOpSupportedOnVALU(const MachineInstr &MI) const;
236 /// \brief Return the correct register class for \p OpNo. For target-specific
237 /// instructions, this will return the register class that has been defined
238 /// in tablegen. For generic instructions, like REG_SEQUENCE it will return
239 /// the register class of its machine operand.
240 /// to infer the correct register class base on the other operands.
241 const TargetRegisterClass *getOpRegClass(const MachineInstr &MI,
242 unsigned OpNo) const;\
244 /// \returns true if it is legal for the operand at index \p OpNo
246 bool canReadVGPR(const MachineInstr &MI, unsigned OpNo) const;
248 /// \brief Legalize the \p OpIndex operand of this instruction by inserting
249 /// a MOV. For example:
250 /// ADD_I32_e32 VGPR0, 15
253 /// ADD_I32_e32 VGPR0, VGPR1
255 /// If the operand being legalized is a register, then a COPY will be used
257 void legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const;
259 /// \brief Check if \p MO is a legal operand if it was the \p OpIdx Operand
261 bool isOperandLegal(const MachineInstr *MI, unsigned OpIdx,
262 const MachineOperand *MO = nullptr) const;
264 /// \brief Legalize all operands in this instruction. This function may
265 /// create new instruction and insert them before \p MI.
266 void legalizeOperands(MachineInstr *MI) const;
268 /// \brief Split an SMRD instruction into two smaller loads of half the
269 // size storing the results in \p Lo and \p Hi.
270 void splitSMRD(MachineInstr *MI, const TargetRegisterClass *HalfRC,
271 unsigned HalfImmOp, unsigned HalfSGPROp,
272 MachineInstr *&Lo, MachineInstr *&Hi) const;
274 void moveSMRDToVALU(MachineInstr *MI, MachineRegisterInfo &MRI) const;
276 /// \brief Replace this instruction's opcode with the equivalent VALU
277 /// opcode. This function will also move the users of \p MI to the
278 /// VALU if necessary.
279 void moveToVALU(MachineInstr &MI) const;
281 unsigned calculateIndirectAddress(unsigned RegIndex,
282 unsigned Channel) const override;
284 const TargetRegisterClass *getIndirectAddrRegClass() const override;
286 MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
287 MachineBasicBlock::iterator I,
290 unsigned OffsetReg) const override;
292 MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
293 MachineBasicBlock::iterator I,
296 unsigned OffsetReg) const override;
297 void reserveIndirectRegisters(BitVector &Reserved,
298 const MachineFunction &MF) const;
300 void LoadM0(MachineInstr *MoveRel, MachineBasicBlock::iterator I,
301 unsigned SavReg, unsigned IndexReg) const;
303 void insertNOPs(MachineBasicBlock::iterator MI, int Count) const;
305 /// \brief Returns the operand named \p Op. If \p MI does not have an
306 /// operand named \c Op, this function returns nullptr.
307 MachineOperand *getNamedOperand(MachineInstr &MI, unsigned OperandName) const;
309 const MachineOperand *getNamedOperand(const MachineInstr &MI,
310 unsigned OpName) const {
311 return getNamedOperand(const_cast<MachineInstr &>(MI), OpName);
314 uint64_t getDefaultRsrcDataFormat() const;
320 int getVOPe64(uint16_t Opcode);
321 int getVOPe32(uint16_t Opcode);
322 int getCommuteRev(uint16_t Opcode);
323 int getCommuteOrig(uint16_t Opcode);
324 int getMCOpcode(uint16_t Opcode, unsigned Gen);
325 int getAddr64Inst(uint16_t Opcode);
326 int getAtomicRetOp(uint16_t Opcode);
327 int getAtomicNoRetOp(uint16_t Opcode);
329 const uint64_t RSRC_DATA_FORMAT = 0xf00000000000LL;
330 const uint64_t RSRC_TID_ENABLE = 1LL << 55;
332 } // End namespace AMDGPU
335 namespace KernelInputOffsets {
337 /// Offsets in bytes from the start of the input buffer
350 } // End namespace KernelInputOffsets
351 } // End namespace SI
353 } // End namespace llvm