lib/Target/R600/SIInstrInfo.cpp

   1 //===-- SIInstrInfo.cpp - SI Instruction Information  ---------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 /// \file
  11 /// \brief SI Implementation of TargetInstrInfo.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15
  16 #include "SIInstrInfo.h"
  17 #include "AMDGPUTargetMachine.h"
  18 #include "llvm/CodeGen/MachineInstrBuilder.h"
  19 #include "llvm/CodeGen/MachineRegisterInfo.h"
  20 #include "llvm/MC/MCInstrDesc.h"
  21 #include <stdio.h>
  22
  23 using namespace llvm;
  24
  25 SIInstrInfo::SIInstrInfo(AMDGPUTargetMachine &tm)
  26   : AMDGPUInstrInfo(tm),
  27     RI(tm, *this)
  28     { }
  29
  30 const SIRegisterInfo &SIInstrInfo::getRegisterInfo() const {
  31   return RI;
  32 }
  33
  34 void
  35 SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
  36                            MachineBasicBlock::iterator MI, DebugLoc DL,
  37                            unsigned DestReg, unsigned SrcReg,
  38                            bool KillSrc) const {
  39   // If we are trying to copy to or from SCC, there is a bug somewhere else in
  40   // the backend.  While it may be theoretically possible to do this, it should
  41   // never be necessary.
  42   assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC);
  43
  44   if (AMDGPU::SReg_64RegClass.contains(DestReg)) {
  45     assert(AMDGPU::SReg_64RegClass.contains(SrcReg));
  46     BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg)
  47             .addReg(SrcReg, getKillRegState(KillSrc));
  48   } else if (AMDGPU::VReg_32RegClass.contains(DestReg)) {
  49     assert(AMDGPU::VReg_32RegClass.contains(SrcReg) ||
  50            AMDGPU::SReg_32RegClass.contains(SrcReg));
  51     BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
  52             .addReg(SrcReg, getKillRegState(KillSrc));
  53   } else {
  54     assert(AMDGPU::SReg_32RegClass.contains(DestReg));
  55     assert(AMDGPU::SReg_32RegClass.contains(SrcReg));
  56     BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)
  57             .addReg(SrcReg, getKillRegState(KillSrc));
  58   }
  59 }
  60
  61 MachineInstr * SIInstrInfo::getMovImmInstr(MachineFunction *MF, unsigned DstReg,
  62                                            int64_t Imm) const {
  63   MachineInstr * MI = MF->CreateMachineInstr(get(AMDGPU::V_MOV_IMM_I32), DebugLoc());
  64   MachineInstrBuilder MIB(*MF, MI);
  65   MIB.addReg(DstReg, RegState::Define);
  66   MIB.addImm(Imm);
  67
  68   return MI;
  69
  70 }
  71
  72 bool SIInstrInfo::isMov(unsigned Opcode) const {
  73   switch(Opcode) {
  74   default: return false;
  75   case AMDGPU::S_MOV_B32:
  76   case AMDGPU::S_MOV_B64:
  77   case AMDGPU::V_MOV_B32_e32:
  78   case AMDGPU::V_MOV_B32_e64:
  79   case AMDGPU::V_MOV_IMM_F32:
  80   case AMDGPU::V_MOV_IMM_I32:
  81   case AMDGPU::S_MOV_IMM_I32:
  82     return true;
  83   }
  84 }
  85
  86 bool
  87 SIInstrInfo::isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
  88   return RC != &AMDGPU::EXECRegRegClass;
  89 }
  90
  91 //===----------------------------------------------------------------------===//
  92 // Indirect addressing callbacks
  93 //===----------------------------------------------------------------------===//
  94
  95 unsigned SIInstrInfo::calculateIndirectAddress(unsigned RegIndex,
  96                                                  unsigned Channel) const {
  97   assert(Channel == 0);
  98   return RegIndex;
  99 }
 100
 101
 102 int SIInstrInfo::getIndirectIndexBegin(const MachineFunction &MF) const {
 103   llvm_unreachable("Unimplemented");
 104 }
 105
 106 int SIInstrInfo::getIndirectIndexEnd(const MachineFunction &MF) const {
 107   llvm_unreachable("Unimplemented");
 108 }
 109
 110 const TargetRegisterClass *SIInstrInfo::getIndirectAddrStoreRegClass(
 111                                                      unsigned SourceReg) const {
 112   llvm_unreachable("Unimplemented");
 113 }
 114
 115 const TargetRegisterClass *SIInstrInfo::getIndirectAddrLoadRegClass() const {
 116   llvm_unreachable("Unimplemented");
 117 }
 118
 119 MachineInstrBuilder SIInstrInfo::buildIndirectWrite(
 120                                    MachineBasicBlock *MBB,
 121                                    MachineBasicBlock::iterator I,
 122                                    unsigned ValueReg,
 123                                    unsigned Address, unsigned OffsetReg) const {
 124   llvm_unreachable("Unimplemented");
 125 }
 126
 127 MachineInstrBuilder SIInstrInfo::buildIndirectRead(
 128                                    MachineBasicBlock *MBB,
 129                                    MachineBasicBlock::iterator I,
 130                                    unsigned ValueReg,
 131                                    unsigned Address, unsigned OffsetReg) const {
 132   llvm_unreachable("Unimplemented");
 133 }
 134
 135 const TargetRegisterClass *SIInstrInfo::getSuperIndirectRegClass() const {
 136   llvm_unreachable("Unimplemented");
 137 }