1 //===-- SIInstrInfo.cpp - SI Instruction Information ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief SI Implementation of TargetInstrInfo.
13 //===----------------------------------------------------------------------===//
16 #include "SIInstrInfo.h"
17 #include "AMDGPUTargetMachine.h"
18 #include "SIDefines.h"
19 #include "SIMachineFunctionInfo.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/IR/Function.h"
24 #include "llvm/CodeGen/RegisterScavenging.h"
25 #include "llvm/MC/MCInstrDesc.h"
29 SIInstrInfo::SIInstrInfo(const AMDGPUSubtarget &st)
30 : AMDGPUInstrInfo(st),
33 //===----------------------------------------------------------------------===//
34 // TargetInstrInfo callbacks
35 //===----------------------------------------------------------------------===//
37 static unsigned getNumOperandsNoGlue(SDNode *Node) {
38 unsigned N = Node->getNumOperands();
39 while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue)
44 static SDValue findChainOperand(SDNode *Load) {
45 SDValue LastOp = Load->getOperand(getNumOperandsNoGlue(Load) - 1);
46 assert(LastOp.getValueType() == MVT::Other && "Chain missing from load node");
50 /// \brief Returns true if both nodes have the same value for the given
51 /// operand \p Op, or if both nodes do not have this operand.
52 static bool nodesHaveSameOperandValue(SDNode *N0, SDNode* N1, unsigned OpName) {
53 unsigned Opc0 = N0->getMachineOpcode();
54 unsigned Opc1 = N1->getMachineOpcode();
56 int Op0Idx = AMDGPU::getNamedOperandIdx(Opc0, OpName);
57 int Op1Idx = AMDGPU::getNamedOperandIdx(Opc1, OpName);
59 if (Op0Idx == -1 && Op1Idx == -1)
63 if ((Op0Idx == -1 && Op1Idx != -1) ||
64 (Op1Idx == -1 && Op0Idx != -1))
67 // getNamedOperandIdx returns the index for the MachineInstr's operands,
68 // which includes the result as the first operand. We are indexing into the
69 // MachineSDNode's operands, so we need to skip the result operand to get
74 return N0->getOperand(Op0Idx) == N1->getOperand(Op1Idx);
77 bool SIInstrInfo::areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1,
79 int64_t &Offset1) const {
80 if (!Load0->isMachineOpcode() || !Load1->isMachineOpcode())
83 unsigned Opc0 = Load0->getMachineOpcode();
84 unsigned Opc1 = Load1->getMachineOpcode();
86 // Make sure both are actually loads.
87 if (!get(Opc0).mayLoad() || !get(Opc1).mayLoad())
90 if (isDS(Opc0) && isDS(Opc1)) {
91 assert(getNumOperandsNoGlue(Load0) == getNumOperandsNoGlue(Load1));
94 if (Load0->getOperand(1) != Load1->getOperand(1))
98 if (findChainOperand(Load0) != findChainOperand(Load1))
101 // Skip read2 / write2 variants for simplicity.
102 // TODO: We should report true if the used offsets are adjacent (excluded
104 if (AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::data1) != -1 ||
105 AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::data1) != -1)
108 Offset0 = cast<ConstantSDNode>(Load0->getOperand(2))->getZExtValue();
109 Offset1 = cast<ConstantSDNode>(Load1->getOperand(2))->getZExtValue();
113 if (isSMRD(Opc0) && isSMRD(Opc1)) {
114 assert(getNumOperandsNoGlue(Load0) == getNumOperandsNoGlue(Load1));
117 if (Load0->getOperand(0) != Load1->getOperand(0))
121 if (findChainOperand(Load0) != findChainOperand(Load1))
124 Offset0 = cast<ConstantSDNode>(Load0->getOperand(1))->getZExtValue();
125 Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue();
129 // MUBUF and MTBUF can access the same addresses.
130 if ((isMUBUF(Opc0) || isMTBUF(Opc0)) && (isMUBUF(Opc1) || isMTBUF(Opc1))) {
132 // MUBUF and MTBUF have vaddr at different indices.
133 if (!nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::soffset) ||
134 findChainOperand(Load0) != findChainOperand(Load1) ||
135 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::vaddr) ||
136 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::srsrc))
139 int OffIdx0 = AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::offset);
140 int OffIdx1 = AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::offset);
142 if (OffIdx0 == -1 || OffIdx1 == -1)
145 // getNamedOperandIdx returns the index for MachineInstrs. Since they
146 // inlcude the output in the operand list, but SDNodes don't, we need to
147 // subtract the index by one.
151 SDValue Off0 = Load0->getOperand(OffIdx0);
152 SDValue Off1 = Load1->getOperand(OffIdx1);
154 // The offset might be a FrameIndexSDNode.
155 if (!isa<ConstantSDNode>(Off0) || !isa<ConstantSDNode>(Off1))
158 Offset0 = cast<ConstantSDNode>(Off0)->getZExtValue();
159 Offset1 = cast<ConstantSDNode>(Off1)->getZExtValue();
166 static bool isStride64(unsigned Opc) {
168 case AMDGPU::DS_READ2ST64_B32:
169 case AMDGPU::DS_READ2ST64_B64:
170 case AMDGPU::DS_WRITE2ST64_B32:
171 case AMDGPU::DS_WRITE2ST64_B64:
178 bool SIInstrInfo::getLdStBaseRegImmOfs(MachineInstr *LdSt,
179 unsigned &BaseReg, unsigned &Offset,
180 const TargetRegisterInfo *TRI) const {
181 unsigned Opc = LdSt->getOpcode();
183 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
184 AMDGPU::OpName::offset);
186 // Normal, single offset LDS instruction.
187 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
188 AMDGPU::OpName::addr);
190 BaseReg = AddrReg->getReg();
191 Offset = OffsetImm->getImm();
195 // The 2 offset instructions use offset0 and offset1 instead. We can treat
196 // these as a load with a single offset if the 2 offsets are consecutive. We
197 // will use this for some partially aligned loads.
198 const MachineOperand *Offset0Imm = getNamedOperand(*LdSt,
199 AMDGPU::OpName::offset0);
200 const MachineOperand *Offset1Imm = getNamedOperand(*LdSt,
201 AMDGPU::OpName::offset1);
203 uint8_t Offset0 = Offset0Imm->getImm();
204 uint8_t Offset1 = Offset1Imm->getImm();
205 assert(Offset1 > Offset0);
207 if (Offset1 - Offset0 == 1) {
208 // Each of these offsets is in element sized units, so we need to convert
209 // to bytes of the individual reads.
213 EltSize = getOpRegClass(*LdSt, 0)->getSize() / 2;
215 assert(LdSt->mayStore());
216 int Data0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data0);
217 EltSize = getOpRegClass(*LdSt, Data0Idx)->getSize();
223 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
224 AMDGPU::OpName::addr);
225 BaseReg = AddrReg->getReg();
226 Offset = EltSize * Offset0;
233 if (isMUBUF(Opc) || isMTBUF(Opc)) {
234 if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::soffset) != -1)
237 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
238 AMDGPU::OpName::vaddr);
242 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
243 AMDGPU::OpName::offset);
244 BaseReg = AddrReg->getReg();
245 Offset = OffsetImm->getImm();
250 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
251 AMDGPU::OpName::offset);
255 const MachineOperand *SBaseReg = getNamedOperand(*LdSt,
256 AMDGPU::OpName::sbase);
257 BaseReg = SBaseReg->getReg();
258 Offset = OffsetImm->getImm();
265 bool SIInstrInfo::shouldClusterLoads(MachineInstr *FirstLdSt,
266 MachineInstr *SecondLdSt,
267 unsigned NumLoads) const {
268 unsigned Opc0 = FirstLdSt->getOpcode();
269 unsigned Opc1 = SecondLdSt->getOpcode();
271 // TODO: This needs finer tuning
275 if (isDS(Opc0) && isDS(Opc1))
278 if (isSMRD(Opc0) && isSMRD(Opc1))
281 if ((isMUBUF(Opc0) || isMTBUF(Opc0)) && (isMUBUF(Opc1) || isMTBUF(Opc1)))
288 SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
289 MachineBasicBlock::iterator MI, DebugLoc DL,
290 unsigned DestReg, unsigned SrcReg,
291 bool KillSrc) const {
293 // If we are trying to copy to or from SCC, there is a bug somewhere else in
294 // the backend. While it may be theoretically possible to do this, it should
295 // never be necessary.
296 assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC);
298 static const int16_t Sub0_15[] = {
299 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
300 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7,
301 AMDGPU::sub8, AMDGPU::sub9, AMDGPU::sub10, AMDGPU::sub11,
302 AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14, AMDGPU::sub15, 0
305 static const int16_t Sub0_7[] = {
306 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
307 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, 0
310 static const int16_t Sub0_3[] = {
311 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, 0
314 static const int16_t Sub0_2[] = {
315 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, 0
318 static const int16_t Sub0_1[] = {
319 AMDGPU::sub0, AMDGPU::sub1, 0
323 const int16_t *SubIndices;
325 if (AMDGPU::M0 == DestReg) {
326 // Check if M0 isn't already set to this value
327 for (MachineBasicBlock::reverse_iterator E = MBB.rend(),
328 I = MachineBasicBlock::reverse_iterator(MI); I != E; ++I) {
330 if (!I->definesRegister(AMDGPU::M0))
333 unsigned Opc = I->getOpcode();
334 if (Opc != TargetOpcode::COPY && Opc != AMDGPU::S_MOV_B32)
337 if (!I->readsRegister(SrcReg))
340 // The copy isn't necessary
345 if (AMDGPU::SReg_32RegClass.contains(DestReg)) {
346 assert(AMDGPU::SReg_32RegClass.contains(SrcReg));
347 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)
348 .addReg(SrcReg, getKillRegState(KillSrc));
351 } else if (AMDGPU::SReg_64RegClass.contains(DestReg)) {
352 assert(AMDGPU::SReg_64RegClass.contains(SrcReg));
353 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg)
354 .addReg(SrcReg, getKillRegState(KillSrc));
357 } else if (AMDGPU::SReg_128RegClass.contains(DestReg)) {
358 assert(AMDGPU::SReg_128RegClass.contains(SrcReg));
359 Opcode = AMDGPU::S_MOV_B32;
362 } else if (AMDGPU::SReg_256RegClass.contains(DestReg)) {
363 assert(AMDGPU::SReg_256RegClass.contains(SrcReg));
364 Opcode = AMDGPU::S_MOV_B32;
367 } else if (AMDGPU::SReg_512RegClass.contains(DestReg)) {
368 assert(AMDGPU::SReg_512RegClass.contains(SrcReg));
369 Opcode = AMDGPU::S_MOV_B32;
370 SubIndices = Sub0_15;
372 } else if (AMDGPU::VReg_32RegClass.contains(DestReg)) {
373 assert(AMDGPU::VReg_32RegClass.contains(SrcReg) ||
374 AMDGPU::SReg_32RegClass.contains(SrcReg));
375 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
376 .addReg(SrcReg, getKillRegState(KillSrc));
379 } else if (AMDGPU::VReg_64RegClass.contains(DestReg)) {
380 assert(AMDGPU::VReg_64RegClass.contains(SrcReg) ||
381 AMDGPU::SReg_64RegClass.contains(SrcReg));
382 Opcode = AMDGPU::V_MOV_B32_e32;
385 } else if (AMDGPU::VReg_96RegClass.contains(DestReg)) {
386 assert(AMDGPU::VReg_96RegClass.contains(SrcReg));
387 Opcode = AMDGPU::V_MOV_B32_e32;
390 } else if (AMDGPU::VReg_128RegClass.contains(DestReg)) {
391 assert(AMDGPU::VReg_128RegClass.contains(SrcReg) ||
392 AMDGPU::SReg_128RegClass.contains(SrcReg));
393 Opcode = AMDGPU::V_MOV_B32_e32;
396 } else if (AMDGPU::VReg_256RegClass.contains(DestReg)) {
397 assert(AMDGPU::VReg_256RegClass.contains(SrcReg) ||
398 AMDGPU::SReg_256RegClass.contains(SrcReg));
399 Opcode = AMDGPU::V_MOV_B32_e32;
402 } else if (AMDGPU::VReg_512RegClass.contains(DestReg)) {
403 assert(AMDGPU::VReg_512RegClass.contains(SrcReg) ||
404 AMDGPU::SReg_512RegClass.contains(SrcReg));
405 Opcode = AMDGPU::V_MOV_B32_e32;
406 SubIndices = Sub0_15;
409 llvm_unreachable("Can't copy register!");
412 while (unsigned SubIdx = *SubIndices++) {
413 MachineInstrBuilder Builder = BuildMI(MBB, MI, DL,
414 get(Opcode), RI.getSubReg(DestReg, SubIdx));
416 Builder.addReg(RI.getSubReg(SrcReg, SubIdx), getKillRegState(KillSrc));
419 Builder.addReg(DestReg, RegState::Define | RegState::Implicit);
423 unsigned SIInstrInfo::commuteOpcode(unsigned Opcode) const {
426 // Try to map original to commuted opcode
427 if ((NewOpc = AMDGPU::getCommuteRev(Opcode)) != -1)
430 // Try to map commuted to original opcode
431 if ((NewOpc = AMDGPU::getCommuteOrig(Opcode)) != -1)
437 static bool shouldTryToSpillVGPRs(MachineFunction *MF) {
439 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
440 const TargetMachine &TM = MF->getTarget();
442 // FIXME: Even though it can cause problems, we need to enable
443 // spilling at -O0, since the fast register allocator always
444 // spills registers that are live at the end of blocks.
445 return MFI->getShaderType() == ShaderType::COMPUTE &&
446 TM.getOptLevel() == CodeGenOpt::None;
450 void SIInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
451 MachineBasicBlock::iterator MI,
452 unsigned SrcReg, bool isKill,
454 const TargetRegisterClass *RC,
455 const TargetRegisterInfo *TRI) const {
456 MachineFunction *MF = MBB.getParent();
457 MachineFrameInfo *FrameInfo = MF->getFrameInfo();
458 DebugLoc DL = MBB.findDebugLoc(MI);
461 if (RI.isSGPRClass(RC)) {
462 // We are only allowed to create one new instruction when spilling
463 // registers, so we need to use pseudo instruction for spilling
465 switch (RC->getSize() * 8) {
466 case 32: Opcode = AMDGPU::SI_SPILL_S32_SAVE; break;
467 case 64: Opcode = AMDGPU::SI_SPILL_S64_SAVE; break;
468 case 128: Opcode = AMDGPU::SI_SPILL_S128_SAVE; break;
469 case 256: Opcode = AMDGPU::SI_SPILL_S256_SAVE; break;
470 case 512: Opcode = AMDGPU::SI_SPILL_S512_SAVE; break;
472 } else if(shouldTryToSpillVGPRs(MF) && RI.hasVGPRs(RC)) {
473 switch(RC->getSize() * 8) {
474 case 32: Opcode = AMDGPU::SI_SPILL_V32_SAVE; break;
475 case 64: Opcode = AMDGPU::SI_SPILL_V64_SAVE; break;
476 case 96: Opcode = AMDGPU::SI_SPILL_V96_SAVE; break;
477 case 128: Opcode = AMDGPU::SI_SPILL_V128_SAVE; break;
478 case 256: Opcode = AMDGPU::SI_SPILL_V256_SAVE; break;
479 case 512: Opcode = AMDGPU::SI_SPILL_V512_SAVE; break;
484 FrameInfo->setObjectAlignment(FrameIndex, 4);
485 BuildMI(MBB, MI, DL, get(Opcode))
487 .addFrameIndex(FrameIndex);
489 LLVMContext &Ctx = MF->getFunction()->getContext();
490 Ctx.emitError("SIInstrInfo::storeRegToStackSlot - Do not know how to"
492 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), AMDGPU::VGPR0)
497 void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
498 MachineBasicBlock::iterator MI,
499 unsigned DestReg, int FrameIndex,
500 const TargetRegisterClass *RC,
501 const TargetRegisterInfo *TRI) const {
502 MachineFunction *MF = MBB.getParent();
503 MachineFrameInfo *FrameInfo = MF->getFrameInfo();
504 DebugLoc DL = MBB.findDebugLoc(MI);
507 if (RI.isSGPRClass(RC)){
508 switch(RC->getSize() * 8) {
509 case 32: Opcode = AMDGPU::SI_SPILL_S32_RESTORE; break;
510 case 64: Opcode = AMDGPU::SI_SPILL_S64_RESTORE; break;
511 case 128: Opcode = AMDGPU::SI_SPILL_S128_RESTORE; break;
512 case 256: Opcode = AMDGPU::SI_SPILL_S256_RESTORE; break;
513 case 512: Opcode = AMDGPU::SI_SPILL_S512_RESTORE; break;
515 } else if(shouldTryToSpillVGPRs(MF) && RI.hasVGPRs(RC)) {
516 switch(RC->getSize() * 8) {
517 case 32: Opcode = AMDGPU::SI_SPILL_V32_RESTORE; break;
518 case 64: Opcode = AMDGPU::SI_SPILL_V64_RESTORE; break;
519 case 96: Opcode = AMDGPU::SI_SPILL_V96_RESTORE; break;
520 case 128: Opcode = AMDGPU::SI_SPILL_V128_RESTORE; break;
521 case 256: Opcode = AMDGPU::SI_SPILL_V256_RESTORE; break;
522 case 512: Opcode = AMDGPU::SI_SPILL_V512_RESTORE; break;
527 FrameInfo->setObjectAlignment(FrameIndex, 4);
528 BuildMI(MBB, MI, DL, get(Opcode), DestReg)
529 .addFrameIndex(FrameIndex);
531 LLVMContext &Ctx = MF->getFunction()->getContext();
532 Ctx.emitError("SIInstrInfo::loadRegFromStackSlot - Do not know how to"
533 " restore register");
534 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
535 .addReg(AMDGPU::VGPR0);
539 /// \param @Offset Offset in bytes of the FrameIndex being spilled
540 unsigned SIInstrInfo::calculateLDSSpillAddress(MachineBasicBlock &MBB,
541 MachineBasicBlock::iterator MI,
542 RegScavenger *RS, unsigned TmpReg,
543 unsigned FrameOffset,
544 unsigned Size) const {
545 MachineFunction *MF = MBB.getParent();
546 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
547 const AMDGPUSubtarget &ST = MF->getTarget().getSubtarget<AMDGPUSubtarget>();
548 const SIRegisterInfo *TRI =
549 static_cast<const SIRegisterInfo*>(ST.getRegisterInfo());
550 DebugLoc DL = MBB.findDebugLoc(MI);
551 unsigned WorkGroupSize = MFI->getMaximumWorkGroupSize(*MF);
552 unsigned WavefrontSize = ST.getWavefrontSize();
554 unsigned TIDReg = MFI->getTIDReg();
555 if (!MFI->hasCalculatedTID()) {
556 MachineBasicBlock &Entry = MBB.getParent()->front();
557 MachineBasicBlock::iterator Insert = Entry.front();
558 DebugLoc DL = Insert->getDebugLoc();
560 TIDReg = RI.findUnusedVGPR(MF->getRegInfo());
561 if (TIDReg == AMDGPU::NoRegister)
565 if (MFI->getShaderType() == ShaderType::COMPUTE &&
566 WorkGroupSize > WavefrontSize) {
568 unsigned TIDIGXReg = TRI->getPreloadedValue(*MF, SIRegisterInfo::TIDIG_X);
569 unsigned TIDIGYReg = TRI->getPreloadedValue(*MF, SIRegisterInfo::TIDIG_Y);
570 unsigned TIDIGZReg = TRI->getPreloadedValue(*MF, SIRegisterInfo::TIDIG_Z);
571 unsigned InputPtrReg =
572 TRI->getPreloadedValue(*MF, SIRegisterInfo::INPUT_PTR);
573 static const unsigned TIDIGRegs[3] = {
574 TIDIGXReg, TIDIGYReg, TIDIGZReg
576 for (unsigned Reg : TIDIGRegs) {
577 if (!Entry.isLiveIn(Reg))
578 Entry.addLiveIn(Reg);
581 RS->enterBasicBlock(&Entry);
582 unsigned STmp0 = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, 0);
583 unsigned STmp1 = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, 0);
584 BuildMI(Entry, Insert, DL, get(AMDGPU::S_LOAD_DWORD_IMM), STmp0)
586 .addImm(SI::KernelInputOffsets::NGROUPS_Z);
587 BuildMI(Entry, Insert, DL, get(AMDGPU::S_LOAD_DWORD_IMM), STmp1)
589 .addImm(SI::KernelInputOffsets::NGROUPS_Y);
591 // NGROUPS.X * NGROUPS.Y
592 BuildMI(Entry, Insert, DL, get(AMDGPU::S_MUL_I32), STmp1)
595 // (NGROUPS.X * NGROUPS.Y) * TIDIG.X
596 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MUL_U32_U24_e32), TIDReg)
599 // NGROUPS.Z * TIDIG.Y + (NGROUPS.X * NGROPUS.Y * TIDIG.X)
600 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MAD_U32_U24), TIDReg)
604 // (NGROUPS.Z * TIDIG.Y + (NGROUPS.X * NGROPUS.Y * TIDIG.X)) + TIDIG.Z
605 BuildMI(Entry, Insert, DL, get(AMDGPU::V_ADD_I32_e32), TIDReg)
610 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MBCNT_LO_U32_B32_e64),
615 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MBCNT_HI_U32_B32_e32),
621 BuildMI(Entry, Insert, DL, get(AMDGPU::V_LSHLREV_B32_e32),
625 MFI->setTIDReg(TIDReg);
628 // Add FrameIndex to LDS offset
629 unsigned LDSOffset = MFI->LDSSize + (FrameOffset * WorkGroupSize);
630 BuildMI(MBB, MI, DL, get(AMDGPU::V_ADD_I32_e32), TmpReg)
637 void SIInstrInfo::insertNOPs(MachineBasicBlock::iterator MI,
646 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(AMDGPU::S_NOP))
651 bool SIInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
652 MachineBasicBlock &MBB = *MI->getParent();
653 DebugLoc DL = MBB.findDebugLoc(MI);
654 switch (MI->getOpcode()) {
655 default: return AMDGPUInstrInfo::expandPostRAPseudo(MI);
657 case AMDGPU::SI_CONSTDATA_PTR: {
658 unsigned Reg = MI->getOperand(0).getReg();
659 unsigned RegLo = RI.getSubReg(Reg, AMDGPU::sub0);
660 unsigned RegHi = RI.getSubReg(Reg, AMDGPU::sub1);
662 BuildMI(MBB, MI, DL, get(AMDGPU::S_GETPC_B64), Reg);
664 // Add 32-bit offset from this instruction to the start of the constant data.
665 BuildMI(MBB, MI, DL, get(AMDGPU::S_ADD_U32), RegLo)
667 .addTargetIndex(AMDGPU::TI_CONSTDATA_START)
668 .addReg(AMDGPU::SCC, RegState::Define | RegState::Implicit);
669 BuildMI(MBB, MI, DL, get(AMDGPU::S_ADDC_U32), RegHi)
672 .addReg(AMDGPU::SCC, RegState::Define | RegState::Implicit)
673 .addReg(AMDGPU::SCC, RegState::Implicit);
674 MI->eraseFromParent();
681 MachineInstr *SIInstrInfo::commuteInstruction(MachineInstr *MI,
684 if (MI->getNumOperands() < 3 || !MI->getOperand(1).isReg())
687 // Make sure it s legal to commute operands for VOP2.
688 if (isVOP2(MI->getOpcode()) &&
689 (!isOperandLegal(MI, 1, &MI->getOperand(2)) ||
690 !isOperandLegal(MI, 2, &MI->getOperand(1))))
693 if (!MI->getOperand(2).isReg()) {
694 // XXX: Commute instructions with FPImm operands
695 if (NewMI || MI->getOperand(2).isFPImm() ||
696 (!isVOP2(MI->getOpcode()) && !isVOP3(MI->getOpcode()))) {
700 // XXX: Commute VOP3 instructions with abs and neg set .
701 const MachineOperand *Abs = getNamedOperand(*MI, AMDGPU::OpName::abs);
702 const MachineOperand *Neg = getNamedOperand(*MI, AMDGPU::OpName::neg);
703 const MachineOperand *Src0Mods = getNamedOperand(*MI,
704 AMDGPU::OpName::src0_modifiers);
705 const MachineOperand *Src1Mods = getNamedOperand(*MI,
706 AMDGPU::OpName::src1_modifiers);
707 const MachineOperand *Src2Mods = getNamedOperand(*MI,
708 AMDGPU::OpName::src2_modifiers);
710 if ((Abs && Abs->getImm()) || (Neg && Neg->getImm()) ||
711 (Src0Mods && Src0Mods->getImm()) || (Src1Mods && Src1Mods->getImm()) ||
712 (Src2Mods && Src2Mods->getImm()))
715 unsigned Reg = MI->getOperand(1).getReg();
716 unsigned SubReg = MI->getOperand(1).getSubReg();
717 MI->getOperand(1).ChangeToImmediate(MI->getOperand(2).getImm());
718 MI->getOperand(2).ChangeToRegister(Reg, false);
719 MI->getOperand(2).setSubReg(SubReg);
721 MI = TargetInstrInfo::commuteInstruction(MI, NewMI);
725 MI->setDesc(get(commuteOpcode(MI->getOpcode())));
730 MachineInstr *SIInstrInfo::buildMovInstr(MachineBasicBlock *MBB,
731 MachineBasicBlock::iterator I,
733 unsigned SrcReg) const {
734 return BuildMI(*MBB, I, MBB->findDebugLoc(I), get(AMDGPU::V_MOV_B32_e32),
735 DstReg) .addReg(SrcReg);
738 bool SIInstrInfo::isMov(unsigned Opcode) const {
740 default: return false;
741 case AMDGPU::S_MOV_B32:
742 case AMDGPU::S_MOV_B64:
743 case AMDGPU::V_MOV_B32_e32:
744 case AMDGPU::V_MOV_B32_e64:
750 SIInstrInfo::isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
751 return RC != &AMDGPU::EXECRegRegClass;
755 SIInstrInfo::isTriviallyReMaterializable(const MachineInstr *MI,
756 AliasAnalysis *AA) const {
757 switch(MI->getOpcode()) {
758 default: return AMDGPUInstrInfo::isTriviallyReMaterializable(MI, AA);
759 case AMDGPU::S_MOV_B32:
760 case AMDGPU::S_MOV_B64:
761 case AMDGPU::V_MOV_B32_e32:
762 return MI->getOperand(1).isImm();
768 // Helper function generated by tablegen. We are wrapping this with
769 // an SIInstrInfo function that returns bool rather than int.
770 int isDS(uint16_t Opcode);
774 bool SIInstrInfo::isDS(uint16_t Opcode) const {
775 return ::AMDGPU::isDS(Opcode) != -1;
778 bool SIInstrInfo::isMIMG(uint16_t Opcode) const {
779 return get(Opcode).TSFlags & SIInstrFlags::MIMG;
782 bool SIInstrInfo::isSMRD(uint16_t Opcode) const {
783 return get(Opcode).TSFlags & SIInstrFlags::SMRD;
786 bool SIInstrInfo::isMUBUF(uint16_t Opcode) const {
787 return get(Opcode).TSFlags & SIInstrFlags::MUBUF;
790 bool SIInstrInfo::isMTBUF(uint16_t Opcode) const {
791 return get(Opcode).TSFlags & SIInstrFlags::MTBUF;
794 bool SIInstrInfo::isFLAT(uint16_t Opcode) const {
795 return get(Opcode).TSFlags & SIInstrFlags::FLAT;
798 bool SIInstrInfo::isVOP1(uint16_t Opcode) const {
799 return get(Opcode).TSFlags & SIInstrFlags::VOP1;
802 bool SIInstrInfo::isVOP2(uint16_t Opcode) const {
803 return get(Opcode).TSFlags & SIInstrFlags::VOP2;
806 bool SIInstrInfo::isVOP3(uint16_t Opcode) const {
807 return get(Opcode).TSFlags & SIInstrFlags::VOP3;
810 bool SIInstrInfo::isVOPC(uint16_t Opcode) const {
811 return get(Opcode).TSFlags & SIInstrFlags::VOPC;
814 bool SIInstrInfo::isSALUInstr(const MachineInstr &MI) const {
815 return get(MI.getOpcode()).TSFlags & SIInstrFlags::SALU;
818 bool SIInstrInfo::isInlineConstant(const APInt &Imm) const {
819 int32_t Val = Imm.getSExtValue();
820 if (Val >= -16 && Val <= 64)
823 // The actual type of the operand does not seem to matter as long
824 // as the bits match one of the inline immediate values. For example:
826 // -nan has the hexadecimal encoding of 0xfffffffe which is -2 in decimal,
827 // so it is a legal inline immediate.
829 // 1065353216 has the hexadecimal encoding 0x3f800000 which is 1.0f in
830 // floating-point, so it is a legal inline immediate.
832 return (APInt::floatToBits(0.0f) == Imm) ||
833 (APInt::floatToBits(1.0f) == Imm) ||
834 (APInt::floatToBits(-1.0f) == Imm) ||
835 (APInt::floatToBits(0.5f) == Imm) ||
836 (APInt::floatToBits(-0.5f) == Imm) ||
837 (APInt::floatToBits(2.0f) == Imm) ||
838 (APInt::floatToBits(-2.0f) == Imm) ||
839 (APInt::floatToBits(4.0f) == Imm) ||
840 (APInt::floatToBits(-4.0f) == Imm);
843 bool SIInstrInfo::isInlineConstant(const MachineOperand &MO) const {
845 return isInlineConstant(APInt(32, MO.getImm(), true));
848 APFloat FpImm = MO.getFPImm()->getValueAPF();
849 return isInlineConstant(FpImm.bitcastToAPInt());
855 bool SIInstrInfo::isLiteralConstant(const MachineOperand &MO) const {
856 return (MO.isImm() || MO.isFPImm()) && !isInlineConstant(MO);
859 static bool compareMachineOp(const MachineOperand &Op0,
860 const MachineOperand &Op1) {
861 if (Op0.getType() != Op1.getType())
864 switch (Op0.getType()) {
865 case MachineOperand::MO_Register:
866 return Op0.getReg() == Op1.getReg();
867 case MachineOperand::MO_Immediate:
868 return Op0.getImm() == Op1.getImm();
869 case MachineOperand::MO_FPImmediate:
870 return Op0.getFPImm() == Op1.getFPImm();
872 llvm_unreachable("Didn't expect to be comparing these operand types");
876 bool SIInstrInfo::isImmOperandLegal(const MachineInstr *MI, unsigned OpNo,
877 const MachineOperand &MO) const {
878 const MCOperandInfo &OpInfo = get(MI->getOpcode()).OpInfo[OpNo];
880 assert(MO.isImm() || MO.isFPImm() || MO.isTargetIndex() || MO.isFI());
882 if (OpInfo.OperandType == MCOI::OPERAND_IMMEDIATE)
885 if (OpInfo.RegClass < 0)
888 if (isLiteralConstant(MO))
889 return RI.regClassCanUseLiteralConstant(OpInfo.RegClass);
891 return RI.regClassCanUseInlineConstant(OpInfo.RegClass);
894 bool SIInstrInfo::canFoldOffset(unsigned OffsetSize, unsigned AS) {
896 case AMDGPUAS::GLOBAL_ADDRESS: {
897 // MUBUF instructions a 12-bit offset in bytes.
898 return isUInt<12>(OffsetSize);
900 case AMDGPUAS::CONSTANT_ADDRESS: {
901 // SMRD instructions have an 8-bit offset in dwords.
902 return (OffsetSize % 4 == 0) && isUInt<8>(OffsetSize / 4);
904 case AMDGPUAS::LOCAL_ADDRESS:
905 case AMDGPUAS::REGION_ADDRESS: {
906 // The single offset versions have a 16-bit offset in bytes.
907 return isUInt<16>(OffsetSize);
909 case AMDGPUAS::PRIVATE_ADDRESS:
910 // Indirect register addressing does not use any offsets.
916 bool SIInstrInfo::hasVALU32BitEncoding(unsigned Opcode) const {
917 return AMDGPU::getVOPe32(Opcode) != -1;
920 bool SIInstrInfo::hasModifiers(unsigned Opcode) const {
921 // The src0_modifier operand is present on all instructions
922 // that have modifiers.
924 return AMDGPU::getNamedOperandIdx(Opcode,
925 AMDGPU::OpName::src0_modifiers) != -1;
928 bool SIInstrInfo::usesConstantBus(const MachineRegisterInfo &MRI,
929 const MachineOperand &MO) const {
930 // Literal constants use the constant bus.
931 if (isLiteralConstant(MO))
934 if (!MO.isReg() || !MO.isUse())
937 if (TargetRegisterInfo::isVirtualRegister(MO.getReg()))
938 return RI.isSGPRClass(MRI.getRegClass(MO.getReg()));
940 // FLAT_SCR is just an SGPR pair.
941 if (!MO.isImplicit() && (MO.getReg() == AMDGPU::FLAT_SCR))
944 // EXEC register uses the constant bus.
945 if (!MO.isImplicit() && MO.getReg() == AMDGPU::EXEC)
948 // SGPRs use the constant bus
949 if (MO.getReg() == AMDGPU::M0 || MO.getReg() == AMDGPU::VCC ||
951 (AMDGPU::SGPR_32RegClass.contains(MO.getReg()) ||
952 AMDGPU::SGPR_64RegClass.contains(MO.getReg())))) {
959 bool SIInstrInfo::verifyInstruction(const MachineInstr *MI,
960 StringRef &ErrInfo) const {
961 uint16_t Opcode = MI->getOpcode();
962 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
963 int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0);
964 int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1);
965 int Src2Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2);
967 // Make sure the number of operands is correct.
968 const MCInstrDesc &Desc = get(Opcode);
969 if (!Desc.isVariadic() &&
970 Desc.getNumOperands() != MI->getNumExplicitOperands()) {
971 ErrInfo = "Instruction has wrong number of operands.";
975 // Make sure the register classes are correct
976 for (int i = 0, e = Desc.getNumOperands(); i != e; ++i) {
977 switch (Desc.OpInfo[i].OperandType) {
978 case MCOI::OPERAND_REGISTER: {
979 if ((MI->getOperand(i).isImm() || MI->getOperand(i).isFPImm()) &&
980 !isImmOperandLegal(MI, i, MI->getOperand(i))) {
981 ErrInfo = "Illegal immediate value for operand.";
986 case MCOI::OPERAND_IMMEDIATE:
987 // Check if this operand is an immediate.
988 // FrameIndex operands will be replaced by immediates, so they are
990 if (!MI->getOperand(i).isImm() && !MI->getOperand(i).isFPImm() &&
991 !MI->getOperand(i).isFI()) {
992 ErrInfo = "Expected immediate, but got non-immediate";
1000 if (!MI->getOperand(i).isReg())
1003 int RegClass = Desc.OpInfo[i].RegClass;
1004 if (RegClass != -1) {
1005 unsigned Reg = MI->getOperand(i).getReg();
1006 if (TargetRegisterInfo::isVirtualRegister(Reg))
1009 const TargetRegisterClass *RC = RI.getRegClass(RegClass);
1010 if (!RC->contains(Reg)) {
1011 ErrInfo = "Operand has incorrect register class.";
1019 if (isVOP1(Opcode) || isVOP2(Opcode) || isVOP3(Opcode) || isVOPC(Opcode)) {
1020 unsigned ConstantBusCount = 0;
1021 unsigned SGPRUsed = AMDGPU::NoRegister;
1022 for (int i = 0, e = MI->getNumOperands(); i != e; ++i) {
1023 const MachineOperand &MO = MI->getOperand(i);
1024 if (usesConstantBus(MRI, MO)) {
1026 if (MO.getReg() != SGPRUsed)
1028 SGPRUsed = MO.getReg();
1034 if (ConstantBusCount > 1) {
1035 ErrInfo = "VOP* instruction uses the constant bus more than once";
1040 // Verify SRC1 for VOP2 and VOPC
1041 if (Src1Idx != -1 && (isVOP2(Opcode) || isVOPC(Opcode))) {
1042 const MachineOperand &Src1 = MI->getOperand(Src1Idx);
1043 if (Src1.isImm() || Src1.isFPImm()) {
1044 ErrInfo = "VOP[2C] src1 cannot be an immediate.";
1050 if (isVOP3(Opcode)) {
1051 if (Src0Idx != -1 && isLiteralConstant(MI->getOperand(Src0Idx))) {
1052 ErrInfo = "VOP3 src0 cannot be a literal constant.";
1055 if (Src1Idx != -1 && isLiteralConstant(MI->getOperand(Src1Idx))) {
1056 ErrInfo = "VOP3 src1 cannot be a literal constant.";
1059 if (Src2Idx != -1 && isLiteralConstant(MI->getOperand(Src2Idx))) {
1060 ErrInfo = "VOP3 src2 cannot be a literal constant.";
1065 // Verify misc. restrictions on specific instructions.
1066 if (Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F32 ||
1067 Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F64) {
1070 const MachineOperand &Src0 = MI->getOperand(2);
1071 const MachineOperand &Src1 = MI->getOperand(3);
1072 const MachineOperand &Src2 = MI->getOperand(4);
1073 if (Src0.isReg() && Src1.isReg() && Src2.isReg()) {
1074 if (!compareMachineOp(Src0, Src1) &&
1075 !compareMachineOp(Src0, Src2)) {
1076 ErrInfo = "v_div_scale_{f32|f64} require src0 = src1 or src2";
1085 unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) {
1086 switch (MI.getOpcode()) {
1087 default: return AMDGPU::INSTRUCTION_LIST_END;
1088 case AMDGPU::REG_SEQUENCE: return AMDGPU::REG_SEQUENCE;
1089 case AMDGPU::COPY: return AMDGPU::COPY;
1090 case AMDGPU::PHI: return AMDGPU::PHI;
1091 case AMDGPU::INSERT_SUBREG: return AMDGPU::INSERT_SUBREG;
1092 case AMDGPU::S_MOV_B32:
1093 return MI.getOperand(1).isReg() ?
1094 AMDGPU::COPY : AMDGPU::V_MOV_B32_e32;
1095 case AMDGPU::S_ADD_I32:
1096 case AMDGPU::S_ADD_U32: return AMDGPU::V_ADD_I32_e32;
1097 case AMDGPU::S_ADDC_U32: return AMDGPU::V_ADDC_U32_e32;
1098 case AMDGPU::S_SUB_I32:
1099 case AMDGPU::S_SUB_U32: return AMDGPU::V_SUB_I32_e32;
1100 case AMDGPU::S_SUBB_U32: return AMDGPU::V_SUBB_U32_e32;
1101 case AMDGPU::S_MUL_I32: return AMDGPU::V_MUL_LO_I32;
1102 case AMDGPU::S_AND_B32: return AMDGPU::V_AND_B32_e32;
1103 case AMDGPU::S_OR_B32: return AMDGPU::V_OR_B32_e32;
1104 case AMDGPU::S_XOR_B32: return AMDGPU::V_XOR_B32_e32;
1105 case AMDGPU::S_MIN_I32: return AMDGPU::V_MIN_I32_e32;
1106 case AMDGPU::S_MIN_U32: return AMDGPU::V_MIN_U32_e32;
1107 case AMDGPU::S_MAX_I32: return AMDGPU::V_MAX_I32_e32;
1108 case AMDGPU::S_MAX_U32: return AMDGPU::V_MAX_U32_e32;
1109 case AMDGPU::S_ASHR_I32: return AMDGPU::V_ASHR_I32_e32;
1110 case AMDGPU::S_ASHR_I64: return AMDGPU::V_ASHR_I64;
1111 case AMDGPU::S_LSHL_B32: return AMDGPU::V_LSHL_B32_e32;
1112 case AMDGPU::S_LSHL_B64: return AMDGPU::V_LSHL_B64;
1113 case AMDGPU::S_LSHR_B32: return AMDGPU::V_LSHR_B32_e32;
1114 case AMDGPU::S_LSHR_B64: return AMDGPU::V_LSHR_B64;
1115 case AMDGPU::S_SEXT_I32_I8: return AMDGPU::V_BFE_I32;
1116 case AMDGPU::S_SEXT_I32_I16: return AMDGPU::V_BFE_I32;
1117 case AMDGPU::S_BFE_U32: return AMDGPU::V_BFE_U32;
1118 case AMDGPU::S_BFE_I32: return AMDGPU::V_BFE_I32;
1119 case AMDGPU::S_BREV_B32: return AMDGPU::V_BFREV_B32_e32;
1120 case AMDGPU::S_NOT_B32: return AMDGPU::V_NOT_B32_e32;
1121 case AMDGPU::S_NOT_B64: return AMDGPU::V_NOT_B32_e32;
1122 case AMDGPU::S_CMP_EQ_I32: return AMDGPU::V_CMP_EQ_I32_e32;
1123 case AMDGPU::S_CMP_LG_I32: return AMDGPU::V_CMP_NE_I32_e32;
1124 case AMDGPU::S_CMP_GT_I32: return AMDGPU::V_CMP_GT_I32_e32;
1125 case AMDGPU::S_CMP_GE_I32: return AMDGPU::V_CMP_GE_I32_e32;
1126 case AMDGPU::S_CMP_LT_I32: return AMDGPU::V_CMP_LT_I32_e32;
1127 case AMDGPU::S_CMP_LE_I32: return AMDGPU::V_CMP_LE_I32_e32;
1128 case AMDGPU::S_LOAD_DWORD_IMM:
1129 case AMDGPU::S_LOAD_DWORD_SGPR: return AMDGPU::BUFFER_LOAD_DWORD_ADDR64;
1130 case AMDGPU::S_LOAD_DWORDX2_IMM:
1131 case AMDGPU::S_LOAD_DWORDX2_SGPR: return AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64;
1132 case AMDGPU::S_LOAD_DWORDX4_IMM:
1133 case AMDGPU::S_LOAD_DWORDX4_SGPR: return AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64;
1134 case AMDGPU::S_BCNT1_I32_B32: return AMDGPU::V_BCNT_U32_B32_e32;
1135 case AMDGPU::S_FF1_I32_B32: return AMDGPU::V_FFBL_B32_e32;
1136 case AMDGPU::S_FLBIT_I32_B32: return AMDGPU::V_FFBH_U32_e32;
1140 bool SIInstrInfo::isSALUOpSupportedOnVALU(const MachineInstr &MI) const {
1141 return getVALUOp(MI) != AMDGPU::INSTRUCTION_LIST_END;
1144 const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI,
1145 unsigned OpNo) const {
1146 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
1147 const MCInstrDesc &Desc = get(MI.getOpcode());
1148 if (MI.isVariadic() || OpNo >= Desc.getNumOperands() ||
1149 Desc.OpInfo[OpNo].RegClass == -1)
1150 return MRI.getRegClass(MI.getOperand(OpNo).getReg());
1152 unsigned RCID = Desc.OpInfo[OpNo].RegClass;
1153 return RI.getRegClass(RCID);
1156 bool SIInstrInfo::canReadVGPR(const MachineInstr &MI, unsigned OpNo) const {
1157 switch (MI.getOpcode()) {
1159 case AMDGPU::REG_SEQUENCE:
1161 case AMDGPU::INSERT_SUBREG:
1162 return RI.hasVGPRs(getOpRegClass(MI, 0));
1164 return RI.hasVGPRs(getOpRegClass(MI, OpNo));
1168 void SIInstrInfo::legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const {
1169 MachineBasicBlock::iterator I = MI;
1170 MachineOperand &MO = MI->getOperand(OpIdx);
1171 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1172 unsigned RCID = get(MI->getOpcode()).OpInfo[OpIdx].RegClass;
1173 const TargetRegisterClass *RC = RI.getRegClass(RCID);
1174 unsigned Opcode = AMDGPU::V_MOV_B32_e32;
1176 Opcode = AMDGPU::COPY;
1177 } else if (RI.isSGPRClass(RC)) {
1178 Opcode = AMDGPU::S_MOV_B32;
1181 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(RC);
1182 if (RI.getCommonSubClass(&AMDGPU::VReg_64RegClass, VRC)) {
1183 VRC = &AMDGPU::VReg_64RegClass;
1185 VRC = &AMDGPU::VReg_32RegClass;
1187 unsigned Reg = MRI.createVirtualRegister(VRC);
1188 BuildMI(*MI->getParent(), I, MI->getParent()->findDebugLoc(I), get(Opcode),
1189 Reg).addOperand(MO);
1190 MO.ChangeToRegister(Reg, false);
1193 unsigned SIInstrInfo::buildExtractSubReg(MachineBasicBlock::iterator MI,
1194 MachineRegisterInfo &MRI,
1195 MachineOperand &SuperReg,
1196 const TargetRegisterClass *SuperRC,
1198 const TargetRegisterClass *SubRC)
1200 assert(SuperReg.isReg());
1202 unsigned NewSuperReg = MRI.createVirtualRegister(SuperRC);
1203 unsigned SubReg = MRI.createVirtualRegister(SubRC);
1205 // Just in case the super register is itself a sub-register, copy it to a new
1206 // value so we don't need to worry about merging its subreg index with the
1207 // SubIdx passed to this function. The register coalescer should be able to
1208 // eliminate this extra copy.
1209 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(TargetOpcode::COPY),
1211 .addOperand(SuperReg);
1213 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(TargetOpcode::COPY),
1215 .addReg(NewSuperReg, 0, SubIdx);
1219 MachineOperand SIInstrInfo::buildExtractSubRegOrImm(
1220 MachineBasicBlock::iterator MII,
1221 MachineRegisterInfo &MRI,
1223 const TargetRegisterClass *SuperRC,
1225 const TargetRegisterClass *SubRC) const {
1227 // XXX - Is there a better way to do this?
1228 if (SubIdx == AMDGPU::sub0)
1229 return MachineOperand::CreateImm(Op.getImm() & 0xFFFFFFFF);
1230 if (SubIdx == AMDGPU::sub1)
1231 return MachineOperand::CreateImm(Op.getImm() >> 32);
1233 llvm_unreachable("Unhandled register index for immediate");
1236 unsigned SubReg = buildExtractSubReg(MII, MRI, Op, SuperRC,
1238 return MachineOperand::CreateReg(SubReg, false);
1241 unsigned SIInstrInfo::split64BitImm(SmallVectorImpl<MachineInstr *> &Worklist,
1242 MachineBasicBlock::iterator MI,
1243 MachineRegisterInfo &MRI,
1244 const TargetRegisterClass *RC,
1245 const MachineOperand &Op) const {
1246 MachineBasicBlock *MBB = MI->getParent();
1247 DebugLoc DL = MI->getDebugLoc();
1248 unsigned LoDst = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1249 unsigned HiDst = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1250 unsigned Dst = MRI.createVirtualRegister(RC);
1252 MachineInstr *Lo = BuildMI(*MBB, MI, DL, get(AMDGPU::S_MOV_B32),
1254 .addImm(Op.getImm() & 0xFFFFFFFF);
1255 MachineInstr *Hi = BuildMI(*MBB, MI, DL, get(AMDGPU::S_MOV_B32),
1257 .addImm(Op.getImm() >> 32);
1259 BuildMI(*MBB, MI, DL, get(TargetOpcode::REG_SEQUENCE), Dst)
1261 .addImm(AMDGPU::sub0)
1263 .addImm(AMDGPU::sub1);
1265 Worklist.push_back(Lo);
1266 Worklist.push_back(Hi);
1271 bool SIInstrInfo::isOperandLegal(const MachineInstr *MI, unsigned OpIdx,
1272 const MachineOperand *MO) const {
1273 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1274 const MCInstrDesc &InstDesc = get(MI->getOpcode());
1275 const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpIdx];
1276 const TargetRegisterClass *DefinedRC =
1277 OpInfo.RegClass != -1 ? RI.getRegClass(OpInfo.RegClass) : nullptr;
1279 MO = &MI->getOperand(OpIdx);
1281 if (usesConstantBus(MRI, *MO)) {
1282 unsigned SGPRUsed = MO->isReg() ? MO->getReg() : AMDGPU::NoRegister;
1283 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1286 if (usesConstantBus(MRI, MI->getOperand(i)) &&
1287 MI->getOperand(i).isReg() && MI->getOperand(i).getReg() != SGPRUsed) {
1295 const TargetRegisterClass *RC = MRI.getRegClass(MO->getReg());
1296 return RI.getCommonSubClass(RC, RI.getRegClass(OpInfo.RegClass));
1300 // Handle non-register types that are treated like immediates.
1301 assert(MO->isImm() || MO->isFPImm() || MO->isTargetIndex() || MO->isFI());
1304 // This operand expects an immediate.
1308 return isImmOperandLegal(MI, OpIdx, *MO);
1311 void SIInstrInfo::legalizeOperands(MachineInstr *MI) const {
1312 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1314 int Src0Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1315 AMDGPU::OpName::src0);
1316 int Src1Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1317 AMDGPU::OpName::src1);
1318 int Src2Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1319 AMDGPU::OpName::src2);
1322 if (isVOP2(MI->getOpcode()) && Src1Idx != -1) {
1324 if (!isOperandLegal(MI, Src0Idx))
1325 legalizeOpWithMove(MI, Src0Idx);
1328 if (isOperandLegal(MI, Src1Idx))
1331 // Usually src0 of VOP2 instructions allow more types of inputs
1332 // than src1, so try to commute the instruction to decrease our
1333 // chances of having to insert a MOV instruction to legalize src1.
1334 if (MI->isCommutable()) {
1335 if (commuteInstruction(MI))
1336 // If we are successful in commuting, then we know MI is legal, so
1341 legalizeOpWithMove(MI, Src1Idx);
1345 // XXX - Do any VOP3 instructions read VCC?
1347 if (isVOP3(MI->getOpcode())) {
1348 int VOP3Idx[3] = {Src0Idx, Src1Idx, Src2Idx};
1349 unsigned SGPRReg = AMDGPU::NoRegister;
1350 for (unsigned i = 0; i < 3; ++i) {
1351 int Idx = VOP3Idx[i];
1354 MachineOperand &MO = MI->getOperand(Idx);
1357 if (!RI.isSGPRClass(MRI.getRegClass(MO.getReg())))
1358 continue; // VGPRs are legal
1360 assert(MO.getReg() != AMDGPU::SCC && "SCC operand to VOP3 instruction");
1362 if (SGPRReg == AMDGPU::NoRegister || SGPRReg == MO.getReg()) {
1363 SGPRReg = MO.getReg();
1364 // We can use one SGPR in each VOP3 instruction.
1367 } else if (!isLiteralConstant(MO)) {
1368 // If it is not a register and not a literal constant, then it must be
1369 // an inline constant which is always legal.
1372 // If we make it this far, then the operand is not legal and we must
1374 legalizeOpWithMove(MI, Idx);
1378 // Legalize REG_SEQUENCE and PHI
1379 // The register class of the operands much be the same type as the register
1380 // class of the output.
1381 if (MI->getOpcode() == AMDGPU::REG_SEQUENCE ||
1382 MI->getOpcode() == AMDGPU::PHI) {
1383 const TargetRegisterClass *RC = nullptr, *SRC = nullptr, *VRC = nullptr;
1384 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
1385 if (!MI->getOperand(i).isReg() ||
1386 !TargetRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg()))
1388 const TargetRegisterClass *OpRC =
1389 MRI.getRegClass(MI->getOperand(i).getReg());
1390 if (RI.hasVGPRs(OpRC)) {
1397 // If any of the operands are VGPR registers, then they all most be
1398 // otherwise we will create illegal VGPR->SGPR copies when legalizing
1400 if (VRC || !RI.isSGPRClass(getOpRegClass(*MI, 0))) {
1403 VRC = RI.getEquivalentVGPRClass(SRC);
1410 // Update all the operands so they have the same type.
1411 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
1412 if (!MI->getOperand(i).isReg() ||
1413 !TargetRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg()))
1415 unsigned DstReg = MRI.createVirtualRegister(RC);
1416 MachineBasicBlock *InsertBB;
1417 MachineBasicBlock::iterator Insert;
1418 if (MI->getOpcode() == AMDGPU::REG_SEQUENCE) {
1419 InsertBB = MI->getParent();
1422 // MI is a PHI instruction.
1423 InsertBB = MI->getOperand(i + 1).getMBB();
1424 Insert = InsertBB->getFirstTerminator();
1426 BuildMI(*InsertBB, Insert, MI->getDebugLoc(),
1427 get(AMDGPU::COPY), DstReg)
1428 .addOperand(MI->getOperand(i));
1429 MI->getOperand(i).setReg(DstReg);
1433 // Legalize INSERT_SUBREG
1434 // src0 must have the same register class as dst
1435 if (MI->getOpcode() == AMDGPU::INSERT_SUBREG) {
1436 unsigned Dst = MI->getOperand(0).getReg();
1437 unsigned Src0 = MI->getOperand(1).getReg();
1438 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
1439 const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0);
1440 if (DstRC != Src0RC) {
1441 MachineBasicBlock &MBB = *MI->getParent();
1442 unsigned NewSrc0 = MRI.createVirtualRegister(DstRC);
1443 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::COPY), NewSrc0)
1445 MI->getOperand(1).setReg(NewSrc0);
1450 // Legalize MUBUF* instructions
1451 // FIXME: If we start using the non-addr64 instructions for compute, we
1452 // may need to legalize them here.
1454 AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::srsrc);
1455 if (SRsrcIdx != -1) {
1456 // We have an MUBUF instruction
1457 MachineOperand *SRsrc = &MI->getOperand(SRsrcIdx);
1458 unsigned SRsrcRC = get(MI->getOpcode()).OpInfo[SRsrcIdx].RegClass;
1459 if (RI.getCommonSubClass(MRI.getRegClass(SRsrc->getReg()),
1460 RI.getRegClass(SRsrcRC))) {
1461 // The operands are legal.
1462 // FIXME: We may need to legalize operands besided srsrc.
1466 MachineBasicBlock &MBB = *MI->getParent();
1467 // Extract the the ptr from the resource descriptor.
1469 // SRsrcPtrLo = srsrc:sub0
1470 unsigned SRsrcPtrLo = buildExtractSubReg(MI, MRI, *SRsrc,
1471 &AMDGPU::VReg_128RegClass, AMDGPU::sub0, &AMDGPU::VReg_32RegClass);
1473 // SRsrcPtrHi = srsrc:sub1
1474 unsigned SRsrcPtrHi = buildExtractSubReg(MI, MRI, *SRsrc,
1475 &AMDGPU::VReg_128RegClass, AMDGPU::sub1, &AMDGPU::VReg_32RegClass);
1477 // Create an empty resource descriptor
1478 unsigned Zero64 = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
1479 unsigned SRsrcFormatLo = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1480 unsigned SRsrcFormatHi = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1481 unsigned NewSRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass);
1484 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B64),
1488 // SRsrcFormatLo = RSRC_DATA_FORMAT{31-0}
1489 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1491 .addImm(AMDGPU::RSRC_DATA_FORMAT & 0xFFFFFFFF);
1493 // SRsrcFormatHi = RSRC_DATA_FORMAT{63-32}
1494 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1496 .addImm(AMDGPU::RSRC_DATA_FORMAT >> 32);
1498 // NewSRsrc = {Zero64, SRsrcFormat}
1499 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE),
1502 .addImm(AMDGPU::sub0_sub1)
1503 .addReg(SRsrcFormatLo)
1504 .addImm(AMDGPU::sub2)
1505 .addReg(SRsrcFormatHi)
1506 .addImm(AMDGPU::sub3);
1508 MachineOperand *VAddr = getNamedOperand(*MI, AMDGPU::OpName::vaddr);
1509 unsigned NewVAddr = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
1510 unsigned NewVAddrLo;
1511 unsigned NewVAddrHi;
1513 // This is already an ADDR64 instruction so we need to add the pointer
1514 // extracted from the resource descriptor to the current value of VAddr.
1515 NewVAddrLo = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
1516 NewVAddrHi = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
1518 // NewVaddrLo = SRsrcPtrLo + VAddr:sub0
1519 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::V_ADD_I32_e32),
1522 .addReg(VAddr->getReg(), 0, AMDGPU::sub0)
1523 .addReg(AMDGPU::VCC, RegState::ImplicitDefine);
1525 // NewVaddrHi = SRsrcPtrHi + VAddr:sub1
1526 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::V_ADDC_U32_e32),
1529 .addReg(VAddr->getReg(), 0, AMDGPU::sub1)
1530 .addReg(AMDGPU::VCC, RegState::ImplicitDefine)
1531 .addReg(AMDGPU::VCC, RegState::Implicit);
1534 // This instructions is the _OFFSET variant, so we need to convert it to
1536 MachineOperand *VData = getNamedOperand(*MI, AMDGPU::OpName::vdata);
1537 MachineOperand *Offset = getNamedOperand(*MI, AMDGPU::OpName::offset);
1538 MachineOperand *SOffset = getNamedOperand(*MI, AMDGPU::OpName::soffset);
1539 assert(SOffset->isImm() && SOffset->getImm() == 0 && "Legalizing MUBUF "
1540 "with non-zero soffset is not implemented");
1543 // Create the new instruction.
1544 unsigned Addr64Opcode = AMDGPU::getAddr64Inst(MI->getOpcode());
1545 MachineInstr *Addr64 =
1546 BuildMI(MBB, MI, MI->getDebugLoc(), get(Addr64Opcode))
1549 .addReg(AMDGPU::NoRegister) // Dummy value for vaddr.
1550 // This will be replaced later
1551 // with the new value of vaddr.
1552 .addOperand(*Offset);
1554 MI->removeFromParent();
1557 NewVAddrLo = SRsrcPtrLo;
1558 NewVAddrHi = SRsrcPtrHi;
1559 VAddr = getNamedOperand(*MI, AMDGPU::OpName::vaddr);
1560 SRsrc = getNamedOperand(*MI, AMDGPU::OpName::srsrc);
1563 // NewVaddr = {NewVaddrHi, NewVaddrLo}
1564 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE),
1567 .addImm(AMDGPU::sub0)
1569 .addImm(AMDGPU::sub1);
1572 // Update the instruction to use NewVaddr
1573 VAddr->setReg(NewVAddr);
1574 // Update the instruction to use NewSRsrc
1575 SRsrc->setReg(NewSRsrc);
1579 void SIInstrInfo::splitSMRD(MachineInstr *MI,
1580 const TargetRegisterClass *HalfRC,
1581 unsigned HalfImmOp, unsigned HalfSGPROp,
1582 MachineInstr *&Lo, MachineInstr *&Hi) const {
1584 DebugLoc DL = MI->getDebugLoc();
1585 MachineBasicBlock *MBB = MI->getParent();
1586 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
1587 unsigned RegLo = MRI.createVirtualRegister(HalfRC);
1588 unsigned RegHi = MRI.createVirtualRegister(HalfRC);
1589 unsigned HalfSize = HalfRC->getSize();
1590 const MachineOperand *OffOp =
1591 getNamedOperand(*MI, AMDGPU::OpName::offset);
1592 const MachineOperand *SBase = getNamedOperand(*MI, AMDGPU::OpName::sbase);
1595 // Handle the _IMM variant
1596 unsigned LoOffset = OffOp->getImm();
1597 unsigned HiOffset = LoOffset + (HalfSize / 4);
1598 Lo = BuildMI(*MBB, MI, DL, get(HalfImmOp), RegLo)
1602 if (!isUInt<8>(HiOffset)) {
1603 unsigned OffsetSGPR =
1604 MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
1605 BuildMI(*MBB, MI, DL, get(AMDGPU::S_MOV_B32), OffsetSGPR)
1606 .addImm(HiOffset << 2); // The immediate offset is in dwords,
1607 // but offset in register is in bytes.
1608 Hi = BuildMI(*MBB, MI, DL, get(HalfSGPROp), RegHi)
1610 .addReg(OffsetSGPR);
1612 Hi = BuildMI(*MBB, MI, DL, get(HalfImmOp), RegHi)
1617 // Handle the _SGPR variant
1618 MachineOperand *SOff = getNamedOperand(*MI, AMDGPU::OpName::soff);
1619 Lo = BuildMI(*MBB, MI, DL, get(HalfSGPROp), RegLo)
1622 unsigned OffsetSGPR = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
1623 BuildMI(*MBB, MI, DL, get(AMDGPU::S_ADD_I32), OffsetSGPR)
1626 Hi = BuildMI(*MBB, MI, DL, get(HalfSGPROp))
1628 .addReg(OffsetSGPR);
1631 unsigned SubLo, SubHi;
1634 SubLo = AMDGPU::sub0;
1635 SubHi = AMDGPU::sub1;
1638 SubLo = AMDGPU::sub0_sub1;
1639 SubHi = AMDGPU::sub2_sub3;
1642 SubLo = AMDGPU::sub0_sub1_sub2_sub3;
1643 SubHi = AMDGPU::sub4_sub5_sub6_sub7;
1646 SubLo = AMDGPU::sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7;
1647 SubHi = AMDGPU::sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15;
1650 llvm_unreachable("Unhandled HalfSize");
1653 BuildMI(*MBB, MI, DL, get(AMDGPU::REG_SEQUENCE))
1654 .addOperand(MI->getOperand(0))
1661 void SIInstrInfo::moveSMRDToVALU(MachineInstr *MI, MachineRegisterInfo &MRI) const {
1662 MachineBasicBlock *MBB = MI->getParent();
1663 switch (MI->getOpcode()) {
1664 case AMDGPU::S_LOAD_DWORD_IMM:
1665 case AMDGPU::S_LOAD_DWORD_SGPR:
1666 case AMDGPU::S_LOAD_DWORDX2_IMM:
1667 case AMDGPU::S_LOAD_DWORDX2_SGPR:
1668 case AMDGPU::S_LOAD_DWORDX4_IMM:
1669 case AMDGPU::S_LOAD_DWORDX4_SGPR: {
1670 unsigned NewOpcode = getVALUOp(*MI);
1674 if (MI->getOperand(2).isReg()) {
1675 RegOffset = MI->getOperand(2).getReg();
1678 assert(MI->getOperand(2).isImm());
1679 // SMRD instructions take a dword offsets and MUBUF instructions
1680 // take a byte offset.
1681 ImmOffset = MI->getOperand(2).getImm() << 2;
1682 RegOffset = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1683 if (isUInt<12>(ImmOffset)) {
1684 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1688 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1695 unsigned SRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass);
1696 unsigned DWord0 = RegOffset;
1697 unsigned DWord1 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1698 unsigned DWord2 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1699 unsigned DWord3 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1701 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord1)
1703 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord2)
1704 .addImm(AMDGPU::RSRC_DATA_FORMAT & 0xFFFFFFFF);
1705 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord3)
1706 .addImm(AMDGPU::RSRC_DATA_FORMAT >> 32);
1707 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), SRsrc)
1709 .addImm(AMDGPU::sub0)
1711 .addImm(AMDGPU::sub1)
1713 .addImm(AMDGPU::sub2)
1715 .addImm(AMDGPU::sub3);
1716 MI->setDesc(get(NewOpcode));
1717 if (MI->getOperand(2).isReg()) {
1718 MI->getOperand(2).setReg(MI->getOperand(1).getReg());
1720 MI->getOperand(2).ChangeToRegister(MI->getOperand(1).getReg(), false);
1722 MI->getOperand(1).setReg(SRsrc);
1723 MI->addOperand(*MBB->getParent(), MachineOperand::CreateImm(ImmOffset));
1725 const TargetRegisterClass *NewDstRC =
1726 RI.getRegClass(get(NewOpcode).OpInfo[0].RegClass);
1728 unsigned DstReg = MI->getOperand(0).getReg();
1729 unsigned NewDstReg = MRI.createVirtualRegister(NewDstRC);
1730 MRI.replaceRegWith(DstReg, NewDstReg);
1733 case AMDGPU::S_LOAD_DWORDX8_IMM:
1734 case AMDGPU::S_LOAD_DWORDX8_SGPR: {
1735 MachineInstr *Lo, *Hi;
1736 splitSMRD(MI, &AMDGPU::SReg_128RegClass, AMDGPU::S_LOAD_DWORDX4_IMM,
1737 AMDGPU::S_LOAD_DWORDX4_SGPR, Lo, Hi);
1738 MI->eraseFromParent();
1739 moveSMRDToVALU(Lo, MRI);
1740 moveSMRDToVALU(Hi, MRI);
1744 case AMDGPU::S_LOAD_DWORDX16_IMM:
1745 case AMDGPU::S_LOAD_DWORDX16_SGPR: {
1746 MachineInstr *Lo, *Hi;
1747 splitSMRD(MI, &AMDGPU::SReg_256RegClass, AMDGPU::S_LOAD_DWORDX8_IMM,
1748 AMDGPU::S_LOAD_DWORDX8_SGPR, Lo, Hi);
1749 MI->eraseFromParent();
1750 moveSMRDToVALU(Lo, MRI);
1751 moveSMRDToVALU(Hi, MRI);
1757 void SIInstrInfo::moveToVALU(MachineInstr &TopInst) const {
1758 SmallVector<MachineInstr *, 128> Worklist;
1759 Worklist.push_back(&TopInst);
1761 while (!Worklist.empty()) {
1762 MachineInstr *Inst = Worklist.pop_back_val();
1763 MachineBasicBlock *MBB = Inst->getParent();
1764 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
1766 unsigned Opcode = Inst->getOpcode();
1767 unsigned NewOpcode = getVALUOp(*Inst);
1769 // Handle some special cases
1772 if (isSMRD(Inst->getOpcode())) {
1773 moveSMRDToVALU(Inst, MRI);
1776 case AMDGPU::S_MOV_B64: {
1777 DebugLoc DL = Inst->getDebugLoc();
1779 // If the source operand is a register we can replace this with a
1781 if (Inst->getOperand(1).isReg()) {
1782 MachineInstr *Copy = BuildMI(*MBB, Inst, DL, get(TargetOpcode::COPY))
1783 .addOperand(Inst->getOperand(0))
1784 .addOperand(Inst->getOperand(1));
1785 Worklist.push_back(Copy);
1787 // Otherwise, we need to split this into two movs, because there is
1788 // no 64-bit VALU move instruction.
1789 unsigned Reg = Inst->getOperand(0).getReg();
1790 unsigned Dst = split64BitImm(Worklist,
1793 MRI.getRegClass(Reg),
1794 Inst->getOperand(1));
1795 MRI.replaceRegWith(Reg, Dst);
1797 Inst->eraseFromParent();
1800 case AMDGPU::S_AND_B64:
1801 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_AND_B32);
1802 Inst->eraseFromParent();
1805 case AMDGPU::S_OR_B64:
1806 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_OR_B32);
1807 Inst->eraseFromParent();
1810 case AMDGPU::S_XOR_B64:
1811 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_XOR_B32);
1812 Inst->eraseFromParent();
1815 case AMDGPU::S_NOT_B64:
1816 splitScalar64BitUnaryOp(Worklist, Inst, AMDGPU::S_NOT_B32);
1817 Inst->eraseFromParent();
1820 case AMDGPU::S_BCNT1_I32_B64:
1821 splitScalar64BitBCNT(Worklist, Inst);
1822 Inst->eraseFromParent();
1825 case AMDGPU::S_BFE_U64:
1826 case AMDGPU::S_BFE_I64:
1827 case AMDGPU::S_BFM_B64:
1828 llvm_unreachable("Moving this op to VALU not implemented");
1831 if (NewOpcode == AMDGPU::INSTRUCTION_LIST_END) {
1832 // We cannot move this instruction to the VALU, so we should try to
1833 // legalize its operands instead.
1834 legalizeOperands(Inst);
1838 // Use the new VALU Opcode.
1839 const MCInstrDesc &NewDesc = get(NewOpcode);
1840 Inst->setDesc(NewDesc);
1842 // Remove any references to SCC. Vector instructions can't read from it, and
1843 // We're just about to add the implicit use / defs of VCC, and we don't want
1845 for (unsigned i = Inst->getNumOperands() - 1; i > 0; --i) {
1846 MachineOperand &Op = Inst->getOperand(i);
1847 if (Op.isReg() && Op.getReg() == AMDGPU::SCC)
1848 Inst->RemoveOperand(i);
1851 if (Opcode == AMDGPU::S_SEXT_I32_I8 || Opcode == AMDGPU::S_SEXT_I32_I16) {
1852 // We are converting these to a BFE, so we need to add the missing
1853 // operands for the size and offset.
1854 unsigned Size = (Opcode == AMDGPU::S_SEXT_I32_I8) ? 8 : 16;
1855 Inst->addOperand(MachineOperand::CreateImm(0));
1856 Inst->addOperand(MachineOperand::CreateImm(Size));
1858 } else if (Opcode == AMDGPU::S_BCNT1_I32_B32) {
1859 // The VALU version adds the second operand to the result, so insert an
1861 Inst->addOperand(MachineOperand::CreateImm(0));
1864 addDescImplicitUseDef(NewDesc, Inst);
1866 if (Opcode == AMDGPU::S_BFE_I32 || Opcode == AMDGPU::S_BFE_U32) {
1867 const MachineOperand &OffsetWidthOp = Inst->getOperand(2);
1868 // If we need to move this to VGPRs, we need to unpack the second operand
1869 // back into the 2 separate ones for bit offset and width.
1870 assert(OffsetWidthOp.isImm() &&
1871 "Scalar BFE is only implemented for constant width and offset");
1872 uint32_t Imm = OffsetWidthOp.getImm();
1874 uint32_t Offset = Imm & 0x3f; // Extract bits [5:0].
1875 uint32_t BitWidth = (Imm & 0x7f0000) >> 16; // Extract bits [22:16].
1876 Inst->RemoveOperand(2); // Remove old immediate.
1877 Inst->addOperand(MachineOperand::CreateImm(Offset));
1878 Inst->addOperand(MachineOperand::CreateImm(BitWidth));
1881 // Update the destination register class.
1883 const TargetRegisterClass *NewDstRC = getOpRegClass(*Inst, 0);
1886 // For target instructions, getOpRegClass just returns the virtual
1887 // register class associated with the operand, so we need to find an
1888 // equivalent VGPR register class in order to move the instruction to the
1892 case AMDGPU::REG_SEQUENCE:
1893 case AMDGPU::INSERT_SUBREG:
1894 if (RI.hasVGPRs(NewDstRC))
1896 NewDstRC = RI.getEquivalentVGPRClass(NewDstRC);
1904 unsigned DstReg = Inst->getOperand(0).getReg();
1905 unsigned NewDstReg = MRI.createVirtualRegister(NewDstRC);
1906 MRI.replaceRegWith(DstReg, NewDstReg);
1908 // Legalize the operands
1909 legalizeOperands(Inst);
1911 for (MachineRegisterInfo::use_iterator I = MRI.use_begin(NewDstReg),
1912 E = MRI.use_end(); I != E; ++I) {
1913 MachineInstr &UseMI = *I->getParent();
1914 if (!canReadVGPR(UseMI, I.getOperandNo())) {
1915 Worklist.push_back(&UseMI);
1921 //===----------------------------------------------------------------------===//
1922 // Indirect addressing callbacks
1923 //===----------------------------------------------------------------------===//
1925 unsigned SIInstrInfo::calculateIndirectAddress(unsigned RegIndex,
1926 unsigned Channel) const {
1927 assert(Channel == 0);
1931 const TargetRegisterClass *SIInstrInfo::getIndirectAddrRegClass() const {
1932 return &AMDGPU::VReg_32RegClass;
1935 void SIInstrInfo::splitScalar64BitUnaryOp(
1936 SmallVectorImpl<MachineInstr *> &Worklist,
1938 unsigned Opcode) const {
1939 MachineBasicBlock &MBB = *Inst->getParent();
1940 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
1942 MachineOperand &Dest = Inst->getOperand(0);
1943 MachineOperand &Src0 = Inst->getOperand(1);
1944 DebugLoc DL = Inst->getDebugLoc();
1946 MachineBasicBlock::iterator MII = Inst;
1948 const MCInstrDesc &InstDesc = get(Opcode);
1949 const TargetRegisterClass *Src0RC = Src0.isReg() ?
1950 MRI.getRegClass(Src0.getReg()) :
1951 &AMDGPU::SGPR_32RegClass;
1953 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
1955 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
1956 AMDGPU::sub0, Src0SubRC);
1958 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
1959 const TargetRegisterClass *DestSubRC = RI.getSubRegClass(DestRC, AMDGPU::sub0);
1961 unsigned DestSub0 = MRI.createVirtualRegister(DestRC);
1962 MachineInstr *LoHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub0)
1963 .addOperand(SrcReg0Sub0);
1965 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
1966 AMDGPU::sub1, Src0SubRC);
1968 unsigned DestSub1 = MRI.createVirtualRegister(DestSubRC);
1969 MachineInstr *HiHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub1)
1970 .addOperand(SrcReg0Sub1);
1972 unsigned FullDestReg = MRI.createVirtualRegister(DestRC);
1973 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
1975 .addImm(AMDGPU::sub0)
1977 .addImm(AMDGPU::sub1);
1979 MRI.replaceRegWith(Dest.getReg(), FullDestReg);
1981 // Try to legalize the operands in case we need to swap the order to keep it
1983 Worklist.push_back(LoHalf);
1984 Worklist.push_back(HiHalf);
1987 void SIInstrInfo::splitScalar64BitBinaryOp(
1988 SmallVectorImpl<MachineInstr *> &Worklist,
1990 unsigned Opcode) const {
1991 MachineBasicBlock &MBB = *Inst->getParent();
1992 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
1994 MachineOperand &Dest = Inst->getOperand(0);
1995 MachineOperand &Src0 = Inst->getOperand(1);
1996 MachineOperand &Src1 = Inst->getOperand(2);
1997 DebugLoc DL = Inst->getDebugLoc();
1999 MachineBasicBlock::iterator MII = Inst;
2001 const MCInstrDesc &InstDesc = get(Opcode);
2002 const TargetRegisterClass *Src0RC = Src0.isReg() ?
2003 MRI.getRegClass(Src0.getReg()) :
2004 &AMDGPU::SGPR_32RegClass;
2006 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
2007 const TargetRegisterClass *Src1RC = Src1.isReg() ?
2008 MRI.getRegClass(Src1.getReg()) :
2009 &AMDGPU::SGPR_32RegClass;
2011 const TargetRegisterClass *Src1SubRC = RI.getSubRegClass(Src1RC, AMDGPU::sub0);
2013 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2014 AMDGPU::sub0, Src0SubRC);
2015 MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
2016 AMDGPU::sub0, Src1SubRC);
2018 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
2019 const TargetRegisterClass *DestSubRC = RI.getSubRegClass(DestRC, AMDGPU::sub0);
2021 unsigned DestSub0 = MRI.createVirtualRegister(DestRC);
2022 MachineInstr *LoHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub0)
2023 .addOperand(SrcReg0Sub0)
2024 .addOperand(SrcReg1Sub0);
2026 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
2027 AMDGPU::sub1, Src0SubRC);
2028 MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
2029 AMDGPU::sub1, Src1SubRC);
2031 unsigned DestSub1 = MRI.createVirtualRegister(DestSubRC);
2032 MachineInstr *HiHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub1)
2033 .addOperand(SrcReg0Sub1)
2034 .addOperand(SrcReg1Sub1);
2036 unsigned FullDestReg = MRI.createVirtualRegister(DestRC);
2037 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
2039 .addImm(AMDGPU::sub0)
2041 .addImm(AMDGPU::sub1);
2043 MRI.replaceRegWith(Dest.getReg(), FullDestReg);
2045 // Try to legalize the operands in case we need to swap the order to keep it
2047 Worklist.push_back(LoHalf);
2048 Worklist.push_back(HiHalf);
2051 void SIInstrInfo::splitScalar64BitBCNT(SmallVectorImpl<MachineInstr *> &Worklist,
2052 MachineInstr *Inst) const {
2053 MachineBasicBlock &MBB = *Inst->getParent();
2054 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2056 MachineBasicBlock::iterator MII = Inst;
2057 DebugLoc DL = Inst->getDebugLoc();
2059 MachineOperand &Dest = Inst->getOperand(0);
2060 MachineOperand &Src = Inst->getOperand(1);
2062 const MCInstrDesc &InstDesc = get(AMDGPU::V_BCNT_U32_B32_e32);
2063 const TargetRegisterClass *SrcRC = Src.isReg() ?
2064 MRI.getRegClass(Src.getReg()) :
2065 &AMDGPU::SGPR_32RegClass;
2067 unsigned MidReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2068 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
2070 const TargetRegisterClass *SrcSubRC = RI.getSubRegClass(SrcRC, AMDGPU::sub0);
2072 MachineOperand SrcRegSub0 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC,
2073 AMDGPU::sub0, SrcSubRC);
2074 MachineOperand SrcRegSub1 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC,
2075 AMDGPU::sub1, SrcSubRC);
2077 MachineInstr *First = BuildMI(MBB, MII, DL, InstDesc, MidReg)
2078 .addOperand(SrcRegSub0)
2081 MachineInstr *Second = BuildMI(MBB, MII, DL, InstDesc, ResultReg)
2082 .addOperand(SrcRegSub1)
2085 MRI.replaceRegWith(Dest.getReg(), ResultReg);
2087 Worklist.push_back(First);
2088 Worklist.push_back(Second);
2091 void SIInstrInfo::addDescImplicitUseDef(const MCInstrDesc &NewDesc,
2092 MachineInstr *Inst) const {
2093 // Add the implict and explicit register definitions.
2094 if (NewDesc.ImplicitUses) {
2095 for (unsigned i = 0; NewDesc.ImplicitUses[i]; ++i) {
2096 unsigned Reg = NewDesc.ImplicitUses[i];
2097 Inst->addOperand(MachineOperand::CreateReg(Reg, false, true));
2101 if (NewDesc.ImplicitDefs) {
2102 for (unsigned i = 0; NewDesc.ImplicitDefs[i]; ++i) {
2103 unsigned Reg = NewDesc.ImplicitDefs[i];
2104 Inst->addOperand(MachineOperand::CreateReg(Reg, true, true));
2109 MachineInstrBuilder SIInstrInfo::buildIndirectWrite(
2110 MachineBasicBlock *MBB,
2111 MachineBasicBlock::iterator I,
2113 unsigned Address, unsigned OffsetReg) const {
2114 const DebugLoc &DL = MBB->findDebugLoc(I);
2115 unsigned IndirectBaseReg = AMDGPU::VReg_32RegClass.getRegister(
2116 getIndirectIndexBegin(*MBB->getParent()));
2118 return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_DST_V1))
2119 .addReg(IndirectBaseReg, RegState::Define)
2120 .addOperand(I->getOperand(0))
2121 .addReg(IndirectBaseReg)
2127 MachineInstrBuilder SIInstrInfo::buildIndirectRead(
2128 MachineBasicBlock *MBB,
2129 MachineBasicBlock::iterator I,
2131 unsigned Address, unsigned OffsetReg) const {
2132 const DebugLoc &DL = MBB->findDebugLoc(I);
2133 unsigned IndirectBaseReg = AMDGPU::VReg_32RegClass.getRegister(
2134 getIndirectIndexBegin(*MBB->getParent()));
2136 return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_SRC))
2137 .addOperand(I->getOperand(0))
2138 .addOperand(I->getOperand(1))
2139 .addReg(IndirectBaseReg)
2145 void SIInstrInfo::reserveIndirectRegisters(BitVector &Reserved,
2146 const MachineFunction &MF) const {
2147 int End = getIndirectIndexEnd(MF);
2148 int Begin = getIndirectIndexBegin(MF);
2154 for (int Index = Begin; Index <= End; ++Index)
2155 Reserved.set(AMDGPU::VReg_32RegClass.getRegister(Index));
2157 for (int Index = std::max(0, Begin - 1); Index <= End; ++Index)
2158 Reserved.set(AMDGPU::VReg_64RegClass.getRegister(Index));
2160 for (int Index = std::max(0, Begin - 2); Index <= End; ++Index)
2161 Reserved.set(AMDGPU::VReg_96RegClass.getRegister(Index));
2163 for (int Index = std::max(0, Begin - 3); Index <= End; ++Index)
2164 Reserved.set(AMDGPU::VReg_128RegClass.getRegister(Index));
2166 for (int Index = std::max(0, Begin - 7); Index <= End; ++Index)
2167 Reserved.set(AMDGPU::VReg_256RegClass.getRegister(Index));
2169 for (int Index = std::max(0, Begin - 15); Index <= End; ++Index)
2170 Reserved.set(AMDGPU::VReg_512RegClass.getRegister(Index));
2173 MachineOperand *SIInstrInfo::getNamedOperand(MachineInstr &MI,
2174 unsigned OperandName) const {
2175 int Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), OperandName);
2179 return &MI.getOperand(Idx);