1 //===-- SIInstrInfo.cpp - SI Instruction Information ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief SI Implementation of TargetInstrInfo.
13 //===----------------------------------------------------------------------===//
16 #include "SIInstrInfo.h"
17 #include "AMDGPUTargetMachine.h"
18 #include "SIDefines.h"
19 #include "SIMachineFunctionInfo.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/IR/Function.h"
23 #include "llvm/MC/MCInstrDesc.h"
27 SIInstrInfo::SIInstrInfo(const AMDGPUSubtarget &st)
28 : AMDGPUInstrInfo(st),
31 //===----------------------------------------------------------------------===//
32 // TargetInstrInfo callbacks
33 //===----------------------------------------------------------------------===//
35 static unsigned getNumOperandsNoGlue(SDNode *Node) {
36 unsigned N = Node->getNumOperands();
37 while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue)
42 static SDValue findChainOperand(SDNode *Load) {
43 SDValue LastOp = Load->getOperand(getNumOperandsNoGlue(Load) - 1);
44 assert(LastOp.getValueType() == MVT::Other && "Chain missing from load node");
48 bool SIInstrInfo::areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1,
50 int64_t &Offset1) const {
51 if (!Load0->isMachineOpcode() || !Load1->isMachineOpcode())
54 unsigned Opc0 = Load0->getMachineOpcode();
55 unsigned Opc1 = Load1->getMachineOpcode();
57 // Make sure both are actually loads.
58 if (!get(Opc0).mayLoad() || !get(Opc1).mayLoad())
61 if (isDS(Opc0) && isDS(Opc1)) {
62 assert(getNumOperandsNoGlue(Load0) == getNumOperandsNoGlue(Load1));
64 // TODO: Also shouldn't see read2st
65 assert(Opc0 != AMDGPU::DS_READ2_B32 &&
66 Opc0 != AMDGPU::DS_READ2_B64 &&
67 Opc1 != AMDGPU::DS_READ2_B32 &&
68 Opc1 != AMDGPU::DS_READ2_B64);
71 if (Load0->getOperand(1) != Load1->getOperand(1))
75 if (findChainOperand(Load0) != findChainOperand(Load1))
78 Offset0 = cast<ConstantSDNode>(Load0->getOperand(2))->getZExtValue();
79 Offset1 = cast<ConstantSDNode>(Load1->getOperand(2))->getZExtValue();
83 if (isSMRD(Opc0) && isSMRD(Opc1)) {
84 assert(getNumOperandsNoGlue(Load0) == getNumOperandsNoGlue(Load1));
87 if (Load0->getOperand(0) != Load1->getOperand(0))
91 if (findChainOperand(Load0) != findChainOperand(Load1))
94 Offset0 = cast<ConstantSDNode>(Load0->getOperand(1))->getZExtValue();
95 Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue();
99 // MUBUF and MTBUF can access the same addresses.
100 if ((isMUBUF(Opc0) || isMTBUF(Opc0)) && (isMUBUF(Opc1) || isMTBUF(Opc1))) {
101 // Skip if an SGPR offset is applied. I don't think we ever emit any of
102 // variants that use this currently.
103 int SoffsetIdx = AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::soffset);
104 if (SoffsetIdx != -1)
107 // getNamedOperandIdx returns the index for the MachineInstr's operands,
108 // which includes the result as the first operand. We are indexing into the
109 // MachineSDNode's operands, so we need to skip the result operand to get
114 if (findChainOperand(Load0) != findChainOperand(Load1))
117 // MUBUF and MTBUF have vaddr at different indices.
118 int VaddrIdx0 = AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::vaddr) - 1;
119 int VaddrIdx1 = AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::vaddr) - 1;
120 if (Load0->getOperand(VaddrIdx0) != Load1->getOperand(VaddrIdx1))
123 int OffIdx0 = AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::offset) - 1;
124 int OffIdx1 = AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::offset) - 1;
125 Offset0 = cast<ConstantSDNode>(Load0->getOperand(OffIdx0))->getZExtValue();
126 Offset1 = cast<ConstantSDNode>(Load1->getOperand(OffIdx1))->getZExtValue();
133 bool SIInstrInfo::getLdStBaseRegImmOfs(MachineInstr *LdSt,
134 unsigned &BaseReg, unsigned &Offset,
135 const TargetRegisterInfo *TRI) const {
136 unsigned Opc = LdSt->getOpcode();
138 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
139 AMDGPU::OpName::offset);
141 // Normal, single offset LDS instruction.
142 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
143 AMDGPU::OpName::addr);
145 BaseReg = AddrReg->getReg();
146 Offset = OffsetImm->getImm();
150 // The 2 offset instructions use offset0 and offset1 instead. We can treat
151 // these as a load with a single offset if the 2 offsets are consecutive. We
152 // will use this for some partially aligned loads.
153 const MachineOperand *Offset0Imm = getNamedOperand(*LdSt,
154 AMDGPU::OpName::offset0);
155 const MachineOperand *Offset1Imm = getNamedOperand(*LdSt,
156 AMDGPU::OpName::offset1);
158 uint8_t Offset0 = Offset0Imm->getImm();
159 uint8_t Offset1 = Offset1Imm->getImm();
160 assert(Offset1 > Offset0);
162 if (Offset1 - Offset0 == 1) {
163 // Each of these offsets is in element sized units, so we need to convert
164 // to bytes of the individual reads.
168 EltSize = getOpRegClass(*LdSt, 0)->getSize() / 2;
170 assert(LdSt->mayStore());
171 int Data0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data0);
172 EltSize = getOpRegClass(*LdSt, Data0Idx)->getSize();
175 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
176 AMDGPU::OpName::addr);
177 BaseReg = AddrReg->getReg();
178 Offset = EltSize * Offset0;
185 if (isMUBUF(Opc) || isMTBUF(Opc)) {
186 if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::soffset) != -1)
189 const MachineOperand *AddrReg = getNamedOperand(*LdSt,
190 AMDGPU::OpName::vaddr);
194 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
195 AMDGPU::OpName::offset);
196 BaseReg = AddrReg->getReg();
197 Offset = OffsetImm->getImm();
202 const MachineOperand *OffsetImm = getNamedOperand(*LdSt,
203 AMDGPU::OpName::offset);
207 const MachineOperand *SBaseReg = getNamedOperand(*LdSt,
208 AMDGPU::OpName::sbase);
209 BaseReg = SBaseReg->getReg();
210 Offset = OffsetImm->getImm();
218 SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
219 MachineBasicBlock::iterator MI, DebugLoc DL,
220 unsigned DestReg, unsigned SrcReg,
221 bool KillSrc) const {
223 // If we are trying to copy to or from SCC, there is a bug somewhere else in
224 // the backend. While it may be theoretically possible to do this, it should
225 // never be necessary.
226 assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC);
228 static const int16_t Sub0_15[] = {
229 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
230 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7,
231 AMDGPU::sub8, AMDGPU::sub9, AMDGPU::sub10, AMDGPU::sub11,
232 AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14, AMDGPU::sub15, 0
235 static const int16_t Sub0_7[] = {
236 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
237 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, 0
240 static const int16_t Sub0_3[] = {
241 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, 0
244 static const int16_t Sub0_2[] = {
245 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, 0
248 static const int16_t Sub0_1[] = {
249 AMDGPU::sub0, AMDGPU::sub1, 0
253 const int16_t *SubIndices;
255 if (AMDGPU::M0 == DestReg) {
256 // Check if M0 isn't already set to this value
257 for (MachineBasicBlock::reverse_iterator E = MBB.rend(),
258 I = MachineBasicBlock::reverse_iterator(MI); I != E; ++I) {
260 if (!I->definesRegister(AMDGPU::M0))
263 unsigned Opc = I->getOpcode();
264 if (Opc != TargetOpcode::COPY && Opc != AMDGPU::S_MOV_B32)
267 if (!I->readsRegister(SrcReg))
270 // The copy isn't necessary
275 if (AMDGPU::SReg_32RegClass.contains(DestReg)) {
276 assert(AMDGPU::SReg_32RegClass.contains(SrcReg));
277 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)
278 .addReg(SrcReg, getKillRegState(KillSrc));
281 } else if (AMDGPU::SReg_64RegClass.contains(DestReg)) {
282 assert(AMDGPU::SReg_64RegClass.contains(SrcReg));
283 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg)
284 .addReg(SrcReg, getKillRegState(KillSrc));
287 } else if (AMDGPU::SReg_128RegClass.contains(DestReg)) {
288 assert(AMDGPU::SReg_128RegClass.contains(SrcReg));
289 Opcode = AMDGPU::S_MOV_B32;
292 } else if (AMDGPU::SReg_256RegClass.contains(DestReg)) {
293 assert(AMDGPU::SReg_256RegClass.contains(SrcReg));
294 Opcode = AMDGPU::S_MOV_B32;
297 } else if (AMDGPU::SReg_512RegClass.contains(DestReg)) {
298 assert(AMDGPU::SReg_512RegClass.contains(SrcReg));
299 Opcode = AMDGPU::S_MOV_B32;
300 SubIndices = Sub0_15;
302 } else if (AMDGPU::VReg_32RegClass.contains(DestReg)) {
303 assert(AMDGPU::VReg_32RegClass.contains(SrcReg) ||
304 AMDGPU::SReg_32RegClass.contains(SrcReg));
305 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
306 .addReg(SrcReg, getKillRegState(KillSrc));
309 } else if (AMDGPU::VReg_64RegClass.contains(DestReg)) {
310 assert(AMDGPU::VReg_64RegClass.contains(SrcReg) ||
311 AMDGPU::SReg_64RegClass.contains(SrcReg));
312 Opcode = AMDGPU::V_MOV_B32_e32;
315 } else if (AMDGPU::VReg_96RegClass.contains(DestReg)) {
316 assert(AMDGPU::VReg_96RegClass.contains(SrcReg));
317 Opcode = AMDGPU::V_MOV_B32_e32;
320 } else if (AMDGPU::VReg_128RegClass.contains(DestReg)) {
321 assert(AMDGPU::VReg_128RegClass.contains(SrcReg) ||
322 AMDGPU::SReg_128RegClass.contains(SrcReg));
323 Opcode = AMDGPU::V_MOV_B32_e32;
326 } else if (AMDGPU::VReg_256RegClass.contains(DestReg)) {
327 assert(AMDGPU::VReg_256RegClass.contains(SrcReg) ||
328 AMDGPU::SReg_256RegClass.contains(SrcReg));
329 Opcode = AMDGPU::V_MOV_B32_e32;
332 } else if (AMDGPU::VReg_512RegClass.contains(DestReg)) {
333 assert(AMDGPU::VReg_512RegClass.contains(SrcReg) ||
334 AMDGPU::SReg_512RegClass.contains(SrcReg));
335 Opcode = AMDGPU::V_MOV_B32_e32;
336 SubIndices = Sub0_15;
339 llvm_unreachable("Can't copy register!");
342 while (unsigned SubIdx = *SubIndices++) {
343 MachineInstrBuilder Builder = BuildMI(MBB, MI, DL,
344 get(Opcode), RI.getSubReg(DestReg, SubIdx));
346 Builder.addReg(RI.getSubReg(SrcReg, SubIdx), getKillRegState(KillSrc));
349 Builder.addReg(DestReg, RegState::Define | RegState::Implicit);
353 unsigned SIInstrInfo::commuteOpcode(unsigned Opcode) const {
356 // Try to map original to commuted opcode
357 if ((NewOpc = AMDGPU::getCommuteRev(Opcode)) != -1)
360 // Try to map commuted to original opcode
361 if ((NewOpc = AMDGPU::getCommuteOrig(Opcode)) != -1)
367 void SIInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
368 MachineBasicBlock::iterator MI,
369 unsigned SrcReg, bool isKill,
371 const TargetRegisterClass *RC,
372 const TargetRegisterInfo *TRI) const {
373 MachineFunction *MF = MBB.getParent();
374 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
375 MachineRegisterInfo &MRI = MF->getRegInfo();
376 DebugLoc DL = MBB.findDebugLoc(MI);
377 unsigned KillFlag = isKill ? RegState::Kill : 0;
379 if (RI.hasVGPRs(RC)) {
380 LLVMContext &Ctx = MF->getFunction()->getContext();
381 Ctx.emitError("SIInstrInfo::storeRegToStackSlot - Can't spill VGPR!");
382 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), AMDGPU::VGPR0)
384 } else if (TRI->getCommonSubClass(RC, &AMDGPU::SGPR_32RegClass)) {
385 unsigned Lane = MFI->SpillTracker.reserveLanes(MRI, MF);
386 unsigned TgtReg = MFI->SpillTracker.LaneVGPR;
388 BuildMI(MBB, MI, DL, get(AMDGPU::V_WRITELANE_B32), TgtReg)
389 .addReg(SrcReg, KillFlag)
391 MFI->SpillTracker.addSpilledReg(FrameIndex, TgtReg, Lane);
392 } else if (RI.isSGPRClass(RC)) {
393 // We are only allowed to create one new instruction when spilling
394 // registers, so we need to use pseudo instruction for vector
397 // Reserve a spot in the spill tracker for each sub-register of
398 // the vector register.
399 unsigned NumSubRegs = RC->getSize() / 4;
400 unsigned FirstLane = MFI->SpillTracker.reserveLanes(MRI, MF, NumSubRegs);
401 MFI->SpillTracker.addSpilledReg(FrameIndex, MFI->SpillTracker.LaneVGPR,
405 switch (RC->getSize() * 8) {
406 case 64: Opcode = AMDGPU::SI_SPILL_S64_SAVE; break;
407 case 128: Opcode = AMDGPU::SI_SPILL_S128_SAVE; break;
408 case 256: Opcode = AMDGPU::SI_SPILL_S256_SAVE; break;
409 case 512: Opcode = AMDGPU::SI_SPILL_S512_SAVE; break;
410 default: llvm_unreachable("Cannot spill register class");
413 BuildMI(MBB, MI, DL, get(Opcode), MFI->SpillTracker.LaneVGPR)
417 llvm_unreachable("VGPR spilling not supported");
421 void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
422 MachineBasicBlock::iterator MI,
423 unsigned DestReg, int FrameIndex,
424 const TargetRegisterClass *RC,
425 const TargetRegisterInfo *TRI) const {
426 MachineFunction *MF = MBB.getParent();
427 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
428 DebugLoc DL = MBB.findDebugLoc(MI);
430 if (RI.hasVGPRs(RC)) {
431 LLVMContext &Ctx = MF->getFunction()->getContext();
432 Ctx.emitError("SIInstrInfo::loadRegToStackSlot - Can't retrieve spilled VGPR!");
433 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
435 } else if (RI.isSGPRClass(RC)){
437 switch(RC->getSize() * 8) {
438 case 32: Opcode = AMDGPU::SI_SPILL_S32_RESTORE; break;
439 case 64: Opcode = AMDGPU::SI_SPILL_S64_RESTORE; break;
440 case 128: Opcode = AMDGPU::SI_SPILL_S128_RESTORE; break;
441 case 256: Opcode = AMDGPU::SI_SPILL_S256_RESTORE; break;
442 case 512: Opcode = AMDGPU::SI_SPILL_S512_RESTORE; break;
443 default: llvm_unreachable("Cannot spill register class");
446 SIMachineFunctionInfo::SpilledReg Spill =
447 MFI->SpillTracker.getSpilledReg(FrameIndex);
449 BuildMI(MBB, MI, DL, get(Opcode), DestReg)
453 llvm_unreachable("VGPR spilling not supported");
457 static unsigned getNumSubRegsForSpillOp(unsigned Op) {
460 case AMDGPU::SI_SPILL_S512_SAVE:
461 case AMDGPU::SI_SPILL_S512_RESTORE:
463 case AMDGPU::SI_SPILL_S256_SAVE:
464 case AMDGPU::SI_SPILL_S256_RESTORE:
466 case AMDGPU::SI_SPILL_S128_SAVE:
467 case AMDGPU::SI_SPILL_S128_RESTORE:
469 case AMDGPU::SI_SPILL_S64_SAVE:
470 case AMDGPU::SI_SPILL_S64_RESTORE:
472 case AMDGPU::SI_SPILL_S32_RESTORE:
474 default: llvm_unreachable("Invalid spill opcode");
478 void SIInstrInfo::insertNOPs(MachineBasicBlock::iterator MI,
487 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(AMDGPU::S_NOP))
492 bool SIInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
493 SIMachineFunctionInfo *MFI =
494 MI->getParent()->getParent()->getInfo<SIMachineFunctionInfo>();
495 MachineBasicBlock &MBB = *MI->getParent();
496 DebugLoc DL = MBB.findDebugLoc(MI);
497 switch (MI->getOpcode()) {
498 default: return AMDGPUInstrInfo::expandPostRAPseudo(MI);
500 // SGPR register spill
501 case AMDGPU::SI_SPILL_S512_SAVE:
502 case AMDGPU::SI_SPILL_S256_SAVE:
503 case AMDGPU::SI_SPILL_S128_SAVE:
504 case AMDGPU::SI_SPILL_S64_SAVE: {
505 unsigned NumSubRegs = getNumSubRegsForSpillOp(MI->getOpcode());
506 unsigned FrameIndex = MI->getOperand(2).getImm();
508 for (unsigned i = 0, e = NumSubRegs; i < e; ++i) {
509 SIMachineFunctionInfo::SpilledReg Spill;
510 unsigned SubReg = RI.getPhysRegSubReg(MI->getOperand(1).getReg(),
511 &AMDGPU::SGPR_32RegClass, i);
512 Spill = MFI->SpillTracker.getSpilledReg(FrameIndex);
514 BuildMI(MBB, MI, DL, get(AMDGPU::V_WRITELANE_B32),
515 MI->getOperand(0).getReg())
517 .addImm(Spill.Lane + i);
519 MI->eraseFromParent();
523 // SGPR register restore
524 case AMDGPU::SI_SPILL_S512_RESTORE:
525 case AMDGPU::SI_SPILL_S256_RESTORE:
526 case AMDGPU::SI_SPILL_S128_RESTORE:
527 case AMDGPU::SI_SPILL_S64_RESTORE:
528 case AMDGPU::SI_SPILL_S32_RESTORE: {
529 unsigned NumSubRegs = getNumSubRegsForSpillOp(MI->getOpcode());
531 for (unsigned i = 0, e = NumSubRegs; i < e; ++i) {
532 SIMachineFunctionInfo::SpilledReg Spill;
533 unsigned FrameIndex = MI->getOperand(2).getImm();
534 unsigned SubReg = RI.getPhysRegSubReg(MI->getOperand(0).getReg(),
535 &AMDGPU::SGPR_32RegClass, i);
536 Spill = MFI->SpillTracker.getSpilledReg(FrameIndex);
538 BuildMI(MBB, MI, DL, get(AMDGPU::V_READLANE_B32), SubReg)
539 .addReg(MI->getOperand(1).getReg())
540 .addImm(Spill.Lane + i);
543 MI->eraseFromParent();
546 case AMDGPU::SI_CONSTDATA_PTR: {
547 unsigned Reg = MI->getOperand(0).getReg();
548 unsigned RegLo = RI.getSubReg(Reg, AMDGPU::sub0);
549 unsigned RegHi = RI.getSubReg(Reg, AMDGPU::sub1);
551 BuildMI(MBB, MI, DL, get(AMDGPU::S_GETPC_B64), Reg);
553 // Add 32-bit offset from this instruction to the start of the constant data.
554 BuildMI(MBB, MI, DL, get(AMDGPU::S_ADD_I32), RegLo)
556 .addTargetIndex(AMDGPU::TI_CONSTDATA_START)
557 .addReg(AMDGPU::SCC, RegState::Define | RegState::Implicit);
558 BuildMI(MBB, MI, DL, get(AMDGPU::S_ADDC_U32), RegHi)
561 .addReg(AMDGPU::SCC, RegState::Define | RegState::Implicit)
562 .addReg(AMDGPU::SCC, RegState::Implicit);
563 MI->eraseFromParent();
570 MachineInstr *SIInstrInfo::commuteInstruction(MachineInstr *MI,
573 if (MI->getNumOperands() < 3 || !MI->getOperand(1).isReg())
576 // Make sure it s legal to commute operands for VOP2.
577 if (isVOP2(MI->getOpcode()) &&
578 (!isOperandLegal(MI, 1, &MI->getOperand(2)) ||
579 !isOperandLegal(MI, 2, &MI->getOperand(1))))
582 if (!MI->getOperand(2).isReg()) {
583 // XXX: Commute instructions with FPImm operands
584 if (NewMI || MI->getOperand(2).isFPImm() ||
585 (!isVOP2(MI->getOpcode()) && !isVOP3(MI->getOpcode()))) {
589 // XXX: Commute VOP3 instructions with abs and neg set .
590 const MachineOperand *Abs = getNamedOperand(*MI, AMDGPU::OpName::abs);
591 const MachineOperand *Neg = getNamedOperand(*MI, AMDGPU::OpName::neg);
592 const MachineOperand *Src0Mods = getNamedOperand(*MI,
593 AMDGPU::OpName::src0_modifiers);
594 const MachineOperand *Src1Mods = getNamedOperand(*MI,
595 AMDGPU::OpName::src1_modifiers);
596 const MachineOperand *Src2Mods = getNamedOperand(*MI,
597 AMDGPU::OpName::src2_modifiers);
599 if ((Abs && Abs->getImm()) || (Neg && Neg->getImm()) ||
600 (Src0Mods && Src0Mods->getImm()) || (Src1Mods && Src1Mods->getImm()) ||
601 (Src2Mods && Src2Mods->getImm()))
604 unsigned Reg = MI->getOperand(1).getReg();
605 unsigned SubReg = MI->getOperand(1).getSubReg();
606 MI->getOperand(1).ChangeToImmediate(MI->getOperand(2).getImm());
607 MI->getOperand(2).ChangeToRegister(Reg, false);
608 MI->getOperand(2).setSubReg(SubReg);
610 MI = TargetInstrInfo::commuteInstruction(MI, NewMI);
614 MI->setDesc(get(commuteOpcode(MI->getOpcode())));
619 MachineInstr *SIInstrInfo::buildMovInstr(MachineBasicBlock *MBB,
620 MachineBasicBlock::iterator I,
622 unsigned SrcReg) const {
623 return BuildMI(*MBB, I, MBB->findDebugLoc(I), get(AMDGPU::V_MOV_B32_e32),
624 DstReg) .addReg(SrcReg);
627 bool SIInstrInfo::isMov(unsigned Opcode) const {
629 default: return false;
630 case AMDGPU::S_MOV_B32:
631 case AMDGPU::S_MOV_B64:
632 case AMDGPU::V_MOV_B32_e32:
633 case AMDGPU::V_MOV_B32_e64:
639 SIInstrInfo::isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
640 return RC != &AMDGPU::EXECRegRegClass;
644 SIInstrInfo::isTriviallyReMaterializable(const MachineInstr *MI,
645 AliasAnalysis *AA) const {
646 switch(MI->getOpcode()) {
647 default: return AMDGPUInstrInfo::isTriviallyReMaterializable(MI, AA);
648 case AMDGPU::S_MOV_B32:
649 case AMDGPU::S_MOV_B64:
650 case AMDGPU::V_MOV_B32_e32:
651 return MI->getOperand(1).isImm();
657 // Helper function generated by tablegen. We are wrapping this with
658 // an SIInstrInfo function that returns bool rather than int.
659 int isDS(uint16_t Opcode);
663 bool SIInstrInfo::isDS(uint16_t Opcode) const {
664 return ::AMDGPU::isDS(Opcode) != -1;
667 bool SIInstrInfo::isMIMG(uint16_t Opcode) const {
668 return get(Opcode).TSFlags & SIInstrFlags::MIMG;
671 bool SIInstrInfo::isSMRD(uint16_t Opcode) const {
672 return get(Opcode).TSFlags & SIInstrFlags::SMRD;
675 bool SIInstrInfo::isMUBUF(uint16_t Opcode) const {
676 return get(Opcode).TSFlags & SIInstrFlags::MUBUF;
679 bool SIInstrInfo::isMTBUF(uint16_t Opcode) const {
680 return get(Opcode).TSFlags & SIInstrFlags::MTBUF;
683 bool SIInstrInfo::isVOP1(uint16_t Opcode) const {
684 return get(Opcode).TSFlags & SIInstrFlags::VOP1;
687 bool SIInstrInfo::isVOP2(uint16_t Opcode) const {
688 return get(Opcode).TSFlags & SIInstrFlags::VOP2;
691 bool SIInstrInfo::isVOP3(uint16_t Opcode) const {
692 return get(Opcode).TSFlags & SIInstrFlags::VOP3;
695 bool SIInstrInfo::isVOPC(uint16_t Opcode) const {
696 return get(Opcode).TSFlags & SIInstrFlags::VOPC;
699 bool SIInstrInfo::isSALUInstr(const MachineInstr &MI) const {
700 return get(MI.getOpcode()).TSFlags & SIInstrFlags::SALU;
703 bool SIInstrInfo::isInlineConstant(const APInt &Imm) const {
704 int32_t Val = Imm.getSExtValue();
705 if (Val >= -16 && Val <= 64)
708 // The actual type of the operand does not seem to matter as long
709 // as the bits match one of the inline immediate values. For example:
711 // -nan has the hexadecimal encoding of 0xfffffffe which is -2 in decimal,
712 // so it is a legal inline immediate.
714 // 1065353216 has the hexadecimal encoding 0x3f800000 which is 1.0f in
715 // floating-point, so it is a legal inline immediate.
717 return (APInt::floatToBits(0.0f) == Imm) ||
718 (APInt::floatToBits(1.0f) == Imm) ||
719 (APInt::floatToBits(-1.0f) == Imm) ||
720 (APInt::floatToBits(0.5f) == Imm) ||
721 (APInt::floatToBits(-0.5f) == Imm) ||
722 (APInt::floatToBits(2.0f) == Imm) ||
723 (APInt::floatToBits(-2.0f) == Imm) ||
724 (APInt::floatToBits(4.0f) == Imm) ||
725 (APInt::floatToBits(-4.0f) == Imm);
728 bool SIInstrInfo::isInlineConstant(const MachineOperand &MO) const {
730 return isInlineConstant(APInt(32, MO.getImm(), true));
733 APFloat FpImm = MO.getFPImm()->getValueAPF();
734 return isInlineConstant(FpImm.bitcastToAPInt());
740 bool SIInstrInfo::isLiteralConstant(const MachineOperand &MO) const {
741 return (MO.isImm() || MO.isFPImm()) && !isInlineConstant(MO);
744 static bool compareMachineOp(const MachineOperand &Op0,
745 const MachineOperand &Op1) {
746 if (Op0.getType() != Op1.getType())
749 switch (Op0.getType()) {
750 case MachineOperand::MO_Register:
751 return Op0.getReg() == Op1.getReg();
752 case MachineOperand::MO_Immediate:
753 return Op0.getImm() == Op1.getImm();
754 case MachineOperand::MO_FPImmediate:
755 return Op0.getFPImm() == Op1.getFPImm();
757 llvm_unreachable("Didn't expect to be comparing these operand types");
761 bool SIInstrInfo::isImmOperandLegal(const MachineInstr *MI, unsigned OpNo,
762 const MachineOperand &MO) const {
763 const MCOperandInfo &OpInfo = get(MI->getOpcode()).OpInfo[OpNo];
765 assert(MO.isImm() || MO.isFPImm());
767 if (OpInfo.OperandType == MCOI::OPERAND_IMMEDIATE)
770 if (OpInfo.RegClass < 0)
773 return RI.regClassCanUseImmediate(OpInfo.RegClass);
776 bool SIInstrInfo::hasVALU32BitEncoding(unsigned Opcode) const {
777 return AMDGPU::getVOPe32(Opcode) != -1;
780 bool SIInstrInfo::hasModifiers(unsigned Opcode) const {
781 // The src0_modifier operand is present on all instructions
782 // that have modifiers.
784 return AMDGPU::getNamedOperandIdx(Opcode,
785 AMDGPU::OpName::src0_modifiers) != -1;
788 bool SIInstrInfo::verifyInstruction(const MachineInstr *MI,
789 StringRef &ErrInfo) const {
790 uint16_t Opcode = MI->getOpcode();
791 int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0);
792 int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1);
793 int Src2Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2);
795 // Make sure the number of operands is correct.
796 const MCInstrDesc &Desc = get(Opcode);
797 if (!Desc.isVariadic() &&
798 Desc.getNumOperands() != MI->getNumExplicitOperands()) {
799 ErrInfo = "Instruction has wrong number of operands.";
803 // Make sure the register classes are correct
804 for (int i = 0, e = Desc.getNumOperands(); i != e; ++i) {
805 switch (Desc.OpInfo[i].OperandType) {
806 case MCOI::OPERAND_REGISTER: {
807 int RegClass = Desc.OpInfo[i].RegClass;
808 if (!RI.regClassCanUseImmediate(RegClass) &&
809 (MI->getOperand(i).isImm() || MI->getOperand(i).isFPImm())) {
810 // Handle some special cases:
811 // Src0 can of VOP1, VOP2, VOPC can be an immediate no matter what
812 // the register class.
813 if (i != Src0Idx || (!isVOP1(Opcode) && !isVOP2(Opcode) &&
815 ErrInfo = "Expected register, but got immediate";
821 case MCOI::OPERAND_IMMEDIATE:
822 // Check if this operand is an immediate.
823 // FrameIndex operands will be replaced by immediates, so they are
825 if (!MI->getOperand(i).isImm() && !MI->getOperand(i).isFPImm() &&
826 !MI->getOperand(i).isFI()) {
827 ErrInfo = "Expected immediate, but got non-immediate";
835 if (!MI->getOperand(i).isReg())
838 int RegClass = Desc.OpInfo[i].RegClass;
839 if (RegClass != -1) {
840 unsigned Reg = MI->getOperand(i).getReg();
841 if (TargetRegisterInfo::isVirtualRegister(Reg))
844 const TargetRegisterClass *RC = RI.getRegClass(RegClass);
845 if (!RC->contains(Reg)) {
846 ErrInfo = "Operand has incorrect register class.";
854 if (isVOP1(Opcode) || isVOP2(Opcode) || isVOP3(Opcode) || isVOPC(Opcode)) {
855 unsigned ConstantBusCount = 0;
856 unsigned SGPRUsed = AMDGPU::NoRegister;
857 for (int i = 0, e = MI->getNumOperands(); i != e; ++i) {
858 const MachineOperand &MO = MI->getOperand(i);
859 if (MO.isReg() && MO.isUse() &&
860 !TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
862 // EXEC register uses the constant bus.
863 if (!MO.isImplicit() && MO.getReg() == AMDGPU::EXEC)
866 // SGPRs use the constant bus
867 if (MO.getReg() == AMDGPU::M0 || MO.getReg() == AMDGPU::VCC ||
869 (AMDGPU::SGPR_32RegClass.contains(MO.getReg()) ||
870 AMDGPU::SGPR_64RegClass.contains(MO.getReg())))) {
871 if (SGPRUsed != MO.getReg()) {
873 SGPRUsed = MO.getReg();
877 // Literal constants use the constant bus.
878 if (isLiteralConstant(MO))
881 if (ConstantBusCount > 1) {
882 ErrInfo = "VOP* instruction uses the constant bus more than once";
887 // Verify SRC1 for VOP2 and VOPC
888 if (Src1Idx != -1 && (isVOP2(Opcode) || isVOPC(Opcode))) {
889 const MachineOperand &Src1 = MI->getOperand(Src1Idx);
890 if (Src1.isImm() || Src1.isFPImm()) {
891 ErrInfo = "VOP[2C] src1 cannot be an immediate.";
897 if (isVOP3(Opcode)) {
898 if (Src0Idx != -1 && isLiteralConstant(MI->getOperand(Src0Idx))) {
899 ErrInfo = "VOP3 src0 cannot be a literal constant.";
902 if (Src1Idx != -1 && isLiteralConstant(MI->getOperand(Src1Idx))) {
903 ErrInfo = "VOP3 src1 cannot be a literal constant.";
906 if (Src2Idx != -1 && isLiteralConstant(MI->getOperand(Src2Idx))) {
907 ErrInfo = "VOP3 src2 cannot be a literal constant.";
912 // Verify misc. restrictions on specific instructions.
913 if (Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F32 ||
914 Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F64) {
917 const MachineOperand &Src0 = MI->getOperand(2);
918 const MachineOperand &Src1 = MI->getOperand(3);
919 const MachineOperand &Src2 = MI->getOperand(4);
920 if (Src0.isReg() && Src1.isReg() && Src2.isReg()) {
921 if (!compareMachineOp(Src0, Src1) &&
922 !compareMachineOp(Src0, Src2)) {
923 ErrInfo = "v_div_scale_{f32|f64} require src0 = src1 or src2";
932 unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) {
933 switch (MI.getOpcode()) {
934 default: return AMDGPU::INSTRUCTION_LIST_END;
935 case AMDGPU::REG_SEQUENCE: return AMDGPU::REG_SEQUENCE;
936 case AMDGPU::COPY: return AMDGPU::COPY;
937 case AMDGPU::PHI: return AMDGPU::PHI;
938 case AMDGPU::INSERT_SUBREG: return AMDGPU::INSERT_SUBREG;
939 case AMDGPU::S_MOV_B32:
940 return MI.getOperand(1).isReg() ?
941 AMDGPU::COPY : AMDGPU::V_MOV_B32_e32;
942 case AMDGPU::S_ADD_I32: return AMDGPU::V_ADD_I32_e32;
943 case AMDGPU::S_ADDC_U32: return AMDGPU::V_ADDC_U32_e32;
944 case AMDGPU::S_SUB_I32: return AMDGPU::V_SUB_I32_e32;
945 case AMDGPU::S_SUBB_U32: return AMDGPU::V_SUBB_U32_e32;
946 case AMDGPU::S_AND_B32: return AMDGPU::V_AND_B32_e32;
947 case AMDGPU::S_OR_B32: return AMDGPU::V_OR_B32_e32;
948 case AMDGPU::S_XOR_B32: return AMDGPU::V_XOR_B32_e32;
949 case AMDGPU::S_MIN_I32: return AMDGPU::V_MIN_I32_e32;
950 case AMDGPU::S_MIN_U32: return AMDGPU::V_MIN_U32_e32;
951 case AMDGPU::S_MAX_I32: return AMDGPU::V_MAX_I32_e32;
952 case AMDGPU::S_MAX_U32: return AMDGPU::V_MAX_U32_e32;
953 case AMDGPU::S_ASHR_I32: return AMDGPU::V_ASHR_I32_e32;
954 case AMDGPU::S_ASHR_I64: return AMDGPU::V_ASHR_I64;
955 case AMDGPU::S_LSHL_B32: return AMDGPU::V_LSHL_B32_e32;
956 case AMDGPU::S_LSHL_B64: return AMDGPU::V_LSHL_B64;
957 case AMDGPU::S_LSHR_B32: return AMDGPU::V_LSHR_B32_e32;
958 case AMDGPU::S_LSHR_B64: return AMDGPU::V_LSHR_B64;
959 case AMDGPU::S_SEXT_I32_I8: return AMDGPU::V_BFE_I32;
960 case AMDGPU::S_SEXT_I32_I16: return AMDGPU::V_BFE_I32;
961 case AMDGPU::S_BFE_U32: return AMDGPU::V_BFE_U32;
962 case AMDGPU::S_BFE_I32: return AMDGPU::V_BFE_I32;
963 case AMDGPU::S_BREV_B32: return AMDGPU::V_BFREV_B32_e32;
964 case AMDGPU::S_NOT_B32: return AMDGPU::V_NOT_B32_e32;
965 case AMDGPU::S_NOT_B64: return AMDGPU::V_NOT_B32_e32;
966 case AMDGPU::S_CMP_EQ_I32: return AMDGPU::V_CMP_EQ_I32_e32;
967 case AMDGPU::S_CMP_LG_I32: return AMDGPU::V_CMP_NE_I32_e32;
968 case AMDGPU::S_CMP_GT_I32: return AMDGPU::V_CMP_GT_I32_e32;
969 case AMDGPU::S_CMP_GE_I32: return AMDGPU::V_CMP_GE_I32_e32;
970 case AMDGPU::S_CMP_LT_I32: return AMDGPU::V_CMP_LT_I32_e32;
971 case AMDGPU::S_CMP_LE_I32: return AMDGPU::V_CMP_LE_I32_e32;
972 case AMDGPU::S_LOAD_DWORD_IMM:
973 case AMDGPU::S_LOAD_DWORD_SGPR: return AMDGPU::BUFFER_LOAD_DWORD_ADDR64;
974 case AMDGPU::S_LOAD_DWORDX2_IMM:
975 case AMDGPU::S_LOAD_DWORDX2_SGPR: return AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64;
976 case AMDGPU::S_LOAD_DWORDX4_IMM:
977 case AMDGPU::S_LOAD_DWORDX4_SGPR: return AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64;
978 case AMDGPU::S_BCNT1_I32_B32: return AMDGPU::V_BCNT_U32_B32_e32;
979 case AMDGPU::S_FF1_I32_B32: return AMDGPU::V_FFBL_B32_e32;
980 case AMDGPU::S_FLBIT_I32_B32: return AMDGPU::V_FFBH_U32_e32;
984 bool SIInstrInfo::isSALUOpSupportedOnVALU(const MachineInstr &MI) const {
985 return getVALUOp(MI) != AMDGPU::INSTRUCTION_LIST_END;
988 const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI,
989 unsigned OpNo) const {
990 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
991 const MCInstrDesc &Desc = get(MI.getOpcode());
992 if (MI.isVariadic() || OpNo >= Desc.getNumOperands() ||
993 Desc.OpInfo[OpNo].RegClass == -1)
994 return MRI.getRegClass(MI.getOperand(OpNo).getReg());
996 unsigned RCID = Desc.OpInfo[OpNo].RegClass;
997 return RI.getRegClass(RCID);
1000 bool SIInstrInfo::canReadVGPR(const MachineInstr &MI, unsigned OpNo) const {
1001 switch (MI.getOpcode()) {
1003 case AMDGPU::REG_SEQUENCE:
1005 case AMDGPU::INSERT_SUBREG:
1006 return RI.hasVGPRs(getOpRegClass(MI, 0));
1008 return RI.hasVGPRs(getOpRegClass(MI, OpNo));
1012 void SIInstrInfo::legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const {
1013 MachineBasicBlock::iterator I = MI;
1014 MachineOperand &MO = MI->getOperand(OpIdx);
1015 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1016 unsigned RCID = get(MI->getOpcode()).OpInfo[OpIdx].RegClass;
1017 const TargetRegisterClass *RC = RI.getRegClass(RCID);
1018 unsigned Opcode = AMDGPU::V_MOV_B32_e32;
1020 Opcode = AMDGPU::COPY;
1021 } else if (RI.isSGPRClass(RC)) {
1022 Opcode = AMDGPU::S_MOV_B32;
1025 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(RC);
1026 unsigned Reg = MRI.createVirtualRegister(VRC);
1027 BuildMI(*MI->getParent(), I, MI->getParent()->findDebugLoc(I), get(Opcode),
1028 Reg).addOperand(MO);
1029 MO.ChangeToRegister(Reg, false);
1032 unsigned SIInstrInfo::buildExtractSubReg(MachineBasicBlock::iterator MI,
1033 MachineRegisterInfo &MRI,
1034 MachineOperand &SuperReg,
1035 const TargetRegisterClass *SuperRC,
1037 const TargetRegisterClass *SubRC)
1039 assert(SuperReg.isReg());
1041 unsigned NewSuperReg = MRI.createVirtualRegister(SuperRC);
1042 unsigned SubReg = MRI.createVirtualRegister(SubRC);
1044 // Just in case the super register is itself a sub-register, copy it to a new
1045 // value so we don't need to worry about merging its subreg index with the
1046 // SubIdx passed to this function. The register coalescer should be able to
1047 // eliminate this extra copy.
1048 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(TargetOpcode::COPY),
1050 .addOperand(SuperReg);
1052 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(TargetOpcode::COPY),
1054 .addReg(NewSuperReg, 0, SubIdx);
1058 MachineOperand SIInstrInfo::buildExtractSubRegOrImm(
1059 MachineBasicBlock::iterator MII,
1060 MachineRegisterInfo &MRI,
1062 const TargetRegisterClass *SuperRC,
1064 const TargetRegisterClass *SubRC) const {
1066 // XXX - Is there a better way to do this?
1067 if (SubIdx == AMDGPU::sub0)
1068 return MachineOperand::CreateImm(Op.getImm() & 0xFFFFFFFF);
1069 if (SubIdx == AMDGPU::sub1)
1070 return MachineOperand::CreateImm(Op.getImm() >> 32);
1072 llvm_unreachable("Unhandled register index for immediate");
1075 unsigned SubReg = buildExtractSubReg(MII, MRI, Op, SuperRC,
1077 return MachineOperand::CreateReg(SubReg, false);
1080 unsigned SIInstrInfo::split64BitImm(SmallVectorImpl<MachineInstr *> &Worklist,
1081 MachineBasicBlock::iterator MI,
1082 MachineRegisterInfo &MRI,
1083 const TargetRegisterClass *RC,
1084 const MachineOperand &Op) const {
1085 MachineBasicBlock *MBB = MI->getParent();
1086 DebugLoc DL = MI->getDebugLoc();
1087 unsigned LoDst = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1088 unsigned HiDst = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1089 unsigned Dst = MRI.createVirtualRegister(RC);
1091 MachineInstr *Lo = BuildMI(*MBB, MI, DL, get(AMDGPU::S_MOV_B32),
1093 .addImm(Op.getImm() & 0xFFFFFFFF);
1094 MachineInstr *Hi = BuildMI(*MBB, MI, DL, get(AMDGPU::S_MOV_B32),
1096 .addImm(Op.getImm() >> 32);
1098 BuildMI(*MBB, MI, DL, get(TargetOpcode::REG_SEQUENCE), Dst)
1100 .addImm(AMDGPU::sub0)
1102 .addImm(AMDGPU::sub1);
1104 Worklist.push_back(Lo);
1105 Worklist.push_back(Hi);
1110 bool SIInstrInfo::isOperandLegal(const MachineInstr *MI, unsigned OpIdx,
1111 const MachineOperand *MO) const {
1112 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1113 const MCInstrDesc &InstDesc = get(MI->getOpcode());
1114 const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpIdx];
1115 const TargetRegisterClass *DefinedRC =
1116 OpInfo.RegClass != -1 ? RI.getRegClass(OpInfo.RegClass) : nullptr;
1118 MO = &MI->getOperand(OpIdx);
1122 const TargetRegisterClass *RC = MRI.getRegClass(MO->getReg());
1123 return RI.getCommonSubClass(RC, RI.getRegClass(OpInfo.RegClass));
1127 // Handle non-register types that are treated like immediates.
1128 assert(MO->isImm() || MO->isFPImm() || MO->isTargetIndex() || MO->isFI());
1131 // This opperand expects an immediate
1134 return RI.regClassCanUseImmediate(DefinedRC);
1137 void SIInstrInfo::legalizeOperands(MachineInstr *MI) const {
1138 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1140 int Src0Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1141 AMDGPU::OpName::src0);
1142 int Src1Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1143 AMDGPU::OpName::src1);
1144 int Src2Idx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1145 AMDGPU::OpName::src2);
1148 if (isVOP2(MI->getOpcode()) && Src1Idx != -1) {
1150 if (!isOperandLegal(MI, Src0Idx))
1151 legalizeOpWithMove(MI, Src0Idx);
1154 if (isOperandLegal(MI, Src1Idx))
1157 // Usually src0 of VOP2 instructions allow more types of inputs
1158 // than src1, so try to commute the instruction to decrease our
1159 // chances of having to insert a MOV instruction to legalize src1.
1160 if (MI->isCommutable()) {
1161 if (commuteInstruction(MI))
1162 // If we are successful in commuting, then we know MI is legal, so
1167 legalizeOpWithMove(MI, Src1Idx);
1171 // XXX - Do any VOP3 instructions read VCC?
1173 if (isVOP3(MI->getOpcode())) {
1174 int VOP3Idx[3] = {Src0Idx, Src1Idx, Src2Idx};
1175 unsigned SGPRReg = AMDGPU::NoRegister;
1176 for (unsigned i = 0; i < 3; ++i) {
1177 int Idx = VOP3Idx[i];
1180 MachineOperand &MO = MI->getOperand(Idx);
1183 if (!RI.isSGPRClass(MRI.getRegClass(MO.getReg())))
1184 continue; // VGPRs are legal
1186 assert(MO.getReg() != AMDGPU::SCC && "SCC operand to VOP3 instruction");
1188 if (SGPRReg == AMDGPU::NoRegister || SGPRReg == MO.getReg()) {
1189 SGPRReg = MO.getReg();
1190 // We can use one SGPR in each VOP3 instruction.
1193 } else if (!isLiteralConstant(MO)) {
1194 // If it is not a register and not a literal constant, then it must be
1195 // an inline constant which is always legal.
1198 // If we make it this far, then the operand is not legal and we must
1200 legalizeOpWithMove(MI, Idx);
1204 // Legalize REG_SEQUENCE and PHI
1205 // The register class of the operands much be the same type as the register
1206 // class of the output.
1207 if (MI->getOpcode() == AMDGPU::REG_SEQUENCE ||
1208 MI->getOpcode() == AMDGPU::PHI) {
1209 const TargetRegisterClass *RC = nullptr, *SRC = nullptr, *VRC = nullptr;
1210 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
1211 if (!MI->getOperand(i).isReg() ||
1212 !TargetRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg()))
1214 const TargetRegisterClass *OpRC =
1215 MRI.getRegClass(MI->getOperand(i).getReg());
1216 if (RI.hasVGPRs(OpRC)) {
1223 // If any of the operands are VGPR registers, then they all most be
1224 // otherwise we will create illegal VGPR->SGPR copies when legalizing
1226 if (VRC || !RI.isSGPRClass(getOpRegClass(*MI, 0))) {
1229 VRC = RI.getEquivalentVGPRClass(SRC);
1236 // Update all the operands so they have the same type.
1237 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
1238 if (!MI->getOperand(i).isReg() ||
1239 !TargetRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg()))
1241 unsigned DstReg = MRI.createVirtualRegister(RC);
1242 MachineBasicBlock *InsertBB;
1243 MachineBasicBlock::iterator Insert;
1244 if (MI->getOpcode() == AMDGPU::REG_SEQUENCE) {
1245 InsertBB = MI->getParent();
1248 // MI is a PHI instruction.
1249 InsertBB = MI->getOperand(i + 1).getMBB();
1250 Insert = InsertBB->getFirstTerminator();
1252 BuildMI(*InsertBB, Insert, MI->getDebugLoc(),
1253 get(AMDGPU::COPY), DstReg)
1254 .addOperand(MI->getOperand(i));
1255 MI->getOperand(i).setReg(DstReg);
1259 // Legalize INSERT_SUBREG
1260 // src0 must have the same register class as dst
1261 if (MI->getOpcode() == AMDGPU::INSERT_SUBREG) {
1262 unsigned Dst = MI->getOperand(0).getReg();
1263 unsigned Src0 = MI->getOperand(1).getReg();
1264 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
1265 const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0);
1266 if (DstRC != Src0RC) {
1267 MachineBasicBlock &MBB = *MI->getParent();
1268 unsigned NewSrc0 = MRI.createVirtualRegister(DstRC);
1269 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::COPY), NewSrc0)
1271 MI->getOperand(1).setReg(NewSrc0);
1276 // Legalize MUBUF* instructions
1277 // FIXME: If we start using the non-addr64 instructions for compute, we
1278 // may need to legalize them here.
1280 int SRsrcIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1281 AMDGPU::OpName::srsrc);
1282 int VAddrIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
1283 AMDGPU::OpName::vaddr);
1284 if (SRsrcIdx != -1 && VAddrIdx != -1) {
1285 const TargetRegisterClass *VAddrRC =
1286 RI.getRegClass(get(MI->getOpcode()).OpInfo[VAddrIdx].RegClass);
1288 if(VAddrRC->getSize() == 8 &&
1289 MRI.getRegClass(MI->getOperand(SRsrcIdx).getReg()) != VAddrRC) {
1290 // We have a MUBUF instruction that uses a 64-bit vaddr register and
1291 // srsrc has the incorrect register class. In order to fix this, we
1292 // need to extract the pointer from the resource descriptor (srsrc),
1293 // add it to the value of vadd, then store the result in the vaddr
1294 // operand. Then, we need to set the pointer field of the resource
1295 // descriptor to zero.
1297 MachineBasicBlock &MBB = *MI->getParent();
1298 MachineOperand &SRsrcOp = MI->getOperand(SRsrcIdx);
1299 MachineOperand &VAddrOp = MI->getOperand(VAddrIdx);
1300 unsigned SRsrcPtrLo, SRsrcPtrHi, VAddrLo, VAddrHi;
1301 unsigned NewVAddrLo = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
1302 unsigned NewVAddrHi = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
1303 unsigned NewVAddr = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
1304 unsigned Zero64 = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
1305 unsigned SRsrcFormatLo = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1306 unsigned SRsrcFormatHi = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1307 unsigned NewSRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass);
1309 // SRsrcPtrLo = srsrc:sub0
1310 SRsrcPtrLo = buildExtractSubReg(MI, MRI, SRsrcOp,
1311 &AMDGPU::VReg_128RegClass, AMDGPU::sub0, &AMDGPU::VReg_32RegClass);
1313 // SRsrcPtrHi = srsrc:sub1
1314 SRsrcPtrHi = buildExtractSubReg(MI, MRI, SRsrcOp,
1315 &AMDGPU::VReg_128RegClass, AMDGPU::sub1, &AMDGPU::VReg_32RegClass);
1317 // VAddrLo = vaddr:sub0
1318 VAddrLo = buildExtractSubReg(MI, MRI, VAddrOp,
1319 &AMDGPU::VReg_64RegClass, AMDGPU::sub0, &AMDGPU::VReg_32RegClass);
1321 // VAddrHi = vaddr:sub1
1322 VAddrHi = buildExtractSubReg(MI, MRI, VAddrOp,
1323 &AMDGPU::VReg_64RegClass, AMDGPU::sub1, &AMDGPU::VReg_32RegClass);
1325 // NewVaddrLo = SRsrcPtrLo + VAddrLo
1326 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::V_ADD_I32_e32),
1330 .addReg(AMDGPU::VCC, RegState::Define | RegState::Implicit);
1332 // NewVaddrHi = SRsrcPtrHi + VAddrHi
1333 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::V_ADDC_U32_e32),
1337 .addReg(AMDGPU::VCC, RegState::ImplicitDefine)
1338 .addReg(AMDGPU::VCC, RegState::Implicit);
1340 // NewVaddr = {NewVaddrHi, NewVaddrLo}
1341 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE),
1344 .addImm(AMDGPU::sub0)
1346 .addImm(AMDGPU::sub1);
1349 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B64),
1353 // SRsrcFormatLo = RSRC_DATA_FORMAT{31-0}
1354 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1356 .addImm(AMDGPU::RSRC_DATA_FORMAT & 0xFFFFFFFF);
1358 // SRsrcFormatHi = RSRC_DATA_FORMAT{63-32}
1359 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1361 .addImm(AMDGPU::RSRC_DATA_FORMAT >> 32);
1363 // NewSRsrc = {Zero64, SRsrcFormat}
1364 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE),
1367 .addImm(AMDGPU::sub0_sub1)
1368 .addReg(SRsrcFormatLo)
1369 .addImm(AMDGPU::sub2)
1370 .addReg(SRsrcFormatHi)
1371 .addImm(AMDGPU::sub3);
1373 // Update the instruction to use NewVaddr
1374 MI->getOperand(VAddrIdx).setReg(NewVAddr);
1375 // Update the instruction to use NewSRsrc
1376 MI->getOperand(SRsrcIdx).setReg(NewSRsrc);
1381 void SIInstrInfo::moveSMRDToVALU(MachineInstr *MI, MachineRegisterInfo &MRI) const {
1382 MachineBasicBlock *MBB = MI->getParent();
1383 switch (MI->getOpcode()) {
1384 case AMDGPU::S_LOAD_DWORD_IMM:
1385 case AMDGPU::S_LOAD_DWORD_SGPR:
1386 case AMDGPU::S_LOAD_DWORDX2_IMM:
1387 case AMDGPU::S_LOAD_DWORDX2_SGPR:
1388 case AMDGPU::S_LOAD_DWORDX4_IMM:
1389 case AMDGPU::S_LOAD_DWORDX4_SGPR:
1390 unsigned NewOpcode = getVALUOp(*MI);
1394 if (MI->getOperand(2).isReg()) {
1395 RegOffset = MI->getOperand(2).getReg();
1398 assert(MI->getOperand(2).isImm());
1399 // SMRD instructions take a dword offsets and MUBUF instructions
1400 // take a byte offset.
1401 ImmOffset = MI->getOperand(2).getImm() << 2;
1402 RegOffset = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1403 if (isUInt<12>(ImmOffset)) {
1404 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1408 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32),
1415 unsigned SRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass);
1416 unsigned DWord0 = RegOffset;
1417 unsigned DWord1 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1418 unsigned DWord2 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1419 unsigned DWord3 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1421 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord1)
1423 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord2)
1424 .addImm(AMDGPU::RSRC_DATA_FORMAT & 0xFFFFFFFF);
1425 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord3)
1426 .addImm(AMDGPU::RSRC_DATA_FORMAT >> 32);
1427 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), SRsrc)
1429 .addImm(AMDGPU::sub0)
1431 .addImm(AMDGPU::sub1)
1433 .addImm(AMDGPU::sub2)
1435 .addImm(AMDGPU::sub3);
1436 MI->setDesc(get(NewOpcode));
1437 if (MI->getOperand(2).isReg()) {
1438 MI->getOperand(2).setReg(MI->getOperand(1).getReg());
1440 MI->getOperand(2).ChangeToRegister(MI->getOperand(1).getReg(), false);
1442 MI->getOperand(1).setReg(SRsrc);
1443 MI->addOperand(*MBB->getParent(), MachineOperand::CreateImm(ImmOffset));
1447 void SIInstrInfo::moveToVALU(MachineInstr &TopInst) const {
1448 SmallVector<MachineInstr *, 128> Worklist;
1449 Worklist.push_back(&TopInst);
1451 while (!Worklist.empty()) {
1452 MachineInstr *Inst = Worklist.pop_back_val();
1453 MachineBasicBlock *MBB = Inst->getParent();
1454 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
1456 unsigned Opcode = Inst->getOpcode();
1457 unsigned NewOpcode = getVALUOp(*Inst);
1459 // Handle some special cases
1462 if (isSMRD(Inst->getOpcode())) {
1463 moveSMRDToVALU(Inst, MRI);
1466 case AMDGPU::S_MOV_B64: {
1467 DebugLoc DL = Inst->getDebugLoc();
1469 // If the source operand is a register we can replace this with a
1471 if (Inst->getOperand(1).isReg()) {
1472 MachineInstr *Copy = BuildMI(*MBB, Inst, DL, get(TargetOpcode::COPY))
1473 .addOperand(Inst->getOperand(0))
1474 .addOperand(Inst->getOperand(1));
1475 Worklist.push_back(Copy);
1477 // Otherwise, we need to split this into two movs, because there is
1478 // no 64-bit VALU move instruction.
1479 unsigned Reg = Inst->getOperand(0).getReg();
1480 unsigned Dst = split64BitImm(Worklist,
1483 MRI.getRegClass(Reg),
1484 Inst->getOperand(1));
1485 MRI.replaceRegWith(Reg, Dst);
1487 Inst->eraseFromParent();
1490 case AMDGPU::S_AND_B64:
1491 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_AND_B32);
1492 Inst->eraseFromParent();
1495 case AMDGPU::S_OR_B64:
1496 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_OR_B32);
1497 Inst->eraseFromParent();
1500 case AMDGPU::S_XOR_B64:
1501 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_XOR_B32);
1502 Inst->eraseFromParent();
1505 case AMDGPU::S_NOT_B64:
1506 splitScalar64BitUnaryOp(Worklist, Inst, AMDGPU::S_NOT_B32);
1507 Inst->eraseFromParent();
1510 case AMDGPU::S_BCNT1_I32_B64:
1511 splitScalar64BitBCNT(Worklist, Inst);
1512 Inst->eraseFromParent();
1515 case AMDGPU::S_BFE_U64:
1516 case AMDGPU::S_BFE_I64:
1517 case AMDGPU::S_BFM_B64:
1518 llvm_unreachable("Moving this op to VALU not implemented");
1521 if (NewOpcode == AMDGPU::INSTRUCTION_LIST_END) {
1522 // We cannot move this instruction to the VALU, so we should try to
1523 // legalize its operands instead.
1524 legalizeOperands(Inst);
1528 // Use the new VALU Opcode.
1529 const MCInstrDesc &NewDesc = get(NewOpcode);
1530 Inst->setDesc(NewDesc);
1532 // Remove any references to SCC. Vector instructions can't read from it, and
1533 // We're just about to add the implicit use / defs of VCC, and we don't want
1535 for (unsigned i = Inst->getNumOperands() - 1; i > 0; --i) {
1536 MachineOperand &Op = Inst->getOperand(i);
1537 if (Op.isReg() && Op.getReg() == AMDGPU::SCC)
1538 Inst->RemoveOperand(i);
1541 if (Opcode == AMDGPU::S_SEXT_I32_I8 || Opcode == AMDGPU::S_SEXT_I32_I16) {
1542 // We are converting these to a BFE, so we need to add the missing
1543 // operands for the size and offset.
1544 unsigned Size = (Opcode == AMDGPU::S_SEXT_I32_I8) ? 8 : 16;
1545 Inst->addOperand(MachineOperand::CreateImm(0));
1546 Inst->addOperand(MachineOperand::CreateImm(Size));
1548 } else if (Opcode == AMDGPU::S_BCNT1_I32_B32) {
1549 // The VALU version adds the second operand to the result, so insert an
1551 Inst->addOperand(MachineOperand::CreateImm(0));
1554 addDescImplicitUseDef(NewDesc, Inst);
1556 if (Opcode == AMDGPU::S_BFE_I32 || Opcode == AMDGPU::S_BFE_U32) {
1557 const MachineOperand &OffsetWidthOp = Inst->getOperand(2);
1558 // If we need to move this to VGPRs, we need to unpack the second operand
1559 // back into the 2 separate ones for bit offset and width.
1560 assert(OffsetWidthOp.isImm() &&
1561 "Scalar BFE is only implemented for constant width and offset");
1562 uint32_t Imm = OffsetWidthOp.getImm();
1564 uint32_t Offset = Imm & 0x3f; // Extract bits [5:0].
1565 uint32_t BitWidth = (Imm & 0x7f0000) >> 16; // Extract bits [22:16].
1566 Inst->RemoveOperand(2); // Remove old immediate.
1567 Inst->addOperand(MachineOperand::CreateImm(Offset));
1568 Inst->addOperand(MachineOperand::CreateImm(BitWidth));
1571 // Update the destination register class.
1573 const TargetRegisterClass *NewDstRC = getOpRegClass(*Inst, 0);
1576 // For target instructions, getOpRegClass just returns the virtual
1577 // register class associated with the operand, so we need to find an
1578 // equivalent VGPR register class in order to move the instruction to the
1582 case AMDGPU::REG_SEQUENCE:
1583 case AMDGPU::INSERT_SUBREG:
1584 if (RI.hasVGPRs(NewDstRC))
1586 NewDstRC = RI.getEquivalentVGPRClass(NewDstRC);
1594 unsigned DstReg = Inst->getOperand(0).getReg();
1595 unsigned NewDstReg = MRI.createVirtualRegister(NewDstRC);
1596 MRI.replaceRegWith(DstReg, NewDstReg);
1598 // Legalize the operands
1599 legalizeOperands(Inst);
1601 for (MachineRegisterInfo::use_iterator I = MRI.use_begin(NewDstReg),
1602 E = MRI.use_end(); I != E; ++I) {
1603 MachineInstr &UseMI = *I->getParent();
1604 if (!canReadVGPR(UseMI, I.getOperandNo())) {
1605 Worklist.push_back(&UseMI);
1611 //===----------------------------------------------------------------------===//
1612 // Indirect addressing callbacks
1613 //===----------------------------------------------------------------------===//
1615 unsigned SIInstrInfo::calculateIndirectAddress(unsigned RegIndex,
1616 unsigned Channel) const {
1617 assert(Channel == 0);
1621 const TargetRegisterClass *SIInstrInfo::getIndirectAddrRegClass() const {
1622 return &AMDGPU::VReg_32RegClass;
1625 void SIInstrInfo::splitScalar64BitUnaryOp(
1626 SmallVectorImpl<MachineInstr *> &Worklist,
1628 unsigned Opcode) const {
1629 MachineBasicBlock &MBB = *Inst->getParent();
1630 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
1632 MachineOperand &Dest = Inst->getOperand(0);
1633 MachineOperand &Src0 = Inst->getOperand(1);
1634 DebugLoc DL = Inst->getDebugLoc();
1636 MachineBasicBlock::iterator MII = Inst;
1638 const MCInstrDesc &InstDesc = get(Opcode);
1639 const TargetRegisterClass *Src0RC = Src0.isReg() ?
1640 MRI.getRegClass(Src0.getReg()) :
1641 &AMDGPU::SGPR_32RegClass;
1643 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
1645 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
1646 AMDGPU::sub0, Src0SubRC);
1648 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
1649 const TargetRegisterClass *DestSubRC = RI.getSubRegClass(DestRC, AMDGPU::sub0);
1651 unsigned DestSub0 = MRI.createVirtualRegister(DestRC);
1652 MachineInstr *LoHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub0)
1653 .addOperand(SrcReg0Sub0);
1655 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
1656 AMDGPU::sub1, Src0SubRC);
1658 unsigned DestSub1 = MRI.createVirtualRegister(DestSubRC);
1659 MachineInstr *HiHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub1)
1660 .addOperand(SrcReg0Sub1);
1662 unsigned FullDestReg = MRI.createVirtualRegister(DestRC);
1663 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
1665 .addImm(AMDGPU::sub0)
1667 .addImm(AMDGPU::sub1);
1669 MRI.replaceRegWith(Dest.getReg(), FullDestReg);
1671 // Try to legalize the operands in case we need to swap the order to keep it
1673 Worklist.push_back(LoHalf);
1674 Worklist.push_back(HiHalf);
1677 void SIInstrInfo::splitScalar64BitBinaryOp(
1678 SmallVectorImpl<MachineInstr *> &Worklist,
1680 unsigned Opcode) const {
1681 MachineBasicBlock &MBB = *Inst->getParent();
1682 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
1684 MachineOperand &Dest = Inst->getOperand(0);
1685 MachineOperand &Src0 = Inst->getOperand(1);
1686 MachineOperand &Src1 = Inst->getOperand(2);
1687 DebugLoc DL = Inst->getDebugLoc();
1689 MachineBasicBlock::iterator MII = Inst;
1691 const MCInstrDesc &InstDesc = get(Opcode);
1692 const TargetRegisterClass *Src0RC = Src0.isReg() ?
1693 MRI.getRegClass(Src0.getReg()) :
1694 &AMDGPU::SGPR_32RegClass;
1696 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
1697 const TargetRegisterClass *Src1RC = Src1.isReg() ?
1698 MRI.getRegClass(Src1.getReg()) :
1699 &AMDGPU::SGPR_32RegClass;
1701 const TargetRegisterClass *Src1SubRC = RI.getSubRegClass(Src1RC, AMDGPU::sub0);
1703 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
1704 AMDGPU::sub0, Src0SubRC);
1705 MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
1706 AMDGPU::sub0, Src1SubRC);
1708 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
1709 const TargetRegisterClass *DestSubRC = RI.getSubRegClass(DestRC, AMDGPU::sub0);
1711 unsigned DestSub0 = MRI.createVirtualRegister(DestRC);
1712 MachineInstr *LoHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub0)
1713 .addOperand(SrcReg0Sub0)
1714 .addOperand(SrcReg1Sub0);
1716 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
1717 AMDGPU::sub1, Src0SubRC);
1718 MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
1719 AMDGPU::sub1, Src1SubRC);
1721 unsigned DestSub1 = MRI.createVirtualRegister(DestSubRC);
1722 MachineInstr *HiHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub1)
1723 .addOperand(SrcReg0Sub1)
1724 .addOperand(SrcReg1Sub1);
1726 unsigned FullDestReg = MRI.createVirtualRegister(DestRC);
1727 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
1729 .addImm(AMDGPU::sub0)
1731 .addImm(AMDGPU::sub1);
1733 MRI.replaceRegWith(Dest.getReg(), FullDestReg);
1735 // Try to legalize the operands in case we need to swap the order to keep it
1737 Worklist.push_back(LoHalf);
1738 Worklist.push_back(HiHalf);
1741 void SIInstrInfo::splitScalar64BitBCNT(SmallVectorImpl<MachineInstr *> &Worklist,
1742 MachineInstr *Inst) const {
1743 MachineBasicBlock &MBB = *Inst->getParent();
1744 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
1746 MachineBasicBlock::iterator MII = Inst;
1747 DebugLoc DL = Inst->getDebugLoc();
1749 MachineOperand &Dest = Inst->getOperand(0);
1750 MachineOperand &Src = Inst->getOperand(1);
1752 const MCInstrDesc &InstDesc = get(AMDGPU::V_BCNT_U32_B32_e32);
1753 const TargetRegisterClass *SrcRC = Src.isReg() ?
1754 MRI.getRegClass(Src.getReg()) :
1755 &AMDGPU::SGPR_32RegClass;
1757 unsigned MidReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
1758 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
1760 const TargetRegisterClass *SrcSubRC = RI.getSubRegClass(SrcRC, AMDGPU::sub0);
1762 MachineOperand SrcRegSub0 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC,
1763 AMDGPU::sub0, SrcSubRC);
1764 MachineOperand SrcRegSub1 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC,
1765 AMDGPU::sub1, SrcSubRC);
1767 MachineInstr *First = BuildMI(MBB, MII, DL, InstDesc, MidReg)
1768 .addOperand(SrcRegSub0)
1771 MachineInstr *Second = BuildMI(MBB, MII, DL, InstDesc, ResultReg)
1772 .addOperand(SrcRegSub1)
1775 MRI.replaceRegWith(Dest.getReg(), ResultReg);
1777 Worklist.push_back(First);
1778 Worklist.push_back(Second);
1781 void SIInstrInfo::addDescImplicitUseDef(const MCInstrDesc &NewDesc,
1782 MachineInstr *Inst) const {
1783 // Add the implict and explicit register definitions.
1784 if (NewDesc.ImplicitUses) {
1785 for (unsigned i = 0; NewDesc.ImplicitUses[i]; ++i) {
1786 unsigned Reg = NewDesc.ImplicitUses[i];
1787 Inst->addOperand(MachineOperand::CreateReg(Reg, false, true));
1791 if (NewDesc.ImplicitDefs) {
1792 for (unsigned i = 0; NewDesc.ImplicitDefs[i]; ++i) {
1793 unsigned Reg = NewDesc.ImplicitDefs[i];
1794 Inst->addOperand(MachineOperand::CreateReg(Reg, true, true));
1799 MachineInstrBuilder SIInstrInfo::buildIndirectWrite(
1800 MachineBasicBlock *MBB,
1801 MachineBasicBlock::iterator I,
1803 unsigned Address, unsigned OffsetReg) const {
1804 const DebugLoc &DL = MBB->findDebugLoc(I);
1805 unsigned IndirectBaseReg = AMDGPU::VReg_32RegClass.getRegister(
1806 getIndirectIndexBegin(*MBB->getParent()));
1808 return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_DST_V1))
1809 .addReg(IndirectBaseReg, RegState::Define)
1810 .addOperand(I->getOperand(0))
1811 .addReg(IndirectBaseReg)
1817 MachineInstrBuilder SIInstrInfo::buildIndirectRead(
1818 MachineBasicBlock *MBB,
1819 MachineBasicBlock::iterator I,
1821 unsigned Address, unsigned OffsetReg) const {
1822 const DebugLoc &DL = MBB->findDebugLoc(I);
1823 unsigned IndirectBaseReg = AMDGPU::VReg_32RegClass.getRegister(
1824 getIndirectIndexBegin(*MBB->getParent()));
1826 return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_SRC))
1827 .addOperand(I->getOperand(0))
1828 .addOperand(I->getOperand(1))
1829 .addReg(IndirectBaseReg)
1835 void SIInstrInfo::reserveIndirectRegisters(BitVector &Reserved,
1836 const MachineFunction &MF) const {
1837 int End = getIndirectIndexEnd(MF);
1838 int Begin = getIndirectIndexBegin(MF);
1844 for (int Index = Begin; Index <= End; ++Index)
1845 Reserved.set(AMDGPU::VReg_32RegClass.getRegister(Index));
1847 for (int Index = std::max(0, Begin - 1); Index <= End; ++Index)
1848 Reserved.set(AMDGPU::VReg_64RegClass.getRegister(Index));
1850 for (int Index = std::max(0, Begin - 2); Index <= End; ++Index)
1851 Reserved.set(AMDGPU::VReg_96RegClass.getRegister(Index));
1853 for (int Index = std::max(0, Begin - 3); Index <= End; ++Index)
1854 Reserved.set(AMDGPU::VReg_128RegClass.getRegister(Index));
1856 for (int Index = std::max(0, Begin - 7); Index <= End; ++Index)
1857 Reserved.set(AMDGPU::VReg_256RegClass.getRegister(Index));
1859 for (int Index = std::max(0, Begin - 15); Index <= End; ++Index)
1860 Reserved.set(AMDGPU::VReg_512RegClass.getRegister(Index));
1863 MachineOperand *SIInstrInfo::getNamedOperand(MachineInstr &MI,
1864 unsigned OperandName) const {
1865 int Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), OperandName);
1869 return &MI.getOperand(Idx);