1 //===-- SIInstrFormats.td - SI Instruction Encodings ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // SI Instruction format definitions.
12 //===----------------------------------------------------------------------===//
14 class InstSI <dag outs, dag ins, string asm, list<dag> pattern> :
15 AMDGPUInst<outs, ins, asm, pattern>, PredicateControl {
17 field bits<1> VM_CNT = 0;
18 field bits<1> EXP_CNT = 0;
19 field bits<1> LGKM_CNT = 0;
20 field bits<1> MIMG = 0;
21 field bits<1> SMRD = 0;
22 field bits<1> VOP1 = 0;
23 field bits<1> VOP2 = 0;
24 field bits<1> VOP3 = 0;
25 field bits<1> VOPC = 0;
26 field bits<1> SALU = 0;
27 field bits<1> MUBUF = 0;
28 field bits<1> MTBUF = 0;
30 // These need to be kept in sync with the enum in SIInstrFlags.
31 let TSFlags{0} = VM_CNT;
32 let TSFlags{1} = EXP_CNT;
33 let TSFlags{2} = LGKM_CNT;
34 let TSFlags{3} = MIMG;
35 let TSFlags{4} = SMRD;
36 let TSFlags{5} = VOP1;
37 let TSFlags{6} = VOP2;
38 let TSFlags{7} = VOP3;
39 let TSFlags{8} = VOPC;
40 let TSFlags{9} = SALU;
41 let TSFlags{10} = MUBUF;
42 let TSFlags{11} = MTBUF;
57 class VOP3Common <dag outs, dag ins, string asm, list<dag> pattern> :
58 InstSI <outs, ins, asm, pattern> {
62 let hasSideEffects = 0;
63 let UseNamedOperandTable = 1;
69 //===----------------------------------------------------------------------===//
71 //===----------------------------------------------------------------------===//
73 class SOP1e <bits<8> op> : Enc32 {
78 let Inst{7-0} = SSRC0;
80 let Inst{22-16} = SDST;
81 let Inst{31-23} = 0x17d; //encoding;
84 class SOP2e <bits<7> op> : Enc32 {
90 let Inst{7-0} = SSRC0;
91 let Inst{15-8} = SSRC1;
92 let Inst{22-16} = SDST;
94 let Inst{31-30} = 0x2; // encoding
97 class SOPCe <bits<7> op> : Enc32 {
102 let Inst{7-0} = SSRC0;
103 let Inst{15-8} = SSRC1;
104 let Inst{22-16} = op;
105 let Inst{31-23} = 0x17e;
108 class SOPKe <bits<5> op> : Enc32 {
113 let Inst{15-0} = SIMM16;
114 let Inst{22-16} = SDST;
115 let Inst{27-23} = op;
116 let Inst{31-28} = 0xb; //encoding
119 class SOPPe <bits<7> op> : Enc32 {
123 let Inst{15-0} = simm16;
124 let Inst{22-16} = op;
125 let Inst{31-23} = 0x17f; // encoding
128 class SMRDe <bits<5> op, bits<1> imm> : Enc32 {
134 let Inst{7-0} = OFFSET;
136 let Inst{14-9} = SBASE{6-1};
137 let Inst{21-15} = SDST;
138 let Inst{26-22} = op;
139 let Inst{31-27} = 0x18; //encoding
142 class SOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
143 InstSI<outs, ins, asm, pattern>, SOP1e <op> {
147 let hasSideEffects = 0;
151 class SOP2 <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
152 InstSI <outs, ins, asm, pattern>, SOP2e<op> {
156 let hasSideEffects = 0;
160 class SOPC <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
161 InstSI<outs, ins, asm, pattern>, SOPCe <op> {
163 let DisableEncoding = "$dst";
166 let hasSideEffects = 0;
170 class SOPK <bits<5> op, dag outs, dag ins, string asm, list<dag> pattern> :
171 InstSI <outs, ins , asm, pattern>, SOPKe<op> {
175 let hasSideEffects = 0;
179 class SOPP <bits<7> op, dag ins, string asm, list<dag> pattern> :
180 InstSI <(outs), ins, asm, pattern >, SOPPe <op> {
184 let hasSideEffects = 0;
188 class SMRD <bits<5> op, bits<1> imm, dag outs, dag ins, string asm,
189 list<dag> pattern> : InstSI<outs, ins, asm, pattern>, SMRDe<op, imm> {
195 let UseNamedOperandTable = 1;
198 //===----------------------------------------------------------------------===//
199 // Vector ALU operations
200 //===----------------------------------------------------------------------===//
202 class VOP1e <bits<8> op> : Enc32 {
207 let Inst{8-0} = SRC0;
209 let Inst{24-17} = VDST;
210 let Inst{31-25} = 0x3f; //encoding
213 class VOP2e <bits<6> op> : Enc32 {
219 let Inst{8-0} = SRC0;
220 let Inst{16-9} = VSRC1;
221 let Inst{24-17} = VDST;
222 let Inst{30-25} = op;
223 let Inst{31} = 0x0; //encoding
226 class VOP3e <bits<9> op> : Enc64 {
229 bits<2> src0_modifiers;
231 bits<2> src1_modifiers;
233 bits<2> src2_modifiers;
239 let Inst{8} = src0_modifiers{1};
240 let Inst{9} = src1_modifiers{1};
241 let Inst{10} = src2_modifiers{1};
242 let Inst{11} = clamp;
243 let Inst{25-17} = op;
244 let Inst{31-26} = 0x34; //encoding
245 let Inst{40-32} = src0;
246 let Inst{49-41} = src1;
247 let Inst{58-50} = src2;
248 let Inst{60-59} = omod;
249 let Inst{61} = src0_modifiers{0};
250 let Inst{62} = src1_modifiers{0};
251 let Inst{63} = src2_modifiers{0};
254 class VOP3be <bits<9> op> : Enc64 {
257 bits<2> src0_modifiers;
259 bits<2> src1_modifiers;
261 bits<2> src2_modifiers;
267 let Inst{14-8} = sdst;
268 let Inst{25-17} = op;
269 let Inst{31-26} = 0x34; //encoding
270 let Inst{40-32} = src0;
271 let Inst{49-41} = src1;
272 let Inst{58-50} = src2;
273 let Inst{60-59} = omod;
274 let Inst{61} = src0_modifiers{0};
275 let Inst{62} = src1_modifiers{0};
276 let Inst{63} = src2_modifiers{0};
279 class VOPCe <bits<8> op> : Enc32 {
284 let Inst{8-0} = SRC0;
285 let Inst{16-9} = VSRC1;
286 let Inst{24-17} = op;
287 let Inst{31-25} = 0x3e;
290 class VINTRPe <bits<2> op> : Enc32 {
297 let Inst{7-0} = VSRC;
298 let Inst{9-8} = ATTRCHAN;
299 let Inst{15-10} = ATTR;
300 let Inst{17-16} = op;
301 let Inst{25-18} = VDST;
302 let Inst{31-26} = 0x32; // encoding
305 class DSe <bits<8> op> : Enc64 {
315 let Inst{7-0} = offset0;
316 let Inst{15-8} = offset1;
318 let Inst{25-18} = op;
319 let Inst{31-26} = 0x36; //encoding
320 let Inst{39-32} = addr;
321 let Inst{47-40} = data0;
322 let Inst{55-48} = data1;
323 let Inst{63-56} = vdst;
326 class MUBUFe <bits<7> op> : Enc64 {
341 let Inst{11-0} = offset;
342 let Inst{12} = offen;
343 let Inst{13} = idxen;
345 let Inst{15} = addr64;
347 let Inst{24-18} = op;
348 let Inst{31-26} = 0x38; //encoding
349 let Inst{39-32} = vaddr;
350 let Inst{47-40} = vdata;
351 let Inst{52-48} = srsrc{6-2};
354 let Inst{63-56} = soffset;
357 class MTBUFe <bits<3> op> : Enc64 {
373 let Inst{11-0} = OFFSET;
374 let Inst{12} = OFFEN;
375 let Inst{13} = IDXEN;
377 let Inst{15} = ADDR64;
378 let Inst{18-16} = op;
379 let Inst{22-19} = DFMT;
380 let Inst{25-23} = NFMT;
381 let Inst{31-26} = 0x3a; //encoding
382 let Inst{39-32} = VADDR;
383 let Inst{47-40} = VDATA;
384 let Inst{52-48} = SRSRC{6-2};
387 let Inst{63-56} = SOFFSET;
390 class MIMGe <bits<7> op> : Enc64 {
405 let Inst{11-8} = DMASK;
406 let Inst{12} = UNORM;
412 let Inst{24-18} = op;
414 let Inst{31-26} = 0x3c;
415 let Inst{39-32} = VADDR;
416 let Inst{47-40} = VDATA;
417 let Inst{52-48} = SRSRC{6-2};
418 let Inst{57-53} = SSAMP{6-2};
435 let Inst{10} = COMPR;
438 let Inst{31-26} = 0x3e;
439 let Inst{39-32} = VSRC0;
440 let Inst{47-40} = VSRC1;
441 let Inst{55-48} = VSRC2;
442 let Inst{63-56} = VSRC3;
445 let Uses = [EXEC] in {
447 class VOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
448 InstSI <outs, ins, asm, pattern>, VOP1e<op> {
452 let hasSideEffects = 0;
453 let UseNamedOperandTable = 1;
457 class VOP2 <bits<6> op, dag outs, dag ins, string asm, list<dag> pattern> :
458 InstSI <outs, ins, asm, pattern>, VOP2e<op> {
462 let hasSideEffects = 0;
463 let UseNamedOperandTable = 1;
467 class VOP3 <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> :
468 VOP3Common <outs, ins, asm, pattern>, VOP3e<op>;
470 class VOP3b <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> :
471 VOP3Common <outs, ins, asm, pattern>, VOP3be<op>;
473 class VOPC <bits<8> op, dag ins, string asm, list<dag> pattern> :
474 InstSI <(outs VCCReg:$dst), ins, asm, pattern>, VOPCe <op> {
476 let DisableEncoding = "$dst";
479 let hasSideEffects = 0;
480 let UseNamedOperandTable = 1;
484 class VINTRP <bits <2> op, dag outs, dag ins, string asm, list<dag> pattern> :
485 InstSI <outs, ins, asm, pattern>, VINTRPe<op> {
487 let neverHasSideEffects = 1;
492 } // End Uses = [EXEC]
494 //===----------------------------------------------------------------------===//
495 // Vector I/O operations
496 //===----------------------------------------------------------------------===//
498 let Uses = [EXEC] in {
500 class DS <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
501 InstSI <outs, ins, asm, pattern> , DSe<op> {
504 let UseNamedOperandTable = 1;
507 class MUBUF <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
508 InstSI<outs, ins, asm, pattern>, MUBUFe <op> {
514 let neverHasSideEffects = 1;
515 let UseNamedOperandTable = 1;
518 class MTBUF <bits<3> op, dag outs, dag ins, string asm, list<dag> pattern> :
519 InstSI<outs, ins, asm, pattern>, MTBUFe <op> {
525 let neverHasSideEffects = 1;
528 class MIMG <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
529 InstSI <outs, ins, asm, pattern>, MIMGe <op> {
538 (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm,
539 VReg_32:$src0, VReg_32:$src1, VReg_32:$src2, VReg_32:$src3),
540 "EXP $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3",
546 } // End Uses = [EXEC]