1 //===-- SIISelLowering.cpp - SI DAG Lowering Implementation ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Custom DAG lowering for SI
13 //===----------------------------------------------------------------------===//
15 #include "SIISelLowering.h"
17 #include "AMDGPUIntrinsicInfo.h"
18 #include "AMDGPUSubtarget.h"
19 #include "SIInstrInfo.h"
20 #include "SIMachineFunctionInfo.h"
21 #include "SIRegisterInfo.h"
22 #include "llvm/CodeGen/CallingConvLower.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/SelectionDAG.h"
26 #include "llvm/IR/Function.h"
27 #include "llvm/ADT/SmallString.h"
31 SITargetLowering::SITargetLowering(TargetMachine &TM) :
32 AMDGPUTargetLowering(TM) {
33 addRegisterClass(MVT::i1, &AMDGPU::VReg_1RegClass);
34 addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass);
36 addRegisterClass(MVT::v32i8, &AMDGPU::SReg_256RegClass);
37 addRegisterClass(MVT::v64i8, &AMDGPU::SReg_512RegClass);
39 addRegisterClass(MVT::i32, &AMDGPU::SReg_32RegClass);
40 addRegisterClass(MVT::f32, &AMDGPU::VReg_32RegClass);
42 addRegisterClass(MVT::f64, &AMDGPU::VReg_64RegClass);
43 addRegisterClass(MVT::v2i32, &AMDGPU::SReg_64RegClass);
44 addRegisterClass(MVT::v2f32, &AMDGPU::VReg_64RegClass);
46 addRegisterClass(MVT::v4i32, &AMDGPU::SReg_128RegClass);
47 addRegisterClass(MVT::v4f32, &AMDGPU::VReg_128RegClass);
49 addRegisterClass(MVT::v8i32, &AMDGPU::VReg_256RegClass);
50 addRegisterClass(MVT::v8f32, &AMDGPU::VReg_256RegClass);
52 addRegisterClass(MVT::v16i32, &AMDGPU::VReg_512RegClass);
53 addRegisterClass(MVT::v16f32, &AMDGPU::VReg_512RegClass);
55 computeRegisterProperties();
58 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
59 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
60 setCondCodeAction(ISD::SETUGE, MVT::f32, Expand);
61 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
62 setCondCodeAction(ISD::SETULE, MVT::f32, Expand);
63 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
65 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
66 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
67 setCondCodeAction(ISD::SETUGE, MVT::f64, Expand);
68 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
69 setCondCodeAction(ISD::SETULE, MVT::f64, Expand);
70 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
72 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i32, Expand);
73 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Expand);
74 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i32, Expand);
75 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16f32, Expand);
77 setOperationAction(ISD::ADD, MVT::i32, Legal);
78 setOperationAction(ISD::ADDC, MVT::i32, Legal);
79 setOperationAction(ISD::ADDE, MVT::i32, Legal);
80 setOperationAction(ISD::SUBC, MVT::i32, Legal);
81 setOperationAction(ISD::SUBE, MVT::i32, Legal);
83 // We need to custom lower vector stores from local memory
84 setOperationAction(ISD::LOAD, MVT::v2i32, Custom);
85 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
86 setOperationAction(ISD::LOAD, MVT::v8i32, Custom);
87 setOperationAction(ISD::LOAD, MVT::v16i32, Custom);
89 setOperationAction(ISD::STORE, MVT::v8i32, Custom);
90 setOperationAction(ISD::STORE, MVT::v16i32, Custom);
92 // We need to custom lower loads/stores from private memory
93 setOperationAction(ISD::LOAD, MVT::i32, Custom);
94 setOperationAction(ISD::LOAD, MVT::v2i32, Custom);
95 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
96 setOperationAction(ISD::LOAD, MVT::v8i32, Custom);
98 setOperationAction(ISD::STORE, MVT::i1, Custom);
99 setOperationAction(ISD::STORE, MVT::i32, Custom);
100 setOperationAction(ISD::STORE, MVT::v2i32, Custom);
101 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
103 setOperationAction(ISD::SELECT, MVT::f32, Promote);
104 AddPromotedToType(ISD::SELECT, MVT::f32, MVT::i32);
105 setOperationAction(ISD::SELECT, MVT::i64, Custom);
106 setOperationAction(ISD::SELECT, MVT::f64, Promote);
107 AddPromotedToType(ISD::SELECT, MVT::f64, MVT::i64);
109 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
110 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
111 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
112 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
114 setOperationAction(ISD::SETCC, MVT::v2i1, Expand);
115 setOperationAction(ISD::SETCC, MVT::v4i1, Expand);
117 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Legal);
118 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Custom);
119 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Custom);
121 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Legal);
122 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
123 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Custom);
125 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Legal);
126 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
127 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Custom);
129 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Custom);
131 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Custom);
133 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
134 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::f32, Custom);
135 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v16i8, Custom);
136 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v4f32, Custom);
138 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
139 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
141 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
142 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Custom);
143 setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Custom);
144 setLoadExtAction(ISD::SEXTLOAD, MVT::i32, Expand);
145 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i16, Expand);
146 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i16, Expand);
148 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
149 setLoadExtAction(ISD::ZEXTLOAD, MVT::i8, Custom);
150 setLoadExtAction(ISD::ZEXTLOAD, MVT::i16, Custom);
151 setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, Expand);
153 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
154 setLoadExtAction(ISD::EXTLOAD, MVT::i8, Custom);
155 setLoadExtAction(ISD::EXTLOAD, MVT::i16, Custom);
156 setLoadExtAction(ISD::EXTLOAD, MVT::i32, Expand);
157 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
159 setTruncStoreAction(MVT::i32, MVT::i8, Custom);
160 setTruncStoreAction(MVT::i32, MVT::i16, Custom);
161 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
162 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
163 setTruncStoreAction(MVT::v8i32, MVT::v8i16, Expand);
164 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Expand);
166 setOperationAction(ISD::LOAD, MVT::i1, Custom);
168 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Expand);
169 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
171 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
172 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
173 setOperationAction(ISD::FrameIndex, MVT::i32, Custom);
175 // These should use UDIVREM, so set them to expand
176 setOperationAction(ISD::UDIV, MVT::i64, Expand);
177 setOperationAction(ISD::UREM, MVT::i64, Expand);
179 // We only support LOAD/STORE and vector manipulation ops for vectors
180 // with > 4 elements.
182 MVT::v8i32, MVT::v8f32, MVT::v16i32, MVT::v16f32
185 for (MVT VT : VecTypes) {
186 for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op) {
190 case ISD::BUILD_VECTOR:
192 case ISD::EXTRACT_VECTOR_ELT:
193 case ISD::INSERT_VECTOR_ELT:
194 case ISD::CONCAT_VECTORS:
195 case ISD::INSERT_SUBVECTOR:
196 case ISD::EXTRACT_SUBVECTOR:
199 setOperationAction(Op, VT, Expand);
205 for (int I = MVT::v1f64; I <= MVT::v8f64; ++I) {
206 MVT::SimpleValueType VT = static_cast<MVT::SimpleValueType>(I);
207 setOperationAction(ISD::FTRUNC, VT, Expand);
208 setOperationAction(ISD::FCEIL, VT, Expand);
209 setOperationAction(ISD::FFLOOR, VT, Expand);
212 if (Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS) {
213 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
214 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
215 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
216 setOperationAction(ISD::FRINT, MVT::f64, Legal);
219 // FIXME: These should be removed and handled the same was as f32 fneg. Source
220 // modifiers also work for the double instructions.
221 setOperationAction(ISD::FNEG, MVT::f64, Expand);
222 setOperationAction(ISD::FABS, MVT::f64, Expand);
224 setTargetDAGCombine(ISD::SELECT_CC);
225 setTargetDAGCombine(ISD::SETCC);
227 setTargetDAGCombine(ISD::UINT_TO_FP);
229 setSchedulingPreference(Sched::RegPressure);
232 //===----------------------------------------------------------------------===//
233 // TargetLowering queries
234 //===----------------------------------------------------------------------===//
236 bool SITargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
238 bool *IsFast) const {
242 // XXX: This depends on the address space and also we may want to revist
243 // the alignment values we specify in the DataLayout.
245 // TODO: I think v3i32 should allow unaligned accesses on CI with DS_READ_B96,
246 // which isn't a simple VT.
247 if (!VT.isSimple() || VT == MVT::Other)
250 // XXX - CI changes say "Support for unaligned memory accesses" but I don't
251 // see what for specifically. The wording everywhere else seems to be the
254 // 3.6.4 - Operations using pairs of VGPRs (for example: double-floats) have
255 // no alignment restrictions.
256 if (AddrSpace == AMDGPUAS::PRIVATE_ADDRESS) {
257 // Using any pair of GPRs should be the same as any other pair.
260 return VT.bitsGE(MVT::i64);
263 // XXX - The only mention I see of this in the ISA manual is for LDS direct
264 // reads the "byte address and must be dword aligned". Is it also true for the
265 // normal loads and stores?
266 if (AddrSpace == AMDGPUAS::LOCAL_ADDRESS)
269 // 8.1.6 - For Dword or larger reads or writes, the two LSBs of the
270 // byte-address are ignored, thus forcing Dword alignment.
273 return VT.bitsGT(MVT::i32);
276 TargetLoweringBase::LegalizeTypeAction
277 SITargetLowering::getPreferredVectorAction(EVT VT) const {
278 if (VT.getVectorNumElements() != 1 && VT.getScalarType().bitsLE(MVT::i16))
279 return TypeSplitVector;
281 return TargetLoweringBase::getPreferredVectorAction(VT);
284 bool SITargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
286 const SIInstrInfo *TII =
287 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
288 return TII->isInlineConstant(Imm);
291 SDValue SITargetLowering::LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT,
292 SDLoc DL, SDValue Chain,
293 unsigned Offset, bool Signed) const {
294 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
295 PointerType *PtrTy = PointerType::get(VT.getTypeForEVT(*DAG.getContext()),
296 AMDGPUAS::CONSTANT_ADDRESS);
297 SDValue BasePtr = DAG.getCopyFromReg(Chain, DL,
298 MRI.getLiveInVirtReg(AMDGPU::SGPR0_SGPR1), MVT::i64);
299 SDValue Ptr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
300 DAG.getConstant(Offset, MVT::i64));
301 return DAG.getExtLoad(Signed ? ISD::SEXTLOAD : ISD::ZEXTLOAD, DL, VT, Chain, Ptr,
302 MachinePointerInfo(UndefValue::get(PtrTy)), MemVT,
303 false, false, MemVT.getSizeInBits() >> 3);
307 SDValue SITargetLowering::LowerFormalArguments(
309 CallingConv::ID CallConv,
311 const SmallVectorImpl<ISD::InputArg> &Ins,
312 SDLoc DL, SelectionDAG &DAG,
313 SmallVectorImpl<SDValue> &InVals) const {
315 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
317 MachineFunction &MF = DAG.getMachineFunction();
318 FunctionType *FType = MF.getFunction()->getFunctionType();
319 SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
321 assert(CallConv == CallingConv::C);
323 SmallVector<ISD::InputArg, 16> Splits;
324 uint32_t Skipped = 0;
326 for (unsigned i = 0, e = Ins.size(), PSInputNum = 0; i != e; ++i) {
327 const ISD::InputArg &Arg = Ins[i];
329 // First check if it's a PS input addr
330 if (Info->ShaderType == ShaderType::PIXEL && !Arg.Flags.isInReg() &&
331 !Arg.Flags.isByVal()) {
333 assert((PSInputNum <= 15) && "Too many PS inputs!");
336 // We can savely skip PS inputs
342 Info->PSInputAddr |= 1 << PSInputNum++;
345 // Second split vertices into their elements
346 if (Info->ShaderType != ShaderType::COMPUTE && Arg.VT.isVector()) {
347 ISD::InputArg NewArg = Arg;
348 NewArg.Flags.setSplit();
349 NewArg.VT = Arg.VT.getVectorElementType();
351 // We REALLY want the ORIGINAL number of vertex elements here, e.g. a
352 // three or five element vertex only needs three or five registers,
353 // NOT four or eigth.
354 Type *ParamType = FType->getParamType(Arg.OrigArgIndex);
355 unsigned NumElements = ParamType->getVectorNumElements();
357 for (unsigned j = 0; j != NumElements; ++j) {
358 Splits.push_back(NewArg);
359 NewArg.PartOffset += NewArg.VT.getStoreSize();
362 } else if (Info->ShaderType != ShaderType::COMPUTE) {
363 Splits.push_back(Arg);
367 SmallVector<CCValAssign, 16> ArgLocs;
368 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
369 getTargetMachine(), ArgLocs, *DAG.getContext());
371 // At least one interpolation mode must be enabled or else the GPU will hang.
372 if (Info->ShaderType == ShaderType::PIXEL && (Info->PSInputAddr & 0x7F) == 0) {
373 Info->PSInputAddr |= 1;
374 CCInfo.AllocateReg(AMDGPU::VGPR0);
375 CCInfo.AllocateReg(AMDGPU::VGPR1);
378 // The pointer to the list of arguments is stored in SGPR0, SGPR1
379 if (Info->ShaderType == ShaderType::COMPUTE) {
380 CCInfo.AllocateReg(AMDGPU::SGPR0);
381 CCInfo.AllocateReg(AMDGPU::SGPR1);
382 MF.addLiveIn(AMDGPU::SGPR0_SGPR1, &AMDGPU::SReg_64RegClass);
385 if (Info->ShaderType == ShaderType::COMPUTE) {
386 getOriginalFunctionArgs(DAG, DAG.getMachineFunction().getFunction(), Ins,
390 AnalyzeFormalArguments(CCInfo, Splits);
392 for (unsigned i = 0, e = Ins.size(), ArgIdx = 0; i != e; ++i) {
394 const ISD::InputArg &Arg = Ins[i];
395 if (Skipped & (1 << i)) {
396 InVals.push_back(DAG.getUNDEF(Arg.VT));
400 CCValAssign &VA = ArgLocs[ArgIdx++];
401 EVT VT = VA.getLocVT();
405 EVT MemVT = Splits[i].VT;
406 // The first 36 bytes of the input buffer contains information about
407 // thread group and global sizes.
408 SDValue Arg = LowerParameter(DAG, VT, MemVT, DL, DAG.getRoot(),
409 36 + VA.getLocMemOffset(),
410 Ins[i].Flags.isSExt());
411 InVals.push_back(Arg);
414 assert(VA.isRegLoc() && "Parameter must be in a register!");
416 unsigned Reg = VA.getLocReg();
418 if (VT == MVT::i64) {
419 // For now assume it is a pointer
420 Reg = TRI->getMatchingSuperReg(Reg, AMDGPU::sub0,
421 &AMDGPU::SReg_64RegClass);
422 Reg = MF.addLiveIn(Reg, &AMDGPU::SReg_64RegClass);
423 InVals.push_back(DAG.getCopyFromReg(Chain, DL, Reg, VT));
427 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
429 Reg = MF.addLiveIn(Reg, RC);
430 SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, VT);
432 if (Arg.VT.isVector()) {
434 // Build a vector from the registers
435 Type *ParamType = FType->getParamType(Arg.OrigArgIndex);
436 unsigned NumElements = ParamType->getVectorNumElements();
438 SmallVector<SDValue, 4> Regs;
440 for (unsigned j = 1; j != NumElements; ++j) {
441 Reg = ArgLocs[ArgIdx++].getLocReg();
442 Reg = MF.addLiveIn(Reg, RC);
443 Regs.push_back(DAG.getCopyFromReg(Chain, DL, Reg, VT));
446 // Fill up the missing vector elements
447 NumElements = Arg.VT.getVectorNumElements() - NumElements;
448 for (unsigned j = 0; j != NumElements; ++j)
449 Regs.push_back(DAG.getUNDEF(VT));
451 InVals.push_back(DAG.getNode(ISD::BUILD_VECTOR, DL, Arg.VT, Regs));
455 InVals.push_back(Val);
460 MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
461 MachineInstr * MI, MachineBasicBlock * BB) const {
463 MachineBasicBlock::iterator I = *MI;
464 const SIInstrInfo *TII =
465 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
466 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
468 switch (MI->getOpcode()) {
470 return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
471 case AMDGPU::BRANCH: return BB;
472 case AMDGPU::SI_ADDR64_RSRC: {
473 unsigned SuperReg = MI->getOperand(0).getReg();
474 unsigned SubRegLo = MRI.createVirtualRegister(&AMDGPU::SGPR_64RegClass);
475 unsigned SubRegHi = MRI.createVirtualRegister(&AMDGPU::SGPR_64RegClass);
476 unsigned SubRegHiHi = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
477 unsigned SubRegHiLo = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
478 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B64), SubRegLo)
479 .addOperand(MI->getOperand(1));
480 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B32), SubRegHiLo)
482 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B32), SubRegHiHi)
483 .addImm(AMDGPU::RSRC_DATA_FORMAT >> 32);
484 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::REG_SEQUENCE), SubRegHi)
486 .addImm(AMDGPU::sub0)
488 .addImm(AMDGPU::sub1);
489 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::REG_SEQUENCE), SuperReg)
491 .addImm(AMDGPU::sub0_sub1)
493 .addImm(AMDGPU::sub2_sub3);
494 MI->eraseFromParent();
497 case AMDGPU::V_SUB_F64: {
498 unsigned DestReg = MI->getOperand(0).getReg();
499 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_ADD_F64), DestReg)
500 .addImm(0) // SRC0 modifiers
501 .addReg(MI->getOperand(1).getReg())
502 .addImm(1) // SRC1 modifiers
503 .addReg(MI->getOperand(2).getReg())
504 .addImm(0) // SRC2 modifiers
508 MI->eraseFromParent();
511 case AMDGPU::SI_RegisterStorePseudo: {
512 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
513 unsigned Reg = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
514 MachineInstrBuilder MIB =
515 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::SI_RegisterStore),
517 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
518 MIB.addOperand(MI->getOperand(i));
520 MI->eraseFromParent();
523 case AMDGPU::FABS_SI: {
524 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
525 const SIInstrInfo *TII =
526 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
527 unsigned Reg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
528 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_MOV_B32_e32),
531 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_AND_B32_e32),
532 MI->getOperand(0).getReg())
533 .addReg(MI->getOperand(1).getReg())
535 MI->eraseFromParent();
538 case AMDGPU::FNEG_SI: {
539 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
540 const SIInstrInfo *TII =
541 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
542 unsigned Reg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
543 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_MOV_B32_e32),
546 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_XOR_B32_e32),
547 MI->getOperand(0).getReg())
548 .addReg(MI->getOperand(1).getReg())
550 MI->eraseFromParent();
553 case AMDGPU::FCLAMP_SI: {
554 const SIInstrInfo *TII =
555 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
556 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_ADD_F32_e64),
557 MI->getOperand(0).getReg())
558 .addImm(0) // SRC0 modifiers
559 .addOperand(MI->getOperand(1))
560 .addImm(0) // SRC1 modifiers
564 MI->eraseFromParent();
570 EVT SITargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
571 if (!VT.isVector()) {
574 return MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
577 MVT SITargetLowering::getScalarShiftAmountTy(EVT VT) const {
581 bool SITargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
582 VT = VT.getScalarType();
587 switch (VT.getSimpleVT().SimpleTy) {
589 return false; /* There is V_MAD_F32 for f32 */
599 //===----------------------------------------------------------------------===//
600 // Custom DAG Lowering Operations
601 //===----------------------------------------------------------------------===//
603 SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
604 MachineFunction &MF = DAG.getMachineFunction();
605 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
606 switch (Op.getOpcode()) {
607 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
608 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
610 LoadSDNode *Load = dyn_cast<LoadSDNode>(Op);
611 EVT VT = Op.getValueType();
613 // These loads are legal.
614 if (Load->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS &&
615 VT.isVector() && VT.getVectorNumElements() == 2 &&
616 VT.getVectorElementType() == MVT::i32)
619 if (Op.getValueType().isVector() &&
620 (Load->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
621 Load->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS ||
622 (Load->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS &&
623 Op.getValueType().getVectorNumElements() > 4))) {
624 return SplitVectorLoad(Op, DAG);
626 SDValue Result = LowerLOAD(Op, DAG);
627 assert((!Result.getNode() ||
628 Result.getNode()->getNumValues() == 2) &&
629 "Load should return a value and a chain");
634 case ISD::SELECT: return LowerSELECT(Op, DAG);
635 case ISD::STORE: return LowerSTORE(Op, DAG);
636 case ISD::GlobalAddress: return LowerGlobalAddress(MFI, Op, DAG);
637 case ISD::INTRINSIC_WO_CHAIN: {
638 unsigned IntrinsicID =
639 cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
640 EVT VT = Op.getValueType();
642 //XXX: Hardcoded we only use two to store the pointer to the parameters.
643 unsigned NumUserSGPRs = 2;
644 switch (IntrinsicID) {
645 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
646 case Intrinsic::r600_read_ngroups_x:
647 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 0, false);
648 case Intrinsic::r600_read_ngroups_y:
649 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 4, false);
650 case Intrinsic::r600_read_ngroups_z:
651 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 8, false);
652 case Intrinsic::r600_read_global_size_x:
653 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 12, false);
654 case Intrinsic::r600_read_global_size_y:
655 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 16, false);
656 case Intrinsic::r600_read_global_size_z:
657 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 20, false);
658 case Intrinsic::r600_read_local_size_x:
659 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 24, false);
660 case Intrinsic::r600_read_local_size_y:
661 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 28, false);
662 case Intrinsic::r600_read_local_size_z:
663 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 32, false);
664 case Intrinsic::r600_read_tgid_x:
665 return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
666 AMDGPU::SReg_32RegClass.getRegister(NumUserSGPRs + 0), VT);
667 case Intrinsic::r600_read_tgid_y:
668 return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
669 AMDGPU::SReg_32RegClass.getRegister(NumUserSGPRs + 1), VT);
670 case Intrinsic::r600_read_tgid_z:
671 return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
672 AMDGPU::SReg_32RegClass.getRegister(NumUserSGPRs + 2), VT);
673 case Intrinsic::r600_read_tidig_x:
674 return CreateLiveInRegister(DAG, &AMDGPU::VReg_32RegClass,
676 case Intrinsic::r600_read_tidig_y:
677 return CreateLiveInRegister(DAG, &AMDGPU::VReg_32RegClass,
679 case Intrinsic::r600_read_tidig_z:
680 return CreateLiveInRegister(DAG, &AMDGPU::VReg_32RegClass,
682 case AMDGPUIntrinsic::SI_load_const: {
688 MachineMemOperand *MMO = MF.getMachineMemOperand(
689 MachinePointerInfo(),
690 MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant,
691 VT.getSizeInBits() / 8, 4);
692 return DAG.getMemIntrinsicNode(AMDGPUISD::LOAD_CONSTANT, DL,
693 Op->getVTList(), Ops, VT, MMO);
695 case AMDGPUIntrinsic::SI_sample:
696 return LowerSampleIntrinsic(AMDGPUISD::SAMPLE, Op, DAG);
697 case AMDGPUIntrinsic::SI_sampleb:
698 return LowerSampleIntrinsic(AMDGPUISD::SAMPLEB, Op, DAG);
699 case AMDGPUIntrinsic::SI_sampled:
700 return LowerSampleIntrinsic(AMDGPUISD::SAMPLED, Op, DAG);
701 case AMDGPUIntrinsic::SI_samplel:
702 return LowerSampleIntrinsic(AMDGPUISD::SAMPLEL, Op, DAG);
703 case AMDGPUIntrinsic::SI_vs_load_input:
704 return DAG.getNode(AMDGPUISD::LOAD_INPUT, DL, VT,
711 case ISD::INTRINSIC_VOID:
712 SDValue Chain = Op.getOperand(0);
713 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
715 switch (IntrinsicID) {
716 case AMDGPUIntrinsic::SI_tbuffer_store: {
734 EVT VT = Op.getOperand(3).getValueType();
736 MachineMemOperand *MMO = MF.getMachineMemOperand(
737 MachinePointerInfo(),
738 MachineMemOperand::MOStore,
739 VT.getSizeInBits() / 8, 4);
740 return DAG.getMemIntrinsicNode(AMDGPUISD::TBUFFER_STORE_FORMAT, DL,
741 Op->getVTList(), Ops, VT, MMO);
750 /// \brief Helper function for LowerBRCOND
751 static SDNode *findUser(SDValue Value, unsigned Opcode) {
753 SDNode *Parent = Value.getNode();
754 for (SDNode::use_iterator I = Parent->use_begin(), E = Parent->use_end();
757 if (I.getUse().get() != Value)
760 if (I->getOpcode() == Opcode)
766 /// This transforms the control flow intrinsics to get the branch destination as
767 /// last parameter, also switches branch target with BR if the need arise
768 SDValue SITargetLowering::LowerBRCOND(SDValue BRCOND,
769 SelectionDAG &DAG) const {
773 SDNode *Intr = BRCOND.getOperand(1).getNode();
774 SDValue Target = BRCOND.getOperand(2);
775 SDNode *BR = nullptr;
777 if (Intr->getOpcode() == ISD::SETCC) {
778 // As long as we negate the condition everything is fine
779 SDNode *SetCC = Intr;
780 assert(SetCC->getConstantOperandVal(1) == 1);
781 assert(cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() ==
783 Intr = SetCC->getOperand(0).getNode();
786 // Get the target from BR if we don't negate the condition
787 BR = findUser(BRCOND, ISD::BR);
788 Target = BR->getOperand(1);
791 assert(Intr->getOpcode() == ISD::INTRINSIC_W_CHAIN);
793 // Build the result and
794 SmallVector<EVT, 4> Res;
795 for (unsigned i = 1, e = Intr->getNumValues(); i != e; ++i)
796 Res.push_back(Intr->getValueType(i));
798 // operands of the new intrinsic call
799 SmallVector<SDValue, 4> Ops;
800 Ops.push_back(BRCOND.getOperand(0));
801 for (unsigned i = 1, e = Intr->getNumOperands(); i != e; ++i)
802 Ops.push_back(Intr->getOperand(i));
803 Ops.push_back(Target);
805 // build the new intrinsic call
806 SDNode *Result = DAG.getNode(
807 Res.size() > 1 ? ISD::INTRINSIC_W_CHAIN : ISD::INTRINSIC_VOID, DL,
808 DAG.getVTList(Res), Ops).getNode();
811 // Give the branch instruction our target
816 DAG.MorphNodeTo(BR, ISD::BR, BR->getVTList(), Ops);
819 SDValue Chain = SDValue(Result, Result->getNumValues() - 1);
821 // Copy the intrinsic results to registers
822 for (unsigned i = 1, e = Intr->getNumValues() - 1; i != e; ++i) {
823 SDNode *CopyToReg = findUser(SDValue(Intr, i), ISD::CopyToReg);
827 Chain = DAG.getCopyToReg(
829 CopyToReg->getOperand(1),
830 SDValue(Result, i - 1),
833 DAG.ReplaceAllUsesWith(SDValue(CopyToReg, 0), CopyToReg->getOperand(0));
836 // Remove the old intrinsic from the chain
837 DAG.ReplaceAllUsesOfValueWith(
838 SDValue(Intr, Intr->getNumValues() - 1),
839 Intr->getOperand(0));
844 SDValue SITargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
846 LoadSDNode *Load = cast<LoadSDNode>(Op);
847 SDValue Lowered = AMDGPUTargetLowering::LowerLOAD(Op, DAG);
848 if (Lowered.getNode())
851 if (Load->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS) {
855 EVT MemVT = Load->getMemoryVT();
857 assert(!MemVT.isVector() && "Private loads should be scalarized");
858 assert(!MemVT.isFloatingPoint() && "FP loads should be promoted to int");
860 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Load->getBasePtr(),
861 DAG.getConstant(2, MVT::i32));
863 // FIXME: REGISTER_LOAD should probably have a chain result.
864 SDValue Chain = Load->getChain();
865 SDValue LoLoad = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, MVT::i32,
867 DAG.getTargetConstant(0, MVT::i32),
870 SDValue Ret = LoLoad.getValue(0);
871 if (MemVT.getSizeInBits() == 64) {
872 // TODO: This needs a test to make sure the right thing is happening with
873 // the chain. That is hard without general function support.
875 SDValue IncPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, Ptr,
876 DAG.getConstant(1, MVT::i32));
878 SDValue HiLoad = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, MVT::i32,
880 DAG.getTargetConstant(0, MVT::i32),
883 Ret = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, LoLoad, HiLoad);
884 // Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
885 // LoLoad.getValue(1), HiLoad.getValue(1));
893 return DAG.getMergeValues(Ops, DL);
896 SDValue SITargetLowering::LowerSampleIntrinsic(unsigned Opcode,
898 SelectionDAG &DAG) const {
899 return DAG.getNode(Opcode, SDLoc(Op), Op.getValueType(), Op.getOperand(1),
905 SDValue SITargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
906 if (Op.getValueType() != MVT::i64)
910 SDValue Cond = Op.getOperand(0);
912 SDValue Zero = DAG.getConstant(0, MVT::i32);
913 SDValue One = DAG.getConstant(1, MVT::i32);
915 SDValue LHS = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, Op.getOperand(1));
916 SDValue RHS = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, Op.getOperand(2));
918 SDValue Lo0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, LHS, Zero);
919 SDValue Lo1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, RHS, Zero);
921 SDValue Lo = DAG.getSelect(DL, MVT::i32, Cond, Lo0, Lo1);
923 SDValue Hi0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, LHS, One);
924 SDValue Hi1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, RHS, One);
926 SDValue Hi = DAG.getSelect(DL, MVT::i32, Cond, Hi0, Hi1);
928 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v2i32, Lo, Hi);
929 return DAG.getNode(ISD::BITCAST, DL, MVT::i64, Res);
932 SDValue SITargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
934 StoreSDNode *Store = cast<StoreSDNode>(Op);
935 EVT VT = Store->getMemoryVT();
937 // These stores are legal.
938 if (Store->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS &&
939 VT.isVector() && VT.getVectorNumElements() == 2 &&
940 VT.getVectorElementType() == MVT::i32)
943 SDValue Ret = AMDGPUTargetLowering::LowerSTORE(Op, DAG);
947 if (VT.isVector() && VT.getVectorNumElements() >= 8)
948 return SplitVectorStore(Op, DAG);
951 return DAG.getTruncStore(Store->getChain(), DL,
952 DAG.getSExtOrTrunc(Store->getValue(), DL, MVT::i32),
953 Store->getBasePtr(), MVT::i1, Store->getMemOperand());
955 if (Store->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS)
958 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Store->getBasePtr(),
959 DAG.getConstant(2, MVT::i32));
960 SDValue Chain = Store->getChain();
961 SmallVector<SDValue, 8> Values;
963 if (Store->isTruncatingStore()) {
965 if (Store->getMemoryVT() == MVT::i8) {
967 } else if (Store->getMemoryVT() == MVT::i16) {
970 SDValue Dst = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, MVT::i32,
971 Chain, Store->getBasePtr(),
972 DAG.getConstant(0, MVT::i32));
973 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, Store->getBasePtr(),
974 DAG.getConstant(0x3, MVT::i32));
975 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
976 DAG.getConstant(3, MVT::i32));
977 SDValue MaskedValue = DAG.getNode(ISD::AND, DL, MVT::i32, Store->getValue(),
978 DAG.getConstant(Mask, MVT::i32));
979 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, MVT::i32,
980 MaskedValue, ShiftAmt);
981 SDValue RotrAmt = DAG.getNode(ISD::SUB, DL, MVT::i32,
982 DAG.getConstant(32, MVT::i32), ShiftAmt);
983 SDValue DstMask = DAG.getNode(ISD::ROTR, DL, MVT::i32,
984 DAG.getConstant(Mask, MVT::i32),
986 Dst = DAG.getNode(ISD::AND, DL, MVT::i32, Dst, DstMask);
987 Dst = DAG.getNode(ISD::OR, DL, MVT::i32, Dst, ShiftedValue);
989 Values.push_back(Dst);
990 } else if (VT == MVT::i64) {
991 for (unsigned i = 0; i < 2; ++i) {
992 Values.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32,
993 Store->getValue(), DAG.getConstant(i, MVT::i32)));
995 } else if (VT == MVT::i128) {
996 for (unsigned i = 0; i < 2; ++i) {
997 for (unsigned j = 0; j < 2; ++j) {
998 Values.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32,
999 DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i64,
1000 Store->getValue(), DAG.getConstant(i, MVT::i32)),
1001 DAG.getConstant(j, MVT::i32)));
1005 Values.push_back(Store->getValue());
1008 for (unsigned i = 0; i < Values.size(); ++i) {
1009 SDValue PartPtr = DAG.getNode(ISD::ADD, DL, MVT::i32,
1010 Ptr, DAG.getConstant(i, MVT::i32));
1011 Chain = DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other,
1012 Chain, Values[i], PartPtr,
1013 DAG.getTargetConstant(0, MVT::i32));
1018 //===----------------------------------------------------------------------===//
1019 // Custom DAG optimizations
1020 //===----------------------------------------------------------------------===//
1022 SDValue SITargetLowering::performUCharToFloatCombine(SDNode *N,
1023 DAGCombinerInfo &DCI) {
1024 EVT VT = N->getValueType(0);
1025 EVT ScalarVT = VT.getScalarType();
1026 if (ScalarVT != MVT::f32)
1029 SelectionDAG &DAG = DCI.DAG;
1032 SDValue Src = N->getOperand(0);
1033 EVT SrcVT = Src.getValueType();
1035 // TODO: We could try to match extracting the higher bytes, which would be
1036 // easier if i8 vectors weren't promoted to i32 vectors, particularly after
1037 // types are legalized. v4i8 -> v4f32 is probably the only case to worry
1038 // about in practice.
1039 if (DCI.isAfterLegalizeVectorOps() && SrcVT == MVT::i32) {
1040 if (DAG.MaskedValueIsZero(Src, APInt::getHighBitsSet(32, 24))) {
1041 SDValue Cvt = DAG.getNode(AMDGPUISD::CVT_F32_UBYTE0, DL, VT, Src);
1042 DCI.AddToWorklist(Cvt.getNode());
1047 // We are primarily trying to catch operations on illegal vector types
1048 // before they are expanded.
1049 // For scalars, we can use the more flexible method of checking masked bits
1050 // after legalization.
1051 if (!DCI.isBeforeLegalize() ||
1052 !SrcVT.isVector() ||
1053 SrcVT.getVectorElementType() != MVT::i8) {
1057 assert(DCI.isBeforeLegalize() && "Unexpected legal type");
1059 // Weird sized vectors are a pain to handle, but we know 3 is really the same
1061 unsigned NElts = SrcVT.getVectorNumElements();
1062 if (!SrcVT.isSimple() && NElts != 3)
1065 // Handle v4i8 -> v4f32 extload. Replace the v4i8 with a legal i32 load to
1066 // prevent a mess from expanding to v4i32 and repacking.
1067 if (ISD::isNormalLoad(Src.getNode()) && Src.hasOneUse()) {
1068 EVT LoadVT = getEquivalentMemType(*DAG.getContext(), SrcVT);
1069 EVT RegVT = getEquivalentLoadRegType(*DAG.getContext(), SrcVT);
1070 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f32, NElts);
1072 LoadSDNode *Load = cast<LoadSDNode>(Src);
1073 SDValue NewLoad = DAG.getExtLoad(ISD::ZEXTLOAD, DL, RegVT,
1077 Load->getMemOperand());
1079 // Make sure successors of the original load stay after it by updating
1080 // them to use the new Chain.
1081 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), NewLoad.getValue(1));
1083 SmallVector<SDValue, 4> Elts;
1084 if (RegVT.isVector())
1085 DAG.ExtractVectorElements(NewLoad, Elts);
1087 Elts.push_back(NewLoad);
1089 SmallVector<SDValue, 4> Ops;
1091 unsigned EltIdx = 0;
1092 for (SDValue Elt : Elts) {
1093 unsigned ComponentsInElt = std::min(4u, NElts - 4 * EltIdx);
1094 for (unsigned I = 0; I < ComponentsInElt; ++I) {
1095 unsigned Opc = AMDGPUISD::CVT_F32_UBYTE0 + I;
1096 SDValue Cvt = DAG.getNode(Opc, DL, MVT::f32, Elt);
1097 DCI.AddToWorklist(Cvt.getNode());
1104 assert(Ops.size() == NElts);
1106 return DAG.getNode(ISD::BUILD_VECTOR, DL, FloatVT, Ops);
1112 SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
1113 DAGCombinerInfo &DCI) const {
1114 SelectionDAG &DAG = DCI.DAG;
1116 EVT VT = N->getValueType(0);
1118 switch (N->getOpcode()) {
1119 default: return AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
1120 case ISD::SELECT_CC: {
1121 ConstantSDNode *True, *False;
1122 // i1 selectcc(l, r, -1, 0, cc) -> i1 setcc(l, r, cc)
1123 if ((True = dyn_cast<ConstantSDNode>(N->getOperand(2)))
1124 && (False = dyn_cast<ConstantSDNode>(N->getOperand(3)))
1125 && True->isAllOnesValue()
1126 && False->isNullValue()
1128 return DAG.getNode(ISD::SETCC, DL, VT, N->getOperand(0),
1129 N->getOperand(1), N->getOperand(4));
1135 SDValue Arg0 = N->getOperand(0);
1136 SDValue Arg1 = N->getOperand(1);
1137 SDValue CC = N->getOperand(2);
1138 ConstantSDNode * C = nullptr;
1139 ISD::CondCode CCOp = dyn_cast<CondCodeSDNode>(CC)->get();
1141 // i1 setcc (sext(i1), 0, setne) -> i1 setcc(i1, 0, setne)
1143 && Arg0.getOpcode() == ISD::SIGN_EXTEND
1144 && Arg0.getOperand(0).getValueType() == MVT::i1
1145 && (C = dyn_cast<ConstantSDNode>(Arg1))
1147 && CCOp == ISD::SETNE) {
1148 return SimplifySetCC(VT, Arg0.getOperand(0),
1149 DAG.getConstant(0, MVT::i1), CCOp, true, DCI, DL);
1154 case AMDGPUISD::CVT_F32_UBYTE0:
1155 case AMDGPUISD::CVT_F32_UBYTE1:
1156 case AMDGPUISD::CVT_F32_UBYTE2:
1157 case AMDGPUISD::CVT_F32_UBYTE3: {
1158 unsigned Offset = N->getOpcode() - AMDGPUISD::CVT_F32_UBYTE0;
1160 SDValue Src = N->getOperand(0);
1161 APInt Demanded = APInt::getBitsSet(32, 8 * Offset, 8 * Offset + 8);
1163 APInt KnownZero, KnownOne;
1164 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
1165 !DCI.isBeforeLegalizeOps());
1166 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1167 if (TLO.ShrinkDemandedConstant(Src, Demanded) ||
1168 TLI.SimplifyDemandedBits(Src, Demanded, KnownZero, KnownOne, TLO)) {
1169 DCI.CommitTargetLoweringOpt(TLO);
1175 case ISD::UINT_TO_FP: {
1176 return performUCharToFloatCombine(N, DCI);
1180 return AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
1183 /// \brief Test if RegClass is one of the VSrc classes
1184 static bool isVSrc(unsigned RegClass) {
1185 return AMDGPU::VSrc_32RegClassID == RegClass ||
1186 AMDGPU::VSrc_64RegClassID == RegClass;
1189 /// \brief Test if RegClass is one of the SSrc classes
1190 static bool isSSrc(unsigned RegClass) {
1191 return AMDGPU::SSrc_32RegClassID == RegClass ||
1192 AMDGPU::SSrc_64RegClassID == RegClass;
1195 /// \brief Analyze the possible immediate value Op
1197 /// Returns -1 if it isn't an immediate, 0 if it's and inline immediate
1198 /// and the immediate value if it's a literal immediate
1199 int32_t SITargetLowering::analyzeImmediate(const SDNode *N) const {
1206 if (const ConstantSDNode *Node = dyn_cast<ConstantSDNode>(N)) {
1207 if (Node->getZExtValue() >> 32) {
1210 Imm.I = Node->getSExtValue();
1211 } else if (const ConstantFPSDNode *Node = dyn_cast<ConstantFPSDNode>(N)) {
1212 if (N->getValueType(0) != MVT::f32)
1214 Imm.F = Node->getValueAPF().convertToFloat();
1216 return -1; // It isn't an immediate
1218 if ((Imm.I >= -16 && Imm.I <= 64) ||
1219 Imm.F == 0.5f || Imm.F == -0.5f ||
1220 Imm.F == 1.0f || Imm.F == -1.0f ||
1221 Imm.F == 2.0f || Imm.F == -2.0f ||
1222 Imm.F == 4.0f || Imm.F == -4.0f)
1223 return 0; // It's an inline immediate
1225 return Imm.I; // It's a literal immediate
1228 /// \brief Try to fold an immediate directly into an instruction
1229 bool SITargetLowering::foldImm(SDValue &Operand, int32_t &Immediate,
1230 bool &ScalarSlotUsed) const {
1232 MachineSDNode *Mov = dyn_cast<MachineSDNode>(Operand);
1233 const SIInstrInfo *TII =
1234 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
1235 if (!Mov || !TII->isMov(Mov->getMachineOpcode()))
1238 const SDValue &Op = Mov->getOperand(0);
1239 int32_t Value = analyzeImmediate(Op.getNode());
1241 // Not an immediate at all
1244 } else if (Value == 0) {
1245 // Inline immediates can always be fold
1249 } else if (Value == Immediate) {
1250 // Already fold literal immediate
1254 } else if (!ScalarSlotUsed && !Immediate) {
1255 // Fold this literal immediate
1256 ScalarSlotUsed = true;
1266 const TargetRegisterClass *SITargetLowering::getRegClassForNode(
1267 SelectionDAG &DAG, const SDValue &Op) const {
1268 const SIInstrInfo *TII =
1269 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
1270 const SIRegisterInfo &TRI = TII->getRegisterInfo();
1272 if (!Op->isMachineOpcode()) {
1273 switch(Op->getOpcode()) {
1274 case ISD::CopyFromReg: {
1275 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1276 unsigned Reg = cast<RegisterSDNode>(Op->getOperand(1))->getReg();
1277 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
1278 return MRI.getRegClass(Reg);
1280 return TRI.getPhysRegClass(Reg);
1282 default: return nullptr;
1285 const MCInstrDesc &Desc = TII->get(Op->getMachineOpcode());
1286 int OpClassID = Desc.OpInfo[Op.getResNo()].RegClass;
1287 if (OpClassID != -1) {
1288 return TRI.getRegClass(OpClassID);
1290 switch(Op.getMachineOpcode()) {
1291 case AMDGPU::COPY_TO_REGCLASS:
1292 // Operand 1 is the register class id for COPY_TO_REGCLASS instructions.
1293 OpClassID = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
1295 // If the COPY_TO_REGCLASS instruction is copying to a VSrc register
1296 // class, then the register class for the value could be either a
1297 // VReg or and SReg. In order to get a more accurate
1298 if (OpClassID == AMDGPU::VSrc_32RegClassID ||
1299 OpClassID == AMDGPU::VSrc_64RegClassID) {
1300 return getRegClassForNode(DAG, Op.getOperand(0));
1302 return TRI.getRegClass(OpClassID);
1303 case AMDGPU::EXTRACT_SUBREG: {
1304 int SubIdx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
1305 const TargetRegisterClass *SuperClass =
1306 getRegClassForNode(DAG, Op.getOperand(0));
1307 return TRI.getSubClassWithSubReg(SuperClass, SubIdx);
1309 case AMDGPU::REG_SEQUENCE:
1310 // Operand 0 is the register class id for REG_SEQUENCE instructions.
1311 return TRI.getRegClass(
1312 cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue());
1314 return getRegClassFor(Op.getSimpleValueType());
1318 /// \brief Does "Op" fit into register class "RegClass" ?
1319 bool SITargetLowering::fitsRegClass(SelectionDAG &DAG, const SDValue &Op,
1320 unsigned RegClass) const {
1321 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
1322 const TargetRegisterClass *RC = getRegClassForNode(DAG, Op);
1326 return TRI->getRegClass(RegClass)->hasSubClassEq(RC);
1329 /// \brief Make sure that we don't exeed the number of allowed scalars
1330 void SITargetLowering::ensureSRegLimit(SelectionDAG &DAG, SDValue &Operand,
1332 bool &ScalarSlotUsed) const {
1334 // First map the operands register class to a destination class
1335 if (RegClass == AMDGPU::VSrc_32RegClassID)
1336 RegClass = AMDGPU::VReg_32RegClassID;
1337 else if (RegClass == AMDGPU::VSrc_64RegClassID)
1338 RegClass = AMDGPU::VReg_64RegClassID;
1342 // Nothing to do if they fit naturally
1343 if (fitsRegClass(DAG, Operand, RegClass))
1346 // If the scalar slot isn't used yet use it now
1347 if (!ScalarSlotUsed) {
1348 ScalarSlotUsed = true;
1352 // This is a conservative aproach. It is possible that we can't determine the
1353 // correct register class and copy too often, but better safe than sorry.
1354 SDValue RC = DAG.getTargetConstant(RegClass, MVT::i32);
1355 SDNode *Node = DAG.getMachineNode(TargetOpcode::COPY_TO_REGCLASS, SDLoc(),
1356 Operand.getValueType(), Operand, RC);
1357 Operand = SDValue(Node, 0);
1360 /// \returns true if \p Node's operands are different from the SDValue list
1362 static bool isNodeChanged(const SDNode *Node, const std::vector<SDValue> &Ops) {
1363 for (unsigned i = 0, e = Node->getNumOperands(); i < e; ++i) {
1364 if (Ops[i].getNode() != Node->getOperand(i).getNode()) {
1371 /// \brief Try to fold the Nodes operands into the Node
1372 SDNode *SITargetLowering::foldOperands(MachineSDNode *Node,
1373 SelectionDAG &DAG) const {
1375 // Original encoding (either e32 or e64)
1376 int Opcode = Node->getMachineOpcode();
1377 const SIInstrInfo *TII =
1378 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
1379 const MCInstrDesc *Desc = &TII->get(Opcode);
1381 unsigned NumDefs = Desc->getNumDefs();
1382 unsigned NumOps = Desc->getNumOperands();
1384 // Commuted opcode if available
1385 int OpcodeRev = Desc->isCommutable() ? TII->commuteOpcode(Opcode) : -1;
1386 const MCInstrDesc *DescRev = OpcodeRev == -1 ? nullptr : &TII->get(OpcodeRev);
1388 assert(!DescRev || DescRev->getNumDefs() == NumDefs);
1389 assert(!DescRev || DescRev->getNumOperands() == NumOps);
1391 // e64 version if available, -1 otherwise
1392 int OpcodeE64 = AMDGPU::getVOPe64(Opcode);
1393 const MCInstrDesc *DescE64 = OpcodeE64 == -1 ? nullptr : &TII->get(OpcodeE64);
1394 int InputModifiers[3] = {0};
1396 assert(!DescE64 || DescE64->getNumDefs() == NumDefs);
1398 int32_t Immediate = Desc->getSize() == 4 ? 0 : -1;
1399 bool HaveVSrc = false, HaveSSrc = false;
1401 // First figure out what we already have in this instruction.
1402 for (unsigned i = 0, e = Node->getNumOperands(), Op = NumDefs;
1403 i != e && Op < NumOps; ++i, ++Op) {
1405 unsigned RegClass = Desc->OpInfo[Op].RegClass;
1406 if (isVSrc(RegClass))
1408 else if (isSSrc(RegClass))
1413 int32_t Imm = analyzeImmediate(Node->getOperand(i).getNode());
1414 if (Imm != -1 && Imm != 0) {
1415 // Literal immediate
1420 // If we neither have VSrc nor SSrc, it makes no sense to continue.
1421 if (!HaveVSrc && !HaveSSrc)
1424 // No scalar allowed when we have both VSrc and SSrc
1425 bool ScalarSlotUsed = HaveVSrc && HaveSSrc;
1427 // Second go over the operands and try to fold them
1428 std::vector<SDValue> Ops;
1429 bool Promote2e64 = false;
1430 for (unsigned i = 0, e = Node->getNumOperands(), Op = NumDefs;
1431 i != e && Op < NumOps; ++i, ++Op) {
1433 const SDValue &Operand = Node->getOperand(i);
1434 Ops.push_back(Operand);
1436 // Already folded immediate?
1437 if (isa<ConstantSDNode>(Operand.getNode()) ||
1438 isa<ConstantFPSDNode>(Operand.getNode()))
1441 // Is this a VSrc or SSrc operand?
1442 unsigned RegClass = Desc->OpInfo[Op].RegClass;
1443 if (isVSrc(RegClass) || isSSrc(RegClass)) {
1444 // Try to fold the immediates
1445 if (!foldImm(Ops[i], Immediate, ScalarSlotUsed)) {
1446 // Folding didn't work, make sure we don't hit the SReg limit.
1447 ensureSRegLimit(DAG, Ops[i], RegClass, ScalarSlotUsed);
1452 if (i == 1 && DescRev && fitsRegClass(DAG, Ops[0], RegClass)) {
1454 unsigned OtherRegClass = Desc->OpInfo[NumDefs].RegClass;
1455 assert(isVSrc(OtherRegClass) || isSSrc(OtherRegClass));
1457 // Test if it makes sense to swap operands
1458 if (foldImm(Ops[1], Immediate, ScalarSlotUsed) ||
1459 (!fitsRegClass(DAG, Ops[1], RegClass) &&
1460 fitsRegClass(DAG, Ops[1], OtherRegClass))) {
1462 // Swap commutable operands
1463 std::swap(Ops[0], Ops[1]);
1475 // Test if it makes sense to switch to e64 encoding
1476 unsigned OtherRegClass = DescE64->OpInfo[Op].RegClass;
1477 if (!isVSrc(OtherRegClass) && !isSSrc(OtherRegClass))
1480 int32_t TmpImm = -1;
1481 if (foldImm(Ops[i], TmpImm, ScalarSlotUsed) ||
1482 (!fitsRegClass(DAG, Ops[i], RegClass) &&
1483 fitsRegClass(DAG, Ops[1], OtherRegClass))) {
1485 // Switch to e64 encoding
1493 if (!DescE64 && !Promote2e64)
1495 if (!Operand.isMachineOpcode())
1497 if (Operand.getMachineOpcode() == AMDGPU::FNEG_SI) {
1499 Ops.push_back(Operand.getOperand(0));
1500 InputModifiers[i] = 1;
1507 else if (Operand.getMachineOpcode() == AMDGPU::FABS_SI) {
1509 Ops.push_back(Operand.getOperand(0));
1510 InputModifiers[i] = 2;
1520 std::vector<SDValue> OldOps(Ops);
1522 for (unsigned i = 0; i < OldOps.size(); ++i) {
1524 Ops.push_back(DAG.getTargetConstant(InputModifiers[i], MVT::i32));
1525 Ops.push_back(OldOps[i]);
1527 // Add the modifier flags while promoting
1528 for (unsigned i = 0; i < 2; ++i)
1529 Ops.push_back(DAG.getTargetConstant(0, MVT::i32));
1532 // Add optional chain and glue
1533 for (unsigned i = NumOps - NumDefs, e = Node->getNumOperands(); i < e; ++i)
1534 Ops.push_back(Node->getOperand(i));
1536 // Nodes that have a glue result are not CSE'd by getMachineNode(), so in
1537 // this case a brand new node is always be created, even if the operands
1538 // are the same as before. So, manually check if anything has been changed.
1539 if (Desc->Opcode == Opcode && !isNodeChanged(Node, Ops)) {
1543 // Create a complete new instruction
1544 return DAG.getMachineNode(Desc->Opcode, SDLoc(Node), Node->getVTList(), Ops);
1547 /// \brief Helper function for adjustWritemask
1548 static unsigned SubIdx2Lane(unsigned Idx) {
1551 case AMDGPU::sub0: return 0;
1552 case AMDGPU::sub1: return 1;
1553 case AMDGPU::sub2: return 2;
1554 case AMDGPU::sub3: return 3;
1558 /// \brief Adjust the writemask of MIMG instructions
1559 void SITargetLowering::adjustWritemask(MachineSDNode *&Node,
1560 SelectionDAG &DAG) const {
1561 SDNode *Users[4] = { };
1563 unsigned OldDmask = Node->getConstantOperandVal(0);
1564 unsigned NewDmask = 0;
1566 // Try to figure out the used register components
1567 for (SDNode::use_iterator I = Node->use_begin(), E = Node->use_end();
1570 // Abort if we can't understand the usage
1571 if (!I->isMachineOpcode() ||
1572 I->getMachineOpcode() != TargetOpcode::EXTRACT_SUBREG)
1575 // Lane means which subreg of %VGPRa_VGPRb_VGPRc_VGPRd is used.
1576 // Note that subregs are packed, i.e. Lane==0 is the first bit set
1577 // in OldDmask, so it can be any of X,Y,Z,W; Lane==1 is the second bit
1579 Lane = SubIdx2Lane(I->getConstantOperandVal(1));
1581 // Set which texture component corresponds to the lane.
1583 for (unsigned i = 0, Dmask = OldDmask; i <= Lane; i++) {
1585 Comp = countTrailingZeros(Dmask);
1586 Dmask &= ~(1 << Comp);
1589 // Abort if we have more than one user per component
1594 NewDmask |= 1 << Comp;
1597 // Abort if there's no change
1598 if (NewDmask == OldDmask)
1601 // Adjust the writemask in the node
1602 std::vector<SDValue> Ops;
1603 Ops.push_back(DAG.getTargetConstant(NewDmask, MVT::i32));
1604 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i)
1605 Ops.push_back(Node->getOperand(i));
1606 Node = (MachineSDNode*)DAG.UpdateNodeOperands(Node, Ops);
1608 // If we only got one lane, replace it with a copy
1609 // (if NewDmask has only one bit set...)
1610 if (NewDmask && (NewDmask & (NewDmask-1)) == 0) {
1611 SDValue RC = DAG.getTargetConstant(AMDGPU::VReg_32RegClassID, MVT::i32);
1612 SDNode *Copy = DAG.getMachineNode(TargetOpcode::COPY_TO_REGCLASS,
1613 SDLoc(), Users[Lane]->getValueType(0),
1614 SDValue(Node, 0), RC);
1615 DAG.ReplaceAllUsesWith(Users[Lane], Copy);
1619 // Update the users of the node with the new indices
1620 for (unsigned i = 0, Idx = AMDGPU::sub0; i < 4; ++i) {
1622 SDNode *User = Users[i];
1626 SDValue Op = DAG.getTargetConstant(Idx, MVT::i32);
1627 DAG.UpdateNodeOperands(User, User->getOperand(0), Op);
1631 case AMDGPU::sub0: Idx = AMDGPU::sub1; break;
1632 case AMDGPU::sub1: Idx = AMDGPU::sub2; break;
1633 case AMDGPU::sub2: Idx = AMDGPU::sub3; break;
1638 /// \brief Fold the instructions after selecting them.
1639 SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node,
1640 SelectionDAG &DAG) const {
1641 const SIInstrInfo *TII =
1642 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
1643 Node = AdjustRegClass(Node, DAG);
1645 if (TII->isMIMG(Node->getMachineOpcode()))
1646 adjustWritemask(Node, DAG);
1648 return foldOperands(Node, DAG);
1651 /// \brief Assign the register class depending on the number of
1652 /// bits set in the writemask
1653 void SITargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
1654 SDNode *Node) const {
1655 const SIInstrInfo *TII =
1656 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
1657 if (!TII->isMIMG(MI->getOpcode()))
1660 unsigned VReg = MI->getOperand(0).getReg();
1661 unsigned Writemask = MI->getOperand(1).getImm();
1662 unsigned BitsSet = 0;
1663 for (unsigned i = 0; i < 4; ++i)
1664 BitsSet += Writemask & (1 << i) ? 1 : 0;
1666 const TargetRegisterClass *RC;
1669 case 1: RC = &AMDGPU::VReg_32RegClass; break;
1670 case 2: RC = &AMDGPU::VReg_64RegClass; break;
1671 case 3: RC = &AMDGPU::VReg_96RegClass; break;
1674 unsigned NewOpcode = TII->getMaskedMIMGOp(MI->getOpcode(), BitsSet);
1675 MI->setDesc(TII->get(NewOpcode));
1676 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1677 MRI.setRegClass(VReg, RC);
1680 MachineSDNode *SITargetLowering::AdjustRegClass(MachineSDNode *N,
1681 SelectionDAG &DAG) const {
1684 unsigned NewOpcode = N->getMachineOpcode();
1686 switch (N->getMachineOpcode()) {
1688 case AMDGPU::S_LOAD_DWORD_IMM:
1689 NewOpcode = AMDGPU::BUFFER_LOAD_DWORD_ADDR64;
1691 case AMDGPU::S_LOAD_DWORDX2_SGPR:
1692 if (NewOpcode == N->getMachineOpcode()) {
1693 NewOpcode = AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64;
1696 case AMDGPU::S_LOAD_DWORDX4_IMM:
1697 case AMDGPU::S_LOAD_DWORDX4_SGPR: {
1698 if (NewOpcode == N->getMachineOpcode()) {
1699 NewOpcode = AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64;
1701 if (fitsRegClass(DAG, N->getOperand(0), AMDGPU::SReg_64RegClassID)) {
1704 ConstantSDNode *Offset = cast<ConstantSDNode>(N->getOperand(1));
1706 SDValue(DAG.getMachineNode(AMDGPU::SI_ADDR64_RSRC, DL, MVT::i128,
1707 DAG.getConstant(0, MVT::i64)), 0),
1709 DAG.getConstant(Offset->getSExtValue() << 2, MVT::i32)
1711 return DAG.getMachineNode(NewOpcode, DL, N->getVTList(), Ops);
1716 SDValue SITargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
1717 const TargetRegisterClass *RC,
1718 unsigned Reg, EVT VT) const {
1719 SDValue VReg = AMDGPUTargetLowering::CreateLiveInRegister(DAG, RC, Reg, VT);
1721 return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(DAG.getEntryNode()),
1722 cast<RegisterSDNode>(VReg)->getReg(), VT);