1 //===-- SIISelLowering.cpp - SI DAG Lowering Implementation ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Custom DAG lowering for SI
13 //===----------------------------------------------------------------------===//
17 #define _USE_MATH_DEFINES
21 #include "SIISelLowering.h"
23 #include "AMDGPUIntrinsicInfo.h"
24 #include "AMDGPUSubtarget.h"
25 #include "SIInstrInfo.h"
26 #include "SIMachineFunctionInfo.h"
27 #include "SIRegisterInfo.h"
28 #include "llvm/CodeGen/CallingConvLower.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/SelectionDAG.h"
32 #include "llvm/IR/Function.h"
33 #include "llvm/ADT/SmallString.h"
37 SITargetLowering::SITargetLowering(TargetMachine &TM) :
38 AMDGPUTargetLowering(TM) {
39 addRegisterClass(MVT::i1, &AMDGPU::VReg_1RegClass);
40 addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass);
42 addRegisterClass(MVT::v32i8, &AMDGPU::SReg_256RegClass);
43 addRegisterClass(MVT::v64i8, &AMDGPU::SReg_512RegClass);
45 addRegisterClass(MVT::i32, &AMDGPU::SReg_32RegClass);
46 addRegisterClass(MVT::f32, &AMDGPU::VReg_32RegClass);
48 addRegisterClass(MVT::f64, &AMDGPU::VReg_64RegClass);
49 addRegisterClass(MVT::v2i32, &AMDGPU::SReg_64RegClass);
50 addRegisterClass(MVT::v2f32, &AMDGPU::VReg_64RegClass);
52 addRegisterClass(MVT::v4i32, &AMDGPU::SReg_128RegClass);
53 addRegisterClass(MVT::v4f32, &AMDGPU::VReg_128RegClass);
55 addRegisterClass(MVT::v8i32, &AMDGPU::VReg_256RegClass);
56 addRegisterClass(MVT::v8f32, &AMDGPU::VReg_256RegClass);
58 addRegisterClass(MVT::v16i32, &AMDGPU::VReg_512RegClass);
59 addRegisterClass(MVT::v16f32, &AMDGPU::VReg_512RegClass);
61 computeRegisterProperties();
64 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
65 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
66 setCondCodeAction(ISD::SETUGE, MVT::f32, Expand);
67 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
68 setCondCodeAction(ISD::SETULE, MVT::f32, Expand);
69 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
71 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
72 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
73 setCondCodeAction(ISD::SETUGE, MVT::f64, Expand);
74 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
75 setCondCodeAction(ISD::SETULE, MVT::f64, Expand);
76 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
78 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i32, Expand);
79 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Expand);
80 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i32, Expand);
81 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16f32, Expand);
83 setOperationAction(ISD::ADD, MVT::i32, Legal);
84 setOperationAction(ISD::ADDC, MVT::i32, Legal);
85 setOperationAction(ISD::ADDE, MVT::i32, Legal);
86 setOperationAction(ISD::SUBC, MVT::i32, Legal);
87 setOperationAction(ISD::SUBE, MVT::i32, Legal);
89 setOperationAction(ISD::FSIN, MVT::f32, Custom);
90 setOperationAction(ISD::FCOS, MVT::f32, Custom);
92 // We need to custom lower vector stores from local memory
93 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
94 setOperationAction(ISD::LOAD, MVT::v8i32, Custom);
95 setOperationAction(ISD::LOAD, MVT::v16i32, Custom);
97 setOperationAction(ISD::STORE, MVT::v8i32, Custom);
98 setOperationAction(ISD::STORE, MVT::v16i32, Custom);
100 setOperationAction(ISD::STORE, MVT::i1, Custom);
101 setOperationAction(ISD::STORE, MVT::i32, Custom);
102 setOperationAction(ISD::STORE, MVT::v2i32, Custom);
103 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
105 setOperationAction(ISD::SELECT, MVT::f32, Promote);
106 AddPromotedToType(ISD::SELECT, MVT::f32, MVT::i32);
107 setOperationAction(ISD::SELECT, MVT::i64, Custom);
108 setOperationAction(ISD::SELECT, MVT::f64, Promote);
109 AddPromotedToType(ISD::SELECT, MVT::f64, MVT::i64);
111 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
112 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
113 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
114 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
116 setOperationAction(ISD::SETCC, MVT::v2i1, Expand);
117 setOperationAction(ISD::SETCC, MVT::v4i1, Expand);
119 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Legal);
120 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Custom);
121 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Custom);
123 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Legal);
124 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
125 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Custom);
127 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Legal);
128 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
129 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Custom);
131 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Custom);
133 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Custom);
135 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
136 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::f32, Custom);
137 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v16i8, Custom);
138 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v4f32, Custom);
140 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
141 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
143 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
144 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Custom);
145 setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Custom);
146 setLoadExtAction(ISD::SEXTLOAD, MVT::i32, Expand);
147 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i16, Expand);
148 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i16, Expand);
150 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
151 setLoadExtAction(ISD::ZEXTLOAD, MVT::i8, Custom);
152 setLoadExtAction(ISD::ZEXTLOAD, MVT::i16, Custom);
153 setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, Expand);
155 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
156 setLoadExtAction(ISD::EXTLOAD, MVT::i8, Custom);
157 setLoadExtAction(ISD::EXTLOAD, MVT::i16, Custom);
158 setLoadExtAction(ISD::EXTLOAD, MVT::i32, Expand);
159 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
161 setTruncStoreAction(MVT::i32, MVT::i8, Custom);
162 setTruncStoreAction(MVT::i32, MVT::i16, Custom);
163 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
164 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
165 setTruncStoreAction(MVT::v8i32, MVT::v8i16, Expand);
166 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Expand);
168 setOperationAction(ISD::LOAD, MVT::i1, Custom);
170 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Expand);
171 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
173 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
174 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
175 setOperationAction(ISD::FrameIndex, MVT::i32, Custom);
177 // These should use UDIVREM, so set them to expand
178 setOperationAction(ISD::UDIV, MVT::i64, Expand);
179 setOperationAction(ISD::UREM, MVT::i64, Expand);
181 // We only support LOAD/STORE and vector manipulation ops for vectors
182 // with > 4 elements.
184 MVT::v8i32, MVT::v8f32, MVT::v16i32, MVT::v16f32
187 setOperationAction(ISD::SELECT_CC, MVT::i1, Expand);
188 setOperationAction(ISD::SELECT, MVT::i1, Promote);
190 for (MVT VT : VecTypes) {
191 for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op) {
195 case ISD::BUILD_VECTOR:
197 case ISD::EXTRACT_VECTOR_ELT:
198 case ISD::INSERT_VECTOR_ELT:
199 case ISD::CONCAT_VECTORS:
200 case ISD::INSERT_SUBVECTOR:
201 case ISD::EXTRACT_SUBVECTOR:
204 setOperationAction(Op, VT, Expand);
210 for (int I = MVT::v1f64; I <= MVT::v8f64; ++I) {
211 MVT::SimpleValueType VT = static_cast<MVT::SimpleValueType>(I);
212 setOperationAction(ISD::FTRUNC, VT, Expand);
213 setOperationAction(ISD::FCEIL, VT, Expand);
214 setOperationAction(ISD::FFLOOR, VT, Expand);
217 if (Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS) {
218 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
219 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
220 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
221 setOperationAction(ISD::FRINT, MVT::f64, Legal);
224 // FIXME: These should be removed and handled the same was as f32 fneg. Source
225 // modifiers also work for the double instructions.
226 setOperationAction(ISD::FNEG, MVT::f64, Expand);
227 setOperationAction(ISD::FABS, MVT::f64, Expand);
229 setOperationAction(ISD::FDIV, MVT::f32, Custom);
231 setTargetDAGCombine(ISD::SELECT_CC);
232 setTargetDAGCombine(ISD::SETCC);
234 setTargetDAGCombine(ISD::UINT_TO_FP);
236 setSchedulingPreference(Sched::RegPressure);
239 //===----------------------------------------------------------------------===//
240 // TargetLowering queries
241 //===----------------------------------------------------------------------===//
243 bool SITargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
245 bool *IsFast) const {
249 // XXX: This depends on the address space and also we may want to revist
250 // the alignment values we specify in the DataLayout.
252 // TODO: I think v3i32 should allow unaligned accesses on CI with DS_READ_B96,
253 // which isn't a simple VT.
254 if (!VT.isSimple() || VT == MVT::Other)
257 // XXX - CI changes say "Support for unaligned memory accesses" but I don't
258 // see what for specifically. The wording everywhere else seems to be the
261 // XXX - The only mention I see of this in the ISA manual is for LDS direct
262 // reads the "byte address and must be dword aligned". Is it also true for the
263 // normal loads and stores?
264 if (AddrSpace == AMDGPUAS::LOCAL_ADDRESS)
267 // 8.1.6 - For Dword or larger reads or writes, the two LSBs of the
268 // byte-address are ignored, thus forcing Dword alignment.
269 // This applies to private, global, and constant memory.
272 return VT.bitsGT(MVT::i32);
275 TargetLoweringBase::LegalizeTypeAction
276 SITargetLowering::getPreferredVectorAction(EVT VT) const {
277 if (VT.getVectorNumElements() != 1 && VT.getScalarType().bitsLE(MVT::i16))
278 return TypeSplitVector;
280 return TargetLoweringBase::getPreferredVectorAction(VT);
283 bool SITargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
285 const SIInstrInfo *TII =
286 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
287 return TII->isInlineConstant(Imm);
290 SDValue SITargetLowering::LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT,
291 SDLoc DL, SDValue Chain,
292 unsigned Offset, bool Signed) const {
293 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
294 PointerType *PtrTy = PointerType::get(VT.getTypeForEVT(*DAG.getContext()),
295 AMDGPUAS::CONSTANT_ADDRESS);
296 SDValue BasePtr = DAG.getCopyFromReg(Chain, DL,
297 MRI.getLiveInVirtReg(AMDGPU::SGPR0_SGPR1), MVT::i64);
298 SDValue Ptr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
299 DAG.getConstant(Offset, MVT::i64));
300 return DAG.getExtLoad(Signed ? ISD::SEXTLOAD : ISD::ZEXTLOAD, DL, VT, Chain, Ptr,
301 MachinePointerInfo(UndefValue::get(PtrTy)), MemVT,
302 false, false, MemVT.getSizeInBits() >> 3);
306 SDValue SITargetLowering::LowerFormalArguments(
308 CallingConv::ID CallConv,
310 const SmallVectorImpl<ISD::InputArg> &Ins,
311 SDLoc DL, SelectionDAG &DAG,
312 SmallVectorImpl<SDValue> &InVals) const {
314 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
316 MachineFunction &MF = DAG.getMachineFunction();
317 FunctionType *FType = MF.getFunction()->getFunctionType();
318 SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
320 assert(CallConv == CallingConv::C);
322 SmallVector<ISD::InputArg, 16> Splits;
323 uint32_t Skipped = 0;
325 for (unsigned i = 0, e = Ins.size(), PSInputNum = 0; i != e; ++i) {
326 const ISD::InputArg &Arg = Ins[i];
328 // First check if it's a PS input addr
329 if (Info->getShaderType() == ShaderType::PIXEL && !Arg.Flags.isInReg() &&
330 !Arg.Flags.isByVal()) {
332 assert((PSInputNum <= 15) && "Too many PS inputs!");
335 // We can savely skip PS inputs
341 Info->PSInputAddr |= 1 << PSInputNum++;
344 // Second split vertices into their elements
345 if (Info->getShaderType() != ShaderType::COMPUTE && Arg.VT.isVector()) {
346 ISD::InputArg NewArg = Arg;
347 NewArg.Flags.setSplit();
348 NewArg.VT = Arg.VT.getVectorElementType();
350 // We REALLY want the ORIGINAL number of vertex elements here, e.g. a
351 // three or five element vertex only needs three or five registers,
352 // NOT four or eigth.
353 Type *ParamType = FType->getParamType(Arg.OrigArgIndex);
354 unsigned NumElements = ParamType->getVectorNumElements();
356 for (unsigned j = 0; j != NumElements; ++j) {
357 Splits.push_back(NewArg);
358 NewArg.PartOffset += NewArg.VT.getStoreSize();
361 } else if (Info->getShaderType() != ShaderType::COMPUTE) {
362 Splits.push_back(Arg);
366 SmallVector<CCValAssign, 16> ArgLocs;
367 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
368 getTargetMachine(), ArgLocs, *DAG.getContext());
370 // At least one interpolation mode must be enabled or else the GPU will hang.
371 if (Info->getShaderType() == ShaderType::PIXEL &&
372 (Info->PSInputAddr & 0x7F) == 0) {
373 Info->PSInputAddr |= 1;
374 CCInfo.AllocateReg(AMDGPU::VGPR0);
375 CCInfo.AllocateReg(AMDGPU::VGPR1);
378 // The pointer to the list of arguments is stored in SGPR0, SGPR1
379 // The pointer to the scratch buffer is stored in SGPR2, SGPR3
380 if (Info->getShaderType() == ShaderType::COMPUTE) {
381 Info->NumUserSGPRs = 4;
382 CCInfo.AllocateReg(AMDGPU::SGPR0);
383 CCInfo.AllocateReg(AMDGPU::SGPR1);
384 CCInfo.AllocateReg(AMDGPU::SGPR2);
385 CCInfo.AllocateReg(AMDGPU::SGPR3);
386 MF.addLiveIn(AMDGPU::SGPR0_SGPR1, &AMDGPU::SReg_64RegClass);
387 MF.addLiveIn(AMDGPU::SGPR2_SGPR3, &AMDGPU::SReg_64RegClass);
390 if (Info->getShaderType() == ShaderType::COMPUTE) {
391 getOriginalFunctionArgs(DAG, DAG.getMachineFunction().getFunction(), Ins,
395 AnalyzeFormalArguments(CCInfo, Splits);
397 for (unsigned i = 0, e = Ins.size(), ArgIdx = 0; i != e; ++i) {
399 const ISD::InputArg &Arg = Ins[i];
400 if (Skipped & (1 << i)) {
401 InVals.push_back(DAG.getUNDEF(Arg.VT));
405 CCValAssign &VA = ArgLocs[ArgIdx++];
406 EVT VT = VA.getLocVT();
410 EVT MemVT = Splits[i].VT;
411 // The first 36 bytes of the input buffer contains information about
412 // thread group and global sizes.
413 SDValue Arg = LowerParameter(DAG, VT, MemVT, DL, DAG.getRoot(),
414 36 + VA.getLocMemOffset(),
415 Ins[i].Flags.isSExt());
416 InVals.push_back(Arg);
419 assert(VA.isRegLoc() && "Parameter must be in a register!");
421 unsigned Reg = VA.getLocReg();
423 if (VT == MVT::i64) {
424 // For now assume it is a pointer
425 Reg = TRI->getMatchingSuperReg(Reg, AMDGPU::sub0,
426 &AMDGPU::SReg_64RegClass);
427 Reg = MF.addLiveIn(Reg, &AMDGPU::SReg_64RegClass);
428 InVals.push_back(DAG.getCopyFromReg(Chain, DL, Reg, VT));
432 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
434 Reg = MF.addLiveIn(Reg, RC);
435 SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, VT);
437 if (Arg.VT.isVector()) {
439 // Build a vector from the registers
440 Type *ParamType = FType->getParamType(Arg.OrigArgIndex);
441 unsigned NumElements = ParamType->getVectorNumElements();
443 SmallVector<SDValue, 4> Regs;
445 for (unsigned j = 1; j != NumElements; ++j) {
446 Reg = ArgLocs[ArgIdx++].getLocReg();
447 Reg = MF.addLiveIn(Reg, RC);
448 Regs.push_back(DAG.getCopyFromReg(Chain, DL, Reg, VT));
451 // Fill up the missing vector elements
452 NumElements = Arg.VT.getVectorNumElements() - NumElements;
453 for (unsigned j = 0; j != NumElements; ++j)
454 Regs.push_back(DAG.getUNDEF(VT));
456 InVals.push_back(DAG.getNode(ISD::BUILD_VECTOR, DL, Arg.VT, Regs));
460 InVals.push_back(Val);
465 MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
466 MachineInstr * MI, MachineBasicBlock * BB) const {
468 MachineBasicBlock::iterator I = *MI;
469 const SIInstrInfo *TII =
470 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
471 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
473 switch (MI->getOpcode()) {
475 return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
476 case AMDGPU::BRANCH: return BB;
477 case AMDGPU::SI_ADDR64_RSRC: {
478 unsigned SuperReg = MI->getOperand(0).getReg();
479 unsigned SubRegLo = MRI.createVirtualRegister(&AMDGPU::SGPR_64RegClass);
480 unsigned SubRegHi = MRI.createVirtualRegister(&AMDGPU::SGPR_64RegClass);
481 unsigned SubRegHiHi = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
482 unsigned SubRegHiLo = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
483 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B64), SubRegLo)
484 .addOperand(MI->getOperand(1));
485 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B32), SubRegHiLo)
487 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B32), SubRegHiHi)
488 .addImm(AMDGPU::RSRC_DATA_FORMAT >> 32);
489 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::REG_SEQUENCE), SubRegHi)
491 .addImm(AMDGPU::sub0)
493 .addImm(AMDGPU::sub1);
494 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::REG_SEQUENCE), SuperReg)
496 .addImm(AMDGPU::sub0_sub1)
498 .addImm(AMDGPU::sub2_sub3);
499 MI->eraseFromParent();
502 case AMDGPU::SI_BUFFER_RSRC: {
503 unsigned SuperReg = MI->getOperand(0).getReg();
505 for (unsigned i = 0, e = 4; i < e; ++i) {
506 MachineOperand &Arg = MI->getOperand(i + 1);
509 Args[i] = Arg.getReg();
514 unsigned Reg = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
515 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B32), Reg)
516 .addImm(Arg.getImm());
519 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::REG_SEQUENCE),
522 .addImm(AMDGPU::sub0)
524 .addImm(AMDGPU::sub1)
526 .addImm(AMDGPU::sub2)
528 .addImm(AMDGPU::sub3);
529 MI->eraseFromParent();
532 case AMDGPU::V_SUB_F64: {
533 unsigned DestReg = MI->getOperand(0).getReg();
534 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_ADD_F64), DestReg)
535 .addImm(0) // SRC0 modifiers
536 .addReg(MI->getOperand(1).getReg())
537 .addImm(1) // SRC1 modifiers
538 .addReg(MI->getOperand(2).getReg())
539 .addImm(0) // SRC2 modifiers
543 MI->eraseFromParent();
546 case AMDGPU::SI_RegisterStorePseudo: {
547 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
548 unsigned Reg = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
549 MachineInstrBuilder MIB =
550 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::SI_RegisterStore),
552 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
553 MIB.addOperand(MI->getOperand(i));
555 MI->eraseFromParent();
558 case AMDGPU::FABS_SI: {
559 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
560 const SIInstrInfo *TII =
561 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
562 unsigned Reg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
563 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_MOV_B32_e32),
566 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_AND_B32_e32),
567 MI->getOperand(0).getReg())
568 .addReg(MI->getOperand(1).getReg())
570 MI->eraseFromParent();
573 case AMDGPU::FNEG_SI: {
574 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
575 const SIInstrInfo *TII =
576 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
577 unsigned Reg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
578 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_MOV_B32_e32),
581 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_XOR_B32_e32),
582 MI->getOperand(0).getReg())
583 .addReg(MI->getOperand(1).getReg())
585 MI->eraseFromParent();
588 case AMDGPU::FCLAMP_SI: {
589 const SIInstrInfo *TII =
590 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
591 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_ADD_F32_e64),
592 MI->getOperand(0).getReg())
593 .addImm(0) // SRC0 modifiers
594 .addOperand(MI->getOperand(1))
595 .addImm(0) // SRC1 modifiers
599 MI->eraseFromParent();
605 EVT SITargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
606 if (!VT.isVector()) {
609 return MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
612 MVT SITargetLowering::getScalarShiftAmountTy(EVT VT) const {
616 bool SITargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
617 VT = VT.getScalarType();
622 switch (VT.getSimpleVT().SimpleTy) {
624 return false; /* There is V_MAD_F32 for f32 */
634 //===----------------------------------------------------------------------===//
635 // Custom DAG Lowering Operations
636 //===----------------------------------------------------------------------===//
638 SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
639 MachineFunction &MF = DAG.getMachineFunction();
640 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
641 switch (Op.getOpcode()) {
642 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
643 case ISD::FrameIndex: return LowerFrameIndex(Op, DAG);
644 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
646 SDValue Result = LowerLOAD(Op, DAG);
647 assert((!Result.getNode() ||
648 Result.getNode()->getNumValues() == 2) &&
649 "Load should return a value and a chain");
655 return LowerTrig(Op, DAG);
656 case ISD::SELECT: return LowerSELECT(Op, DAG);
657 case ISD::FDIV: return LowerFDIV(Op, DAG);
658 case ISD::STORE: return LowerSTORE(Op, DAG);
659 case ISD::GlobalAddress: return LowerGlobalAddress(MFI, Op, DAG);
660 case ISD::INTRINSIC_WO_CHAIN: {
661 unsigned IntrinsicID =
662 cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
663 EVT VT = Op.getValueType();
665 switch (IntrinsicID) {
666 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
667 case Intrinsic::r600_read_ngroups_x:
668 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 0, false);
669 case Intrinsic::r600_read_ngroups_y:
670 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 4, false);
671 case Intrinsic::r600_read_ngroups_z:
672 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 8, false);
673 case Intrinsic::r600_read_global_size_x:
674 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 12, false);
675 case Intrinsic::r600_read_global_size_y:
676 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 16, false);
677 case Intrinsic::r600_read_global_size_z:
678 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 20, false);
679 case Intrinsic::r600_read_local_size_x:
680 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 24, false);
681 case Intrinsic::r600_read_local_size_y:
682 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 28, false);
683 case Intrinsic::r600_read_local_size_z:
684 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 32, false);
685 case Intrinsic::r600_read_tgid_x:
686 return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
687 AMDGPU::SReg_32RegClass.getRegister(MFI->NumUserSGPRs + 0), VT);
688 case Intrinsic::r600_read_tgid_y:
689 return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
690 AMDGPU::SReg_32RegClass.getRegister(MFI->NumUserSGPRs + 1), VT);
691 case Intrinsic::r600_read_tgid_z:
692 return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
693 AMDGPU::SReg_32RegClass.getRegister(MFI->NumUserSGPRs + 2), VT);
694 case Intrinsic::r600_read_tidig_x:
695 return CreateLiveInRegister(DAG, &AMDGPU::VReg_32RegClass,
697 case Intrinsic::r600_read_tidig_y:
698 return CreateLiveInRegister(DAG, &AMDGPU::VReg_32RegClass,
700 case Intrinsic::r600_read_tidig_z:
701 return CreateLiveInRegister(DAG, &AMDGPU::VReg_32RegClass,
703 case AMDGPUIntrinsic::SI_load_const: {
709 MachineMemOperand *MMO = MF.getMachineMemOperand(
710 MachinePointerInfo(),
711 MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant,
712 VT.getSizeInBits() / 8, 4);
713 return DAG.getMemIntrinsicNode(AMDGPUISD::LOAD_CONSTANT, DL,
714 Op->getVTList(), Ops, VT, MMO);
716 case AMDGPUIntrinsic::SI_sample:
717 return LowerSampleIntrinsic(AMDGPUISD::SAMPLE, Op, DAG);
718 case AMDGPUIntrinsic::SI_sampleb:
719 return LowerSampleIntrinsic(AMDGPUISD::SAMPLEB, Op, DAG);
720 case AMDGPUIntrinsic::SI_sampled:
721 return LowerSampleIntrinsic(AMDGPUISD::SAMPLED, Op, DAG);
722 case AMDGPUIntrinsic::SI_samplel:
723 return LowerSampleIntrinsic(AMDGPUISD::SAMPLEL, Op, DAG);
724 case AMDGPUIntrinsic::SI_vs_load_input:
725 return DAG.getNode(AMDGPUISD::LOAD_INPUT, DL, VT,
732 case ISD::INTRINSIC_VOID:
733 SDValue Chain = Op.getOperand(0);
734 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
736 switch (IntrinsicID) {
737 case AMDGPUIntrinsic::SI_tbuffer_store: {
755 EVT VT = Op.getOperand(3).getValueType();
757 MachineMemOperand *MMO = MF.getMachineMemOperand(
758 MachinePointerInfo(),
759 MachineMemOperand::MOStore,
760 VT.getSizeInBits() / 8, 4);
761 return DAG.getMemIntrinsicNode(AMDGPUISD::TBUFFER_STORE_FORMAT, DL,
762 Op->getVTList(), Ops, VT, MMO);
771 /// \brief Helper function for LowerBRCOND
772 static SDNode *findUser(SDValue Value, unsigned Opcode) {
774 SDNode *Parent = Value.getNode();
775 for (SDNode::use_iterator I = Parent->use_begin(), E = Parent->use_end();
778 if (I.getUse().get() != Value)
781 if (I->getOpcode() == Opcode)
787 SDValue SITargetLowering::LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const {
789 MachineFunction &MF = DAG.getMachineFunction();
790 const SIInstrInfo *TII =
791 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
792 const SIRegisterInfo &TRI = TII->getRegisterInfo();
793 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Op);
794 unsigned FrameIndex = FINode->getIndex();
796 CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
797 TRI.getPreloadedValue(MF, SIRegisterInfo::SCRATCH_WAVE_OFFSET), MVT::i32);
799 return DAG.getTargetFrameIndex(FrameIndex, MVT::i32);
802 /// This transforms the control flow intrinsics to get the branch destination as
803 /// last parameter, also switches branch target with BR if the need arise
804 SDValue SITargetLowering::LowerBRCOND(SDValue BRCOND,
805 SelectionDAG &DAG) const {
809 SDNode *Intr = BRCOND.getOperand(1).getNode();
810 SDValue Target = BRCOND.getOperand(2);
811 SDNode *BR = nullptr;
813 if (Intr->getOpcode() == ISD::SETCC) {
814 // As long as we negate the condition everything is fine
815 SDNode *SetCC = Intr;
816 assert(SetCC->getConstantOperandVal(1) == 1);
817 assert(cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() ==
819 Intr = SetCC->getOperand(0).getNode();
822 // Get the target from BR if we don't negate the condition
823 BR = findUser(BRCOND, ISD::BR);
824 Target = BR->getOperand(1);
827 assert(Intr->getOpcode() == ISD::INTRINSIC_W_CHAIN);
829 // Build the result and
830 SmallVector<EVT, 4> Res;
831 for (unsigned i = 1, e = Intr->getNumValues(); i != e; ++i)
832 Res.push_back(Intr->getValueType(i));
834 // operands of the new intrinsic call
835 SmallVector<SDValue, 4> Ops;
836 Ops.push_back(BRCOND.getOperand(0));
837 for (unsigned i = 1, e = Intr->getNumOperands(); i != e; ++i)
838 Ops.push_back(Intr->getOperand(i));
839 Ops.push_back(Target);
841 // build the new intrinsic call
842 SDNode *Result = DAG.getNode(
843 Res.size() > 1 ? ISD::INTRINSIC_W_CHAIN : ISD::INTRINSIC_VOID, DL,
844 DAG.getVTList(Res), Ops).getNode();
847 // Give the branch instruction our target
852 DAG.MorphNodeTo(BR, ISD::BR, BR->getVTList(), Ops);
855 SDValue Chain = SDValue(Result, Result->getNumValues() - 1);
857 // Copy the intrinsic results to registers
858 for (unsigned i = 1, e = Intr->getNumValues() - 1; i != e; ++i) {
859 SDNode *CopyToReg = findUser(SDValue(Intr, i), ISD::CopyToReg);
863 Chain = DAG.getCopyToReg(
865 CopyToReg->getOperand(1),
866 SDValue(Result, i - 1),
869 DAG.ReplaceAllUsesWith(SDValue(CopyToReg, 0), CopyToReg->getOperand(0));
872 // Remove the old intrinsic from the chain
873 DAG.ReplaceAllUsesOfValueWith(
874 SDValue(Intr, Intr->getNumValues() - 1),
875 Intr->getOperand(0));
880 SDValue SITargetLowering::LowerGlobalAddress(AMDGPUMachineFunction *MFI,
882 SelectionDAG &DAG) const {
883 GlobalAddressSDNode *GSD = cast<GlobalAddressSDNode>(Op);
885 if (GSD->getAddressSpace() != AMDGPUAS::CONSTANT_ADDRESS)
886 return AMDGPUTargetLowering::LowerGlobalAddress(MFI, Op, DAG);
889 const GlobalValue *GV = GSD->getGlobal();
890 MVT PtrVT = getPointerTy(GSD->getAddressSpace());
892 SDValue Ptr = DAG.getNode(AMDGPUISD::CONST_DATA_PTR, DL, PtrVT);
893 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i32);
895 SDValue PtrLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, Ptr,
896 DAG.getConstant(0, MVT::i32));
897 SDValue PtrHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, Ptr,
898 DAG.getConstant(1, MVT::i32));
900 SDValue Lo = DAG.getNode(ISD::ADDC, DL, DAG.getVTList(MVT::i32, MVT::Glue),
902 SDValue Hi = DAG.getNode(ISD::ADDE, DL, DAG.getVTList(MVT::i32, MVT::Glue),
903 PtrHi, DAG.getConstant(0, MVT::i32),
904 SDValue(Lo.getNode(), 1));
905 return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi);
908 SDValue SITargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
910 LoadSDNode *Load = cast<LoadSDNode>(Op);
912 if (Op.getValueType().isVector()) {
913 assert(Op.getValueType().getVectorElementType() == MVT::i32 &&
914 "Custom lowering for non-i32 vectors hasn't been implemented.");
915 unsigned NumElements = Op.getValueType().getVectorNumElements();
916 assert(NumElements != 2 && "v2 loads are supported for all address spaces.");
917 switch (Load->getAddressSpace()) {
919 case AMDGPUAS::GLOBAL_ADDRESS:
920 case AMDGPUAS::PRIVATE_ADDRESS:
921 // v4 loads are supported for private and global memory.
922 if (NumElements <= 4)
925 case AMDGPUAS::LOCAL_ADDRESS:
926 return SplitVectorLoad(Op, DAG);
930 return AMDGPUTargetLowering::LowerLOAD(Op, DAG);
933 SDValue SITargetLowering::LowerSampleIntrinsic(unsigned Opcode,
935 SelectionDAG &DAG) const {
936 return DAG.getNode(Opcode, SDLoc(Op), Op.getValueType(), Op.getOperand(1),
942 SDValue SITargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
943 if (Op.getValueType() != MVT::i64)
947 SDValue Cond = Op.getOperand(0);
949 SDValue Zero = DAG.getConstant(0, MVT::i32);
950 SDValue One = DAG.getConstant(1, MVT::i32);
952 SDValue LHS = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, Op.getOperand(1));
953 SDValue RHS = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, Op.getOperand(2));
955 SDValue Lo0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, LHS, Zero);
956 SDValue Lo1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, RHS, Zero);
958 SDValue Lo = DAG.getSelect(DL, MVT::i32, Cond, Lo0, Lo1);
960 SDValue Hi0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, LHS, One);
961 SDValue Hi1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, RHS, One);
963 SDValue Hi = DAG.getSelect(DL, MVT::i32, Cond, Hi0, Hi1);
965 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v2i32, Lo, Hi);
966 return DAG.getNode(ISD::BITCAST, DL, MVT::i64, Res);
969 // Catch division cases where we can use shortcuts with rcp and rsq
971 SDValue SITargetLowering::LowerFastFDIV(SDValue Op, SelectionDAG &DAG) const {
973 SDValue LHS = Op.getOperand(0);
974 SDValue RHS = Op.getOperand(1);
975 EVT VT = Op.getValueType();
976 bool Unsafe = DAG.getTarget().Options.UnsafeFPMath;
978 if (const ConstantFPSDNode *CLHS = dyn_cast<ConstantFPSDNode>(LHS)) {
979 if ((Unsafe || (VT == MVT::f32 && !Subtarget->hasFP32Denormals())) &&
980 CLHS->isExactlyValue(1.0)) {
981 // v_rcp_f32 and v_rsq_f32 do not support denormals, and according to
982 // the CI documentation has a worst case error of 1 ulp.
983 // OpenCL requires <= 2.5 ulp for 1.0 / x, so it should always be OK to
984 // use it as long as we aren't trying to use denormals.
986 // 1.0 / sqrt(x) -> rsq(x)
988 // XXX - Is UnsafeFPMath sufficient to do this for f64? The maximum ULP
989 // error seems really high at 2^29 ULP.
990 if (RHS.getOpcode() == ISD::FSQRT)
991 return DAG.getNode(AMDGPUISD::RSQ, SL, VT, RHS.getOperand(0));
994 return DAG.getNode(AMDGPUISD::RCP, SL, VT, RHS);
999 // Turn into multiply by the reciprocal.
1000 // x / y -> x * (1.0 / y)
1001 SDValue Recip = DAG.getNode(AMDGPUISD::RCP, SL, VT, RHS);
1002 return DAG.getNode(ISD::FMUL, SL, VT, LHS, Recip);
1008 SDValue SITargetLowering::LowerFDIV32(SDValue Op, SelectionDAG &DAG) const {
1009 SDValue FastLowered = LowerFastFDIV(Op, DAG);
1010 if (FastLowered.getNode())
1013 // This uses v_rcp_f32 which does not handle denormals. Let this hit a
1014 // selection error for now rather than do something incorrect.
1015 if (Subtarget->hasFP32Denormals())
1019 SDValue LHS = Op.getOperand(0);
1020 SDValue RHS = Op.getOperand(1);
1022 SDValue r1 = DAG.getNode(ISD::FABS, SL, MVT::f32, RHS);
1024 const APFloat K0Val(BitsToFloat(0x6f800000));
1025 const SDValue K0 = DAG.getConstantFP(K0Val, MVT::f32);
1027 const APFloat K1Val(BitsToFloat(0x2f800000));
1028 const SDValue K1 = DAG.getConstantFP(K1Val, MVT::f32);
1030 const SDValue One = DAG.getTargetConstantFP(1.0, MVT::f32);
1032 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::f32);
1034 SDValue r2 = DAG.getSetCC(SL, SetCCVT, r1, K0, ISD::SETOGT);
1036 SDValue r3 = DAG.getNode(ISD::SELECT, SL, MVT::f32, r2, K1, One);
1038 r1 = DAG.getNode(ISD::FMUL, SL, MVT::f32, RHS, r3);
1040 SDValue r0 = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f32, r1);
1042 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f32, LHS, r0);
1044 return DAG.getNode(ISD::FMUL, SL, MVT::f32, r3, Mul);
1047 SDValue SITargetLowering::LowerFDIV64(SDValue Op, SelectionDAG &DAG) const {
1051 SDValue SITargetLowering::LowerFDIV(SDValue Op, SelectionDAG &DAG) const {
1052 EVT VT = Op.getValueType();
1055 return LowerFDIV32(Op, DAG);
1058 return LowerFDIV64(Op, DAG);
1060 llvm_unreachable("Unexpected type for fdiv");
1063 SDValue SITargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1065 StoreSDNode *Store = cast<StoreSDNode>(Op);
1066 EVT VT = Store->getMemoryVT();
1068 // These stores are legal.
1069 if (Store->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS &&
1070 VT.isVector() && VT.getVectorNumElements() == 2 &&
1071 VT.getVectorElementType() == MVT::i32)
1074 if (Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS) {
1075 if (VT.isVector() && VT.getVectorNumElements() > 4)
1076 return SplitVectorStore(Op, DAG);
1080 SDValue Ret = AMDGPUTargetLowering::LowerSTORE(Op, DAG);
1084 if (VT.isVector() && VT.getVectorNumElements() >= 8)
1085 return SplitVectorStore(Op, DAG);
1088 return DAG.getTruncStore(Store->getChain(), DL,
1089 DAG.getSExtOrTrunc(Store->getValue(), DL, MVT::i32),
1090 Store->getBasePtr(), MVT::i1, Store->getMemOperand());
1095 SDValue SITargetLowering::LowerTrig(SDValue Op, SelectionDAG &DAG) const {
1096 EVT VT = Op.getValueType();
1097 SDValue Arg = Op.getOperand(0);
1098 SDValue FractPart = DAG.getNode(AMDGPUISD::FRACT, SDLoc(Op), VT,
1099 DAG.getNode(ISD::FMUL, SDLoc(Op), VT, Arg,
1100 DAG.getConstantFP(0.5 / M_PI, VT)));
1102 switch (Op.getOpcode()) {
1104 return DAG.getNode(AMDGPUISD::COS_HW, SDLoc(Op), VT, FractPart);
1106 return DAG.getNode(AMDGPUISD::SIN_HW, SDLoc(Op), VT, FractPart);
1108 llvm_unreachable("Wrong trig opcode");
1112 //===----------------------------------------------------------------------===//
1113 // Custom DAG optimizations
1114 //===----------------------------------------------------------------------===//
1116 SDValue SITargetLowering::performUCharToFloatCombine(SDNode *N,
1117 DAGCombinerInfo &DCI) {
1118 EVT VT = N->getValueType(0);
1119 EVT ScalarVT = VT.getScalarType();
1120 if (ScalarVT != MVT::f32)
1123 SelectionDAG &DAG = DCI.DAG;
1126 SDValue Src = N->getOperand(0);
1127 EVT SrcVT = Src.getValueType();
1129 // TODO: We could try to match extracting the higher bytes, which would be
1130 // easier if i8 vectors weren't promoted to i32 vectors, particularly after
1131 // types are legalized. v4i8 -> v4f32 is probably the only case to worry
1132 // about in practice.
1133 if (DCI.isAfterLegalizeVectorOps() && SrcVT == MVT::i32) {
1134 if (DAG.MaskedValueIsZero(Src, APInt::getHighBitsSet(32, 24))) {
1135 SDValue Cvt = DAG.getNode(AMDGPUISD::CVT_F32_UBYTE0, DL, VT, Src);
1136 DCI.AddToWorklist(Cvt.getNode());
1141 // We are primarily trying to catch operations on illegal vector types
1142 // before they are expanded.
1143 // For scalars, we can use the more flexible method of checking masked bits
1144 // after legalization.
1145 if (!DCI.isBeforeLegalize() ||
1146 !SrcVT.isVector() ||
1147 SrcVT.getVectorElementType() != MVT::i8) {
1151 assert(DCI.isBeforeLegalize() && "Unexpected legal type");
1153 // Weird sized vectors are a pain to handle, but we know 3 is really the same
1155 unsigned NElts = SrcVT.getVectorNumElements();
1156 if (!SrcVT.isSimple() && NElts != 3)
1159 // Handle v4i8 -> v4f32 extload. Replace the v4i8 with a legal i32 load to
1160 // prevent a mess from expanding to v4i32 and repacking.
1161 if (ISD::isNormalLoad(Src.getNode()) && Src.hasOneUse()) {
1162 EVT LoadVT = getEquivalentMemType(*DAG.getContext(), SrcVT);
1163 EVT RegVT = getEquivalentLoadRegType(*DAG.getContext(), SrcVT);
1164 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f32, NElts);
1166 LoadSDNode *Load = cast<LoadSDNode>(Src);
1167 SDValue NewLoad = DAG.getExtLoad(ISD::ZEXTLOAD, DL, RegVT,
1171 Load->getMemOperand());
1173 // Make sure successors of the original load stay after it by updating
1174 // them to use the new Chain.
1175 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), NewLoad.getValue(1));
1177 SmallVector<SDValue, 4> Elts;
1178 if (RegVT.isVector())
1179 DAG.ExtractVectorElements(NewLoad, Elts);
1181 Elts.push_back(NewLoad);
1183 SmallVector<SDValue, 4> Ops;
1185 unsigned EltIdx = 0;
1186 for (SDValue Elt : Elts) {
1187 unsigned ComponentsInElt = std::min(4u, NElts - 4 * EltIdx);
1188 for (unsigned I = 0; I < ComponentsInElt; ++I) {
1189 unsigned Opc = AMDGPUISD::CVT_F32_UBYTE0 + I;
1190 SDValue Cvt = DAG.getNode(Opc, DL, MVT::f32, Elt);
1191 DCI.AddToWorklist(Cvt.getNode());
1198 assert(Ops.size() == NElts);
1200 return DAG.getNode(ISD::BUILD_VECTOR, DL, FloatVT, Ops);
1206 SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
1207 DAGCombinerInfo &DCI) const {
1208 SelectionDAG &DAG = DCI.DAG;
1210 EVT VT = N->getValueType(0);
1212 switch (N->getOpcode()) {
1213 default: return AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
1215 SDValue Arg0 = N->getOperand(0);
1216 SDValue Arg1 = N->getOperand(1);
1217 SDValue CC = N->getOperand(2);
1218 ConstantSDNode * C = nullptr;
1219 ISD::CondCode CCOp = dyn_cast<CondCodeSDNode>(CC)->get();
1221 // i1 setcc (sext(i1), 0, setne) -> i1 setcc(i1, 0, setne)
1223 && Arg0.getOpcode() == ISD::SIGN_EXTEND
1224 && Arg0.getOperand(0).getValueType() == MVT::i1
1225 && (C = dyn_cast<ConstantSDNode>(Arg1))
1227 && CCOp == ISD::SETNE) {
1228 return SimplifySetCC(VT, Arg0.getOperand(0),
1229 DAG.getConstant(0, MVT::i1), CCOp, true, DCI, DL);
1234 case AMDGPUISD::CVT_F32_UBYTE0:
1235 case AMDGPUISD::CVT_F32_UBYTE1:
1236 case AMDGPUISD::CVT_F32_UBYTE2:
1237 case AMDGPUISD::CVT_F32_UBYTE3: {
1238 unsigned Offset = N->getOpcode() - AMDGPUISD::CVT_F32_UBYTE0;
1240 SDValue Src = N->getOperand(0);
1241 APInt Demanded = APInt::getBitsSet(32, 8 * Offset, 8 * Offset + 8);
1243 APInt KnownZero, KnownOne;
1244 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
1245 !DCI.isBeforeLegalizeOps());
1246 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1247 if (TLO.ShrinkDemandedConstant(Src, Demanded) ||
1248 TLI.SimplifyDemandedBits(Src, Demanded, KnownZero, KnownOne, TLO)) {
1249 DCI.CommitTargetLoweringOpt(TLO);
1255 case ISD::UINT_TO_FP: {
1256 return performUCharToFloatCombine(N, DCI);
1260 return AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
1263 /// \brief Test if RegClass is one of the VSrc classes
1264 static bool isVSrc(unsigned RegClass) {
1265 return AMDGPU::VSrc_32RegClassID == RegClass ||
1266 AMDGPU::VSrc_64RegClassID == RegClass;
1269 /// \brief Test if RegClass is one of the SSrc classes
1270 static bool isSSrc(unsigned RegClass) {
1271 return AMDGPU::SSrc_32RegClassID == RegClass ||
1272 AMDGPU::SSrc_64RegClassID == RegClass;
1275 /// \brief Analyze the possible immediate value Op
1277 /// Returns -1 if it isn't an immediate, 0 if it's and inline immediate
1278 /// and the immediate value if it's a literal immediate
1279 int32_t SITargetLowering::analyzeImmediate(const SDNode *N) const {
1286 if (const ConstantSDNode *Node = dyn_cast<ConstantSDNode>(N)) {
1287 if (Node->getZExtValue() >> 32) {
1290 Imm.I = Node->getSExtValue();
1291 } else if (const ConstantFPSDNode *Node = dyn_cast<ConstantFPSDNode>(N)) {
1292 if (N->getValueType(0) != MVT::f32)
1294 Imm.F = Node->getValueAPF().convertToFloat();
1296 return -1; // It isn't an immediate
1298 if ((Imm.I >= -16 && Imm.I <= 64) ||
1299 Imm.F == 0.5f || Imm.F == -0.5f ||
1300 Imm.F == 1.0f || Imm.F == -1.0f ||
1301 Imm.F == 2.0f || Imm.F == -2.0f ||
1302 Imm.F == 4.0f || Imm.F == -4.0f)
1303 return 0; // It's an inline immediate
1305 return Imm.I; // It's a literal immediate
1308 /// \brief Try to fold an immediate directly into an instruction
1309 bool SITargetLowering::foldImm(SDValue &Operand, int32_t &Immediate,
1310 bool &ScalarSlotUsed) const {
1312 MachineSDNode *Mov = dyn_cast<MachineSDNode>(Operand);
1313 const SIInstrInfo *TII =
1314 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
1315 if (!Mov || !TII->isMov(Mov->getMachineOpcode()))
1318 const SDValue &Op = Mov->getOperand(0);
1319 int32_t Value = analyzeImmediate(Op.getNode());
1321 // Not an immediate at all
1324 } else if (Value == 0) {
1325 // Inline immediates can always be fold
1329 } else if (Value == Immediate) {
1330 // Already fold literal immediate
1334 } else if (!ScalarSlotUsed && !Immediate) {
1335 // Fold this literal immediate
1336 ScalarSlotUsed = true;
1346 const TargetRegisterClass *SITargetLowering::getRegClassForNode(
1347 SelectionDAG &DAG, const SDValue &Op) const {
1348 const SIInstrInfo *TII =
1349 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
1350 const SIRegisterInfo &TRI = TII->getRegisterInfo();
1352 if (!Op->isMachineOpcode()) {
1353 switch(Op->getOpcode()) {
1354 case ISD::CopyFromReg: {
1355 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1356 unsigned Reg = cast<RegisterSDNode>(Op->getOperand(1))->getReg();
1357 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
1358 return MRI.getRegClass(Reg);
1360 return TRI.getPhysRegClass(Reg);
1362 default: return nullptr;
1365 const MCInstrDesc &Desc = TII->get(Op->getMachineOpcode());
1366 int OpClassID = Desc.OpInfo[Op.getResNo()].RegClass;
1367 if (OpClassID != -1) {
1368 return TRI.getRegClass(OpClassID);
1370 switch(Op.getMachineOpcode()) {
1371 case AMDGPU::COPY_TO_REGCLASS:
1372 // Operand 1 is the register class id for COPY_TO_REGCLASS instructions.
1373 OpClassID = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
1375 // If the COPY_TO_REGCLASS instruction is copying to a VSrc register
1376 // class, then the register class for the value could be either a
1377 // VReg or and SReg. In order to get a more accurate
1378 if (OpClassID == AMDGPU::VSrc_32RegClassID ||
1379 OpClassID == AMDGPU::VSrc_64RegClassID) {
1380 return getRegClassForNode(DAG, Op.getOperand(0));
1382 return TRI.getRegClass(OpClassID);
1383 case AMDGPU::EXTRACT_SUBREG: {
1384 int SubIdx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
1385 const TargetRegisterClass *SuperClass =
1386 getRegClassForNode(DAG, Op.getOperand(0));
1387 return TRI.getSubClassWithSubReg(SuperClass, SubIdx);
1389 case AMDGPU::REG_SEQUENCE:
1390 // Operand 0 is the register class id for REG_SEQUENCE instructions.
1391 return TRI.getRegClass(
1392 cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue());
1394 return getRegClassFor(Op.getSimpleValueType());
1398 /// \brief Does "Op" fit into register class "RegClass" ?
1399 bool SITargetLowering::fitsRegClass(SelectionDAG &DAG, const SDValue &Op,
1400 unsigned RegClass) const {
1401 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
1402 const TargetRegisterClass *RC = getRegClassForNode(DAG, Op);
1406 return TRI->getRegClass(RegClass)->hasSubClassEq(RC);
1409 /// \brief Make sure that we don't exeed the number of allowed scalars
1410 void SITargetLowering::ensureSRegLimit(SelectionDAG &DAG, SDValue &Operand,
1412 bool &ScalarSlotUsed) const {
1414 // First map the operands register class to a destination class
1415 if (RegClass == AMDGPU::VSrc_32RegClassID)
1416 RegClass = AMDGPU::VReg_32RegClassID;
1417 else if (RegClass == AMDGPU::VSrc_64RegClassID)
1418 RegClass = AMDGPU::VReg_64RegClassID;
1422 // Nothing to do if they fit naturally
1423 if (fitsRegClass(DAG, Operand, RegClass))
1426 // If the scalar slot isn't used yet use it now
1427 if (!ScalarSlotUsed) {
1428 ScalarSlotUsed = true;
1432 // This is a conservative aproach. It is possible that we can't determine the
1433 // correct register class and copy too often, but better safe than sorry.
1436 // We can't use COPY_TO_REGCLASS with FrameIndex arguments.
1437 if (isa<FrameIndexSDNode>(Operand)) {
1438 unsigned Opcode = Operand.getValueType() == MVT::i32 ?
1439 AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64;
1440 Node = DAG.getMachineNode(Opcode, SDLoc(), Operand.getValueType(),
1443 SDValue RC = DAG.getTargetConstant(RegClass, MVT::i32);
1444 Node = DAG.getMachineNode(TargetOpcode::COPY_TO_REGCLASS, SDLoc(),
1445 Operand.getValueType(), Operand, RC);
1447 Operand = SDValue(Node, 0);
1450 /// \returns true if \p Node's operands are different from the SDValue list
1452 static bool isNodeChanged(const SDNode *Node, const std::vector<SDValue> &Ops) {
1453 for (unsigned i = 0, e = Node->getNumOperands(); i < e; ++i) {
1454 if (Ops[i].getNode() != Node->getOperand(i).getNode()) {
1461 /// \brief Try to fold the Nodes operands into the Node
1462 SDNode *SITargetLowering::foldOperands(MachineSDNode *Node,
1463 SelectionDAG &DAG) const {
1465 // Original encoding (either e32 or e64)
1466 int Opcode = Node->getMachineOpcode();
1467 const SIInstrInfo *TII =
1468 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
1469 const MCInstrDesc *Desc = &TII->get(Opcode);
1471 unsigned NumDefs = Desc->getNumDefs();
1472 unsigned NumOps = Desc->getNumOperands();
1474 // Commuted opcode if available
1475 int OpcodeRev = Desc->isCommutable() ? TII->commuteOpcode(Opcode) : -1;
1476 const MCInstrDesc *DescRev = OpcodeRev == -1 ? nullptr : &TII->get(OpcodeRev);
1478 assert(!DescRev || DescRev->getNumDefs() == NumDefs);
1479 assert(!DescRev || DescRev->getNumOperands() == NumOps);
1481 // e64 version if available, -1 otherwise
1482 int OpcodeE64 = AMDGPU::getVOPe64(Opcode);
1483 const MCInstrDesc *DescE64 = OpcodeE64 == -1 ? nullptr : &TII->get(OpcodeE64);
1484 int InputModifiers[3] = {0};
1486 assert(!DescE64 || DescE64->getNumDefs() == NumDefs);
1488 int32_t Immediate = Desc->getSize() == 4 ? 0 : -1;
1489 bool HaveVSrc = false, HaveSSrc = false;
1491 // First figure out what we already have in this instruction.
1492 for (unsigned i = 0, e = Node->getNumOperands(), Op = NumDefs;
1493 i != e && Op < NumOps; ++i, ++Op) {
1495 unsigned RegClass = Desc->OpInfo[Op].RegClass;
1496 if (isVSrc(RegClass))
1498 else if (isSSrc(RegClass))
1503 int32_t Imm = analyzeImmediate(Node->getOperand(i).getNode());
1504 if (Imm != -1 && Imm != 0) {
1505 // Literal immediate
1510 // If we neither have VSrc nor SSrc, it makes no sense to continue.
1511 if (!HaveVSrc && !HaveSSrc)
1514 // No scalar allowed when we have both VSrc and SSrc
1515 bool ScalarSlotUsed = HaveVSrc && HaveSSrc;
1517 // Second go over the operands and try to fold them
1518 std::vector<SDValue> Ops;
1519 bool Promote2e64 = false;
1520 for (unsigned i = 0, e = Node->getNumOperands(), Op = NumDefs;
1521 i != e && Op < NumOps; ++i, ++Op) {
1523 const SDValue &Operand = Node->getOperand(i);
1524 Ops.push_back(Operand);
1526 // Already folded immediate?
1527 if (isa<ConstantSDNode>(Operand.getNode()) ||
1528 isa<ConstantFPSDNode>(Operand.getNode()))
1531 // Is this a VSrc or SSrc operand?
1532 unsigned RegClass = Desc->OpInfo[Op].RegClass;
1533 if (isVSrc(RegClass) || isSSrc(RegClass)) {
1534 // Try to fold the immediates
1535 if (!foldImm(Ops[i], Immediate, ScalarSlotUsed)) {
1536 // Folding didn't work, make sure we don't hit the SReg limit.
1537 ensureSRegLimit(DAG, Ops[i], RegClass, ScalarSlotUsed);
1541 // If it's not a VSrc or SSrc operand check if we have a GlobalAddress.
1542 // These will be lowered to immediates, so we will need to insert a MOV.
1543 if (isa<GlobalAddressSDNode>(Ops[i])) {
1544 SDNode *Node = DAG.getMachineNode(AMDGPU::V_MOV_B32_e32, SDLoc(),
1545 Operand.getValueType(), Operand);
1546 Ops[i] = SDValue(Node, 0);
1550 if (i == 1 && DescRev && fitsRegClass(DAG, Ops[0], RegClass)) {
1552 unsigned OtherRegClass = Desc->OpInfo[NumDefs].RegClass;
1553 assert(isVSrc(OtherRegClass) || isSSrc(OtherRegClass));
1555 // Test if it makes sense to swap operands
1556 if (foldImm(Ops[1], Immediate, ScalarSlotUsed) ||
1557 (!fitsRegClass(DAG, Ops[1], RegClass) &&
1558 fitsRegClass(DAG, Ops[1], OtherRegClass))) {
1560 // Swap commutable operands
1561 std::swap(Ops[0], Ops[1]);
1573 // Test if it makes sense to switch to e64 encoding
1574 unsigned OtherRegClass = DescE64->OpInfo[Op].RegClass;
1575 if (!isVSrc(OtherRegClass) && !isSSrc(OtherRegClass))
1578 int32_t TmpImm = -1;
1579 if (foldImm(Ops[i], TmpImm, ScalarSlotUsed) ||
1580 (!fitsRegClass(DAG, Ops[i], RegClass) &&
1581 fitsRegClass(DAG, Ops[1], OtherRegClass))) {
1583 // Switch to e64 encoding
1591 if (!DescE64 && !Promote2e64)
1593 if (!Operand.isMachineOpcode())
1595 if (Operand.getMachineOpcode() == AMDGPU::FNEG_SI) {
1597 Ops.push_back(Operand.getOperand(0));
1598 InputModifiers[i] = 1;
1605 else if (Operand.getMachineOpcode() == AMDGPU::FABS_SI) {
1607 Ops.push_back(Operand.getOperand(0));
1608 InputModifiers[i] = 2;
1618 std::vector<SDValue> OldOps(Ops);
1620 for (unsigned i = 0; i < OldOps.size(); ++i) {
1622 Ops.push_back(DAG.getTargetConstant(InputModifiers[i], MVT::i32));
1623 Ops.push_back(OldOps[i]);
1625 // Add the modifier flags while promoting
1626 for (unsigned i = 0; i < 2; ++i)
1627 Ops.push_back(DAG.getTargetConstant(0, MVT::i32));
1630 // Add optional chain and glue
1631 for (unsigned i = NumOps - NumDefs, e = Node->getNumOperands(); i < e; ++i)
1632 Ops.push_back(Node->getOperand(i));
1634 // Nodes that have a glue result are not CSE'd by getMachineNode(), so in
1635 // this case a brand new node is always be created, even if the operands
1636 // are the same as before. So, manually check if anything has been changed.
1637 if (Desc->Opcode == Opcode && !isNodeChanged(Node, Ops)) {
1641 // Create a complete new instruction
1642 return DAG.getMachineNode(Desc->Opcode, SDLoc(Node), Node->getVTList(), Ops);
1645 /// \brief Helper function for adjustWritemask
1646 static unsigned SubIdx2Lane(unsigned Idx) {
1649 case AMDGPU::sub0: return 0;
1650 case AMDGPU::sub1: return 1;
1651 case AMDGPU::sub2: return 2;
1652 case AMDGPU::sub3: return 3;
1656 /// \brief Adjust the writemask of MIMG instructions
1657 void SITargetLowering::adjustWritemask(MachineSDNode *&Node,
1658 SelectionDAG &DAG) const {
1659 SDNode *Users[4] = { };
1661 unsigned OldDmask = Node->getConstantOperandVal(0);
1662 unsigned NewDmask = 0;
1664 // Try to figure out the used register components
1665 for (SDNode::use_iterator I = Node->use_begin(), E = Node->use_end();
1668 // Abort if we can't understand the usage
1669 if (!I->isMachineOpcode() ||
1670 I->getMachineOpcode() != TargetOpcode::EXTRACT_SUBREG)
1673 // Lane means which subreg of %VGPRa_VGPRb_VGPRc_VGPRd is used.
1674 // Note that subregs are packed, i.e. Lane==0 is the first bit set
1675 // in OldDmask, so it can be any of X,Y,Z,W; Lane==1 is the second bit
1677 Lane = SubIdx2Lane(I->getConstantOperandVal(1));
1679 // Set which texture component corresponds to the lane.
1681 for (unsigned i = 0, Dmask = OldDmask; i <= Lane; i++) {
1683 Comp = countTrailingZeros(Dmask);
1684 Dmask &= ~(1 << Comp);
1687 // Abort if we have more than one user per component
1692 NewDmask |= 1 << Comp;
1695 // Abort if there's no change
1696 if (NewDmask == OldDmask)
1699 // Adjust the writemask in the node
1700 std::vector<SDValue> Ops;
1701 Ops.push_back(DAG.getTargetConstant(NewDmask, MVT::i32));
1702 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i)
1703 Ops.push_back(Node->getOperand(i));
1704 Node = (MachineSDNode*)DAG.UpdateNodeOperands(Node, Ops);
1706 // If we only got one lane, replace it with a copy
1707 // (if NewDmask has only one bit set...)
1708 if (NewDmask && (NewDmask & (NewDmask-1)) == 0) {
1709 SDValue RC = DAG.getTargetConstant(AMDGPU::VReg_32RegClassID, MVT::i32);
1710 SDNode *Copy = DAG.getMachineNode(TargetOpcode::COPY_TO_REGCLASS,
1711 SDLoc(), Users[Lane]->getValueType(0),
1712 SDValue(Node, 0), RC);
1713 DAG.ReplaceAllUsesWith(Users[Lane], Copy);
1717 // Update the users of the node with the new indices
1718 for (unsigned i = 0, Idx = AMDGPU::sub0; i < 4; ++i) {
1720 SDNode *User = Users[i];
1724 SDValue Op = DAG.getTargetConstant(Idx, MVT::i32);
1725 DAG.UpdateNodeOperands(User, User->getOperand(0), Op);
1729 case AMDGPU::sub0: Idx = AMDGPU::sub1; break;
1730 case AMDGPU::sub1: Idx = AMDGPU::sub2; break;
1731 case AMDGPU::sub2: Idx = AMDGPU::sub3; break;
1736 /// \brief Fold the instructions after selecting them.
1737 SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node,
1738 SelectionDAG &DAG) const {
1739 const SIInstrInfo *TII =
1740 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
1741 Node = AdjustRegClass(Node, DAG);
1743 if (TII->isMIMG(Node->getMachineOpcode()))
1744 adjustWritemask(Node, DAG);
1746 return foldOperands(Node, DAG);
1749 /// \brief Assign the register class depending on the number of
1750 /// bits set in the writemask
1751 void SITargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
1752 SDNode *Node) const {
1753 const SIInstrInfo *TII =
1754 static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
1755 if (!TII->isMIMG(MI->getOpcode()))
1758 unsigned VReg = MI->getOperand(0).getReg();
1759 unsigned Writemask = MI->getOperand(1).getImm();
1760 unsigned BitsSet = 0;
1761 for (unsigned i = 0; i < 4; ++i)
1762 BitsSet += Writemask & (1 << i) ? 1 : 0;
1764 const TargetRegisterClass *RC;
1767 case 1: RC = &AMDGPU::VReg_32RegClass; break;
1768 case 2: RC = &AMDGPU::VReg_64RegClass; break;
1769 case 3: RC = &AMDGPU::VReg_96RegClass; break;
1772 unsigned NewOpcode = TII->getMaskedMIMGOp(MI->getOpcode(), BitsSet);
1773 MI->setDesc(TII->get(NewOpcode));
1774 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1775 MRI.setRegClass(VReg, RC);
1778 MachineSDNode *SITargetLowering::AdjustRegClass(MachineSDNode *N,
1779 SelectionDAG &DAG) const {
1782 unsigned NewOpcode = N->getMachineOpcode();
1784 switch (N->getMachineOpcode()) {
1786 case AMDGPU::S_LOAD_DWORD_IMM:
1787 NewOpcode = AMDGPU::BUFFER_LOAD_DWORD_ADDR64;
1789 case AMDGPU::S_LOAD_DWORDX2_SGPR:
1790 if (NewOpcode == N->getMachineOpcode()) {
1791 NewOpcode = AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64;
1794 case AMDGPU::S_LOAD_DWORDX4_IMM:
1795 case AMDGPU::S_LOAD_DWORDX4_SGPR: {
1796 if (NewOpcode == N->getMachineOpcode()) {
1797 NewOpcode = AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64;
1799 if (fitsRegClass(DAG, N->getOperand(0), AMDGPU::SReg_64RegClassID)) {
1802 ConstantSDNode *Offset = cast<ConstantSDNode>(N->getOperand(1));
1804 SDValue(DAG.getMachineNode(AMDGPU::SI_ADDR64_RSRC, DL, MVT::i128,
1805 DAG.getConstant(0, MVT::i64)), 0),
1807 DAG.getConstant(Offset->getSExtValue() << 2, MVT::i32)
1809 return DAG.getMachineNode(NewOpcode, DL, N->getVTList(), Ops);
1814 SDValue SITargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
1815 const TargetRegisterClass *RC,
1816 unsigned Reg, EVT VT) const {
1817 SDValue VReg = AMDGPUTargetLowering::CreateLiveInRegister(DAG, RC, Reg, VT);
1819 return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(DAG.getEntryNode()),
1820 cast<RegisterSDNode>(VReg)->getReg(), VT);