1 //===-- SIISelLowering.cpp - SI DAG Lowering Implementation ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Custom DAG lowering for SI
13 //===----------------------------------------------------------------------===//
17 #define _USE_MATH_DEFINES
21 #include "SIISelLowering.h"
23 #include "AMDGPUIntrinsicInfo.h"
24 #include "AMDGPUSubtarget.h"
25 #include "SIInstrInfo.h"
26 #include "SIMachineFunctionInfo.h"
27 #include "SIRegisterInfo.h"
28 #include "llvm/ADT/BitVector.h"
29 #include "llvm/CodeGen/CallingConvLower.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/SelectionDAG.h"
33 #include "llvm/IR/Function.h"
34 #include "llvm/ADT/SmallString.h"
38 SITargetLowering::SITargetLowering(TargetMachine &TM) :
39 AMDGPUTargetLowering(TM) {
40 addRegisterClass(MVT::i1, &AMDGPU::VReg_1RegClass);
41 addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass);
43 addRegisterClass(MVT::v32i8, &AMDGPU::SReg_256RegClass);
44 addRegisterClass(MVT::v64i8, &AMDGPU::SReg_512RegClass);
46 addRegisterClass(MVT::i32, &AMDGPU::SReg_32RegClass);
47 addRegisterClass(MVT::f32, &AMDGPU::VGPR_32RegClass);
49 addRegisterClass(MVT::f64, &AMDGPU::VReg_64RegClass);
50 addRegisterClass(MVT::v2i32, &AMDGPU::SReg_64RegClass);
51 addRegisterClass(MVT::v2f32, &AMDGPU::VReg_64RegClass);
53 addRegisterClass(MVT::v4i32, &AMDGPU::SReg_128RegClass);
54 addRegisterClass(MVT::v4f32, &AMDGPU::VReg_128RegClass);
56 addRegisterClass(MVT::v8i32, &AMDGPU::SReg_256RegClass);
57 addRegisterClass(MVT::v8f32, &AMDGPU::VReg_256RegClass);
59 addRegisterClass(MVT::v16i32, &AMDGPU::SReg_512RegClass);
60 addRegisterClass(MVT::v16f32, &AMDGPU::VReg_512RegClass);
62 computeRegisterProperties();
64 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i32, Expand);
65 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Expand);
66 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i32, Expand);
67 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16f32, Expand);
69 setOperationAction(ISD::ADD, MVT::i32, Legal);
70 setOperationAction(ISD::ADDC, MVT::i32, Legal);
71 setOperationAction(ISD::ADDE, MVT::i32, Legal);
72 setOperationAction(ISD::SUBC, MVT::i32, Legal);
73 setOperationAction(ISD::SUBE, MVT::i32, Legal);
75 setOperationAction(ISD::FSIN, MVT::f32, Custom);
76 setOperationAction(ISD::FCOS, MVT::f32, Custom);
78 setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
79 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
80 setOperationAction(ISD::FMINNUM, MVT::f64, Legal);
81 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal);
83 // We need to custom lower vector stores from local memory
84 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
85 setOperationAction(ISD::LOAD, MVT::v8i32, Custom);
86 setOperationAction(ISD::LOAD, MVT::v16i32, Custom);
88 setOperationAction(ISD::STORE, MVT::v8i32, Custom);
89 setOperationAction(ISD::STORE, MVT::v16i32, Custom);
91 setOperationAction(ISD::STORE, MVT::i1, Custom);
92 setOperationAction(ISD::STORE, MVT::i32, Custom);
93 setOperationAction(ISD::STORE, MVT::v2i32, Custom);
94 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
96 setOperationAction(ISD::SELECT, MVT::i64, Custom);
97 setOperationAction(ISD::SELECT, MVT::f64, Promote);
98 AddPromotedToType(ISD::SELECT, MVT::f64, MVT::i64);
100 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
101 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
102 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
103 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
105 setOperationAction(ISD::SETCC, MVT::v2i1, Expand);
106 setOperationAction(ISD::SETCC, MVT::v4i1, Expand);
108 setOperationAction(ISD::BSWAP, MVT::i32, Legal);
110 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Legal);
111 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Custom);
112 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Custom);
114 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Legal);
115 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
116 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Custom);
118 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Legal);
119 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
120 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Custom);
122 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
123 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Custom);
125 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
126 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::f32, Custom);
127 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v16i8, Custom);
128 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v4f32, Custom);
130 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
131 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
133 for (MVT VT : MVT::integer_valuetypes()) {
134 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
135 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Custom);
136 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Custom);
137 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i32, Expand);
139 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
140 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i8, Custom);
141 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Custom);
142 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i32, Expand);
144 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
145 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i8, Custom);
146 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i16, Custom);
147 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i32, Expand);
150 for (MVT VT : MVT::integer_vector_valuetypes()) {
151 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i16, Expand);
152 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v16i16, Expand);
155 for (MVT VT : MVT::fp_valuetypes())
156 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
158 setTruncStoreAction(MVT::i32, MVT::i8, Custom);
159 setTruncStoreAction(MVT::i32, MVT::i16, Custom);
160 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
161 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
162 setTruncStoreAction(MVT::v8i32, MVT::v8i16, Expand);
163 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Expand);
165 setOperationAction(ISD::LOAD, MVT::i1, Custom);
167 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
168 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
169 setOperationAction(ISD::FrameIndex, MVT::i32, Custom);
171 // These should use UDIVREM, so set them to expand
172 setOperationAction(ISD::UDIV, MVT::i64, Expand);
173 setOperationAction(ISD::UREM, MVT::i64, Expand);
175 // We only support LOAD/STORE and vector manipulation ops for vectors
176 // with > 4 elements.
178 MVT::v8i32, MVT::v8f32, MVT::v16i32, MVT::v16f32
181 setOperationAction(ISD::SELECT_CC, MVT::i1, Expand);
182 setOperationAction(ISD::SELECT, MVT::i1, Promote);
184 for (MVT VT : VecTypes) {
185 for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op) {
189 case ISD::BUILD_VECTOR:
191 case ISD::EXTRACT_VECTOR_ELT:
192 case ISD::INSERT_VECTOR_ELT:
193 case ISD::INSERT_SUBVECTOR:
194 case ISD::EXTRACT_SUBVECTOR:
196 case ISD::CONCAT_VECTORS:
197 setOperationAction(Op, VT, Custom);
200 setOperationAction(Op, VT, Expand);
206 if (Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS) {
207 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
208 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
209 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
210 setOperationAction(ISD::FRINT, MVT::f64, Legal);
213 setOperationAction(ISD::FDIV, MVT::f32, Custom);
215 setTargetDAGCombine(ISD::FADD);
216 setTargetDAGCombine(ISD::FSUB);
217 setTargetDAGCombine(ISD::FMINNUM);
218 setTargetDAGCombine(ISD::FMAXNUM);
219 setTargetDAGCombine(ISD::SELECT_CC);
220 setTargetDAGCombine(ISD::SETCC);
221 setTargetDAGCombine(ISD::AND);
222 setTargetDAGCombine(ISD::OR);
223 setTargetDAGCombine(ISD::UINT_TO_FP);
225 // All memory operations. Some folding on the pointer operand is done to help
226 // matching the constant offsets in the addressing modes.
227 setTargetDAGCombine(ISD::LOAD);
228 setTargetDAGCombine(ISD::STORE);
229 setTargetDAGCombine(ISD::ATOMIC_LOAD);
230 setTargetDAGCombine(ISD::ATOMIC_STORE);
231 setTargetDAGCombine(ISD::ATOMIC_CMP_SWAP);
232 setTargetDAGCombine(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS);
233 setTargetDAGCombine(ISD::ATOMIC_SWAP);
234 setTargetDAGCombine(ISD::ATOMIC_LOAD_ADD);
235 setTargetDAGCombine(ISD::ATOMIC_LOAD_SUB);
236 setTargetDAGCombine(ISD::ATOMIC_LOAD_AND);
237 setTargetDAGCombine(ISD::ATOMIC_LOAD_OR);
238 setTargetDAGCombine(ISD::ATOMIC_LOAD_XOR);
239 setTargetDAGCombine(ISD::ATOMIC_LOAD_NAND);
240 setTargetDAGCombine(ISD::ATOMIC_LOAD_MIN);
241 setTargetDAGCombine(ISD::ATOMIC_LOAD_MAX);
242 setTargetDAGCombine(ISD::ATOMIC_LOAD_UMIN);
243 setTargetDAGCombine(ISD::ATOMIC_LOAD_UMAX);
245 setSchedulingPreference(Sched::RegPressure);
248 //===----------------------------------------------------------------------===//
249 // TargetLowering queries
250 //===----------------------------------------------------------------------===//
252 bool SITargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &,
254 // SI has some legal vector types, but no legal vector operations. Say no
255 // shuffles are legal in order to prefer scalarizing some vector operations.
259 // FIXME: This really needs an address space argument. The immediate offset
260 // size is different for different sets of memory instruction sets.
262 // The single offset DS instructions have a 16-bit unsigned byte offset.
264 // MUBUF / MTBUF have a 12-bit unsigned byte offset, and additionally can do r +
265 // r + i with addr64. 32-bit has more addressing mode options. Depending on the
266 // resource constant, it can also do (i64 r0) + (i32 r1) * (i14 i).
268 // SMRD instructions have an 8-bit, dword offset.
270 bool SITargetLowering::isLegalAddressingMode(const AddrMode &AM,
272 // No global is ever allowed as a base.
276 // Allow a 16-bit unsigned immediate field, since this is what DS instructions
278 if (!isUInt<16>(AM.BaseOffs))
283 case 0: // "r+i" or just "i", depending on HasBaseReg.
286 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
288 // Otherwise we have r+r or r+i.
291 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
295 default: // Don't allow n * r
302 bool SITargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
305 bool *IsFast) const {
309 // TODO: I think v3i32 should allow unaligned accesses on CI with DS_READ_B96,
310 // which isn't a simple VT.
311 if (!VT.isSimple() || VT == MVT::Other)
314 // XXX - CI changes say "Support for unaligned memory accesses" but I don't
315 // see what for specifically. The wording everywhere else seems to be the
318 // XXX - The only mention I see of this in the ISA manual is for LDS direct
319 // reads the "byte address and must be dword aligned". Is it also true for the
320 // normal loads and stores?
321 if (AddrSpace == AMDGPUAS::LOCAL_ADDRESS) {
322 // ds_read/write_b64 require 8-byte alignment, but we can do a 4 byte
323 // aligned, 8 byte access in a single operation using ds_read2/write2_b32
324 // with adjacent offsets.
325 return Align % 4 == 0;
328 // 8.1.6 - For Dword or larger reads or writes, the two LSBs of the
329 // byte-address are ignored, thus forcing Dword alignment.
330 // This applies to private, global, and constant memory.
333 return VT.bitsGT(MVT::i32);
336 EVT SITargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
337 unsigned SrcAlign, bool IsMemset,
340 MachineFunction &MF) const {
341 // FIXME: Should account for address space here.
343 // The default fallback uses the private pointer size as a guess for a type to
344 // use. Make sure we switch these to 64-bit accesses.
346 if (Size >= 16 && DstAlign >= 4) // XXX: Should only do for global
349 if (Size >= 8 && DstAlign >= 4)
356 TargetLoweringBase::LegalizeTypeAction
357 SITargetLowering::getPreferredVectorAction(EVT VT) const {
358 if (VT.getVectorNumElements() != 1 && VT.getScalarType().bitsLE(MVT::i16))
359 return TypeSplitVector;
361 return TargetLoweringBase::getPreferredVectorAction(VT);
364 bool SITargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
366 const SIInstrInfo *TII = static_cast<const SIInstrInfo *>(
367 getTargetMachine().getSubtargetImpl()->getInstrInfo());
368 return TII->isInlineConstant(Imm);
371 SDValue SITargetLowering::LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT,
372 SDLoc SL, SDValue Chain,
373 unsigned Offset, bool Signed) const {
374 const DataLayout *DL = getDataLayout();
375 MachineFunction &MF = DAG.getMachineFunction();
376 const SIRegisterInfo *TRI =
377 static_cast<const SIRegisterInfo*>(Subtarget->getRegisterInfo());
378 unsigned InputPtrReg = TRI->getPreloadedValue(MF, SIRegisterInfo::INPUT_PTR);
380 Type *Ty = VT.getTypeForEVT(*DAG.getContext());
382 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
383 PointerType *PtrTy = PointerType::get(Ty, AMDGPUAS::CONSTANT_ADDRESS);
384 SDValue BasePtr = DAG.getCopyFromReg(Chain, SL,
385 MRI.getLiveInVirtReg(InputPtrReg), MVT::i64);
386 SDValue Ptr = DAG.getNode(ISD::ADD, SL, MVT::i64, BasePtr,
387 DAG.getConstant(Offset, MVT::i64));
388 SDValue PtrOffset = DAG.getUNDEF(getPointerTy(AMDGPUAS::CONSTANT_ADDRESS));
389 MachinePointerInfo PtrInfo(UndefValue::get(PtrTy));
391 return DAG.getLoad(ISD::UNINDEXED, Signed ? ISD::SEXTLOAD : ISD::ZEXTLOAD,
392 VT, SL, Chain, Ptr, PtrOffset, PtrInfo, MemVT,
394 true, // isNonTemporal
396 DL->getABITypeAlignment(Ty)); // Alignment
399 SDValue SITargetLowering::LowerFormalArguments(
401 CallingConv::ID CallConv,
403 const SmallVectorImpl<ISD::InputArg> &Ins,
404 SDLoc DL, SelectionDAG &DAG,
405 SmallVectorImpl<SDValue> &InVals) const {
407 const TargetMachine &TM = getTargetMachine();
408 const SIRegisterInfo *TRI =
409 static_cast<const SIRegisterInfo*>(TM.getSubtargetImpl()->getRegisterInfo());
411 MachineFunction &MF = DAG.getMachineFunction();
412 FunctionType *FType = MF.getFunction()->getFunctionType();
413 SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
415 assert(CallConv == CallingConv::C);
417 SmallVector<ISD::InputArg, 16> Splits;
418 BitVector Skipped(Ins.size());
420 for (unsigned i = 0, e = Ins.size(), PSInputNum = 0; i != e; ++i) {
421 const ISD::InputArg &Arg = Ins[i];
423 // First check if it's a PS input addr
424 if (Info->getShaderType() == ShaderType::PIXEL && !Arg.Flags.isInReg() &&
425 !Arg.Flags.isByVal()) {
427 assert((PSInputNum <= 15) && "Too many PS inputs!");
430 // We can savely skip PS inputs
436 Info->PSInputAddr |= 1 << PSInputNum++;
439 // Second split vertices into their elements
440 if (Info->getShaderType() != ShaderType::COMPUTE && Arg.VT.isVector()) {
441 ISD::InputArg NewArg = Arg;
442 NewArg.Flags.setSplit();
443 NewArg.VT = Arg.VT.getVectorElementType();
445 // We REALLY want the ORIGINAL number of vertex elements here, e.g. a
446 // three or five element vertex only needs three or five registers,
447 // NOT four or eigth.
448 Type *ParamType = FType->getParamType(Arg.OrigArgIndex);
449 unsigned NumElements = ParamType->getVectorNumElements();
451 for (unsigned j = 0; j != NumElements; ++j) {
452 Splits.push_back(NewArg);
453 NewArg.PartOffset += NewArg.VT.getStoreSize();
456 } else if (Info->getShaderType() != ShaderType::COMPUTE) {
457 Splits.push_back(Arg);
461 SmallVector<CCValAssign, 16> ArgLocs;
462 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
465 // At least one interpolation mode must be enabled or else the GPU will hang.
466 if (Info->getShaderType() == ShaderType::PIXEL &&
467 (Info->PSInputAddr & 0x7F) == 0) {
468 Info->PSInputAddr |= 1;
469 CCInfo.AllocateReg(AMDGPU::VGPR0);
470 CCInfo.AllocateReg(AMDGPU::VGPR1);
473 // The pointer to the list of arguments is stored in SGPR0, SGPR1
474 // The pointer to the scratch buffer is stored in SGPR2, SGPR3
475 if (Info->getShaderType() == ShaderType::COMPUTE) {
476 if (Subtarget->isAmdHsaOS())
477 Info->NumUserSGPRs = 2; // FIXME: Need to support scratch buffers.
479 Info->NumUserSGPRs = 4;
481 unsigned InputPtrReg =
482 TRI->getPreloadedValue(MF, SIRegisterInfo::INPUT_PTR);
483 unsigned InputPtrRegLo =
484 TRI->getPhysRegSubReg(InputPtrReg, &AMDGPU::SReg_32RegClass, 0);
485 unsigned InputPtrRegHi =
486 TRI->getPhysRegSubReg(InputPtrReg, &AMDGPU::SReg_32RegClass, 1);
488 unsigned ScratchPtrReg =
489 TRI->getPreloadedValue(MF, SIRegisterInfo::SCRATCH_PTR);
490 unsigned ScratchPtrRegLo =
491 TRI->getPhysRegSubReg(ScratchPtrReg, &AMDGPU::SReg_32RegClass, 0);
492 unsigned ScratchPtrRegHi =
493 TRI->getPhysRegSubReg(ScratchPtrReg, &AMDGPU::SReg_32RegClass, 1);
495 CCInfo.AllocateReg(InputPtrRegLo);
496 CCInfo.AllocateReg(InputPtrRegHi);
497 CCInfo.AllocateReg(ScratchPtrRegLo);
498 CCInfo.AllocateReg(ScratchPtrRegHi);
499 MF.addLiveIn(InputPtrReg, &AMDGPU::SReg_64RegClass);
500 MF.addLiveIn(ScratchPtrReg, &AMDGPU::SReg_64RegClass);
503 if (Info->getShaderType() == ShaderType::COMPUTE) {
504 getOriginalFunctionArgs(DAG, DAG.getMachineFunction().getFunction(), Ins,
508 AnalyzeFormalArguments(CCInfo, Splits);
510 for (unsigned i = 0, e = Ins.size(), ArgIdx = 0; i != e; ++i) {
512 const ISD::InputArg &Arg = Ins[i];
514 InVals.push_back(DAG.getUNDEF(Arg.VT));
518 CCValAssign &VA = ArgLocs[ArgIdx++];
519 MVT VT = VA.getLocVT();
523 EVT MemVT = Splits[i].VT;
524 const unsigned Offset = 36 + VA.getLocMemOffset();
525 // The first 36 bytes of the input buffer contains information about
526 // thread group and global sizes.
527 SDValue Arg = LowerParameter(DAG, VT, MemVT, DL, DAG.getRoot(),
528 Offset, Ins[i].Flags.isSExt());
530 const PointerType *ParamTy =
531 dyn_cast<PointerType>(FType->getParamType(Ins[i].OrigArgIndex));
532 if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS &&
533 ParamTy && ParamTy->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS) {
534 // On SI local pointers are just offsets into LDS, so they are always
535 // less than 16-bits. On CI and newer they could potentially be
536 // real pointers, so we can't guarantee their size.
537 Arg = DAG.getNode(ISD::AssertZext, DL, Arg.getValueType(), Arg,
538 DAG.getValueType(MVT::i16));
541 InVals.push_back(Arg);
542 Info->ABIArgOffset = Offset + MemVT.getStoreSize();
545 assert(VA.isRegLoc() && "Parameter must be in a register!");
547 unsigned Reg = VA.getLocReg();
549 if (VT == MVT::i64) {
550 // For now assume it is a pointer
551 Reg = TRI->getMatchingSuperReg(Reg, AMDGPU::sub0,
552 &AMDGPU::SReg_64RegClass);
553 Reg = MF.addLiveIn(Reg, &AMDGPU::SReg_64RegClass);
554 InVals.push_back(DAG.getCopyFromReg(Chain, DL, Reg, VT));
558 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
560 Reg = MF.addLiveIn(Reg, RC);
561 SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, VT);
563 if (Arg.VT.isVector()) {
565 // Build a vector from the registers
566 Type *ParamType = FType->getParamType(Arg.OrigArgIndex);
567 unsigned NumElements = ParamType->getVectorNumElements();
569 SmallVector<SDValue, 4> Regs;
571 for (unsigned j = 1; j != NumElements; ++j) {
572 Reg = ArgLocs[ArgIdx++].getLocReg();
573 Reg = MF.addLiveIn(Reg, RC);
574 Regs.push_back(DAG.getCopyFromReg(Chain, DL, Reg, VT));
577 // Fill up the missing vector elements
578 NumElements = Arg.VT.getVectorNumElements() - NumElements;
579 for (unsigned j = 0; j != NumElements; ++j)
580 Regs.push_back(DAG.getUNDEF(VT));
582 InVals.push_back(DAG.getNode(ISD::BUILD_VECTOR, DL, Arg.VT, Regs));
586 InVals.push_back(Val);
591 MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
592 MachineInstr * MI, MachineBasicBlock * BB) const {
594 MachineBasicBlock::iterator I = *MI;
595 const SIInstrInfo *TII = static_cast<const SIInstrInfo *>(
596 getTargetMachine().getSubtargetImpl()->getInstrInfo());
598 switch (MI->getOpcode()) {
600 return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
601 case AMDGPU::BRANCH: return BB;
602 case AMDGPU::V_SUB_F64: {
603 unsigned DestReg = MI->getOperand(0).getReg();
604 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_ADD_F64), DestReg)
605 .addImm(0) // SRC0 modifiers
606 .addReg(MI->getOperand(1).getReg())
607 .addImm(1) // SRC1 modifiers
608 .addReg(MI->getOperand(2).getReg())
611 MI->eraseFromParent();
614 case AMDGPU::SI_RegisterStorePseudo: {
615 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
616 unsigned Reg = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
617 MachineInstrBuilder MIB =
618 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::SI_RegisterStore),
620 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
621 MIB.addOperand(MI->getOperand(i));
623 MI->eraseFromParent();
630 EVT SITargetLowering::getSetCCResultType(LLVMContext &Ctx, EVT VT) const {
631 if (!VT.isVector()) {
634 return EVT::getVectorVT(Ctx, MVT::i1, VT.getVectorNumElements());
637 MVT SITargetLowering::getScalarShiftAmountTy(EVT VT) const {
641 bool SITargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
642 VT = VT.getScalarType();
647 switch (VT.getSimpleVT().SimpleTy) {
649 return false; /* There is V_MAD_F32 for f32 */
659 //===----------------------------------------------------------------------===//
660 // Custom DAG Lowering Operations
661 //===----------------------------------------------------------------------===//
663 SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
664 switch (Op.getOpcode()) {
665 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
666 case ISD::FrameIndex: return LowerFrameIndex(Op, DAG);
667 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
669 SDValue Result = LowerLOAD(Op, DAG);
670 assert((!Result.getNode() ||
671 Result.getNode()->getNumValues() == 2) &&
672 "Load should return a value and a chain");
678 return LowerTrig(Op, DAG);
679 case ISD::SELECT: return LowerSELECT(Op, DAG);
680 case ISD::FDIV: return LowerFDIV(Op, DAG);
681 case ISD::STORE: return LowerSTORE(Op, DAG);
682 case ISD::GlobalAddress: {
683 MachineFunction &MF = DAG.getMachineFunction();
684 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
685 return LowerGlobalAddress(MFI, Op, DAG);
687 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
688 case ISD::INTRINSIC_VOID: return LowerINTRINSIC_VOID(Op, DAG);
693 /// \brief Helper function for LowerBRCOND
694 static SDNode *findUser(SDValue Value, unsigned Opcode) {
696 SDNode *Parent = Value.getNode();
697 for (SDNode::use_iterator I = Parent->use_begin(), E = Parent->use_end();
700 if (I.getUse().get() != Value)
703 if (I->getOpcode() == Opcode)
709 SDValue SITargetLowering::LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const {
711 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Op);
712 unsigned FrameIndex = FINode->getIndex();
714 return DAG.getTargetFrameIndex(FrameIndex, MVT::i32);
717 /// This transforms the control flow intrinsics to get the branch destination as
718 /// last parameter, also switches branch target with BR if the need arise
719 SDValue SITargetLowering::LowerBRCOND(SDValue BRCOND,
720 SelectionDAG &DAG) const {
724 SDNode *Intr = BRCOND.getOperand(1).getNode();
725 SDValue Target = BRCOND.getOperand(2);
726 SDNode *BR = nullptr;
728 if (Intr->getOpcode() == ISD::SETCC) {
729 // As long as we negate the condition everything is fine
730 SDNode *SetCC = Intr;
731 assert(SetCC->getConstantOperandVal(1) == 1);
732 assert(cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() ==
734 Intr = SetCC->getOperand(0).getNode();
737 // Get the target from BR if we don't negate the condition
738 BR = findUser(BRCOND, ISD::BR);
739 Target = BR->getOperand(1);
742 assert(Intr->getOpcode() == ISD::INTRINSIC_W_CHAIN);
744 // Build the result and
745 SmallVector<EVT, 4> Res;
746 for (unsigned i = 1, e = Intr->getNumValues(); i != e; ++i)
747 Res.push_back(Intr->getValueType(i));
749 // operands of the new intrinsic call
750 SmallVector<SDValue, 4> Ops;
751 Ops.push_back(BRCOND.getOperand(0));
752 for (unsigned i = 1, e = Intr->getNumOperands(); i != e; ++i)
753 Ops.push_back(Intr->getOperand(i));
754 Ops.push_back(Target);
756 // build the new intrinsic call
757 SDNode *Result = DAG.getNode(
758 Res.size() > 1 ? ISD::INTRINSIC_W_CHAIN : ISD::INTRINSIC_VOID, DL,
759 DAG.getVTList(Res), Ops).getNode();
762 // Give the branch instruction our target
767 SDValue NewBR = DAG.getNode(ISD::BR, DL, BR->getVTList(), Ops);
768 DAG.ReplaceAllUsesWith(BR, NewBR.getNode());
769 BR = NewBR.getNode();
772 SDValue Chain = SDValue(Result, Result->getNumValues() - 1);
774 // Copy the intrinsic results to registers
775 for (unsigned i = 1, e = Intr->getNumValues() - 1; i != e; ++i) {
776 SDNode *CopyToReg = findUser(SDValue(Intr, i), ISD::CopyToReg);
780 Chain = DAG.getCopyToReg(
782 CopyToReg->getOperand(1),
783 SDValue(Result, i - 1),
786 DAG.ReplaceAllUsesWith(SDValue(CopyToReg, 0), CopyToReg->getOperand(0));
789 // Remove the old intrinsic from the chain
790 DAG.ReplaceAllUsesOfValueWith(
791 SDValue(Intr, Intr->getNumValues() - 1),
792 Intr->getOperand(0));
797 SDValue SITargetLowering::LowerGlobalAddress(AMDGPUMachineFunction *MFI,
799 SelectionDAG &DAG) const {
800 GlobalAddressSDNode *GSD = cast<GlobalAddressSDNode>(Op);
802 if (GSD->getAddressSpace() != AMDGPUAS::CONSTANT_ADDRESS)
803 return AMDGPUTargetLowering::LowerGlobalAddress(MFI, Op, DAG);
806 const GlobalValue *GV = GSD->getGlobal();
807 MVT PtrVT = getPointerTy(GSD->getAddressSpace());
809 SDValue Ptr = DAG.getNode(AMDGPUISD::CONST_DATA_PTR, DL, PtrVT);
810 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i32);
812 SDValue PtrLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, Ptr,
813 DAG.getConstant(0, MVT::i32));
814 SDValue PtrHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, Ptr,
815 DAG.getConstant(1, MVT::i32));
817 SDValue Lo = DAG.getNode(ISD::ADDC, DL, DAG.getVTList(MVT::i32, MVT::Glue),
819 SDValue Hi = DAG.getNode(ISD::ADDE, DL, DAG.getVTList(MVT::i32, MVT::Glue),
820 PtrHi, DAG.getConstant(0, MVT::i32),
821 SDValue(Lo.getNode(), 1));
822 return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi);
825 SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
826 SelectionDAG &DAG) const {
827 MachineFunction &MF = DAG.getMachineFunction();
828 const SIRegisterInfo *TRI =
829 static_cast<const SIRegisterInfo*>(MF.getSubtarget().getRegisterInfo());
831 EVT VT = Op.getValueType();
833 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
835 switch (IntrinsicID) {
836 case Intrinsic::r600_read_ngroups_x:
837 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
838 SI::KernelInputOffsets::NGROUPS_X, false);
839 case Intrinsic::r600_read_ngroups_y:
840 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
841 SI::KernelInputOffsets::NGROUPS_Y, false);
842 case Intrinsic::r600_read_ngroups_z:
843 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
844 SI::KernelInputOffsets::NGROUPS_Z, false);
845 case Intrinsic::r600_read_global_size_x:
846 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
847 SI::KernelInputOffsets::GLOBAL_SIZE_X, false);
848 case Intrinsic::r600_read_global_size_y:
849 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
850 SI::KernelInputOffsets::GLOBAL_SIZE_Y, false);
851 case Intrinsic::r600_read_global_size_z:
852 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
853 SI::KernelInputOffsets::GLOBAL_SIZE_Z, false);
854 case Intrinsic::r600_read_local_size_x:
855 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
856 SI::KernelInputOffsets::LOCAL_SIZE_X, false);
857 case Intrinsic::r600_read_local_size_y:
858 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
859 SI::KernelInputOffsets::LOCAL_SIZE_Y, false);
860 case Intrinsic::r600_read_local_size_z:
861 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
862 SI::KernelInputOffsets::LOCAL_SIZE_Z, false);
864 case Intrinsic::AMDGPU_read_workdim:
865 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
866 MF.getInfo<SIMachineFunctionInfo>()->ABIArgOffset,
869 case Intrinsic::r600_read_tgid_x:
870 return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
871 TRI->getPreloadedValue(MF, SIRegisterInfo::TGID_X), VT);
872 case Intrinsic::r600_read_tgid_y:
873 return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
874 TRI->getPreloadedValue(MF, SIRegisterInfo::TGID_Y), VT);
875 case Intrinsic::r600_read_tgid_z:
876 return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
877 TRI->getPreloadedValue(MF, SIRegisterInfo::TGID_Z), VT);
878 case Intrinsic::r600_read_tidig_x:
879 return CreateLiveInRegister(DAG, &AMDGPU::VGPR_32RegClass,
880 TRI->getPreloadedValue(MF, SIRegisterInfo::TIDIG_X), VT);
881 case Intrinsic::r600_read_tidig_y:
882 return CreateLiveInRegister(DAG, &AMDGPU::VGPR_32RegClass,
883 TRI->getPreloadedValue(MF, SIRegisterInfo::TIDIG_Y), VT);
884 case Intrinsic::r600_read_tidig_z:
885 return CreateLiveInRegister(DAG, &AMDGPU::VGPR_32RegClass,
886 TRI->getPreloadedValue(MF, SIRegisterInfo::TIDIG_Z), VT);
887 case AMDGPUIntrinsic::SI_load_const: {
893 MachineMemOperand *MMO = MF.getMachineMemOperand(
894 MachinePointerInfo(),
895 MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant,
896 VT.getStoreSize(), 4);
897 return DAG.getMemIntrinsicNode(AMDGPUISD::LOAD_CONSTANT, DL,
898 Op->getVTList(), Ops, VT, MMO);
900 case AMDGPUIntrinsic::SI_sample:
901 return LowerSampleIntrinsic(AMDGPUISD::SAMPLE, Op, DAG);
902 case AMDGPUIntrinsic::SI_sampleb:
903 return LowerSampleIntrinsic(AMDGPUISD::SAMPLEB, Op, DAG);
904 case AMDGPUIntrinsic::SI_sampled:
905 return LowerSampleIntrinsic(AMDGPUISD::SAMPLED, Op, DAG);
906 case AMDGPUIntrinsic::SI_samplel:
907 return LowerSampleIntrinsic(AMDGPUISD::SAMPLEL, Op, DAG);
908 case AMDGPUIntrinsic::SI_vs_load_input:
909 return DAG.getNode(AMDGPUISD::LOAD_INPUT, DL, VT,
914 return AMDGPUTargetLowering::LowerOperation(Op, DAG);
918 SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue Op,
919 SelectionDAG &DAG) const {
920 MachineFunction &MF = DAG.getMachineFunction();
921 SDValue Chain = Op.getOperand(0);
922 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
924 switch (IntrinsicID) {
925 case AMDGPUIntrinsic::SI_tbuffer_store: {
944 EVT VT = Op.getOperand(3).getValueType();
946 MachineMemOperand *MMO = MF.getMachineMemOperand(
947 MachinePointerInfo(),
948 MachineMemOperand::MOStore,
949 VT.getStoreSize(), 4);
950 return DAG.getMemIntrinsicNode(AMDGPUISD::TBUFFER_STORE_FORMAT, DL,
951 Op->getVTList(), Ops, VT, MMO);
958 SDValue SITargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
960 LoadSDNode *Load = cast<LoadSDNode>(Op);
962 if (Op.getValueType().isVector()) {
963 assert(Op.getValueType().getVectorElementType() == MVT::i32 &&
964 "Custom lowering for non-i32 vectors hasn't been implemented.");
965 unsigned NumElements = Op.getValueType().getVectorNumElements();
966 assert(NumElements != 2 && "v2 loads are supported for all address spaces.");
967 switch (Load->getAddressSpace()) {
969 case AMDGPUAS::GLOBAL_ADDRESS:
970 case AMDGPUAS::PRIVATE_ADDRESS:
971 // v4 loads are supported for private and global memory.
972 if (NumElements <= 4)
975 case AMDGPUAS::LOCAL_ADDRESS:
976 return ScalarizeVectorLoad(Op, DAG);
980 return AMDGPUTargetLowering::LowerLOAD(Op, DAG);
983 SDValue SITargetLowering::LowerSampleIntrinsic(unsigned Opcode,
985 SelectionDAG &DAG) const {
986 return DAG.getNode(Opcode, SDLoc(Op), Op.getValueType(), Op.getOperand(1),
992 SDValue SITargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
993 if (Op.getValueType() != MVT::i64)
997 SDValue Cond = Op.getOperand(0);
999 SDValue Zero = DAG.getConstant(0, MVT::i32);
1000 SDValue One = DAG.getConstant(1, MVT::i32);
1002 SDValue LHS = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, Op.getOperand(1));
1003 SDValue RHS = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, Op.getOperand(2));
1005 SDValue Lo0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, LHS, Zero);
1006 SDValue Lo1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, RHS, Zero);
1008 SDValue Lo = DAG.getSelect(DL, MVT::i32, Cond, Lo0, Lo1);
1010 SDValue Hi0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, LHS, One);
1011 SDValue Hi1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, RHS, One);
1013 SDValue Hi = DAG.getSelect(DL, MVT::i32, Cond, Hi0, Hi1);
1015 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v2i32, Lo, Hi);
1016 return DAG.getNode(ISD::BITCAST, DL, MVT::i64, Res);
1019 // Catch division cases where we can use shortcuts with rcp and rsq
1021 SDValue SITargetLowering::LowerFastFDIV(SDValue Op, SelectionDAG &DAG) const {
1023 SDValue LHS = Op.getOperand(0);
1024 SDValue RHS = Op.getOperand(1);
1025 EVT VT = Op.getValueType();
1026 bool Unsafe = DAG.getTarget().Options.UnsafeFPMath;
1028 if (const ConstantFPSDNode *CLHS = dyn_cast<ConstantFPSDNode>(LHS)) {
1029 if ((Unsafe || (VT == MVT::f32 && !Subtarget->hasFP32Denormals())) &&
1030 CLHS->isExactlyValue(1.0)) {
1031 // v_rcp_f32 and v_rsq_f32 do not support denormals, and according to
1032 // the CI documentation has a worst case error of 1 ulp.
1033 // OpenCL requires <= 2.5 ulp for 1.0 / x, so it should always be OK to
1034 // use it as long as we aren't trying to use denormals.
1036 // 1.0 / sqrt(x) -> rsq(x)
1038 // XXX - Is UnsafeFPMath sufficient to do this for f64? The maximum ULP
1039 // error seems really high at 2^29 ULP.
1040 if (RHS.getOpcode() == ISD::FSQRT)
1041 return DAG.getNode(AMDGPUISD::RSQ, SL, VT, RHS.getOperand(0));
1043 // 1.0 / x -> rcp(x)
1044 return DAG.getNode(AMDGPUISD::RCP, SL, VT, RHS);
1049 // Turn into multiply by the reciprocal.
1050 // x / y -> x * (1.0 / y)
1051 SDValue Recip = DAG.getNode(AMDGPUISD::RCP, SL, VT, RHS);
1052 return DAG.getNode(ISD::FMUL, SL, VT, LHS, Recip);
1058 SDValue SITargetLowering::LowerFDIV32(SDValue Op, SelectionDAG &DAG) const {
1059 SDValue FastLowered = LowerFastFDIV(Op, DAG);
1060 if (FastLowered.getNode())
1063 // This uses v_rcp_f32 which does not handle denormals. Let this hit a
1064 // selection error for now rather than do something incorrect.
1065 if (Subtarget->hasFP32Denormals())
1069 SDValue LHS = Op.getOperand(0);
1070 SDValue RHS = Op.getOperand(1);
1072 SDValue r1 = DAG.getNode(ISD::FABS, SL, MVT::f32, RHS);
1074 const APFloat K0Val(BitsToFloat(0x6f800000));
1075 const SDValue K0 = DAG.getConstantFP(K0Val, MVT::f32);
1077 const APFloat K1Val(BitsToFloat(0x2f800000));
1078 const SDValue K1 = DAG.getConstantFP(K1Val, MVT::f32);
1080 const SDValue One = DAG.getTargetConstantFP(1.0, MVT::f32);
1082 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::f32);
1084 SDValue r2 = DAG.getSetCC(SL, SetCCVT, r1, K0, ISD::SETOGT);
1086 SDValue r3 = DAG.getNode(ISD::SELECT, SL, MVT::f32, r2, K1, One);
1088 r1 = DAG.getNode(ISD::FMUL, SL, MVT::f32, RHS, r3);
1090 SDValue r0 = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f32, r1);
1092 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f32, LHS, r0);
1094 return DAG.getNode(ISD::FMUL, SL, MVT::f32, r3, Mul);
1097 SDValue SITargetLowering::LowerFDIV64(SDValue Op, SelectionDAG &DAG) const {
1101 SDValue SITargetLowering::LowerFDIV(SDValue Op, SelectionDAG &DAG) const {
1102 EVT VT = Op.getValueType();
1105 return LowerFDIV32(Op, DAG);
1108 return LowerFDIV64(Op, DAG);
1110 llvm_unreachable("Unexpected type for fdiv");
1113 SDValue SITargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1115 StoreSDNode *Store = cast<StoreSDNode>(Op);
1116 EVT VT = Store->getMemoryVT();
1118 // These stores are legal.
1119 if (Store->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS &&
1120 VT.isVector() && VT.getVectorNumElements() == 2 &&
1121 VT.getVectorElementType() == MVT::i32)
1124 if (Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS) {
1125 if (VT.isVector() && VT.getVectorNumElements() > 4)
1126 return ScalarizeVectorStore(Op, DAG);
1130 SDValue Ret = AMDGPUTargetLowering::LowerSTORE(Op, DAG);
1134 if (VT.isVector() && VT.getVectorNumElements() >= 8)
1135 return ScalarizeVectorStore(Op, DAG);
1138 return DAG.getTruncStore(Store->getChain(), DL,
1139 DAG.getSExtOrTrunc(Store->getValue(), DL, MVT::i32),
1140 Store->getBasePtr(), MVT::i1, Store->getMemOperand());
1145 SDValue SITargetLowering::LowerTrig(SDValue Op, SelectionDAG &DAG) const {
1146 EVT VT = Op.getValueType();
1147 SDValue Arg = Op.getOperand(0);
1148 SDValue FractPart = DAG.getNode(AMDGPUISD::FRACT, SDLoc(Op), VT,
1149 DAG.getNode(ISD::FMUL, SDLoc(Op), VT, Arg,
1150 DAG.getConstantFP(0.5 / M_PI, VT)));
1152 switch (Op.getOpcode()) {
1154 return DAG.getNode(AMDGPUISD::COS_HW, SDLoc(Op), VT, FractPart);
1156 return DAG.getNode(AMDGPUISD::SIN_HW, SDLoc(Op), VT, FractPart);
1158 llvm_unreachable("Wrong trig opcode");
1162 //===----------------------------------------------------------------------===//
1163 // Custom DAG optimizations
1164 //===----------------------------------------------------------------------===//
1166 SDValue SITargetLowering::performUCharToFloatCombine(SDNode *N,
1167 DAGCombinerInfo &DCI) {
1168 EVT VT = N->getValueType(0);
1169 EVT ScalarVT = VT.getScalarType();
1170 if (ScalarVT != MVT::f32)
1173 SelectionDAG &DAG = DCI.DAG;
1176 SDValue Src = N->getOperand(0);
1177 EVT SrcVT = Src.getValueType();
1179 // TODO: We could try to match extracting the higher bytes, which would be
1180 // easier if i8 vectors weren't promoted to i32 vectors, particularly after
1181 // types are legalized. v4i8 -> v4f32 is probably the only case to worry
1182 // about in practice.
1183 if (DCI.isAfterLegalizeVectorOps() && SrcVT == MVT::i32) {
1184 if (DAG.MaskedValueIsZero(Src, APInt::getHighBitsSet(32, 24))) {
1185 SDValue Cvt = DAG.getNode(AMDGPUISD::CVT_F32_UBYTE0, DL, VT, Src);
1186 DCI.AddToWorklist(Cvt.getNode());
1191 // We are primarily trying to catch operations on illegal vector types
1192 // before they are expanded.
1193 // For scalars, we can use the more flexible method of checking masked bits
1194 // after legalization.
1195 if (!DCI.isBeforeLegalize() ||
1196 !SrcVT.isVector() ||
1197 SrcVT.getVectorElementType() != MVT::i8) {
1201 assert(DCI.isBeforeLegalize() && "Unexpected legal type");
1203 // Weird sized vectors are a pain to handle, but we know 3 is really the same
1205 unsigned NElts = SrcVT.getVectorNumElements();
1206 if (!SrcVT.isSimple() && NElts != 3)
1209 // Handle v4i8 -> v4f32 extload. Replace the v4i8 with a legal i32 load to
1210 // prevent a mess from expanding to v4i32 and repacking.
1211 if (ISD::isNormalLoad(Src.getNode()) && Src.hasOneUse()) {
1212 EVT LoadVT = getEquivalentMemType(*DAG.getContext(), SrcVT);
1213 EVT RegVT = getEquivalentLoadRegType(*DAG.getContext(), SrcVT);
1214 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f32, NElts);
1216 LoadSDNode *Load = cast<LoadSDNode>(Src);
1217 SDValue NewLoad = DAG.getExtLoad(ISD::ZEXTLOAD, DL, RegVT,
1221 Load->getMemOperand());
1223 // Make sure successors of the original load stay after it by updating
1224 // them to use the new Chain.
1225 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), NewLoad.getValue(1));
1227 SmallVector<SDValue, 4> Elts;
1228 if (RegVT.isVector())
1229 DAG.ExtractVectorElements(NewLoad, Elts);
1231 Elts.push_back(NewLoad);
1233 SmallVector<SDValue, 4> Ops;
1235 unsigned EltIdx = 0;
1236 for (SDValue Elt : Elts) {
1237 unsigned ComponentsInElt = std::min(4u, NElts - 4 * EltIdx);
1238 for (unsigned I = 0; I < ComponentsInElt; ++I) {
1239 unsigned Opc = AMDGPUISD::CVT_F32_UBYTE0 + I;
1240 SDValue Cvt = DAG.getNode(Opc, DL, MVT::f32, Elt);
1241 DCI.AddToWorklist(Cvt.getNode());
1248 assert(Ops.size() == NElts);
1250 return DAG.getNode(ISD::BUILD_VECTOR, DL, FloatVT, Ops);
1256 // (shl (add x, c1), c2) -> add (shl x, c2), (shl c1, c2)
1258 // This is a variant of
1259 // (mul (add x, c1), c2) -> add (mul x, c2), (mul c1, c2),
1261 // The normal DAG combiner will do this, but only if the add has one use since
1262 // that would increase the number of instructions.
1264 // This prevents us from seeing a constant offset that can be folded into a
1265 // memory instruction's addressing mode. If we know the resulting add offset of
1266 // a pointer can be folded into an addressing offset, we can replace the pointer
1267 // operand with the add of new constant offset. This eliminates one of the uses,
1268 // and may allow the remaining use to also be simplified.
1270 SDValue SITargetLowering::performSHLPtrCombine(SDNode *N,
1272 DAGCombinerInfo &DCI) const {
1273 SDValue N0 = N->getOperand(0);
1274 SDValue N1 = N->getOperand(1);
1276 if (N0.getOpcode() != ISD::ADD)
1279 const ConstantSDNode *CN1 = dyn_cast<ConstantSDNode>(N1);
1283 const ConstantSDNode *CAdd = dyn_cast<ConstantSDNode>(N0.getOperand(1));
1287 const SIInstrInfo *TII = static_cast<const SIInstrInfo *>(
1288 getTargetMachine().getSubtargetImpl()->getInstrInfo());
1290 // If the resulting offset is too large, we can't fold it into the addressing
1292 APInt Offset = CAdd->getAPIntValue() << CN1->getAPIntValue();
1293 if (!TII->canFoldOffset(Offset.getZExtValue(), AddrSpace))
1296 SelectionDAG &DAG = DCI.DAG;
1298 EVT VT = N->getValueType(0);
1300 SDValue ShlX = DAG.getNode(ISD::SHL, SL, VT, N0.getOperand(0), N1);
1301 SDValue COffset = DAG.getConstant(Offset, MVT::i32);
1303 return DAG.getNode(ISD::ADD, SL, VT, ShlX, COffset);
1306 SDValue SITargetLowering::performAndCombine(SDNode *N,
1307 DAGCombinerInfo &DCI) const {
1308 if (DCI.isBeforeLegalize())
1311 SelectionDAG &DAG = DCI.DAG;
1313 // (and (fcmp ord x, x), (fcmp une (fabs x), inf)) ->
1314 // fp_class x, ~(s_nan | q_nan | n_infinity | p_infinity)
1315 SDValue LHS = N->getOperand(0);
1316 SDValue RHS = N->getOperand(1);
1318 if (LHS.getOpcode() == ISD::SETCC &&
1319 RHS.getOpcode() == ISD::SETCC) {
1320 ISD::CondCode LCC = cast<CondCodeSDNode>(LHS.getOperand(2))->get();
1321 ISD::CondCode RCC = cast<CondCodeSDNode>(RHS.getOperand(2))->get();
1323 SDValue X = LHS.getOperand(0);
1324 SDValue Y = RHS.getOperand(0);
1325 if (Y.getOpcode() != ISD::FABS || Y.getOperand(0) != X)
1328 if (LCC == ISD::SETO) {
1329 if (X != LHS.getOperand(1))
1332 if (RCC == ISD::SETUNE) {
1333 const ConstantFPSDNode *C1 = dyn_cast<ConstantFPSDNode>(RHS.getOperand(1));
1334 if (!C1 || !C1->isInfinity() || C1->isNegative())
1337 const uint32_t Mask = SIInstrFlags::N_NORMAL |
1338 SIInstrFlags::N_SUBNORMAL |
1339 SIInstrFlags::N_ZERO |
1340 SIInstrFlags::P_ZERO |
1341 SIInstrFlags::P_SUBNORMAL |
1342 SIInstrFlags::P_NORMAL;
1344 static_assert(((~(SIInstrFlags::S_NAN |
1345 SIInstrFlags::Q_NAN |
1346 SIInstrFlags::N_INFINITY |
1347 SIInstrFlags::P_INFINITY)) & 0x3ff) == Mask,
1350 return DAG.getNode(AMDGPUISD::FP_CLASS, SDLoc(N), MVT::i1,
1351 X, DAG.getConstant(Mask, MVT::i32));
1359 SDValue SITargetLowering::performOrCombine(SDNode *N,
1360 DAGCombinerInfo &DCI) const {
1361 SelectionDAG &DAG = DCI.DAG;
1362 SDValue LHS = N->getOperand(0);
1363 SDValue RHS = N->getOperand(1);
1365 // or (fp_class x, c1), (fp_class x, c2) -> fp_class x, (c1 | c2)
1366 if (LHS.getOpcode() == AMDGPUISD::FP_CLASS &&
1367 RHS.getOpcode() == AMDGPUISD::FP_CLASS) {
1368 SDValue Src = LHS.getOperand(0);
1369 if (Src != RHS.getOperand(0))
1372 const ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(LHS.getOperand(1));
1373 const ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(RHS.getOperand(1));
1377 // Only 10 bits are used.
1378 static const uint32_t MaxMask = 0x3ff;
1380 uint32_t NewMask = (CLHS->getZExtValue() | CRHS->getZExtValue()) & MaxMask;
1381 return DAG.getNode(AMDGPUISD::FP_CLASS, SDLoc(N), MVT::i1,
1382 Src, DAG.getConstant(NewMask, MVT::i32));
1388 SDValue SITargetLowering::performClassCombine(SDNode *N,
1389 DAGCombinerInfo &DCI) const {
1390 SelectionDAG &DAG = DCI.DAG;
1391 SDValue Mask = N->getOperand(1);
1393 // fp_class x, 0 -> false
1394 if (const ConstantSDNode *CMask = dyn_cast<ConstantSDNode>(Mask)) {
1395 if (CMask->isNullValue())
1396 return DAG.getConstant(0, MVT::i1);
1402 static unsigned minMaxOpcToMin3Max3Opc(unsigned Opc) {
1405 return AMDGPUISD::FMAX3;
1406 case AMDGPUISD::SMAX:
1407 return AMDGPUISD::SMAX3;
1408 case AMDGPUISD::UMAX:
1409 return AMDGPUISD::UMAX3;
1411 return AMDGPUISD::FMIN3;
1412 case AMDGPUISD::SMIN:
1413 return AMDGPUISD::SMIN3;
1414 case AMDGPUISD::UMIN:
1415 return AMDGPUISD::UMIN3;
1417 llvm_unreachable("Not a min/max opcode");
1421 SDValue SITargetLowering::performMin3Max3Combine(SDNode *N,
1422 DAGCombinerInfo &DCI) const {
1423 SelectionDAG &DAG = DCI.DAG;
1425 unsigned Opc = N->getOpcode();
1426 SDValue Op0 = N->getOperand(0);
1427 SDValue Op1 = N->getOperand(1);
1429 // Only do this if the inner op has one use since this will just increases
1430 // register pressure for no benefit.
1432 // max(max(a, b), c)
1433 if (Op0.getOpcode() == Opc && Op0.hasOneUse()) {
1435 return DAG.getNode(minMaxOpcToMin3Max3Opc(Opc),
1443 // max(a, max(b, c))
1444 if (Op1.getOpcode() == Opc && Op1.hasOneUse()) {
1446 return DAG.getNode(minMaxOpcToMin3Max3Opc(Opc),
1457 SDValue SITargetLowering::performSetCCCombine(SDNode *N,
1458 DAGCombinerInfo &DCI) const {
1459 SelectionDAG &DAG = DCI.DAG;
1462 SDValue LHS = N->getOperand(0);
1463 SDValue RHS = N->getOperand(1);
1464 EVT VT = LHS.getValueType();
1466 if (VT != MVT::f32 && VT != MVT::f64)
1469 // Match isinf pattern
1470 // (fcmp oeq (fabs x), inf) -> (fp_class x, (p_infinity | n_infinity))
1471 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
1472 if (CC == ISD::SETOEQ && LHS.getOpcode() == ISD::FABS) {
1473 const ConstantFPSDNode *CRHS = dyn_cast<ConstantFPSDNode>(RHS);
1477 const APFloat &APF = CRHS->getValueAPF();
1478 if (APF.isInfinity() && !APF.isNegative()) {
1479 unsigned Mask = SIInstrFlags::P_INFINITY | SIInstrFlags::N_INFINITY;
1480 return DAG.getNode(AMDGPUISD::FP_CLASS, SL, MVT::i1,
1481 LHS.getOperand(0), DAG.getConstant(Mask, MVT::i32));
1488 SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
1489 DAGCombinerInfo &DCI) const {
1490 SelectionDAG &DAG = DCI.DAG;
1493 switch (N->getOpcode()) {
1495 return AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
1497 return performSetCCCombine(N, DCI);
1498 case ISD::FMAXNUM: // TODO: What about fmax_legacy?
1500 case AMDGPUISD::SMAX:
1501 case AMDGPUISD::SMIN:
1502 case AMDGPUISD::UMAX:
1503 case AMDGPUISD::UMIN: {
1504 if (DCI.getDAGCombineLevel() >= AfterLegalizeDAG &&
1505 getTargetMachine().getOptLevel() > CodeGenOpt::None)
1506 return performMin3Max3Combine(N, DCI);
1510 case AMDGPUISD::CVT_F32_UBYTE0:
1511 case AMDGPUISD::CVT_F32_UBYTE1:
1512 case AMDGPUISD::CVT_F32_UBYTE2:
1513 case AMDGPUISD::CVT_F32_UBYTE3: {
1514 unsigned Offset = N->getOpcode() - AMDGPUISD::CVT_F32_UBYTE0;
1516 SDValue Src = N->getOperand(0);
1517 APInt Demanded = APInt::getBitsSet(32, 8 * Offset, 8 * Offset + 8);
1519 APInt KnownZero, KnownOne;
1520 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
1521 !DCI.isBeforeLegalizeOps());
1522 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1523 if (TLO.ShrinkDemandedConstant(Src, Demanded) ||
1524 TLI.SimplifyDemandedBits(Src, Demanded, KnownZero, KnownOne, TLO)) {
1525 DCI.CommitTargetLoweringOpt(TLO);
1531 case ISD::UINT_TO_FP: {
1532 return performUCharToFloatCombine(N, DCI);
1535 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG)
1538 EVT VT = N->getValueType(0);
1542 SDValue LHS = N->getOperand(0);
1543 SDValue RHS = N->getOperand(1);
1545 // These should really be instruction patterns, but writing patterns with
1546 // source modiifiers is a pain.
1548 // fadd (fadd (a, a), b) -> mad 2.0, a, b
1549 if (LHS.getOpcode() == ISD::FADD) {
1550 SDValue A = LHS.getOperand(0);
1551 if (A == LHS.getOperand(1)) {
1552 const SDValue Two = DAG.getTargetConstantFP(2.0, MVT::f32);
1553 return DAG.getNode(AMDGPUISD::MAD, DL, VT, Two, A, RHS);
1557 // fadd (b, fadd (a, a)) -> mad 2.0, a, b
1558 if (RHS.getOpcode() == ISD::FADD) {
1559 SDValue A = RHS.getOperand(0);
1560 if (A == RHS.getOperand(1)) {
1561 const SDValue Two = DAG.getTargetConstantFP(2.0, MVT::f32);
1562 return DAG.getNode(AMDGPUISD::MAD, DL, VT, Two, A, LHS);
1569 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG)
1572 EVT VT = N->getValueType(0);
1574 // Try to get the fneg to fold into the source modifier. This undoes generic
1575 // DAG combines and folds them into the mad.
1576 if (VT == MVT::f32) {
1577 SDValue LHS = N->getOperand(0);
1578 SDValue RHS = N->getOperand(1);
1580 if (LHS.getOpcode() == ISD::FMUL) {
1581 // (fsub (fmul a, b), c) -> mad a, b, (fneg c)
1583 SDValue A = LHS.getOperand(0);
1584 SDValue B = LHS.getOperand(1);
1585 SDValue C = DAG.getNode(ISD::FNEG, DL, VT, RHS);
1587 return DAG.getNode(AMDGPUISD::MAD, DL, VT, A, B, C);
1590 if (RHS.getOpcode() == ISD::FMUL) {
1591 // (fsub c, (fmul a, b)) -> mad (fneg a), b, c
1593 SDValue A = DAG.getNode(ISD::FNEG, DL, VT, RHS.getOperand(0));
1594 SDValue B = RHS.getOperand(1);
1597 return DAG.getNode(AMDGPUISD::MAD, DL, VT, A, B, C);
1600 if (LHS.getOpcode() == ISD::FADD) {
1601 // (fsub (fadd a, a), c) -> mad 2.0, a, (fneg c)
1603 SDValue A = LHS.getOperand(0);
1604 if (A == LHS.getOperand(1)) {
1605 const SDValue Two = DAG.getTargetConstantFP(2.0, MVT::f32);
1606 SDValue NegRHS = DAG.getNode(ISD::FNEG, DL, VT, RHS);
1608 return DAG.getNode(AMDGPUISD::MAD, DL, VT, Two, A, NegRHS);
1612 if (RHS.getOpcode() == ISD::FADD) {
1613 // (fsub c, (fadd a, a)) -> mad -2.0, a, c
1615 SDValue A = RHS.getOperand(0);
1616 if (A == RHS.getOperand(1)) {
1617 const SDValue NegTwo = DAG.getTargetConstantFP(-2.0, MVT::f32);
1618 return DAG.getNode(AMDGPUISD::MAD, DL, VT, NegTwo, A, LHS);
1628 case ISD::ATOMIC_LOAD:
1629 case ISD::ATOMIC_STORE:
1630 case ISD::ATOMIC_CMP_SWAP:
1631 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
1632 case ISD::ATOMIC_SWAP:
1633 case ISD::ATOMIC_LOAD_ADD:
1634 case ISD::ATOMIC_LOAD_SUB:
1635 case ISD::ATOMIC_LOAD_AND:
1636 case ISD::ATOMIC_LOAD_OR:
1637 case ISD::ATOMIC_LOAD_XOR:
1638 case ISD::ATOMIC_LOAD_NAND:
1639 case ISD::ATOMIC_LOAD_MIN:
1640 case ISD::ATOMIC_LOAD_MAX:
1641 case ISD::ATOMIC_LOAD_UMIN:
1642 case ISD::ATOMIC_LOAD_UMAX: { // TODO: Target mem intrinsics.
1643 if (DCI.isBeforeLegalize())
1646 MemSDNode *MemNode = cast<MemSDNode>(N);
1647 SDValue Ptr = MemNode->getBasePtr();
1649 // TODO: We could also do this for multiplies.
1650 unsigned AS = MemNode->getAddressSpace();
1651 if (Ptr.getOpcode() == ISD::SHL && AS != AMDGPUAS::PRIVATE_ADDRESS) {
1652 SDValue NewPtr = performSHLPtrCombine(Ptr.getNode(), AS, DCI);
1654 SmallVector<SDValue, 8> NewOps;
1655 for (unsigned I = 0, E = MemNode->getNumOperands(); I != E; ++I)
1656 NewOps.push_back(MemNode->getOperand(I));
1658 NewOps[N->getOpcode() == ISD::STORE ? 2 : 1] = NewPtr;
1659 return SDValue(DAG.UpdateNodeOperands(MemNode, NewOps), 0);
1665 return performAndCombine(N, DCI);
1667 return performOrCombine(N, DCI);
1668 case AMDGPUISD::FP_CLASS:
1669 return performClassCombine(N, DCI);
1671 return AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
1674 /// \brief Test if RegClass is one of the VSrc classes
1675 static bool isVSrc(unsigned RegClass) {
1677 default: return false;
1678 case AMDGPU::VS_32RegClassID:
1679 case AMDGPU::VS_64RegClassID:
1684 /// \brief Analyze the possible immediate value Op
1686 /// Returns -1 if it isn't an immediate, 0 if it's and inline immediate
1687 /// and the immediate value if it's a literal immediate
1688 int32_t SITargetLowering::analyzeImmediate(const SDNode *N) const {
1690 const SIInstrInfo *TII = static_cast<const SIInstrInfo *>(
1691 getTargetMachine().getSubtargetImpl()->getInstrInfo());
1693 if (const ConstantSDNode *Node = dyn_cast<ConstantSDNode>(N)) {
1694 if (Node->getZExtValue() >> 32)
1697 if (TII->isInlineConstant(Node->getAPIntValue()))
1700 return Node->getZExtValue();
1703 if (const ConstantFPSDNode *Node = dyn_cast<ConstantFPSDNode>(N)) {
1704 if (TII->isInlineConstant(Node->getValueAPF().bitcastToAPInt()))
1707 if (Node->getValueType(0) == MVT::f32)
1708 return FloatToBits(Node->getValueAPF().convertToFloat());
1716 const TargetRegisterClass *SITargetLowering::getRegClassForNode(
1717 SelectionDAG &DAG, const SDValue &Op) const {
1718 const SIInstrInfo *TII = static_cast<const SIInstrInfo *>(
1719 getTargetMachine().getSubtargetImpl()->getInstrInfo());
1720 const SIRegisterInfo &TRI = TII->getRegisterInfo();
1722 if (!Op->isMachineOpcode()) {
1723 switch(Op->getOpcode()) {
1724 case ISD::CopyFromReg: {
1725 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1726 unsigned Reg = cast<RegisterSDNode>(Op->getOperand(1))->getReg();
1727 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
1728 return MRI.getRegClass(Reg);
1730 return TRI.getPhysRegClass(Reg);
1732 default: return nullptr;
1735 const MCInstrDesc &Desc = TII->get(Op->getMachineOpcode());
1736 int OpClassID = Desc.OpInfo[Op.getResNo()].RegClass;
1737 if (OpClassID != -1) {
1738 return TRI.getRegClass(OpClassID);
1740 switch(Op.getMachineOpcode()) {
1741 case AMDGPU::COPY_TO_REGCLASS:
1742 // Operand 1 is the register class id for COPY_TO_REGCLASS instructions.
1743 OpClassID = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
1745 // If the COPY_TO_REGCLASS instruction is copying to a VSrc register
1746 // class, then the register class for the value could be either a
1747 // VReg or and SReg. In order to get a more accurate
1748 if (isVSrc(OpClassID))
1749 return getRegClassForNode(DAG, Op.getOperand(0));
1751 return TRI.getRegClass(OpClassID);
1752 case AMDGPU::EXTRACT_SUBREG: {
1753 int SubIdx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
1754 const TargetRegisterClass *SuperClass =
1755 getRegClassForNode(DAG, Op.getOperand(0));
1756 return TRI.getSubClassWithSubReg(SuperClass, SubIdx);
1758 case AMDGPU::REG_SEQUENCE:
1759 // Operand 0 is the register class id for REG_SEQUENCE instructions.
1760 return TRI.getRegClass(
1761 cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue());
1763 return getRegClassFor(Op.getSimpleValueType());
1767 /// \brief Does "Op" fit into register class "RegClass" ?
1768 bool SITargetLowering::fitsRegClass(SelectionDAG &DAG, const SDValue &Op,
1769 unsigned RegClass) const {
1770 const TargetRegisterInfo *TRI =
1771 getTargetMachine().getSubtargetImpl()->getRegisterInfo();
1772 const TargetRegisterClass *RC = getRegClassForNode(DAG, Op);
1776 return TRI->getRegClass(RegClass)->hasSubClassEq(RC);
1779 /// \brief Helper function for adjustWritemask
1780 static unsigned SubIdx2Lane(unsigned Idx) {
1783 case AMDGPU::sub0: return 0;
1784 case AMDGPU::sub1: return 1;
1785 case AMDGPU::sub2: return 2;
1786 case AMDGPU::sub3: return 3;
1790 /// \brief Adjust the writemask of MIMG instructions
1791 void SITargetLowering::adjustWritemask(MachineSDNode *&Node,
1792 SelectionDAG &DAG) const {
1793 SDNode *Users[4] = { };
1795 unsigned OldDmask = Node->getConstantOperandVal(0);
1796 unsigned NewDmask = 0;
1798 // Try to figure out the used register components
1799 for (SDNode::use_iterator I = Node->use_begin(), E = Node->use_end();
1802 // Abort if we can't understand the usage
1803 if (!I->isMachineOpcode() ||
1804 I->getMachineOpcode() != TargetOpcode::EXTRACT_SUBREG)
1807 // Lane means which subreg of %VGPRa_VGPRb_VGPRc_VGPRd is used.
1808 // Note that subregs are packed, i.e. Lane==0 is the first bit set
1809 // in OldDmask, so it can be any of X,Y,Z,W; Lane==1 is the second bit
1811 Lane = SubIdx2Lane(I->getConstantOperandVal(1));
1813 // Set which texture component corresponds to the lane.
1815 for (unsigned i = 0, Dmask = OldDmask; i <= Lane; i++) {
1817 Comp = countTrailingZeros(Dmask);
1818 Dmask &= ~(1 << Comp);
1821 // Abort if we have more than one user per component
1826 NewDmask |= 1 << Comp;
1829 // Abort if there's no change
1830 if (NewDmask == OldDmask)
1833 // Adjust the writemask in the node
1834 std::vector<SDValue> Ops;
1835 Ops.push_back(DAG.getTargetConstant(NewDmask, MVT::i32));
1836 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i)
1837 Ops.push_back(Node->getOperand(i));
1838 Node = (MachineSDNode*)DAG.UpdateNodeOperands(Node, Ops);
1840 // If we only got one lane, replace it with a copy
1841 // (if NewDmask has only one bit set...)
1842 if (NewDmask && (NewDmask & (NewDmask-1)) == 0) {
1843 SDValue RC = DAG.getTargetConstant(AMDGPU::VGPR_32RegClassID, MVT::i32);
1844 SDNode *Copy = DAG.getMachineNode(TargetOpcode::COPY_TO_REGCLASS,
1845 SDLoc(), Users[Lane]->getValueType(0),
1846 SDValue(Node, 0), RC);
1847 DAG.ReplaceAllUsesWith(Users[Lane], Copy);
1851 // Update the users of the node with the new indices
1852 for (unsigned i = 0, Idx = AMDGPU::sub0; i < 4; ++i) {
1854 SDNode *User = Users[i];
1858 SDValue Op = DAG.getTargetConstant(Idx, MVT::i32);
1859 DAG.UpdateNodeOperands(User, User->getOperand(0), Op);
1863 case AMDGPU::sub0: Idx = AMDGPU::sub1; break;
1864 case AMDGPU::sub1: Idx = AMDGPU::sub2; break;
1865 case AMDGPU::sub2: Idx = AMDGPU::sub3; break;
1870 /// \brief Legalize target independent instructions (e.g. INSERT_SUBREG)
1871 /// with frame index operands.
1872 /// LLVM assumes that inputs are to these instructions are registers.
1873 void SITargetLowering::legalizeTargetIndependentNode(SDNode *Node,
1874 SelectionDAG &DAG) const {
1876 SmallVector<SDValue, 8> Ops;
1877 for (unsigned i = 0; i < Node->getNumOperands(); ++i) {
1878 if (!isa<FrameIndexSDNode>(Node->getOperand(i))) {
1879 Ops.push_back(Node->getOperand(i));
1884 Ops.push_back(SDValue(DAG.getMachineNode(AMDGPU::S_MOV_B32, DL,
1885 Node->getOperand(i).getValueType(),
1886 Node->getOperand(i)), 0));
1889 DAG.UpdateNodeOperands(Node, Ops);
1892 /// \brief Fold the instructions after selecting them.
1893 SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node,
1894 SelectionDAG &DAG) const {
1895 const SIInstrInfo *TII = static_cast<const SIInstrInfo *>(
1896 getTargetMachine().getSubtargetImpl()->getInstrInfo());
1897 Node = AdjustRegClass(Node, DAG);
1899 if (TII->isMIMG(Node->getMachineOpcode()))
1900 adjustWritemask(Node, DAG);
1902 if (Node->getMachineOpcode() == AMDGPU::INSERT_SUBREG ||
1903 Node->getMachineOpcode() == AMDGPU::REG_SEQUENCE) {
1904 legalizeTargetIndependentNode(Node, DAG);
1910 /// \brief Assign the register class depending on the number of
1911 /// bits set in the writemask
1912 void SITargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
1913 SDNode *Node) const {
1914 const SIInstrInfo *TII = static_cast<const SIInstrInfo *>(
1915 getTargetMachine().getSubtargetImpl()->getInstrInfo());
1917 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1918 TII->legalizeOperands(MI);
1920 if (TII->isMIMG(MI->getOpcode())) {
1921 unsigned VReg = MI->getOperand(0).getReg();
1922 unsigned Writemask = MI->getOperand(1).getImm();
1923 unsigned BitsSet = 0;
1924 for (unsigned i = 0; i < 4; ++i)
1925 BitsSet += Writemask & (1 << i) ? 1 : 0;
1927 const TargetRegisterClass *RC;
1930 case 1: RC = &AMDGPU::VGPR_32RegClass; break;
1931 case 2: RC = &AMDGPU::VReg_64RegClass; break;
1932 case 3: RC = &AMDGPU::VReg_96RegClass; break;
1935 unsigned NewOpcode = TII->getMaskedMIMGOp(MI->getOpcode(), BitsSet);
1936 MI->setDesc(TII->get(NewOpcode));
1937 MRI.setRegClass(VReg, RC);
1941 // Replace unused atomics with the no return version.
1942 int NoRetAtomicOp = AMDGPU::getAtomicNoRetOp(MI->getOpcode());
1943 if (NoRetAtomicOp != -1) {
1944 if (!Node->hasAnyUseOfValue(0)) {
1945 MI->setDesc(TII->get(NoRetAtomicOp));
1946 MI->RemoveOperand(0);
1953 static SDValue buildSMovImm32(SelectionDAG &DAG, SDLoc DL, uint64_t Val) {
1954 SDValue K = DAG.getTargetConstant(Val, MVT::i32);
1955 return SDValue(DAG.getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32, K), 0);
1958 MachineSDNode *SITargetLowering::wrapAddr64Rsrc(SelectionDAG &DAG,
1960 SDValue Ptr) const {
1961 const SIInstrInfo *TII = static_cast<const SIInstrInfo *>(
1962 getTargetMachine().getSubtargetImpl()->getInstrInfo());
1964 // XXX - Workaround for moveToVALU not handling different register class
1965 // inserts for REG_SEQUENCE.
1967 // Build the half of the subregister with the constants.
1968 const SDValue Ops0[] = {
1969 DAG.getTargetConstant(AMDGPU::SGPR_64RegClassID, MVT::i32),
1970 buildSMovImm32(DAG, DL, 0),
1971 DAG.getTargetConstant(AMDGPU::sub0, MVT::i32),
1972 buildSMovImm32(DAG, DL, TII->getDefaultRsrcDataFormat() >> 32),
1973 DAG.getTargetConstant(AMDGPU::sub1, MVT::i32)
1976 SDValue SubRegHi = SDValue(DAG.getMachineNode(AMDGPU::REG_SEQUENCE, DL,
1977 MVT::v2i32, Ops0), 0);
1979 // Combine the constants and the pointer.
1980 const SDValue Ops1[] = {
1981 DAG.getTargetConstant(AMDGPU::SReg_128RegClassID, MVT::i32),
1983 DAG.getTargetConstant(AMDGPU::sub0_sub1, MVT::i32),
1985 DAG.getTargetConstant(AMDGPU::sub2_sub3, MVT::i32)
1988 return DAG.getMachineNode(AMDGPU::REG_SEQUENCE, DL, MVT::v4i32, Ops1);
1990 const SDValue Ops[] = {
1991 DAG.getTargetConstant(AMDGPU::SReg_128RegClassID, MVT::i32),
1993 DAG.getTargetConstant(AMDGPU::sub0_sub1, MVT::i32),
1994 buildSMovImm32(DAG, DL, 0),
1995 DAG.getTargetConstant(AMDGPU::sub2, MVT::i32),
1996 buildSMovImm32(DAG, DL, TII->getDefaultRsrcFormat() >> 32),
1997 DAG.getTargetConstant(AMDGPU::sub3, MVT::i32)
2000 return DAG.getMachineNode(AMDGPU::REG_SEQUENCE, DL, MVT::v4i32, Ops);
2005 /// \brief Return a resource descriptor with the 'Add TID' bit enabled
2006 /// The TID (Thread ID) is multipled by the stride value (bits [61:48]
2007 /// of the resource descriptor) to create an offset, which is added to the
2008 /// resource ponter.
2009 MachineSDNode *SITargetLowering::buildRSRC(SelectionDAG &DAG,
2012 uint32_t RsrcDword1,
2013 uint64_t RsrcDword2And3) const {
2014 SDValue PtrLo = DAG.getTargetExtractSubreg(AMDGPU::sub0, DL, MVT::i32, Ptr);
2015 SDValue PtrHi = DAG.getTargetExtractSubreg(AMDGPU::sub1, DL, MVT::i32, Ptr);
2017 PtrHi = SDValue(DAG.getMachineNode(AMDGPU::S_OR_B32, DL, MVT::i32, PtrHi,
2018 DAG.getConstant(RsrcDword1, MVT::i32)), 0);
2021 SDValue DataLo = buildSMovImm32(DAG, DL,
2022 RsrcDword2And3 & UINT64_C(0xFFFFFFFF));
2023 SDValue DataHi = buildSMovImm32(DAG, DL, RsrcDword2And3 >> 32);
2025 const SDValue Ops[] = {
2026 DAG.getTargetConstant(AMDGPU::SReg_128RegClassID, MVT::i32),
2028 DAG.getTargetConstant(AMDGPU::sub0, MVT::i32),
2030 DAG.getTargetConstant(AMDGPU::sub1, MVT::i32),
2032 DAG.getTargetConstant(AMDGPU::sub2, MVT::i32),
2034 DAG.getTargetConstant(AMDGPU::sub3, MVT::i32)
2037 return DAG.getMachineNode(AMDGPU::REG_SEQUENCE, DL, MVT::v4i32, Ops);
2040 MachineSDNode *SITargetLowering::buildScratchRSRC(SelectionDAG &DAG,
2042 SDValue Ptr) const {
2043 const SIInstrInfo *TII = static_cast<const SIInstrInfo *>(
2044 getTargetMachine().getSubtargetImpl()->getInstrInfo());
2045 uint64_t Rsrc = TII->getDefaultRsrcDataFormat() | AMDGPU::RSRC_TID_ENABLE |
2048 return buildRSRC(DAG, DL, Ptr, 0, Rsrc);
2051 MachineSDNode *SITargetLowering::AdjustRegClass(MachineSDNode *N,
2052 SelectionDAG &DAG) const {
2055 unsigned NewOpcode = N->getMachineOpcode();
2057 switch (N->getMachineOpcode()) {
2059 case AMDGPU::S_LOAD_DWORD_IMM:
2060 NewOpcode = AMDGPU::BUFFER_LOAD_DWORD_ADDR64;
2062 case AMDGPU::S_LOAD_DWORDX2_SGPR:
2063 if (NewOpcode == N->getMachineOpcode()) {
2064 NewOpcode = AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64;
2067 case AMDGPU::S_LOAD_DWORDX4_IMM:
2068 case AMDGPU::S_LOAD_DWORDX4_SGPR: {
2069 if (NewOpcode == N->getMachineOpcode()) {
2070 NewOpcode = AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64;
2072 if (fitsRegClass(DAG, N->getOperand(0), AMDGPU::SReg_64RegClassID)) {
2075 ConstantSDNode *Offset = cast<ConstantSDNode>(N->getOperand(1));
2077 const SDValue Zero64 = DAG.getTargetConstant(0, MVT::i64);
2078 SDValue Ptr(DAG.getMachineNode(AMDGPU::S_MOV_B64, DL, MVT::i64, Zero64), 0);
2079 MachineSDNode *RSrc = wrapAddr64Rsrc(DAG, DL, Ptr);
2081 SmallVector<SDValue, 8> Ops;
2082 Ops.push_back(SDValue(RSrc, 0));
2083 Ops.push_back(N->getOperand(0));
2085 // The immediate offset is in dwords on SI and in bytes on VI.
2086 if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
2087 Ops.push_back(DAG.getTargetConstant(Offset->getSExtValue(), MVT::i32));
2089 Ops.push_back(DAG.getTargetConstant(Offset->getSExtValue() << 2, MVT::i32));
2091 // Copy remaining operands so we keep any chain and glue nodes that follow
2092 // the normal operands.
2093 for (unsigned I = 2, E = N->getNumOperands(); I != E; ++I)
2094 Ops.push_back(N->getOperand(I));
2096 return DAG.getMachineNode(NewOpcode, DL, N->getVTList(), Ops);
2101 SDValue SITargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
2102 const TargetRegisterClass *RC,
2103 unsigned Reg, EVT VT) const {
2104 SDValue VReg = AMDGPUTargetLowering::CreateLiveInRegister(DAG, RC, Reg, VT);
2106 return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(DAG.getEntryNode()),
2107 cast<RegisterSDNode>(VReg)->getReg(), VT);